POWER SEMICONDUCTOR ELEMENT

Abstract

Power semiconductor device, comprising: a semiconductor layer (105) made of silicon carbide (SiC); a plurality of trough areas (110) arranged in the semiconductor layer (105), which are spaced apart from each other and have a second conductivity type; a plurality of source regions (112) which are arranged in the semiconductor layer (105) on the plurality of well regions (110), are spaced apart from each other and have a first conductivity type; a drift region (107) having the first conductivity type and arranged in the semiconductor layer (105), wherein the drift region (107) extends from a lower side of the plurality of trough regions (110) to a surface of the semiconductor layer between the plurality of trough regions (110) through (105); a plurality of trenches (116) arranged to extend from the surface of the semiconductor layer (105) into an interior of the semiconductor layer (105), such that each of the plurality of trenches (116) connects two adjacent source regions (112) from the plurality of source regions (112) together; a gate insulating layer (118) arranged on the inner walls of the plurality of grooves (116) and the surface of the semiconductor layer (105); and a gate electrode layer (120) arranged on the gate insulating layer (118) and having a first section burying the plurality of trenches (116) and a second section on the surface of the semiconductor layer (105).

Description

TECHNICAL AREA

[0001] The present disclosure relates to a semiconductor device and in particular a power semiconductor device for switching a power transmission. BACKGROUND

[0002] A power semiconductor device refers to a semiconductor device that operates in a high-voltage and high-current environment. Power semiconductor devices are used in applications requiring high-power switching, such as power conversion, power converters, inverters, or similar devices. Examples of power semiconductor devices include insulated-gate bipolar transistors (IGBTs), power metal-oxide-semiconductor field-effect transistors (MOSFETs), and similar devices. Power semiconductor devices generally require a high-voltage capability, and nowadays, they also require high-speed switching operation.

[0003] Therefore, a power semiconductor device is being developed that uses silicon carbide (SiC) instead of the existing silicon (Si). Silicon carbide (SiC) is a wide-bandgap semiconductor material with a larger bandgap than silicon and remains stable at high temperatures compared to silicon. Since the electrical breakdown field of silicon carbide is much higher than that of silicon, it can operate stably even at high temperatures. Accordingly, silicon carbide enables high-temperature operation due to the following properties: a high breakdown voltage compared to silicon and excellent heat dissipation.

[0004] In the case of a power semiconductor device using silicon carbide, the band gap of the silicon carbide surface can be bent upwards due to the influence of negative charges originating from the formation of carbon clusters in a gate insulating layer. This means that the threshold voltage of the power semiconductor device can increase, and its channel resistance can also increase. A further limitation is that the channel density can only be increased by an existing planar or trench structure.

[0005] A charge pump circuit is known from US Patent 2004 / 0124498A1. The charge pump circuit comprises MOSFETs and MOS capacitors formed on the same substrate. Each of the MOS capacitors has a plurality of first electrodes formed in a region of the substrate, as well as insulating layers formed on / over respective substrate regions between adjacent first electrodes, each layer covering at least the respective substrate region, and a plurality of second electrodes formed on / over the respective insulating layers.

[0006] A silicon carbide semiconductor device is known from DE 11 2013 006 303 T5. The device comprises a drift region of a first conductivity type, formed on a first main surface of a silicon carbide semiconductor substrate with a tilt angle and consisting of silicon carbide. The device comprises a well region of a second conductivity type, formed on a surface of the drift region and consisting of silicon carbide. The device also includes, among other things, a highly concentrated well region of the second conductivity type, formed within the well region and having a higher dopant concentration than the well region.A distance from a first side wall surface of a trench to the highly concentrated basin area on one side of a first side wall surface is shorter than a distance from a second side wall surface of the trench to the highly concentrated basin area on one side of the second side wall surface.

[0007] From US patent 2013 / 0140586A1, a silicon carbide semiconductor device is known. The semiconductor device has a body region of a second conductivity type located on a drift layer of a first conductivity type. The semiconductor device has an impurity region of the first conductivity type located on the body region. The semiconductor device has a trench extending through the body region and the impurity region to reach the drift layer. The semiconductor device has a gate insulating film arranged on the surfaces of the trench. The semiconductor device has a gate electrode arranged on the gate insulating film. The surfaces of the trench comprise a first side face and a second side face opposite the first side face.The concentration of a doping agent of the second conductivity type is higher, at least locally, in one section of the body region adjacent to the first lateral surface than in another section of the body region adjacent to the second lateral surface.

[0008] A semiconductor device is known from JP 2015 162 577 A. The semiconductor device comprises a large-bandgap semiconductor layer, a drift layer with a first conductivity type and containing a second primary surface, and a body region provided on the drift layer and having a second conductivity type. The semiconductor device further comprises a source region provided on the body region such that it is separated from the drift layer, contains a portion of the first primary surface, and has the first conductivity type. The semiconductor device has a contact region provided and arranged on the body region such that it adjoins the source region and has the second conductivity type. An opening exposing the drift layer to the first primary surface is provided on the body region.A source electrode is electrically connected to the source area and the contact area, and electrically connected to the drift layer via the opening.

[0009] A SiC semiconductor device is known from DE 10 2011 088 867 A1. The SiC semiconductor device comprises a substrate, a drift layer, a base region, a source region, a trench, a gate oxide film, a gate electrode, a source electrode, and a drain electrode. The substrate has a silicon surface as its main surface. The source region also has a silicon surface. The trench extends from a surface of the source region to a section deeper than the base region, runs longitudinally in one direction, and has a silicon surface at its bottom. The trench has an inverted tapered shape or a wedge shape in cross-section, with a smaller width at the entry section than at the bottom, at least in the section that is in contact with the base region.

[0010] An electronic device is known from US Patent 2017 / 0179233A1. The device comprises a trigonal crystal substrate defining a (0001) C-plane. A plurality of rhombohedrally oriented SiGe (111) crystals are arranged on the (0001) C-plane of the crystal substrate. A first material region is arranged on the rhombohedrally oriented SiGe layer. The first region comprises an intrinsic or doped Si, Ge, or SiGe layer. The first region can be positioned between two secondary regions comprising n+-doped SiGe or n+-doped Ge, whereby the first region collects electrons from the two secondary regions. SUMMARY

[0011] The present disclosure was made to solve the above-mentioned problems that arise in the prior art, while retaining the advantages of the prior art.

[0012] One aspect of the present disclosure provides a silicon carbide-based power semiconductor device capable of increasing channel density and improving stability.

[0013] According to one aspect of the present disclosure, a power semiconductor device can comprise a silicon carbide (SiC) semiconductor layer, a plurality of well regions arranged in the semiconductor layer, spaced apart from one another and having a second conductivity type, a plurality of source regions arranged in the semiconductor layer, each on the plurality of well regions, spaced apart from one another and having a first conductivity type, a drift region having the first conductivity type and arranged in the semiconductor layer, wherein the drift region extends from a lower side of the plurality of well regions to a surface of the semiconductor layer through between the plurality of well regions, and a plurality of trenches arranged such that they are recessed from the surface of the semiconductor layer into the interior of the semiconductor layer.that each of the multitude of trenches connects two adjacent source regions from the multitude of source regions, a gate insulating layer arranged on the inner walls of the multitude of trenches and the surface of the semiconductor layer, and a gate electrode layer arranged on the gate insulating layer having a first section burying the multitude of trenches and a second section on the surface of the semiconductor layer.

[0014] According to the power semiconductor device, distances between three adjacent well regions from the plurality of well regions can be equal, and distances between three adjacent source regions from the plurality of source regions can be equal.

[0015] According to the power semiconductor device, the drift region can have a projection extending to the surface of the semiconductor layer between three mutually adjacent well regions from the plurality of well regions, and the second section of the gate electrode layer can be located on the projection of the drift region and two adjacent well regions of the three adjacent well regions.

[0016] According to the power semiconductor device, centers of seven adjacent well regions from the plurality of well regions can each be located in a center and at vertices of a regular hexagon, and centers of seven source regions located on the seven adjacent well regions from the plurality of source regions can each be located in the center and at the vertices of the regular hexagon.

[0017] According to the power semiconductor device, the multitude of trenches can contain sections of lines that connect two adjacent ones from the center and the vertices of the regular hexagon in such a way that the seven adjacent source areas are connected.

[0018] According to the power semiconductor device, a first channel region, which is confined to the semiconductor layer in order to correspond to the first section of the gate electrode layer and to be connected to the drift region and the source regions which are in contact with the plurality of trenches along the plurality of trenches, and a second channel region below the second section of the gate electrode layer and confined to the semiconductor layer in order to be in contact with the plurality of source regions, may further be provided.

[0019] According to the power semiconductor device, the first channel area and the second channel area can have the second conductivity type, so that an inversion channel is formed, and the first channel area and the second channel area can be sections of the plurality of basin areas.

[0020] According to the power semiconductor device, the first channel region can have the second conductivity type, so that an inversion channel is formed; the second channel region can have the first conductivity type, so that an accumulation channel is formed; the first channel region can correspond to sections of the multitude of trough regions; the second channel region can be a section of the drift region; and the multitude of source regions can be in contact with the drift region on the surface of the semiconductor layer.

[0021] According to the power semiconductor device, a plurality of well contact areas arranged in the plurality of source areas and on the plurality of well areas, exhibiting the second conductivity type, and a source electrode layer connected to the plurality of source areas and the plurality of well contact areas may also be provided.

[0022] According to the power semiconductor device, the multitude of well contact areas can have a circular shape in a top view, and the multitude of source areas can have a doughnut shape surrounding the multitude of well contact areas.

[0023] According to the power semiconductor device, the multitude of basin regions can have a shape in which their width increases from the surface of the semiconductor layer to an interior of the semiconductor layer and then decreases.

[0024] According to the power semiconductor device, opposite lower corners of the first section of the gate electrode layer can be surrounded by the multitude of trough areas.

[0025] The power semiconductor device may further have a drain region in the semiconductor layer below the drift region and exhibit the first conductivity type, and the drift region may have an epitaxial layer on the drift region.

[0026] A power semiconductor device according to one aspect of the present disclosure for solving the problem can have a silicon carbide (SiC) semiconductor layer, a plurality of well regions arranged in the semiconductor layer and having a second conductivity type, a plurality of source regions arranged in the semiconductor layer, each on the plurality of well regions and having a first conductivity type, a drift region having the first conductivity type and arranged in the semiconductor layer, extending from a lower side of the plurality of well regions to a surface of the semiconductor layer through between the plurality of well regions and providing a vertical transport path for charges, and a plurality of trenches arranged to be embedded from the surface of the semiconductor layer into the interior of the semiconductor layer.such that each of the multitude of trenches connects two mutually adjacent source regions from the multitude of source regions, a gate insulating layer arranged on the inner walls of the multitude of trenches and the surface of the semiconductor layer, a gate electrode layer arranged on the gate insulating layer and having a first section burying the multitude of trenches and a second section on the surface of the semiconductor layer, a first channel region confined to the semiconductor layer such that an inversion channel extends along the multitude of trenches to correspond to the first section of the gate electrode layer, and a second channel region located below the second section of the gate electrode layer and confined to the semiconductor layer such that an accumulation channel is formed.

[0027] According to the power semiconductor device, distances between three adjacent well regions from the plurality of well regions can be equal, and distances between three adjacent source regions from the plurality of source regions can be equal.

[0028] According to the power semiconductor device, the drift region can have a projection extending to the surface of the semiconductor layer between three mutually adjacent well regions from the plurality of well regions, and the second section of the gate electrode layer can be arranged on the projection of the drift region and the two adjacent well regions of the three adjacent well regions.

[0029] According to the power semiconductor device, centers of seven adjacent well regions from the plurality of well regions can each be located in a center and at vertices of a regular hexagon, and centers of seven source regions located on the seven adjacent well regions from the plurality of source regions can each be located in the center and at the vertices of the regular hexagon.

[0030] According to the power semiconductor device, the multitude of trenches can form sections of lines that connect two adjacent ones from the center and the vertices of the regular hexagon, so that the seven adjacent source areas are connected.

[0031] According to the power semiconductor device, the first channel area can exhibit the second conductivity type and correspond to sections of the multitude of basin areas.

[0032] According to the power semiconductor device, the multitude of source areas can be in contact with the drift area on the surface of the semiconductor layer, and the second channel area can have the first conductivity type and can be a section of the drift area that is in contact with the multitude of source areas.

[0033] According to the power semiconductor device, the plurality of source regions can each have counter-doping regions formed by doping with impurities of the first conductivity type in the plurality of basin regions at sections where the plurality of source regions and the drift region touch each other.

[0034] According to the power semiconductor device, a plurality of well contact areas formed in the plurality of source areas and on the plurality of well areas, exhibiting the second conductivity type, and a source electrode layer connected to the plurality of source areas and the plurality of well contact areas may also be provided.

[0035] According to the power semiconductor device, the plurality of well contact areas can be circular in a top view, and the plurality of source areas can be shaped like a doughnut surrounding the plurality of well contact areas.

[0036] The power semiconductor device may further include a drain region in the semiconductor layer below the drift region, which exhibits the first conductivity type, and the drift region may be formed from an epitaxial layer on the drift region.

[0037] According to the power semiconductor device, the multitude of basin areas can be shaped such that two adjacent basin areas at least partially touch each other beneath the basin areas.

[0038] According to the power semiconductor device, the plurality of basin regions can have a shape in which one of their widths increases from the surface of the semiconductor layer to the interior of the semiconductor layer and then decreases, and two adjacent basin regions from the basin regions can touch each other at a point where at least one of their widths is greatest within the semiconductor layer, and can be spaced apart from each other on the surface of the semiconductor layer.

[0039] According to the power semiconductor device, from a cross-section of the first section of the gate electrode layer seen in one direction of extension, a bottom surface of the first section can be surrounded by a multitude of trough areas.

[0040] According to the power semiconductor device, the plurality of basin regions in the semiconductor layer can be formed such that they are spaced apart from each other, and the plurality of basin regions can have a shape in which their width increases as they move from the surface of the semiconductor layer into an interior of the semiconductor layer and then decreases.

[0041] According to the power semiconductor device, opposite lower corners of the first section of the gate electrode layer can be surrounded by the multitude of trough areas.

[0042] A power semiconductor device fabrication method according to another aspect of the present disclosure may comprise forming a drift region with a first conductivity type in a silicon carbide (SiC) semiconductor layer to provide a vertical transport path for charges, forming a plurality of well regions with a second conductivity type in the semiconductor layer, forming a plurality of source regions with the first conductivity type in the semiconductor layer, each on the plurality of well regions, forming a plurality of trenches that extend from the surface of the semiconductor layer into an interior of the semiconductor layer such that each of the plurality of trenches connects two mutually adjacent source regions from the plurality of source regions, and forming a gate insulating layer on the inner walls of the plurality of trenches and the surface of the semiconductor layer.and forming a gate electrode layer on the gate insulating layer, which has a first section burying the plurality of trenches and a second section on the surface of the semiconductor layer. The drift region can be configured to extend from a lower side of the plurality of trenches to the surface of the semiconductor layer through between the plurality of trenches; the first channel region can be confined to the semiconductor layer, forming an inversion channel along the plurality of trenches corresponding to the first section of the gate electrode layer; and the second channel region can lie below the second section of the gate electrode layer and can be confined to the semiconductor layer, forming an accumulation channel.

[0043] According to the power semiconductor device manufacturing process, the multitude of well areas can be shaped to have a form in which their width increases from the surface of the semiconductor layer to an interior of the semiconductor layer and then decreases.

[0044] According to the power semiconductor device manufacturing process, the formation of the plurality of well areas can include such a formation of the plurality of well areas that centers of seven mutually adjacent well areas from the plurality of well areas are each arranged in a center and at vertices of a regular hexagon.

[0045] A power semiconductor device according to one aspect of the present disclosure for solving the problem can comprise a silicon carbide (SiC) semiconductor layer, a plurality of well regions arranged in the semiconductor layer such that two adjacent well regions are at least partially in contact with each other and have a second conductivity type, a plurality of source regions formed in the semiconductor layer on the plurality of well regions and having a first conductivity type, a drift region having the first conductivity type and formed in the semiconductor layer such that it extends from a lower side of the plurality of well regions to a surface of the semiconductor layer through the plurality of well regions, thus providing a vertical transport path for charges, and a plurality of trenches formed in such a way thatthat they are embedded from the surface of the semiconductor layer into an interior of the semiconductor layer, such that each of the plurality of trenches connects two adjacent source regions from the plurality of source regions via a point where two adjacent basin regions from the plurality of basin regions touch each other, a gate insulating layer formed on the inner walls of the plurality of trenches and the surface of the semiconductor layer, and a gate electrode layer formed on the gate insulating layer, having a first section burying the plurality of trenches and a second section on the surface of the semiconductor layer,

[0046] According to the power semiconductor device, distances between three adjacent well regions from the plurality of well regions can be the same, and distances between three adjacent source regions from the plurality of source regions can be the same.

[0047] According to the power semiconductor device, the drift region can have a projection extending to the surface of the semiconductor layer between three adjacent well regions from the plurality of well regions, and the second section of the gate electrode layer can be formed on the projection of the drift region and the two adjacent well regions.

[0048] According to the power semiconductor device, centers of seven adjacent well regions from the plurality of well regions can each be located in a center and at vertices of a regular hexagon, and centers of seven source regions located on the seven adjacent well regions from the plurality of source regions can each be located in the center and at the vertices of the regular hexagon.

[0049] According to the power semiconductor device, the multitude of trenches can form sections of lines that connect two adjacent ones from the center and the vertices of the regular hexagon, so that the seven adjacent source areas are connected.

[0050] According to the power semiconductor device, a first channel region, which is confined to the semiconductor layer, so that it corresponds to the first section of the gate electrode layer and is in contact with the drift region and the source regions, which are in contact with the plurality of trenches along the plurality of trenches, and a second channel region below the second section of the gate electrode layer, which is confined to the semiconductor layer, so that it is in contact with the plurality of source regions, can further be provided.

[0051] According to the power semiconductor device, the first channel area and the second channel area can have the second conductivity type, so that an inversion channel is formed, and the first channel area and the second channel area can be sections of the multitude of basin areas.

[0052] According to the power semiconductor device, the first channel area can have the second conductivity type, so that an inversion channel is formed; the second channel area can have the first conductivity type, so that an accumulation channel is formed; the first channel area can correspond to sections of the majority of trough areas; the second channel area can be a section of the drift area; and the majority of source areas can be in contact with the drift area on the surface of the semiconductor layer.

[0053] According to the power semiconductor device, a plurality of well contact areas formed in the plurality of source areas and on the plurality of well areas, exhibiting the second conductivity type, and a source electrode layer connected to the plurality of source areas and the plurality of well contact areas may also be provided.

[0054] According to the power semiconductor device, the plurality of well contact areas can be circular in a top view, and the plurality of source areas can be shaped like a doughnut surrounding the plurality of well contact areas.

[0055] According to the power semiconductor device, the plurality of well regions can have a shape in which their width increases from the surface of the semiconductor layer to an interior of the semiconductor layer and then decreases, and two adjacent well regions from the well regions can touch each other at a point where at least their width is greatest within the semiconductor layer, and can be spaced apart from each other on the surface of the semiconductor layer.

[0056] According to the power semiconductor device, in the first section of the gate electrode layer, a cross-section of a floor surface in one direction of extension can be surrounded by a multitude of trough areas.

[0057] According to the power semiconductor device, from a cross-section of the first section of the gate electrode layer seen in one direction of extension, a bottom surface of the first section can be surrounded by a multitude of trough areas.

[0058] The power semiconductor device may further have a drain region in the semiconductor layer below the drift region and with the first conductivity type, and the drift region may be formed from an epitaxial layer on the drift region.

[0059] A power semiconductor device fabrication method according to another aspect of the present disclosure may comprise forming a drift region with a first conductivity type in a silicon carbide (SiC) semiconductor layer to provide a vertical transport path for charges, forming a plurality of well regions with a second conductivity type in the semiconductor layer such that two adjacent well regions are at least partially in contact with each other, forming a plurality of source regions, each with the first conductivity type in the semiconductor layer on the plurality of well regions, forming a plurality of trenches that are sunk into an interior of the semiconductor layer from a surface of the semiconductor layer such that each of the plurality of trenches connects two adjacent source regions from the plurality of source regions at one point.where two adjacent well regions from the plurality of well regions touch each other, a gate insulating layer is formed on the inner walls of the plurality of trenches and the surface of the semiconductor layer, and a gate electrode layer is formed on the gate insulating layer, having a first section that buries the plurality of trenches and a second section on the surface of the semiconductor layer. The drift region can be formed to be in contact with the drift region such that the drift region extends from a lower side of the plurality of well regions to the surface of the semiconductor layer through between the plurality of well regions.

[0060] According to the power semiconductor device manufacturing process, the plurality of well regions can be formed to have a shape in which their width increases from the surface of the semiconductor layer to an interior of the semiconductor layer and then decreases, and two mutually adjacent well regions from the well regions can touch each other at a point where at least their width is greatest within the semiconductor layer, and can be spaced apart from each other on the surface of the semiconductor layer.

[0061] According to the power semiconductor device manufacturing process, the formation of the plurality of well areas can include forming the plurality of well areas in such a way that the centers of seven adjacent well areas from the plurality of well areas are each arranged in a center and at vertices of a regular hexagon.

[0062] According to the power semiconductor device manufacturing process, a plurality of well contact areas with the second conductivity type can be formed in the plurality of source areas and on the plurality of well areas, and a source electrode layer connected to the plurality of source areas and the plurality of well contact areas can be formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The above and other tasks, features and advantages of the present disclosure will become clearer from the following detailed description in conjunction with the accompanying drawings: Fig. Figure 1 is a schematic perspective view showing a power semiconductor device according to an embodiment of the present disclosure; Fig. 2 is a top view showing a power semiconductor device along line II-II of Fig. 1 shows; Fig. 3 is a cross-sectional view showing a power semiconductor device along line III-III of Fig. 2 shows; Fig. 4 is a cross-sectional view showing a power semiconductor device along line IV-IV of Fig. 2 shows; Fig. Figure 5 is a cross-sectional view of a power semiconductor device along line VV of Fig. 2; Fig. 6 is a top view showing a power semiconductor device according to another embodiment of the present disclosure; Fig. 7 and Fig. Figure 8 are cross-sectional views showing a power semiconductor device according to another embodiment of the present disclosure; Fig. Figures 9 to 11 and 13 are cross-sectional views showing a method for manufacturing a power semiconductor device according to an embodiment of the present disclosure; Fig. 12 is a top view showing a power semiconductor device made of Fig. 11 shows; Fig. Figure 14 is a schematic perspective view showing a power semiconductor device according to an embodiment of the present disclosure; Fig. 15 is a top view showing a power semiconductor device along line II-II of Fig. 14 shows; Fig. Figure 16 is a cross-sectional view showing a power semiconductor device along line III-III of Fig. 15 shows; Fig. Figure 17 is a cross-sectional view showing a power semiconductor device along line IV-IV of Fig. 15 shows; Fig. 18 is a cross-sectional view showing a power semiconductor device along line VV of Fig. 15 shows; Fig. 19 is a top view showing a power semiconductor device along line VI-VI of Fig. 14 shows; Fig. 20 is a top view showing a power semiconductor device according to another embodiment of the present disclosure; Fig. Figure 21 is a cross-sectional view showing a power semiconductor device according to another embodiment of the present disclosure; Fig. Figure 22 is a perspective view showing a power semiconductor device according to another embodiment of the present disclosure; Fig. Figures 23 to 25 and 27 are cross-sectional views showing a method for manufacturing a power semiconductor device according to an embodiment of the present disclosure; Fig. Figure 26 is a top view showing a method for manufacturing a power semiconductor device from Fig. 25 shows; Fig. 28 is a schematic perspective view showing a power semiconductor device according to an embodiment of the present disclosure; Fig. 29 is a top view showing a power semiconductor device along line II-II of Fig. 28 shows; Fig. 30 is a cross-sectional view showing a power semiconductor device along line III-III of Fig. 29 shows; Fig. 31 is a cross-sectional view showing a power semiconductor device along line IV-IV of Fig. 29 shows; Fig. 32 is a cross-sectional view showing a power semiconductor device along line VV of Fig. 29 shows; Fig. 33 is a top view showing a power semiconductor device along line VI-VI of Fig. 28 shows; Fig. 34 is a top view showing a power semiconductor device according to another embodiment of the present disclosure; Fig. 35 and Fig. Figure 36 are cross-sectional views showing a power semiconductor device according to another embodiment of the present disclosure; Fig. Figures 37 to 39 and 41 are cross-sectional views showing a method for manufacturing a power semiconductor device according to an embodiment of the present disclosure; and Fig. 40 is a top view showing a power semiconductor device made of Fig. 39 shows. DETAILED DESCRIPTION

[0064] The same reference symbols denote the same components. If a first component, such as a layer, area, or substrate, is described as being located on a second component, this can be understood to mean that the first component lies directly on top of the second component or that a third component is positioned between them. Conversely, if a first component is described as lying "directly on" a second component, this means that there is no intermediate component between them.

[0065] Fig. Figure 1 is a schematic perspective view showing a power semiconductor device 100-1 according to an embodiment of the present disclosure, Fig. Figure 2 is a top view showing the power semiconductor device 100-1 along line II-II of Fig. 1 shows, Fig. Figure 3 is a cross-sectional view showing the power semiconductor device 100-1 along line III-III of Fig. 2 shows, Fig. Figure 4 is a cross-sectional view showing the power semiconductor device 100-1 along line IV-IV of Fig. 2 shows, and Fig. Figure 5 is a cross-sectional view showing the power semiconductor device 100-1 along line VV of Fig. 2 shows.

[0066] As in the Fig. As shown in Figures 1 to 5, the power semiconductor device 100-1 can have at least one semiconductor layer 105, one gate insulating layer 118, and one gate electrode layer 120. For example, the power semiconductor device 100-1 can have a power MOSFET structure.

[0067] Semiconductor layer 105 can refer to a single semiconductor material layer or a plurality of semiconductor material layers, for example, an epitaxial layer or a plurality of epitaxial layers. Furthermore, semiconductor layer 105 can refer to one or more epitaxial layers on a semiconductor substrate.

[0068] Semiconductor layer 105 can, for example, be made of silicon carbide (SiC). More precisely, semiconductor layer 105 can have at least one epitaxial layer of silicon carbide.

[0069] Silicon carbide (SiC) can have a wider band gap than silicon, thus remaining stable at high temperatures compared to silicon. Since the electrical breakdown field of silicon carbide is much higher than that of silicon, silicon carbide can operate stably even at high temperatures. Accordingly, the power semiconductor device 100-1, which uses silicon carbide as the semiconductor layer 105, can exhibit a high breakdown voltage compared to the case where silicon is used and offers excellent heat dissipation (or release) characteristics and stable operation at high temperatures.

[0070] Specifically, the semiconductor layer 105 can have a multitude of well regions 110, a multitude of source regions 112 and a drift region 107.

[0071] The drift region 107 can exhibit a first conductivity type and can be formed by implanting first conductivity-type impurities into a section of the semiconductor layer 105. For example, the drift region 107 can be formed by doping first conductivity-type impurities into an epitaxial layer of silicon carbide. The drift region 107 can provide a vertical transport pathway for charges.

[0072] The well regions can be arranged in the semiconductor layer 105 to be spaced apart from one another and can have a second conductivity type. For example, the well regions 110 in the semiconductor layer 105 can be configured to be in contact with at least a portion of the drift region 107. In some embodiments, the well regions 110 can be formed by doping impurities of the second conductivity type, which is opposite to the first conductivity type, into the semiconductor layer 105 or the drift region 107.

[0073] The source regions 112 can be formed in the semiconductor layer 105 on the well regions 110 such that they are spaced apart from one another and can exhibit the first conductivity type. The source regions 112 can be formed, for example, by doping impurities of the first conductivity type in the semiconductor layer 105 or the well region 110. The concentration of the impurities of the first conductivity type with which the source region 112 is doped can be higher than that with which the drift region 107 is doped.

[0074] A multitude of basin contact areas 114 can be formed in the source areas 112 and on the basin areas 110. For example, the multitude of basin contact areas 114 on the basin areas 110 can be configured to be connected to the basin areas 110 via the source areas 112. The basin contact areas 114 can be configured to exhibit the second conductivity type.

[0075] The trough contact areas 114 can be connected to a source electrode layer 140 and can be doped with impurities of the second conductivity type at a higher concentration than the trough areas 110 in order to reduce contact resistance when connected to the source electrode layer 140.

[0076] In some embodiments, the trough contact areas 114 can be formed in a recessed groove that is in contact with the trough areas 110. In this case, the source electrode layer 140 can be shaped so that it fills the recessed groove and can be connected to the trough contact area 114.

[0077] Furthermore, a drain region 102 may be formed in the semiconductor layer 105 below the drift region 107, which may exhibit the first conductivity type. The drain region 102 may, for example, be doped with impurities at a higher concentration compared to the drift region 107.

[0078] In some embodiments, the drain region 102 can be implemented with a silicon carbide substrate of the first conductivity type. In this case, the drain region 102 can be understood as a section of the semiconductor layer 105 or as a substrate independent of the semiconductor layer 105. Furthermore, in some embodiments, the drain region 102 can be implemented with a silicon carbide substrate of the first conductivity type, and the drift region 107 can be formed on the drain region 102 using one or more epitaxial layers.

[0079] In some embodiments, the drift region 107 in the semiconductor layer 105 can be configured to extend from the underside of the well regions 110 through the space between the well regions 110 to a surface of the semiconductor layer 105. For example, the drift region 107 can include projections 107a that extend to the surface of the semiconductor layer 105 between the well regions 110.

[0080] A multitude of trenches 116 can be configured to extend from the surface of the semiconductor layer 105 to a certain depth within the semiconductor layer 105. For example, each of the trenches 116 can be configured to connect two adjacent source regions from the source regions 112. Specifically, each trench 116 can be formed in a line type in which a source region 112 is connected to an adjacent source region 112 via a trough region 110 that surrounds one source region 112, the projection 107a of the drift region 107, and an adjacent trough region 110.

[0081] For example, the trenches 116 may be shaped such that they penetrate sections of the source areas 112 and are set back to a certain depth from the trough areas 110 and the projections 107a of the drift area 107. Accordingly, opposite corners (or edges) of the trenches 116 may be surrounded by the trough areas 110.

[0082] The gate insulating layer 118 can be formed on the inner walls of the grooves 116 and at least one section of the semiconductor layer 105. For example, the gate insulating layer 118 can be formed on the inner walls of the grooves 116 and the surface of the semiconductor layer 105.

[0083] The gate insulating layer 118 can, for example, comprise an insulating material such as silicon oxide, silicon carbide oxide, silicon nitride, hafnium oxide, zirconium oxide or aluminum oxide, or a layer structure consisting thereof.

[0084] The gate electrode layer 120 can be formed on the gate insulating layer 118. The gate electrode layer 120 can, for example, comprise a first section 120a, which encloses the trenches 116, and a second section 120b on the surface of the semiconductor layer 105. The first section 120a of the gate electrode layer 120 can, for example, have a trench-type gate structure, and the second section 120b can have a planar-type gate structure. Accordingly, the gate electrode layer 120 can have a hybrid structure that incorporates both the trench-type gate structure and the planar-type gate structure.

[0085] For example, the second section 120b of the gate electrode layer 120 can be formed on the projections 107a of the drift region 107 and the well regions 110. Specifically, the second section 120b of the gate electrode layer 120 can be formed on 1) the projections 107a of the drift region 107 that are exposed on the surface of the semiconductor layer 105, 2) surfaces of the well regions 110, and 3) surfaces of sections of the peripheries of the source regions 112. The well contact regions 114 and the remaining sections of the source regions 112 can be located on the outside of the gate electrode layer 120 and be exposed from the gate electrode layer 120.

[0086] The gate electrode layer 120 can, for example, contain a suitable conductive material such as polysilicon, metal, metal nitride or metal silicide, or a layer structure thereof.

[0087] An insulating intermediate layer 130 can be formed on the gate electrode layer 120. The insulating intermediate layer 130 can, for example, contain a suitable insulating material such as an oxide layer or a nitride layer, or a stacked structure thereof.

[0088] The source electrode layer 140 can be formed on the insulating intermediate layer 130. Furthermore, the source electrode layer 140 can be connected to the source regions 112 and the well contact regions 114. For example, the source electrode layer 140 can be connected to the source region 112 and the well contact region 114 via a section exposed by the gate electrode layer 120, and it can be arranged to extend further onto the gate electrode layer 120. The source electrode layer 140 can be made of, for example, a suitable conductive material, metal, or the like.

[0089] A first channel region C1 can be formed in the semiconductor layer 105 along the trench 116, corresponding to the first section 120a of the gate electrode layer 120, to connect with the source regions 112 and the drift region 107. For example, the first channel region C1 can be formed in the semiconductor layer 105 along the side walls of the trench 116 to connect the drift region 107 below the trench 116, for example, the projection 107a of the drift region 107, and the source regions 112 touching the trench 116. Accordingly, the first channel region C1 can have a trench-like channel structure.

[0090] A second channel region C2 can be formed in the semiconductor layer 105 below the second section 120b of the gate electrode layer 120 to contact the source regions 112. For example, the second channel region C2 can be formed on the semiconductor layer 105 between the projection 107a of the drift region 107 and the source regions 112. The second channel region C2 can be configured to cover surfaces of the trough regions 110. Accordingly, the second channel region C2 can have a planar channel structure.

[0091] For example, the first channel region C1 and the second channel region C2 can have the second conductivity type, thus forming an inversion channel. Since the first channel region C1 and the second channel region C2 have a doping type opposite to that of the source region 112 and the drift region 107, the first channel region C1 and the second channel region C2 can form a diode junction with the source region 112 and the drift region 107.

[0092] Accordingly, the first channel region C1 and the second channel region C2 cannot allow charge movement in a normal situation; however, if an operating voltage is applied to the gate electrode layer 120, the inversion channel can be formed in it in such a way that the movement of charges is allowed.

[0093] For example, the first channel region C1 and the second channel region C2 can be sections of the trough regions 110. Specifically, the first channel region C1 can be parts of the trough regions 110 that are adjacent to a lower surface of the first section 120a of the gate electrode layer 120, and the second channel region C2 can be sections of the trough regions 110 that are adjacent to a lower surface of the second section 120b of the gate electrode layer 120.

[0094] In this case, the first channel region C1 and the second channel region C2 can be formed integrally with the basin regions 110 or continuously connected to the basin regions 110. The doping concentration of the second conductivity type impurities in the first channel region C1 and the second channel region C2 can be the same as that of the remaining section of the basin region 110, or it can differ from it for the purpose of setting a threshold voltage.

[0095] In some embodiments, the distances between three adjacent basin regions 110 below the basin regions 110 can be equal. Furthermore, the distances between three adjacent source regions 112 from the source regions 112 can be equal. For example, the centers of three adjacent basin regions 110 can each be located at the vertices of a regular triangle, and the centers of three adjacent source regions 112 on the three basin regions 110 can also each be located at the vertices of the same regular triangle. For example, the basin regions 110 and the source regions 112 can be understood to denote three triangles that are in Fig. 2 are arranged.

[0096] In some embodiments, the centers of seven adjacent basin regions 110 can each be arranged at the center and at the vertices of a regular hexagon. Furthermore, the centers of seven source regions 112, located on the seven adjacent basin regions 110 of the source regions 112, can each be arranged at the center and at the vertices of the regular hexagon. For example, the Fig. to be understood as showing the 7 tub areas 110 and 7 source areas 112 described above.

[0097] In this structure, the basin areas 110 and the source areas 112 can be arranged such that they resemble a planar arrangement structure within a hexagonal, closed-packed arrangement structure. Furthermore, the distance between two adjacent basin areas 110 can be uniform, and the distance between two adjacent source areas 112 can also be uniform.

[0098] In this structure, the trenches 116 can be arranged to form sections of lines, each connecting two adjacent lines from the center and vertices of the regular hexagon, so that seven adjacent source areas 112 are connected. Specifically, the trenches 116 can be arranged in Fig. 2 6 lines that connect 6 source regions 112 arranged at the vertices with a source region 112 arranged in the center of the regular hexagon, and 6 lines that each connect two adjacent source regions from the 6 source regions 112 arranged at the vertices.

[0099] In some embodiments, the basin regions 110 can have a shape in which their width increases from the surface of the semiconductor layer 105 towards the interior of the semiconductor layer 105 and then decreases. For example, the basin region 110 can be part of a spherical shape, and a cross-section of the basin region 110 can be circular.

[0100] Furthermore, the borehole contact area 114 can be circular in plan view. For example, the circular well contact area 114 can be formed within the circular well area 110 in plan view. The lower surfaces of the well contact areas 114 can be connected to the well areas 110. In a plan view, the source area 112 can be shaped like a donut surrounding the well contact area 114. The above shape, viewed from above the surface of the semiconductor layer 105, can extend to a certain depth from the surface of the semiconductor layer 105.

[0101] In the power semiconductor device 100-1 described above, the first conductivity type and the second conductivity type can be opposite to each other, and each of the first and second conductivity types can be either n-type or p-type. For example, if the first conductivity type is n-type, the second conductivity type is p-type, and vice versa.

[0102] If the power semiconductor device 100-1 is an N-type MOSFET, the drift area 107 can be an N-area, the source area 112 and the drain area 102 can be N+ areas, the well area 110, the first channel area C1 and the second channel area C2 can be P-areas, and the well contact area 114 can be a P+ area.

[0103] According to the power semiconductor device 100-1, the depth of the basin areas 110 can be deeper than that of the trenches 116 and the gate electrode layer 120. Thus, a trench bottom corner of the first section 120a of the gate electrode layer 120 can be surrounded by the basin area 110. This structure can reduce the concentration of the electric field at the trench bottom corner in the trench-gate structure.

[0104] In the operation of the power semiconductor device 100-1, a current can generally flow in a vertical direction from the drain region 102 along the drift region 107 and then through the first channel region C1 and the second channel region C2 to the source region 112.

[0105] The power semiconductor device 100-1 can have a hybrid structure incorporating both trench-type and planar-type gate structures. Furthermore, the power semiconductor device 100-1 can have a regular hexagonal structure and, by combining the trench-type and planar-type gate structures, achieve a high degree of integration with a high channel density. Moreover, compared to a device using only a planar structure, the power semiconductor device 100-1 can maintain the degree of integration and improve channel mobility by adding the trench structure.

[0106] Fig. Figure 6 is a cross-sectional view showing a power semiconductor device 100a-1 according to another embodiment of the present disclosure.

[0107] The power semiconductor device 100a-1 (see Fig. 6) shows part of a structure in which a variety of power semiconductor devices 100-1 (see Fig. 1 to 5) are arranged.

[0108] By repeating the hexagonal structure with closed packing, the 100a-1 power semiconductor device can exhibit a high degree of integration.

[0109] Fig. 7 and Fig. Figure 8 are cross-sectional views showing a power semiconductor device 100b-1 according to another embodiment of the present disclosure. The power semiconductor device 100b-1 can be obtained by modifying a partial configuration of the power semiconductor device 100-1 from the Fig. 1 to 5 can be implemented, and therefore an additional description is omitted to avoid redundancy, as they can refer to each other.

[0110] With reference to the Fig. In the power semiconductor device 100b-1, a second channel region C2a can be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the second channel region C2a can be formed in the semiconductor layer 105 between the projection 107a of the drift region 107 and the source region 112. The second channel region C2a can have the first conductivity type, thus forming an accumulation channel.

[0111] For example, the second channel region C2a can have the same doping type as the source region 112 and the drift region 107. In this case, the source region 112, the second channel region C2a, and the drift region 107 are normally electrically connected. However, a potential barrier is formed in the structure of the silicon carbide semiconductor layer 105, while a band of the second channel region C2a is bent upwards due to the influence of negative charges generated by the formation of carbon clusters in the gate insulating layer 118. In this way, an accumulation channel can be formed, which allows a charge or current flow in the second channel region C2a when an operating voltage is applied to the gate electrode layer 120.

[0112] Accordingly, a threshold voltage that must be applied to the gate electrode layer 120 to form the accumulation channel in the second channel region C2a can be considerably lower than a threshold voltage that must be applied to the gate electrode layer 120 to form a normal inversion channel.

[0113] In some embodiments, the second channel region C2a can be part of the drift region 107. More precisely, the second channel region C2a can be part of the projection 107a of the drift region 107. For example, the second channel region C2a can be formed integrally with the drift region 107. Thus, in the power semiconductor device 100b-1, the source regions 112 can be in direct contact with the drift region 107, e.g., with the projection 107a, and the second channel region C2a can be limited to a portion of the drift region 107 where the direct contact is established.

[0114] For example, the doping concentration of the impurities of the first conductivity type of the second channel region C2a may be the same as that of the remaining part of the drift region 107 or may differ from it for the purpose of setting a threshold voltage.

[0115] In some embodiments, the basin region 110 beneath the source regions 112 can be configured to project further than the source regions 112 in the direction of the projection 107a of the drift region 107. In this case, the second channel region C2a in the semiconductor layer 105 can be formed on the projecting portion of the basin region 110. For example, the projection 107a of the drift region 107 can extend further to a groove section between the basin region 110 and the gate electrode layer 120, and the second channel region C2a can be formed on this projecting section. The above structure can allow the second channel region C2a to be bounded between the second section 120b of the gate electrode layer 120 and the basin region 110.

[0116] In the power semiconductor device 100b-1, the first channel area C1 can be used as an inversion channel, as in the power semiconductor device 100-1 of the Fig. Numbers 1 to 5 are planned.

[0117] Fig. Figures 9 to 11 and 13 are cross-sectional views illustrating a method for manufacturing the power semiconductor device 100-1 according to an embodiment of the present disclosure, and Fig. 12 is a top view of Fig. 11.

[0118] As in Fig. As shown in Figure 9, the drift region 107 can be formed with the first conductivity type in the silicon carbide (SiC) semiconductor layer 105. For example, the drift region 107 can be formed on the drain region 102 with the first conductivity type. In some embodiments, the drain region 102 can be realized with a substrate of the first conductivity type, and the drift region 107 can be formed on the substrate with one or more epitaxial layers.

[0119] Subsequently, the trough regions 110 of the second conductivity type in the semiconductor layer 105 can be formed such that they are in contact with the drift region 107. The formation of the trough regions 110 can, for example, involve the implantation of impurities of the second conductivity type into the semiconductor layer 105. The trough regions 110 can be formed to a certain depth essentially from the surface of the semiconductor layer 105.

[0120] For example, the well regions 110 in the semiconductor layer 105 can be configured such that the drift region 107 contains the projections 107a, at least sections of which are surrounded by the well regions 110. Specifically, the well regions 110 can be formed in the drift region 107 by doping with impurities of a conductivity opposite to that of the drift region 107.

[0121] The source regions 112 with the first conductivity type can be formed in or on the well regions 110. For example, the source regions 112 can be formed by implanting impurities of the first conductivity type into the well regions 110 and the drift region 107. The source regions 112 can be formed in the well regions 110 to a certain depth essentially from the surface of the semiconductor layer 105.

[0122] The trough contact areas 114 can be formed by implanting impurities of the second conductivity type into the trough areas 110 or into the source areas 112. For example, the trough contact areas 114 can be circular in a top view.

[0123] In a modified example of this embodiment, the sequence in which the trough areas 110, the trough contact areas 114 and the source B areas 112 are doped with impurities can be changed arbitrarily.

[0124] In the above manufacturing process, impurity implantation or doping can be carried out in such a way that the impurities are mixed when the impurities are implanted into semiconductor layer 105 or when an epitaxial layer is formed. However, the ion implantation method using a mask pattern can be used to implant impurities into a selective area.

[0125] Optionally, a heat treatment process can be carried out after ion implantation to activate or diffuse the impurities.

[0126] With reference to Fig. 10 A large number of trenches 116 can be formed, which are cut from the surface of the semiconductor layer 105 to a certain depth into the semiconductor layer 105.

[0127] For example, the trenches 116 can be shaped so that they penetrate sections of the source areas 112 and are set back to a certain depth of the basin areas 110 and the projections 107a of the drift region 107.

[0128] The trenches 116 can be formed, for example, by creating a photomask using photolithography and subsequently etching the semiconductor layer 105 using the photomask as an etching protection layer.

[0129] As in the Fig. 11 and Fig. As shown in Figure 12, the gate insulating layer 118 can be formed on the inner walls of the grooves 116 and the surface of the semiconductor layer 105. The gate insulating layer 118 can be formed, for example, by oxidizing the semiconductor layer 105 to form an oxide or by applying an insulating material such as oxide or nitride to the semiconductor layer 105.

[0130] Subsequently, the gate electrode layer 120, comprising the first section 120a, which encloses the trenches 116, and the second section 120b on the surface of the semiconductor layer 105, can be formed on the gate insulating layer 118. The gate electrode layer 120 can be formed, for example, by forming a conductive layer on the gate insulating layer 118 and subsequently structuring the conductive layer. The gate electrode layer 120 can be formed by doping impurities into polysilicon or by containing a conductive metal or metal silicide.

[0131] A pattern formation process can be carried out using photolithography and etching. The photolithography process can involve creating a photoresist pattern as a mask layer using a photographic and development process, while the etching process can involve selectively etching an underlying structure using the photoresist pattern.

[0132] As in Fig. As shown in Figure 13, the insulating intermediate layer 130 can be formed on the gate electrode layer 120.

[0133] Subsequently, the source electrode layer 140 can be formed on the insulating intermediate layer 130 such that it is connected to the source regions 112 and the trough contact regions 114. The source electrode layer 140 can be formed, for example, by forming a conductive layer, such as a metal layer, on the insulating intermediate layer 130 and by structuring the conductive layer.

[0134] Fig. Figure 14 is a schematic perspective view showing a power semiconductor device 100-2 according to an embodiment of the present disclosure, Fig. Figure 15 is a top view showing the power semiconductor device 100-2 along line II-II of Fig. 14 shows, Fig. Figure 16 is a cross-sectional view showing the power semiconductor device 100-2 along line III-III of Fig. 15 shows, Fig. Figure 17 is a cross-sectional view showing the power semiconductor device 100-2 along line IV-IV of Fig. 15 shows, and Fig. Figure 18 is a cross-sectional view showing the power semiconductor device 100-2 along line VV of Fig. 15 shows, and Fig. Figure 19 is a top view showing the power semiconductor device 100-2 along line VI-VI of Fig. 14 shows.

[0135] As in the Fig. As shown in Figures 14 to 19, the power semiconductor device 100-2 can contain at least the semiconductor layer 105, the gate insulating layer 118, and the gate electrode layer 120. For example, the power semiconductor device 100-2 can have a power MOSFET structure.

[0136] Semiconductor layer 105 can refer to a single semiconductor material layer or a plurality of semiconductor material layers, for example, an epitaxial layer or a plurality of epitaxial layers. Furthermore, semiconductor layer 105 can refer to one or more epitaxial layers on a semiconductor substrate.

[0137] Semiconductor layer 105 can, for example, be made of silicon carbide (SiC). More precisely, semiconductor layer 105 can contain at least one epitaxial layer of silicon carbide.

[0138] Silicon carbide (SiC) can have a wider band gap than silicon and therefore remains stable at high temperatures compared to silicon. Since the electrical breakdown field of silicon carbide is much higher than that of silicon, silicon carbide can operate stably even at high temperatures. Accordingly, the power semiconductor device 100-2, which uses silicon carbide as the semiconductor layer 105, can exhibit a high breakdown voltage compared to silicon and offers excellent heat dissipation characteristics and stable operation at high temperatures.

[0139] Specifically, the semiconductor layer 105 can comprise the multitude of well areas 110, the multitude of source areas 112 and the drift area 107.

[0140] The drift region 107 can exhibit the first conductivity type and can be formed by implanting first conductivity-type impurities into a portion of the semiconductor layer 105. For example, the drift region 107 can be formed by doping first conductivity-type impurities into an epitaxial layer of silicon carbide. The drift region 107 can form a vertical transport pathway for charges.

[0141] The basin regions 110 can be formed in the semiconductor layer 105 and exhibit the second conductivity type. For example, the basin regions 110 in the semiconductor layer 105 can be configured to be in contact with at least one section of the drift region 107. In some embodiments, the basin regions 110 can be formed by doping impurities of the second conductivity type, which is opposite to the first conductivity type, in the semiconductor layer 105 or the drift region 107.

[0142] The source regions 112 can be formed in the semiconductor layer 105 on the well regions 110 and can exhibit the first conductivity type. For example, the source regions 112 can be formed by doping impurities of the first conductivity type in the semiconductor layer 105 or the well region 110. The concentration of the impurities of the first conductivity type with which the source region 112 is doped can be higher than the concentration in the drift region 107.

[0143] The multitude of basin contact areas 114 can be formed in the source areas 112 and on the basin areas 110. For example, the multitude of basin contact areas 114 on the basin areas 110 can be formed such that they are connected to the basin areas 110 via the source areas 112. The basin contact areas 114 can be formed such that they exhibit the second conductivity type.

[0144] The trough contact areas 114 can be connected to the source electrode layer 140 and can be doped with impurities of the second conductivity type at a higher concentration than the trough areas 110 to reduce contact resistance when connected to the source electrode layer 140.

[0145] In some embodiments, the trough contact areas 114 can be formed in a recessed groove that is in contact with the trough areas 110. In this case, the source electrode layer 140 can be shaped so that it fills the recessed groove and can be connected to the trough contact area 114.

[0146] Furthermore, the drain region 102 can be formed in the semiconductor layer 105 below the drift region 107 and exhibit the first conductivity type. For example, the drain region 102 can be doped with impurities that have a high concentration compared to the drift region 107.

[0147] In some embodiments, the drain region 102 can be implemented with a silicon carbide substrate of the first conductivity type. In this case, the drain region 102 can be understood as part of the semiconductor layer 105 or as a substrate independent of the semiconductor layer 105. Furthermore, in some embodiments, the drain region 102 can be implemented with a silicon carbide substrate of the first conductivity type, and the drift region 107 can be formed on the drain region 102 using one or more epitaxial layers.

[0148] The well regions 110 in the semiconductor layer 105 can be configured such that two adjacent well regions at least partially touch each other. Furthermore, the well regions 110 can have a shape in which their width increases from the surface of the semiconductor layer 105 towards the interior of the semiconductor layer 105 and then decreases. Specifically, two adjacent well regions of the well regions 110 can touch each other as shown in Fig. 19 shown, touch at a point where at least their width is greatest, and can be spaced apart from each other on the surface of the semiconductor layer 105, as in Fig. 15 shown.

[0149] In some embodiments, the drift region 107 in the semiconductor layer 105 can be configured such that it is connected from the underside of the trough regions 110, via the trough regions 110, to the surface of the semiconductor layer 105. For example, the drift region 107 can include projections 107a that extend between the trough regions 110 to the surface of the semiconductor layer 105.

[0150] The multitude of trenches 116 can be configured such that they extend from the surface of the semiconductor layer 105 to a specific depth within the semiconductor layer 105. For example, the trenches 116 can be configured to connect two adjacent source regions 112 via a point where two adjacent trough regions 110 touch each other. Specifically, each trench 116 can be formed in a line type where a source region 112 is connected to an adjacent source region 112 via a trough region 110 surrounding the source region 112, the projection 107a of the drift region 107, and an adjacent trough region 110.

[0151] For example, the trenches 116 may be shaped to penetrate sections of the source areas 112 and be set back to a certain depth of the trough areas 110 and the projections 107a of the drift area 107. Accordingly, opposite corners (or edges) of the trenches 116 may be surrounded by the trough areas 110.

[0152] Furthermore, the bottom surfaces of the trenches 116 can be completely surrounded by the depression areas 110 in cross-section along one direction of extension of the trenches 116. For example, two adjacent trough areas from the trough areas 110 can be designed such that they touch on the bottom surfaces of the trenches 116 or around their bottom surfaces, so that the bottom surfaces of the trenches 116 can be surrounded by the trough areas 110 at least along one line in the direction of extension.

[0153] The gate insulating layer 118 can be formed on the inner walls of the grooves 116 and at least a part of the semiconductor layer 105. For example, the gate insulating layer 118 can be formed on the inner walls of the grooves 116 and the surface of the semiconductor layer 105.

[0154] The gate insulating layer 118 can, for example, contain an insulating material such as silicon oxide, silicon carbide oxide, silicon nitride, hafnium oxide, zirconium oxide or aluminum oxide, or a stacked structure thereof.

[0155] The gate electrode layer 120 can be formed on the gate insulating layer 118. The gate electrode layer 120 can, for example, comprise the first section 120a, which encloses the trenches 116, and the second section 120b on the surface of the semiconductor layer 105. For example, the first section 120a of the gate electrode layer 120 can have a trench-type gate structure, and the second section 120b can have a planar-type gate structure. Accordingly, the gate electrode layer 120 can have a hybrid structure, incorporating both the trench-type gate structure and the planar-type gate structure.

[0156] For example, the second section 120b of the gate electrode layer 120 can be formed on the projections 107a of the drift region 107 and the source regions 112. Specifically, the second section 120b of the gate electrode layer 120 can be formed on 1) the projections 107a of the drift region 107 that are exposed on the surface of the semiconductor layer 105, and 2) surfaces of sections of the peripheries of the source regions 112. The trough contact regions 114 and the remaining sections of the source regions 112 can be located on the outside of the gate electrode layer 120 and exposed by the gate electrode layer 120.

[0157] The lower corner regions of the first section 120a of the gate electrode layer 120 can be surrounded by the trough regions 110. Furthermore, viewed from the cross-section of the first section 120a taken along one of its extension directions, a floor surface of the first section 120a can be entirely surrounded by the trough regions 110. For example, sections of the trough regions 110 surrounding the floor surface of the first section 120a can be thinnest at a central section of the floor surface of the first section 120a and gradually become thicker as they move towards a corner section therefrom.

[0158] An example where two adjacent basin areas 110 touch in the center of the floor surface of the trench 116 is shown in Fig. Figure 16 shows that the two adjacent basin areas 110 can overlap further around the center of the base of the trench 116. In this case, the basin areas 110 can be in Fig. 18 further below the bottom surface of trench 116.

[0159] The gate electrode layer 120 can, for example, contain a suitable conductive material such as polysilicon, metal, metal nitride or metal silicide, or a layer structure thereof.

[0160] An insulating intermediate layer 130 can be formed on the gate electrode layer 120. The insulating intermediate layer 130 can, for example, contain a suitable insulating material such as an oxide layer or a nitride layer, or a stacked structure thereof.

[0161] The source electrode layer 140 can be formed on the insulating intermediate layer 130. Furthermore, the source electrode layer 140 can be connected to the source regions 112 and the well contact regions 114. For example, the source electrode layer 140 can be connected to the source region 112 and the well contact region 114 via a section exposed by the gate electrode layer 120, and it can be arranged to extend further onto the gate electrode layer 120. The source electrode layer 140 can, for example, consist of a suitable conductive material, metal, or the like.

[0162] As in Fig. As shown in Figure 17, at least the edge sections of the source areas 112 on the trough areas 110 can be exposed. Thus, the edge sections of the source areas 112 can be in contact with the projection of the drift area 107.

[0163] The first channel region C1 can be restricted to the semiconductor layer 105 along the trench 116, which corresponds to the first section 120a of the gate electrode layer 120. For example, the first channel region C1 in the semiconductor layer 105 along the trench 116 can be configured to be connected to the source regions 112 and the drift region 107.

[0164] Specifically, the first channel region C1 in the semiconductor layer 105 can be formed along the side walls of the trench 116 to connect the drift region 107 located below the trench 116 or on a side face of the trench 116, e.g., the projection 107a of the drift region 107, and the source regions 112 contacting the trench 116. Accordingly, the first channel region C1 can have a trench-like channel structure.

[0165] For example, the first channel region C1 can have the second conductivity type, thus forming an inversion channel. Since the first channel region C1 has a doping type opposite to that of the source region 112 and the drift region 107, the first channel region C1 can form a diode junction with the source region 112 and the drift region 107.

[0166] Accordingly, the first channel region C1 cannot normally allow charge movement; however, if an operating voltage is applied to the gate electrode layer 120, an inversion channel can be formed in it, so that the movement of charges is allowed.

[0167] In some embodiments, the first channel region C1 can correspond to sections of the basin regions 110. More precisely, the first channel region C1 can correspond to sections of the basin regions 110 that adjoin a lower surface of the first section 120a of the gate electrode layer 120.

[0168] In this case, the first channel region C1 can be formed integrally with the well regions 110 or be continuously connected to them. The doping concentration of the impurities of the second conductivity type in the first channel region C1 can be the same as that of the rest of the well region 110 or differ from it for the purpose of setting a threshold voltage.

[0169] The second channel region C2a can be confined to semiconductor layer 105 below the second section 120b of the gate electrode layer 120. The second channel region C2a can be formed in semiconductor layer 105 between drift region 107 and source region 112. For example, the second channel region C2a can be formed in semiconductor layer 105 between the projection 107a of drift region 107 and the first source region 112a. Accordingly, the second channel region C2a can have a planar channel structure.

[0170] The second channel region C2a can have the first conductivity type, thus forming an accumulation channel. The second channel region C2a can be in contact with the source regions 112. For example, the second channel region C2a can have the same doping type as the source region 112 and the drift region 107. In this case, the source region 112, the second channel region C2a, and the drift region 107 can typically be electrically connected in their structure.

[0171] However, a potential barrier is formed in the structure of the silicon carbide semiconductor layer 105, while a band of the second channel region C2a is bent upwards due to the influence of negative charges generated by the formation of carbon clusters in the gate insulating layer 118. In this way, an accumulation channel can be formed, which allows a charge or current flow in the second channel region C2a when an operating voltage is applied to the gate electrode layer 120.

[0172] Accordingly, a threshold voltage that must be applied to the gate electrode layer 120 to form the accumulation channel in the second channel region C2a can be considerably lower than a threshold voltage that must be applied to the gate electrode layer 120 to form a normal inversion channel.

[0173] In some embodiments, the second channel region C2a can be a section of the drift region 107. More precisely, the second channel region C2a can be a section of the projection 107a of the drift region 107. For example, the second channel region C2a can be formed integrally with the drift region 107. Thus, the source regions 112 can be in direct contact with the drift region 107, for example, the projection 107a, and the second channel region C2a can be limited to a portion of the drift region 107 where the direct contact is established.

[0174] For example, the doping concentration of the impurities of the first conductivity type of the second channel region C2a may be the same as that of the remaining part of the drift region 107 or may differ from it for the purpose of setting a threshold voltage.

[0175] In some embodiments, the basin region 110 beneath the source regions 112 can be configured to project further than the source regions 112 in the direction of the projection 107a of the drift region 107. In this case, the second channel region C2a in the semiconductor layer 105 can be formed on the projecting portion of the basin region 110. For example, the projection 107a of the drift region 107 can extend further to a groove section between the basin region 110 and the gate electrode layer 120, and the second channel region C2a can be formed on this projecting section. The above structure can allow the second channel region C2a to be bounded between the second section 120b of the gate electrode layer 120 and the basin region 110.

[0176] In some embodiments, the distances between three adjacent basin regions 110 below the basin regions 110 can be equal. Furthermore, the distances between three adjacent source regions 112 of the source regions 112 can be equal. For example, the centers of three adjacent basin regions 110 can each be located at the vertices of a regular triangle, and the centers of three adjacent source regions 112 on the three basin regions 110 can also each be located at the vertices of the same regular triangle. For example, the basin regions 110 and the source regions 112 can be understood to represent three triangles that are in Fig. 15 are arranged.

[0177] In some embodiments, the centers of seven adjacent basin regions 110 can each be arranged at a center and at vertices of a regular hexagon. Furthermore, the centers of seven source regions 112, located on the seven adjacent source regions 110, can each be arranged at a center and at vertices of the regular hexagon. For example, the Fig. to be understood as showing the 7 tub areas 110 and 7 source areas 112 described above.

[0178] In this structure, the basin areas 110 and the source areas 112 can be arranged to resemble a planar arrangement structure within a hexagonal, closed-packed arrangement structure. Furthermore, the distance between two adjacent basin areas 110 can be uniform, and the distance between two adjacent source areas 112 can also be uniform.

[0179] In this structure, the trenches 116 can be arranged to form sections of lines, each connecting two adjacent lines from the center and the vertices of the regular hexagon, thus connecting seven adjacent source areas 112. Specifically, the trenches 116 can be arranged in Fig. 2 comprise six lines connecting six source areas 112 arranged at the vertices with a source area 112 arranged in the center of the regular hexagon, and six lines connecting two adjacent source areas from the six source areas 112 arranged at the vertices.

[0180] In some embodiments, the well region 110 can be a section of a spherical shape, and a cross-section of the well region 110 can be circular. Furthermore, the well contact region 114 can be circular in a top view. For example, the circular well contact region 114 can be formed within the circular well region 110 in a top view. The lower surfaces of the well contact regions 114 can be connected to the well regions 110. In a top view, the source region 112 can be shaped like a donut, surrounding the well contact region 114. The above shape, viewed from above the surface of the semiconductor layer 105, can extend to a certain depth from the surface of the semiconductor layer 105.

[0181] In some embodiments, the first channel area C1 can be connected to the drift area 107 below the corresponding sections if the thickness of sections of the trough areas 110 below the bottom surface of the trench 116, e.g. the thickness of the trough areas 110 around the center of the bottom surface of the trench 116, is equal to or thinner than that of the first channel area C1.

[0182] Another example: If the thickness of the trough areas 110 below the bottom surface of the trench 116 is greater overall than that of the first channel area C1, connecting the first channel area C1 to the drift area 107 below the trench 116 is difficult. However, if the trough areas 110 are spherical because at least the side surfaces of the trenches 116 are exposed by the trough areas 110 and surrounded by the projection 107a of the drift area 107, the first channel area C1 can be connected to the source areas 112 by the projection 107a of the drift area 107 at the side surfaces of the trenches 116 or at the side wall of the first section 120a of the gate electrode layer 120.

[0183] In the power semiconductor device 100-2 described above, the first conductivity type and the second conductivity type can be opposite to each other, and each of the first and second conductivity types can be either n-type or p-type. For example, if the first conductivity type is n-type, the second conductivity type is p-type, and vice versa.

[0184] If the power semiconductor device 100-2 is an N-type MOSFET, the drift region 107 and the second channel region C2a can be N- regions, the source region 112 and the drain region 102 can be N+ regions, the well region 110 and the first channel region C1 can be P- regions, and the well contact region 114 can be a P+ region.

[0185] According to the power semiconductor device 100-2, the depth of the basin areas 110 can be greater than that of the trenches 116 and the gate electrode layer 120. Thus, a trench bottom corner of the first section 120a of the gate electrode layer 120 can be surrounded by the basin area 110. Furthermore, the entire bottom surface of the first section 120a can be surrounded by the basin areas 110; this structure can reduce the concentration of the electric field at the trench bottom corners in the trench-gate structure by the charge build-up between the basin areas 110.

[0186] In the operation of the power semiconductor device 100-2, a current can generally flow in a vertical direction from the drain region 102 along the drift region 107 and then through the first channel region C1 and the second channel region C2a to the source region 112.

[0187] The 100-2 power semiconductor device can feature a hybrid structure incorporating both trench-gate and planar-gate structures. Furthermore, by utilizing both trench-type inversion channels and planar-type accumulation channels, the 100-2 power semiconductor device can increase current density and reduce threshold voltage.

[0188] Furthermore, the 100-2 power semiconductor device can have a regular hexagonal structure and, through the combination of trench-type and planar-type gate structures, achieve a high degree of integration with a high channel density. Moreover, compared to a planar-type structure alone, the 100-2 power semiconductor device can maintain the degree of integration and improve channel mobility by adding the trench structure.

[0189] Fig. Figure 20 is a cross-sectional view showing a power semiconductor device 100a-2 according to another embodiment of the present disclosure.

[0190] In Fig. Figure 20 shows the power semiconductor device 100a-2 as part of a structure in which a multitude of power semiconductor devices 100-2 (see Fig. 14 to 19) are arranged.

[0191] Since the hexagonal structure with closed packing is repeated, the 100a-2 power semiconductor device can exhibit a high degree of integration.

[0192] Fig. Figure 21 is a cross-sectional view showing a power semiconductor device 100b-2 according to another embodiment of the present disclosure. The power semiconductor device 100b-2 can be formed by modifying a partial configuration of the power semiconductor device 100-2 or 100a-2 from the Fig. 14 to 20 can be realized, and therefore an additional description is omitted to avoid redundancy, as they can refer to each other.

[0193] Referring to Fig. 21 In the power semiconductor device 100b-2, the source regions 112 and counter-doping regions 112a can be formed by doping impurities of the first conductivity type in the trough regions 110 at sections where the source regions 112 and the drift region 107 touch each other.

[0194] In this embodiment, the counter-doping regions 112a can be separated and formed from the remaining sections of the source regions 112. The doping concentration of the impurities in the counter-doping regions 112a can be the same or different from that in the remaining sections of the source regions 112. In some embodiments, the doping concentration of the impurities in the counter-doping regions 112a can be lower than that of the remaining sections of the source regions 112 or higher than that of the drift region 107.

[0195] Fig. Figure 22 is a perspective view showing a power semiconductor device 100c-2 according to another embodiment of the present disclosure. The power semiconductor device 100c-2 can be modified by altering a partial configuration of the power semiconductor device 100-2, 100a-2 or 100b-2 of the Fig. 14 to 21 can be realized, and therefore an additional description is omitted to avoid redundancy, as they can refer to each other.

[0196] Referring to Fig. 22 In the power semiconductor device 100c-2, the well regions 110 in the semiconductor layer 105 can be configured such that they are spaced apart from one another. In this case, a central part of the bottom of the first section 120a of the gate electrode layer 120 can be exposed to the well regions 110, but at least opposite lower corners thereof can be surrounded by the well regions 110.

[0197] As opposed to Fig. In this embodiment, since the trough areas 110 are spaced apart from each other, a central part of the bottom of the trench 116 can be in contact with the drift area 107.

[0198] Fig. Figures 23 to 25 and 27 are cross-sectional views illustrating a method for manufacturing the power semiconductor device 100-2 according to an embodiment of the present disclosure, and Fig. 26 is a top view of Fig. 25.

[0199] Referring to Fig. 23 The drift region 107 can be formed with the first conductivity type in the silicon carbide (SiC) semiconductor layer 105, thus providing a vertical transport path for charges. For example, the drift region 107 can be formed on the drain region 102 with the first conductivity type. In some embodiments, the drain region 102 can be realized with a substrate of the first conductivity type, and the drift region 107 can be formed on the substrate with one or more epitaxial layers.

[0200] Subsequently, the trough regions 110 of the second conductivity type in the semiconductor layer 105 can be formed such that they are in contact with the drift region 107. For example, the trough regions 110 can be formed such that two adjacent trough regions are at least partially in contact with each other. Furthermore, the formation of the trough regions 110 can include the implantation of impurities of the second conductivity type into the semiconductor layer 105. The trough regions 110 can be formed to a specific depth substantially from the surface of the semiconductor layer 105.

[0201] For example, the well regions 110 in the semiconductor layer 105 can be configured such that the drift region 107 contains the projections 107a, which are at least partially surrounded by the well regions 110. Specifically, the well regions 110 can be formed in the drift region 107 by doping impurities of a conductivity opposite to that of the drift region 107.

[0202] The source regions 112 with the first conductivity type can be formed in the well regions 110 or in the semiconductor layer 105 on the well regions 110. For example, the source regions 112 can be formed by implanting impurities of the first conductivity type into the well regions 110 and the drift region 107. The source regions 112 can be formed in the well regions 110 to a certain depth essentially from the surface of the semiconductor layer 105.

[0203] Furthermore, the trough contact areas 114 with the second conductivity type can be formed in the source areas 112 or on the trough areas 110. For example, the trough contact areas 114 can be formed by implanting impurities of the second conductivity type into the trough areas 110 or into the source areas 112 in high concentration. The trough contact areas 114 can, for example, be shaped so that they have a circular shape in plan view.

[0204] In some embodiments, the basin areas 110 can be designed to be in contact with the drift area 107, so that the drift area 107 is connected from the underside of the basin areas 110 through between the basin areas 110 to the surface of the semiconductor layer 105.

[0205] In a modified example of this embodiment, the order in which the trough areas 110, the trough contact areas 114 and the source areas 112 are doped with impurities can be changed arbitrarily.

[0206] In the above manufacturing process, impurity implantation or doping can be carried out in such a way that the impurities are mixed when the impurities are implanted into semiconductor layer 105 or when an epitaxial layer is formed. However, the ion implantation method using a mask pattern can be used to implant impurities into a selective area.

[0207] Optionally, a heat treatment process can be carried out after ion implantation to activate or diffuse the impurities.

[0208] With reference to Fig. 24 The multitude of trenches 116 can be designed such that they extend from the surface of the semiconductor layer 105 to a certain depth in the semiconductor layer 105.

[0209] For example, the trenches 116 can be designed to penetrate sections of the source regions 112 and extend to a certain depth of the trough regions 110 and the projections 107a of the drift region 107. More precisely, the trenches 116 can be designed to extend from the surface of the semiconductor layer 105 into the semiconductor layer 105 in order to connect two adjacent source regions from the source regions 112 via a point where the two adjacent trough regions touch each other.

[0210] The trenches 116 can be formed, for example, by creating a photomask using photolithography and subsequently etching the semiconductor layer 105 using the photomask as an etch protection layer.

[0211] As in the Fig. As shown, the gate insulating layer 118 can be formed on the inner walls of the grooves 116 and the surface of the semiconductor layer 105. The gate insulating layer 118 can be formed, for example, by oxidizing the semiconductor layer 105 to form an oxide or by applying an insulating material such as oxide or nitride to the semiconductor layer 105.

[0212] Subsequently, the gate electrode layer 120, comprising the first part 120a, which encloses the trenches 116, and the second part 120b on the surface of the semiconductor layer 105, can be formed on the gate insulating layer 118. The gate electrode layer 120 can be formed, for example, by forming a conductive layer on the gate insulating layer 118 and subsequently structuring the conductive layer. The gate electrode layer 120 can be formed by doping impurities into polysilicon or by containing a conductive metal or metal silicide.

[0213] A pattern formation process can be carried out using photolithography and etching. The photolithography process can include a process for creating a photoresist pattern as a mask layer using a photographic process and a development process, and the etching process can include a process for selectively etching an underlying structure using the photoresist pattern.

[0214] As in Fig. As shown in Figure 27, the insulating intermediate layer 130 can be formed on the gate electrode layer 120.

[0215] Subsequently, the source electrode layer 140 can be formed on the insulating intermediate layer 130. Furthermore, the source electrode layer 140 can be configured to connect with the source regions 112 and the trough contact regions 114. The source electrode layer 140 can be formed, for example, by depositing a conductive layer, such as a metal layer, onto the insulating intermediate layer 130 and structuring the conductive layer.

[0216] The MOSFET structure with the hexagonal, closed packed arrangement in the semiconductor layer 105 can be manufactured economically using the manufacturing process described above.

[0217] The manufacturing process described above can be applied without modification to the power semiconductor devices 100a-2, 100b-2 and 100c-2 of the Fig. 20 to 22 are applied.

[0218] Fig. Figure 28 is a schematic perspective view showing a power semiconductor device 100-3 according to an embodiment of the present disclosure, Fig. Figure 29 is a top view showing the power semiconductor device 100-3 along line II-II of Fig. 28 shows, Fig. Figure 30 is a cross-sectional view showing the power semiconductor device 100-3 along line III-III of Fig. 29, Fig. Figure 31 is a cross-sectional view showing the power semiconductor device 100-3 along line IV-IV of Fig. 29 shows, and Fig. Figure 32 is a cross-sectional view showing the power semiconductor device 100-3 along line VV of Fig. 29 shows, and Fig. Figure 33 is a top view showing the power semiconductor device 100-3 along line VI-VI of Fig. 28 shows.

[0219] With reference to the Fig. 28 to 33, the power semiconductor device 100-3 can contain at least the semiconductor layer 105, the gate insulating layer 118, and the gate electrode layer 120. For example, the power semiconductor device 100-3 can have a power MOSFET structure.

[0220] Semiconductor layer 105 can refer to a single semiconductor material layer or a plurality of semiconductor material layers, for example, an epitaxial layer or a plurality of epitaxial layers. Furthermore, semiconductor layer 105 can refer to one or more epitaxial layers on a semiconductor substrate.

[0221] Semiconductor layer 105 can, for example, consist of silicon carbide (SiC). More precisely, semiconductor layer 105 can contain at least one epitaxial layer of silicon carbide.

[0222] Silicon carbide (SiC) can have a wider band gap than silicon and therefore remains stable at high temperatures compared to silicon. Since the electrical breakdown field of silicon carbide is much higher than that of silicon, silicon carbide can also operate stably at high temperatures. Accordingly, the power semiconductor device 100-3, which uses silicon carbide as the semiconductor layer 105, can exhibit a high breakdown voltage compared to silicon and offers excellent heat dissipation characteristics and stable operation at high temperatures.

[0223] Specifically, the semiconductor layer 105 can comprise the multitude of well regions 110, the multitude of source regions 112 and the drift region 107.

[0224] The drift region 107 can exhibit the first conductivity type and can be formed by implanting first conductivity-type impurities into a portion of the semiconductor layer 105. For example, the drift region 107 can be formed by doping first conductivity-type impurities into an epitaxial layer of silicon carbide. The drift region 107 can form a vertical transport pathway for charges.

[0225] The basin regions 110 can be formed in the semiconductor layer 105 and exhibit the second conductivity type. For example, the basin regions 110 in the semiconductor layer 105 can be configured to be in contact with at least a portion of the drift region 107. In some embodiments, the basin regions 110 can be formed by doping impurities of the second conductivity type, which is opposite to the first conductivity type, in the semiconductor layer 105 or the drift region 107.

[0226] The source regions 112 can be formed in the semiconductor layer 105 on the well regions 110 and can exhibit the first conductivity type. For example, the source regions 112 can be formed by doping impurities of the first conductivity type in the semiconductor layer 105 or the well region 110. The concentration of the impurities of the first conductivity type with which the source region 112 is doped can be higher than the concentration in the drift region 107.

[0227] Several well contact areas 114 can be formed in the source areas 112 and on the well areas 110. For example, the majority of the well contact areas 114 on the well areas 110 can be configured such that they are connected to the well areas 110 via the source areas 112. The well contact areas 114 can be configured to exhibit the second conductivity type.

[0228] The basin contact areas 114 can be connected to a source electrode layer 140 and can be doped with impurities of the second conductivity type at a higher concentration than the basin areas 110 to reduce contact resistance when connected to the source electrode layer 140.

[0229] In some embodiments, the recess contact areas 114 can be formed in a recess groove that is in contact with the recess areas 110. In this case, the source electrode layer 140 can be shaped so that it fills the recess groove and can be connected to the recess contact area 114.

[0230] Furthermore, the drain region 102 can be formed in the semiconductor layer 105 below the drift region 107 and exhibit the first conductivity type. For example, the drain region 102 can be doped with impurities that have a high concentration compared to the drift region 107.

[0231] In some embodiments, the drain region 102 can be implemented with a silicon carbide substrate of the first conductivity type. In this case, the drain region 102 can be understood as part of the semiconductor layer 105 or as a substrate independent of the semiconductor layer 105. Furthermore, in some embodiments, the drain region 102 can be implemented with a silicon carbide substrate of the first conductivity type, and the drift region 107 can be formed on the drain region 102 using one or more epitaxial layers.

[0232] In some embodiments, the basin regions 110 in the semiconductor layer 105 can be configured such that two adjacent basin regions at least partially touch each other. Furthermore, the basin regions 110 can have a shape in which their width increases from the surface of the semiconductor layer 105 towards the interior of the semiconductor layer 105 and then decreases. Specifically, two adjacent basin regions of the basin regions 110 can touch each other, as shown in Fig. 33 shown, touch at a point where at least one of their widths is greatest, and can be spaced apart from each other on the surface of the semiconductor layer 105, as shown in Fig. 29 shown.

[0233] In some embodiments, the drift region 107 in the semiconductor layer 105 can be configured such that it is connected from the underside of the trough regions 110, via the trough regions 110, to the surface of the semiconductor layer 105. For example, the drift region 107 can include projections 107a that extend between the trough regions 110 to the surface of the semiconductor layer 105.

[0234] The majority of the trenches 116 can be configured to extend from the surface of the semiconductor layer 105 to a certain depth within the semiconductor layer 105. For example, the trenches 116 can be configured to connect two adjacent source regions from the source regions 112 via a point where two adjacent well regions from the well regions 110 touch each other. Specifically, each trench 116 can be formed in a line type where a source region 112 is connected to an adjacent source region 112 via a well region 110 surrounding the source region 112, the projection 107a of the drift region 107, and an adjacent well region 110.

[0235] For example, the trenches 116 can be shaped such that they penetrate parts of the source regions 112 and are set back to a certain depth from the well regions 110 and the projections 107a of the drift region 107. Accordingly, opposite corners (or edges) of the trenches 116 can be surrounded by the well regions 110. Furthermore, the bottom surfaces of the trenches 116 can be completely surrounded by the borehole regions 110 in cross-section along a direction of extension of the trenches 116. For example, two adjacent well regions from the well regions 110 can be configured such that they touch on or around the bottom surfaces of the trenches 116, so that the bottom surfaces of the trenches 116 can be surrounded by the well regions 110 at least along a line in the direction of extension.

[0236] The gate insulating layer 118 can be formed on the inner walls of the grooves 116 and at least a part of the semiconductor layer 105. For example, the gate insulating layer 118 can be formed on the inner walls of the grooves 116 and the surface of the semiconductor layer 105.

[0237] The gate insulating layer 118 can, for example, contain an insulating material such as silicon oxide, silicon carbide oxide, silicon nitride, hafnium oxide, zirconium oxide or aluminum oxide, or a layer structure made up of these.

[0238] The gate electrode layer 120 can be formed on the gate insulating layer 118. The gate electrode layer 120 can, for example, comprise the first section 120a, which encloses the trenches 116, and the second section 120b on the surface of the semiconductor layer 105. For example, the first section 120a of the gate electrode layer 120 can have a trench-type gate structure, and the second section 120b can have a planar-type gate structure. Accordingly, the gate electrode layer 120 can have a hybrid structure, incorporating both the trench-type gate structure and the planar-type gate structure.

[0239] For example, the second section 120b of the gate electrode layer 120 can be formed on the projections 107a of the drift region 107 and the well regions 110. Specifically, the second section 120b of the gate electrode layer 120 can be formed on 1) the projections 107a of the drift region 107 that are exposed on the surface of the semiconductor layer 105, 2) surfaces of the well regions 112, and 3) surfaces of parts of the periphery of the source regions 112. The well contact regions 114 and the remaining parts of the source regions 112 can be located on the outside of the gate electrode layer 120 and exposed from the gate electrode layer 120.

[0240] The lower corner regions of the first section 120a of the gate electrode layer 120 can be surrounded by the trough regions 110. Furthermore, viewed from the cross-section of the first section 120a taken along one of its extension directions, a bottom surface of the first section 120a can be entirely surrounded by the trough regions 110. For example, sections of the trough regions 110 surrounding the bottom surface of the first section 120a can be thinnest at a central section of the bottom surface of the first section 120a and gradually become thicker as they move towards a corner section.

[0241] An example where two adjacent borehole areas 110 touch in the middle of the bottom surface of the trench 116 is shown in Fig. Figure 30 shows that the two adjacent borehole areas 110 may overlap further around the center of the trench floor 116. In this case, in Fig. 32, the well areas 110 can be arranged further below the bottom surface of the trench 116.

[0242] The gate electrode layer 120 can, for example, contain a suitable conductive material such as polysilicon, metal, metal nitride or metal silicide, or a stacked structure thereof.

[0243] An insulating intermediate layer 130 can be formed on the gate electrode layer 120. The insulating intermediate layer 130 can, for example, contain a suitable insulating material such as an oxide layer or a nitride layer, or a stacked structure thereof.

[0244] The source electrode layer 140 can be formed on the insulating intermediate layer 130. Furthermore, the source electrode layer 140 can be connected to the source regions 112 and the well contact regions 114. For example, the source electrode layer 140 can be connected to the source region 112 and the well contact region 114 via a portion exposed by the gate electrode layer 120, and it can be arranged to extend further onto the gate electrode layer 120. The source electrode layer 140 can be made of, for example, a suitable conductive material, metal, or the like.

[0245] A first channel region C1 can be formed in the semiconductor layer 105 along the trench 116, corresponding to the first section 120a of the gate electrode layer 120, to connect with the source regions 112 and the drift region 107. For example, the first channel region C1 can be formed in the semiconductor layer 105 along the side walls of the trench 116 to connect the drift region 107 below the trench 116 or on a side face of the trench 116, for example, the projection 107a of the drift region 107, and the source regions 112 touching the trench 116. Accordingly, the first channel region C1 can have a trench-like channel structure.

[0246] A second channel region C2 can be formed in the semiconductor layer 105 below the second section 120b of the gate electrode layer 120, so that it is in contact with the source regions 112. For example, the second channel region C2 can be formed on the semiconductor layer 105 between the projection 107a of the drift region 107 and the source regions 112. The second channel region C2 can be configured to cover the surfaces of the trough regions 110. Accordingly, the second channel region C2 can have a planar channel structure.

[0247] For example, the first channel region C1 and the second channel region C2 can have the second conductivity type, thus forming an inversion channel. Since the first channel region C1 and the second channel region C2 have a doping type opposite to that of the source region 112 and the drift region 107, the first channel region C1 and the second channel region C2 can form a diode junction with the source region 112 and the drift region 107.

[0248] Accordingly, the first channel region C1 and the second channel region C2 cannot allow charge movement in a normal situation; however, if an operating voltage is applied to the gate electrode layer 120, the inversion channel can be formed in it in such a way that the movement of charges is allowed.

[0249] For example, the first channel region C1 and the second channel region C2 can be parts of the basin regions 110. Specifically, the first channel region C1 can be parts of the basin regions 110 that adjoin a lower surface of the first section 120a of the gate electrode layer 120, and the second channel region C2 can be parts of the basin regions 110 that adjoin a lower surface of the second section 120b of the gate electrode layer 120.

[0250] In this case, the first channel region C1 and the second channel region C2 can be formed integrally with the basin regions 110 or continuously connected to the basin regions 110. The doping concentration of the second conductivity type impurities in the first channel region C1 and the second channel region C2 can be the same as that of the remaining section of the basin region 110, or it can differ from it for the purpose of setting a threshold voltage.

[0251] In some embodiments, the distances between three adjacent source regions 110 below the source regions 110 can be equal. Furthermore, the distances between three adjacent source regions 112 of the source regions 112 can be equal. For example, the centers of three adjacent well regions 110 can each be located at the vertices of a regular triangle, and the centers of three adjacent source regions 112 above the three well regions 110 can also each be located at the vertices of the same regular triangle. For example, the depression regions 110 and the source regions 112 can be understood as designating three triangles that are in Fig. 29 are arranged.

[0252] In some embodiments, the centers of seven adjacent basin regions 110 can each be arranged at the center and at the vertices of a regular hexagon. Furthermore, the centers of seven source regions 112, located on the seven adjacent basin regions 110, can each be arranged at the center and at the vertices of the regular hexagon. For example, Fig. 28 to 32 can be understood as showing the 7 tub areas 110 and 7 source areas 112 described above.

[0253] In this structure, the trough areas 110 and the source areas 112 can be arranged to resemble a planar arrangement within a hexagonal, closed-packed arrangement. Furthermore, the distance between two adjacent trough areas 110 can be uniform, and the distance between two adjacent source areas 112 can also be uniform.

[0254] In this structure, the trenches 116 can be arranged such that they form sections of lines, each connecting two adjacent lines from the center and vertices of the regular hexagon, so that seven adjacent source areas 112 are connected. Specifically, the trenches 116 can be arranged in Fig. 29 comprise six lines connecting six source areas 112 arranged at the vertices with one source area 112 arranged in the center of the regular hexagon, and 6 lines connecting two adjacent source areas from the 6 source areas 112 arranged at the vertices.

[0255] In some embodiments, the well region 110 can be a section of a spherical shape, and a cross-section of the well region 110 can be circular. Furthermore, the well contact region 114 can be circular in a top view. For example, the circular well contact region 114 can be formed within the circular well region 110 in a top view. The lower surfaces of the well contact regions 114 can be connected to the well regions 110. In a top view, the source region 112 can be shaped like a donut, surrounding the well contact region 114. The above shape, viewed from above the surface of the semiconductor layer 105, can extend to a certain depth from the surface of the semiconductor layer 105.

[0256] In some embodiments, the first channel area C1 can be connected to the drift area 107 below the corresponding sections if the thickness of sections of the trough areas 110 below the bottom surface of the trench 116, e.g. the thickness of the trough areas 110 around the center of the bottom surface of the trench 116, is equal to or thinner than that of the first channel area C1.

[0257] Another example: If the thickness of the trough areas 110 below the bottom surface of the trench 116 is greater overall than that of the first channel area C1, connecting the first channel area C1 to the drift area 107 below the trench 116 is difficult. However, if the trough areas 110 are spherical because at least the side surfaces of the trenches 116 are exposed by the trough areas 110 and surrounded by the projection 107a of the drift area 107, the first channel area C1 can be connected to the source areas 112 by the projection 107a of the drift area 107 on the side surfaces of the trenches 116 or on the side wall of the first section 120a of the gate electrode layer 120.

[0258] In the power semiconductor device 100-3 described above, the first conductivity type and the second conductivity type can be opposite to each other, and each of the first and second conductivity types can be either n-type or p-type. For example, if the first conductivity type is n-type, the second conductivity type is p-type, and vice versa.

[0259] If the power semiconductor device 100-3 is an N-type MOSFET, the drift area 107 can be an N- area, the source area 112 and the drain area 102 can be N+ areas, the well area 110, the first channel area C1 and the second channel area C2 can be P- areas, and the well contact area 114 can be a P+ area.

[0260] According to the power semiconductor device 100-3, the depth of the basin areas 110 can be greater than that of the trenches 116 and the gate electrode layer 120. Thus, a trench bottom corner of the first section 120a of the gate electrode layer 120 can be surrounded by the basin area 110. Furthermore, the entire bottom surface of the first section 120a can be surrounded by the basin areas 110; this structure can reduce the concentration of the electric field on the trench bottom corners in the trench-gate structure.

[0261] In the operation of the power semiconductor device 100-3, a current can generally flow in a vertical direction from the drain region 102 along the drift region 107 and then through the first channel region C1 and the second channel region C2 to the source region 112.

[0262] The 100-3 power semiconductor device can feature a hybrid structure incorporating both trench-type and planar-type gate structures. Furthermore, the 100-3 power semiconductor device can exhibit a regular hexagonal structure, achieving a high degree of integration and high channel density through the combination of trench-gate and planar-gate structures. Moreover, compared to a device using only a planar structure, the 100-3 power semiconductor device can maintain the degree of integration and improve channel mobility by adding the trench structure.

[0263] Fig. Figure 34 is a perspective view showing a power semiconductor device 100a-3 according to another embodiment of the present disclosure.

[0264] Fig. Figure 34 shows the power semiconductor device 100a-3 as part of a structure in which a plurality of power semiconductor devices 100-3 (see Fig. 28 to 33) are arranged.

[0265] Since the hexagonal structure with closed packing is repeated, the 100a-3 power semiconductor device can exhibit a high degree of integration.

[0266] Fig. 35 and Fig. Figure 36 are cross-sectional views showing a power semiconductor device 100b-3 according to another embodiment of the present disclosure. The power semiconductor device 100b-3 can be obtained by modifying a partial configuration of the power semiconductor device 100-3 from the Fig. 28 to 33 can be realized, and therefore an additional description is omitted to avoid redundancy, as they can refer to each other.

[0267] With reference to the Fig. 35 and Fig. 36 In the power semiconductor device 100b-3, a second channel region C2a can be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the second channel region C2a can be formed in the semiconductor layer 105 between the projection 107a of the drift region 107 and the first source region 112a. The second channel region C2a can have the first conductivity type, so that an accumulation channel is formed.

[0268] For example, the second channel region C2a can have the same doping type as the source region 112 and the drift region 107. In this case, the source region 112, the second channel region C2a, and the drift region 107 are normally electrically connected. However, a potential barrier is formed in the structure of the silicon carbide semiconductor layer 105, while a band of the second channel region C2a is bent upwards due to the influence of negative charges generated by the formation of carbon clusters in the gate insulating layer 118. In this way, an accumulation channel can be formed, which allows a charge or current flow in the second channel region C2a when an operating voltage is applied to the gate electrode layer 120.

[0269] Accordingly, a threshold voltage that must be applied to the gate electrode layer 120 to form the accumulation channel in the second channel region C2a can be considerably lower than a threshold voltage that must be applied to the gate electrode layer 120 to form a normal inversion channel.

[0270] In some embodiments, the second channel region C2a can be part of the drift region 107. More precisely, the second channel region C2a can be part of the projection 107a of the drift region 107. For example, the second channel region C2a can be formed integrally with the drift region 107. Thus, in the power semiconductor device 100b-3, the source regions 112 can be in direct contact with the drift region 107, e.g., with the projection 107a, and the second channel region C2a can be limited to a portion of the drift region 107 where the direct contact is established.

[0271] For example, the doping concentration of the impurities of the first conductivity type of the second channel region C2a may be the same as that of the remaining section of the drift region 107 or may differ from it for the purpose of setting a threshold voltage.

[0272] In some embodiments, the basin region 110 beneath the source regions 112 can be configured to project further than the source regions 112 in the direction of the projection 107a of the drift region 107. In this case, the second channel region C2a in the semiconductor layer 105 can be formed on the projecting portion of the basin region 110. For example, the projection 107a of the drift region 107 can extend further to a groove section between the basin region 110 and the gate electrode layer 120, and the second channel region C2a can be formed on this projecting section. The above structure can allow the second channel region C2a to be bounded between the second section 120b of the gate electrode layer 120 and the basin region 110.

[0273] In the power semiconductor device 100b-3, the first channel region C1 can be used as an inversion channel, as in the power semiconductor device 100-3 of Fig. 28 to 33 are planned.

[0274] Fig. Figures 37 to 39 and 41 are cross-sectional views illustrating a method for manufacturing the power semiconductor device 100-3 according to an embodiment of the present disclosure, and Fig. 40 is a top view of Fig. 39.

[0275] With reference to Fig. 37 The drift region 107 can be formed with the first conductivity type in the silicon carbide (SiC) semiconductor layer 105, thus providing a vertical transport path for charges. For example, the drift region 107 can be formed on the drain region 102 with the first conductivity type. In some embodiments, the drain region 102 can be realized with a substrate of the first conductivity type, and the drift region 107 can be formed on the substrate with one or more epitaxial layers.

[0276] Subsequently, the trough regions 110 of the second conductivity type in the semiconductor layer 105 can be formed such that they are in contact with the drift region 107. For example, the trough regions 110 can be formed such that two adjacent trough regions are at least partially in contact with each other. Furthermore, the formation of the trough regions 110 can include the implantation of impurities of the second conductivity type into the semiconductor layer 105. The trough regions 110 can be formed to a specific depth essentially from the surface of the semiconductor layer 105.

[0277] For example, the well regions 110 in the semiconductor layer 105 can be configured such that the drift region 107 contains the projections 107a, which are at least partially surrounded by the well regions 110. Specifically, the well regions 110 can be formed in the drift region 107 by doping impurities of a conductivity opposite to that of the drift region 107.

[0278] The source regions 112 with the first conductivity type can be formed in the well regions 110 or in the semiconductor layer 105 on the well regions 110. For example, the source regions 112 can be formed by implanting impurities of the first conductivity type into the well regions 110 and the drift region 107. The source regions 112 can be formed in the well regions 110 to a certain depth, essentially from the surface of the semiconductor layer 105.

[0279] Furthermore, the trough contact areas 114 with the second conductivity type can be formed in the source areas 112 or on the trough areas 110. For example, the trough contact areas 114 can be formed by implanting impurities of the second conductivity type into the trough areas 110 or into the source areas 112 in high concentration. The trough contact areas 114 can, for example, be shaped so that they have a circular shape in plan view.

[0280] In some embodiments, the basin areas 110 can be designed to be in contact with the drift area 107, so that the drift area 107 is connected from the underside of the basin areas 110 through between the basin areas 110 to the surface of the semiconductor layer 105.

[0281] In a modified example of this embodiment, the order in which the trough areas 110, the trough contact areas 114 and the source areas 112 are doped with impurities can be changed arbitrarily.

[0282] In the above manufacturing process, impurity implantation or doping can be carried out in such a way that the impurities are mixed when the impurities are implanted into semiconductor layer 105 or when an epitaxial layer is formed. However, the ion implantation method using a mask pattern can be used to implant impurities into a selective area.

[0283] Optionally, a heat treatment process can be carried out after ion implantation to activate or diffuse the impurities.

[0284] With reference to Fig. 38 A multitude of trenches 116 can be formed, which are cut from the surface of the semiconductor layer 105 to a certain depth into the semiconductor layer 105.

[0285] For example, the trenches 116 can be designed to penetrate sections of the source regions 112 and extend to a certain depth of the trough regions 110 and the projections 107a of the drift region 107. More precisely, the trenches 116 can be designed to extend from the surface of the semiconductor layer 105 into the semiconductor layer 105 in order to connect two adjacent source regions from the source regions 112 via a point where the two adjacent trough regions touch each other.

[0286] The trenches 116 can be formed, for example, by creating a photomask using photolithography and subsequently etching the semiconductor layer 105 using the photomask as an etch protection layer.

[0287] The gate insulating layer 118 can be formed on the inner walls of the grooves 116 and the surface of the semiconductor layer 105 (see Fig. 39 and Fig. 40). The gate insulating layer 118 can be formed, for example, by oxidizing the semiconductor layer 105 to form an oxide or by applying an insulating material such as oxide or nitride to the semiconductor layer 105.

[0288] Subsequently, the gate electrode layer 120, comprising the first section 120a, which encloses the trenches 116, and the second section 120b on the surface of the semiconductor layer 105, can be formed on the gate insulating layer 118. The gate electrode layer 120 can be formed, for example, by forming a conductive layer on the gate insulating layer 118 and subsequently structuring the conductive layer. The gate electrode layer 120 can be formed by doping impurities in polysilicon or by containing a conductive metal or metal silicide.

[0289] A pattern formation process can be carried out using photolithography and etching. The photolithography process can involve creating a photoresist pattern as a mask layer using a photographic and development process, while the etching process can involve selectively etching an underlying structure using the photoresist pattern.

[0290] As in Fig. As shown in Figure 41, the insulating intermediate layer 130 can be formed on the gate electrode layer 120.

[0291] Subsequently, the source electrode layer 140 can be formed on the insulating intermediate layer 130. Furthermore, the source electrode layer 140 can be configured to connect with the source regions 112 and the well contact regions 114. The source electrode layer 140 can be formed, for example, by applying a conductive layer, such as a metal layer, to the insulating intermediate layer 130 and structuring the conductive layer.

[0292] The MOSFET structure with the hexagonal, closed packed arrangement in the semiconductor layer 105 can be manufactured economically using the manufacturing process described above.

[0293] A power semiconductor device according to an embodiment described above in the present disclosure can make it possible to improve the level of integration through the high channel density and the reliability through the protection of a trench corner.

Claims

[1] Power semiconductor device comprising: a semiconductor layer (105) made of silicon carbide (SiC); a plurality of trough areas (110) arranged in the semiconductor layer (105), which are spaced apart from each other and have a second conductivity type; a plurality of source regions (112) which are arranged in the semiconductor layer (105) on the plurality of well regions (110), are spaced apart from each other and have a first conductivity type; a drift region (107) having the first conductivity type and arranged in the semiconductor layer (105), wherein the drift region (107) extends from a lower side of the plurality of trough regions (110) to a surface of the semiconductor layer between the plurality of trough regions (110) through (105); a plurality of trenches (116) arranged to extend from the surface of the semiconductor layer (105) into an interior of the semiconductor layer (105), such that each of the plurality of trenches (116) connects two adjacent source regions (112) from the plurality of source regions (112) together; a gate insulating layer (118) arranged on the inner walls of the plurality of grooves (116) and the surface of the semiconductor layer (105); and a gate electrode layer (120) arranged on the gate insulating layer (118) and having a first section burying the plurality of trenches (116) and a second section on the surface of the semiconductor layer (105). [2] Power semiconductor device according to claim 1, wherein the distances between three adjacent well regions (110) from the plurality of well regions (110) are equal to each other, and wherein the distances between three adjacent source regions (112) from the plurality of source regions (112) are equal to each other. [3] Power semiconductor device according to claim 1 or 2, wherein the drift region (107) has a projection extending to the surface of the semiconductor layer (105) between three adjacent well regions (110) from the plurality of well regions (110), and wherein the second section of the gate electrode layer (120) is arranged on the projection of the drift region (107) and two adjacent well regions (110) of the three adjacent well regions (110). [4] Power semiconductor device according to one of claims 1 to 3, wherein centers of seven adjacent well regions (110) from the plurality of well regions (110) are each arranged in a center and at vertices of a regular hexagon, and wherein centers of seven source regions (112) located on the seven adjacent well regions (110) from the plurality of source regions (112) are each arranged in the center and at the vertices of the regular hexagon. [5] Power semiconductor device according to claim 4, wherein the plurality of trenches (116) have sections of lines that connect two adjacent lines from the center and the vertices of the regular hexagon, such that the seven adjacent source regions (112) are connected. [6] Power semiconductor device according to any one of claims 1 to 5, comprising: a first channel region restricted to the semiconductor layer (105) to correspond to the first section of the gate electrode layer (120) and to be connected to the drift region (107) and the source regions (112) which are in contact with the plurality of trenches (116) along the plurality of trenches (116); and a second channel area below the second section of the gate electrode layer (120) and which is limited to the semiconductor layer (105) in order to be in contact with the multitude of source areas (112). [7] Power semiconductor device according to claim 6, wherein the first channel region and the second channel region have the second conductivity type, such that an inversion channel is formed, and wherein the first channel region and the second channel region are sections of the plurality of trough regions (110). [8] Power semiconductor device according to claim 6, wherein the first channel region has the second conductivity type, such that an inversion channel is formed, wherein the second channel area exhibits the first conductivity type, so that an accumulation channel is formed, wherein the first channel area corresponds to sections of the multitude of tub areas (110), wherein the second channel area is a section of the drift area (107), and wherein the multitude of source areas (112) on the surface of the semiconductor layer (105) are in contact with the drift area (107). [9] Power semiconductor device according to any one of claims 1 to 8, further comprising: a plurality of basin contact areas arranged in the plurality of source areas (112) and on the plurality of basin areas (110) and exhibiting the second conductivity type; and a source electrode layer connected to the multitude of source areas (112) and the multitude of basin contact areas. [10] Power semiconductor device according to claim 9, wherein the plurality of well contact areas have a circular shape in a top view, and wherein the plurality of source areas (112) have a donut shape surrounding the plurality of well contact areas. [11] Power semiconductor device according to claim 9 or 10, wherein the number of well regions (110) have a shape in which a width of them increases from the surface of the semiconductor layer (105) to an interior of the semiconductor layer (105) and then decreases. [12] Power semiconductor device according to one of claims 1 to 11, wherein opposite lower corners of the first section of the gate electrode layer (120) are surrounded by the plurality of well areas (110). [13] Power semiconductor device according to any one of claims 1 to 12, further comprising: a drain region in the semiconductor layer (105) below the drift region (107) which exhibits the first conductivity type, wherein the drift region (107) has an epitaxial layer on the drain region. [14] comprising a power semiconductor device: a semiconductor layer (105) made of silicon carbide (SiC); a plurality of basin areas (110) arranged in the semiconductor layer (105) and exhibiting a second conductivity type; a plurality of source regions (112) which are arranged in the semiconductor layer (105) on the plurality of well regions (110) and which have a first conductivity type; a drift region (107) having the first conductivity type and arranged in the semiconductor layer (105), extending from a lower side of the plurality of trough regions (110) to a surface of the semiconductor layer (105) extending between the multiple tub areas (110) and providing a vertical transport route for loads; a plurality of trenches (116) arranged to extend from the surface of the semiconductor layer (105) into an interior of the semiconductor layer (105), such that each of the plurality of trenches (116) connects two mutually adjacent source regions (112) from the plurality of source regions (112); a gate insulating layer arranged on the inner walls of the plurality of trenches and the surface of the semiconductor layer (105); a gate electrode layer (120) arranged on the gate insulating layer (118) and having a first section burying the plurality of trenches (116) and a second section on the surface of the semiconductor layer (105); a first channel region restricted to the semiconductor layer (105) such that an inversion channel extends along the plurality of trenches (116) to correspond to the first section of the gate electrode layer (120); and a second channel area below the second section of the gate electrode layer (120) and limited to the semiconductor layer (105), so that an accumulation channel is formed. [15] Power semiconductor device according to claim 14, wherein distances between three adjacent well regions (110) from the plurality of well regions (110) are equal to each other, and wherein distances between three adjacent source regions (112) from the plurality of source regions (112) are equal to each other. [16] Power semiconductor device according to claim 14 or 15, wherein the drift region (107) has a projection extending to the surface of the semiconductor layer (105) between three adjacent well regions (110) from the plurality of well regions (110), and wherein the second section of the gate electrode layer (120) is arranged on the projection of the drift region (107) and the two adjacent well regions (110) of the three adjacent well regions (110). [17] Power semiconductor device according to one of claims 14 to 16, wherein centers of seven adjacent well regions (110) from the plurality of well regions (110) are each arranged in a center and at vertices of a regular hexagon, and wherein centers of seven source regions (112) located on the seven adjacent source regions (112) from the plurality of source regions (112) are each arranged in the center and at the vertices of the regular hexagon. [18] Power semiconductor device comprising: a semiconductor layer (105) made of silicon carbide (SiC); a plurality of well areas (110) arranged in the semiconductor layer (105) such that two adjacent well areas (110) are at least partially in contact with each other and have a second conductivity type; a plurality of source regions (112) which are arranged in the semiconductor layer (105) on the plurality of well regions (110) and which have a first conductivity type; a drift region of the first conductivity type and arranged in the semiconductor layer (105), which extends from a lower side of the plurality of trough regions (110) to a surface of the semiconductor layer (105) between the plurality of trough regions (110) and provides a vertical transport path for charges; a plurality of trenches (116) arranged to extend from the surface of the semiconductor layer (105) into an interior of the semiconductor layer (105), such that each of the plurality of trenches (116) connects two adjacent source regions (112) from the plurality of source regions (112) via a point where two adjacent trough regions (110) from the plurality of source regions (112) touch each other; a gate insulating layer (118) arranged on the inner walls of the plurality of grooves (116) and the surface of the semiconductor layer (105); and a gate electrode layer (120) arranged on the gate insulating layer (118) and having a first section burying the plurality of trenches (116) and a second section on the surface of the semiconductor layer (105). [19] Power semiconductor device according to claim 18, wherein the distances between three adjacent well regions (110) from the plurality of well regions (110) are equal to each other, and wherein the distances between three adjacent source regions (112) from the plurality of source regions (112) are equal to each other. [20] Power semiconductor device according to claim 18 or 19, wherein the drift region (107) has a projection extending to the surface of the semiconductor layer (105) between three adjacent well regions (110) from the plurality of well regions (110), and wherein the second section of the gate electrode layer (120) is arranged on the projection of the drift region (107) and the two adjacent well regions (110) of the three adjacent well regions (110).

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