METHOD FOR APPROXIMATELY CALCULATED BUTTERFLY UNITS OF A FOURIER TRANSFORMATION OF A SIGNAL

Abstract

Method for the approximate calculation of butterfly units of a Fourier transform of a signal in which binary or ternary quantization is performed, wherein the method comprises: Representing a number of butterfly units of a Fourier transform; approximating the number of butterfly units by quantizing rotation factors associated with the butterfly units to obtain approximate rotation factors, wherein a bit width of a quantized, approximate rotation factor is less than or equal to 8 bits, wherein, in the case of binary or ternary quantization, the procedure comprises: minimizing an error between the approximate rotation factors and the rotation factors by using a correction factor α, wherein the correction factor α is a non-1 constant known prior to α.

Description

[0001] The present invention relates to a method for the approximate calculation of butterfly units of a Fourier transform of a signal, a circuit for the approximate calculation of butterfly units of a Fourier transform of a signal and a corresponding computer program product.

[0002] The ongoing development of the Internet of Things (IoT) is leading to the omnipresence of intelligent systems. These are directly embedded in applications and consist of sensors for environmental monitoring, processors for direct data processing, and external communication interfaces. The relocation of the necessary calculations close to the action (edge ​​computing) using embedded systems is leading to new challenges, especially with regard to resource requirements (energy, runtime, memory, etc.). Optimized and specialized systems and methods are being sought for this purpose [1] that can also be used under real-time requirements with low latency.

[0003] A particularly important method for calculating frequency spectra or convolutions in digital signal processing of, for example, image or audio data is the Discrete Fourier Transformation (DFT) or the Fast Fourier Transformation (FFT).

[0004] Furthermore, the development of the Internet of Things (IoT) is leading to the acquisition of large amounts of data. In order to manage this volume of data, it is essential to shift the calculations required for data processing close to the event (edge ​​computing). Machine learning models and methods are often used to extract knowledge from the acquired data. One type of model that is particularly important for processing image or audio data, for example, is convolutional neural networks (CNNs), which can utilize the Fourier transform. The inference and training of CNNs are characterized by high computational effort due to the large number of convolution operations required. The use of CNNs in resource-limited edge systems therefore requires specialized algorithms that are resource-efficient (energy, runtime, memory, etc.).) optimized software and hardware architectures.

[0005] As already mentioned, the basis for a transformation of time-discrete, finite signals into the frequency domain is the discrete Fourier transform (DFT) [2]: γ→=W⋅x→=Wr⋅x→−iWi⋅x→ y[k]=∑j=0N−1e−i2πjkN⋅x[j]=∑j=0N−1cos(2πjkN)⋅x[j]−i∑j=0N−1sin(2πjkN)⋅x[j]

[0006] Equation (1a) describes the transformation into the frequency domain for a signal vector x→ in matrix-vector notation. For a component y[k] in the frequency domain, the calculation according to equation (1b) is carried out by component-wise multiplication with the corresponding row of the DFT matrix W and summation of the products. The vectors x→ and y→ can be real-valued or complex-valued. The DFT matrix W has a real part W r and an imaginary part W i and can be written as follows: W=((e−2πjkN)k,j)=Wr−iWi=((wr)k,j)−i((wi)k,j) =((cos(2πjkN))k,j)−i((sin(2πjkN))k,j)

[0007] The inversion of DFT, i.e. the transformation of discrete frequency spectra into discrete-time signals, is called inverse DFT (iDFT). It is performed by multiplying the inverted DFT matrix W -1 with a vector in the frequency domain and a scalar multiplication with a constant factor 1N. Since the inversion of the DFT matrix is ​​equivalent to the conjugate complex representation of its components, the calculation of the iDFT can be done analogously to the calculation of the DFT.

[0008] The basis for the FFT or inverse FFT (iFFT) is the Cooley-Tukey algorithm [3] [4] [5]. This method allows the decomposition of a DFT or iDFT into smaller DFT calculation blocks and so-called butterfly units according to the divide-and-conquer principle. This already reduces the number of required calculation operations. By applying the method recursively, a representation of the DFT can also be achieved exclusively using the butterfly units. The butterfly units can have different numbers of input values. An FFT consisting of butterfly units with n inputs is called a radix-n FFT. FFT variants with different butterfly units (split-radix and mixed-radix FFT) are also known. Depending on the arrangement of the input values ​​when dividing the DFT into the butterfly units, a distinction is also made between the decimation-in-time (DIT) and decimation-in-frequency (DFT) FFT.

[0009] A DIT or DIF Radix-2 butterfly unit is, for example, Fig. 10a and Fig. 10b is shown schematically. A DIT or DIF radix-2 butterfly unit consists of one complex multiplication and two complex additions / subtractions (four real multiplications and six real additions / subtractions). Similarly, butterfly units with more than two input values ​​can also be described. An essential operation is multiplication by a twiddle factor. WNk, which can be written as follows: WNk=e−(i2πkN)=cos(2πkN)−i sin(2πkN)=wr,Nk−iwi,Nk

[0010] The following formula describes the calculations to be performed when multiplying by a rotation factor within a DIT / DIF radix n butterfly unit: a=WNk⋅x=(wr,Nk−iwi,Nk)⋅(xr+ixi)=(wr,Nk⋅xr+wi,Nk⋅xi)+i(wr,Nk⋅xi−wi,Nk⋅xr) x and a are the complex inputs and outputs of the multiplication, respectively.

[0011] Previous approaches to increasing the energy efficiency and performance of (i)DFT or (i)FFT are based on approximate calculation methods using the quantization of the rotation factors or input variables, as well as on methods for multiplication-free representation of the calculations. Various studies investigate the influence of quantization widths and types (uniform and non-uniform quantization) on the resulting accuracy of the FFT and the algorithmic derivation of optimal quantization widths for the respective application requirements [6] [7] [8]. Furthermore, research has been carried out on how to perform multiplication-free FFT calculations. Resource-intensive multiplications are usually replaced by shift operations and additions or subtractions by decomposing the rotation factors using the sum-of-powers-of-two or canonical signed digit representation [9]

[10] or by using so-called lifting structures

[11] .Furthermore, multiplications can be replaced by distributed arithmetic

[12] .

[0012] US 7 428 564 B2 describes an FFT processor with an address generator for reordering the rotation factors so that certain butterfly operations can be performed without multiplication. WO 0 055 757 A1 describes a fast, multiplication-free discrete cosine transform in which multiplications are replaced by additions / subtractions and shift operations. US 8 239 442 describes a hardware accelerator that can be used as an FFT butterfly unit or FIR filter unit. US 5917 737 describes a DFT using a binary kernel function and a static implementation of the DFT as a circuit for a fixed number of input values.

[0013] Previous approaches to accelerating convolutional neural networks primarily focus on resource-optimized inference. These include methods for quantizing weights and inputs of the networks

[13] ,

[14] ,

[15] , methods for eliminating weights that do not significantly contribute to the network's functionality (pruning)

[16] ,

[17] ,

[18] , and the automated search for network architectures that are adapted to the underlying hardware

[19] ,

[20] ,

[21] . Especially for the inference of quantized CNNs, hardware architectures also exist, implemented as application-specific integrated circuits (ASICs)

[22] or on field-programmable gate arrays (FPGAs)

[23] .

[0014] To accelerate the training of convolutional neural networks, training data are pre-filtered based on their importance to directly eliminate computational steps that do not contribute to the network's functionality

[24] . A disadvantage of this method is that the possible degree of optimization is completely dependent on the input data. Therefore, an actually possible optimization cannot be known in advance.

[0015] To accelerate the training and inference of convolutional neural networks, existing work uses the convolution theorem

[25] ,

[26] ,

[27] . The convolution between an input and the convolution kernel in the time domain can thus be replaced by pointwise multiplication in the frequency domain. By repeatedly applying the fast Fourier transform (FFT) and its inverse, the number of required operations can be reduced.

[0016] US 10 902 318 B2 describes a method for optimizing the number of memory operations required when using the FFT or the Winograd transform to calculate convolutions in CNNs. US 9 904 874 B2 describes a hardware system for processing camera images using CNNs. CNN execution is accelerated by using a dedicated time-to-frequency domain converter.

[0017] DE 100 06 154 A1 discloses a method for calculating heart rate variability for use in an ECG monitor and an ECG monitor with a corresponding calculation program.

[0018] The Wikipedia article on “butterfly graph” from October 28, 2021, reveals the definition of a butterfly graph.

[0019] The paper by Chan, Shing-chow; Yiu, PM “An efficient multiplierless approximation of the fast Fourier transform using sum-of-powers-of-two (SOPOT) coefficients”, IEEE signal processing letters, 2002, 9th vol., no. 10, pp. 322-325, discloses an efficient multiplierless approximation of the fast Fourier transform using sum-of-powers-of-two (SOPOT) coefficients.

[0020] An object of the present invention is to provide an improved method, an improved circuit and an improved computer program product with which a resource requirement of the FFT can be reduced in order to enable efficient use of the method / circuit / computer program product on embedded, resource-limited systems.

[0021] This problem is solved by the subject matter of the independent patent claims.

[0022] The core idea of ​​the present invention is to approximate the calculation of the FFT butterfly units by quantizing the rotation factors, in particular with a particularly small bit width of less than or equal to 8 bits, particularly preferably of one and two bits, i.e., by binary or ternary quantization of the rotation factors, and to implement such a calculation on derivable hardware architectures, i.e., a circuit, with minimal resource requirements. With the proposed solution, existing methods for calculating the FFT can be significantly accelerated and optimized with regard to their resource requirements, in particular by requiring fewer resources.

[0023] According to the proposal, the method for the approximate calculation of butterfly units of a Fourier transform of a signal subject to binary or ternary quantization involves representing a number of butterfly units of a Fourier transform. The Fourier transform of a signal is first decomposed into butterfly units, or the Fourier transform is represented as a number of butterfly units.The number of butterfly units is then approximated by quantizing rotation factors, in particular actual ones, belonging to the butterfly units in order to obtain approximated rotation factors, wherein a bit width of a quantized, approximated rotation factor is less than or equal to 8 bits, wherein in the case of binary or ternary quantization the method comprises: minimizing an error between the approximated rotation factors and the rotation factors by using a correction factor α, wherein the correction factor α is a constant not equal to 1 known α-priori. Each of the rotation factors belonging to the butterfly units comprises a real part and an imaginary part, as shown for example in equation (3). In the present case the butterfly units and thus the rotation factors are thus approximated, i.e. brought closer.

[0024] According to a further aspect of the present invention, a circuit for the approximate calculation of butterfly units of a Fourier transform of a signal is proposed, which circuit is designed to implement the proposed method. For this purpose, the circuit for the approximate calculation of butterfly units of a Fourier transform of a signal comprises a number of M:1 multiplexers, where M=2, ..., 256 is a natural number. M specifies the number of inputs of the multiplexer(s). The circuit is designed to replace a multiplication based on a quantization of rotation factors associated with butterfly units, in particular actual ones, without an actual hardware multiplier before a signal flow by at least one multiplexer of the number of multiplexers. For example, the circuit is designed to invert a sign of the signal in a binary or ternary quantization.For this purpose, a device called "invert sign" is provided for inverting the signal's sign. Furthermore, the circuit is designed to replace multiplication with reduced-complexity constant multiplication for quantization bit widths greater than 2 bits.

[0025] The solution proposed herein for the butterfly unit, particularly a binary or ternary approximation, relates to the transformation of discrete time-domain signals into the frequency domain using the discrete Fourier transform. The present invention enables the approximate calculation of FFT butterfly units with any number of input parameters within the framework of DIT and DIF radix-n FFT and iFFT, either completely without multiplication or with a reduced number of required multiplications, as well as reduced memory requirements for real- and complex-valued input values.

[0026] Furthermore, a computer program product is proposed which comprises instructions which, when executed by a computer, cause the computer to carry out the proposed method, in particular with the proposed circuit.

[0027] Advantageous embodiments of the present invention are the subject of the dependent patent claims. Preferred embodiments of the present invention are explained in detail below with reference to the accompanying drawings. They show: Fig. 1 a detailed flowchart for calculating the parameters of the approximated butterfly units; Fig. 2 a schematic representation of binary quantized rotation factors; Fig. 3 a schematic representation of ternary quantized rotation factors; Fig. 4 a mean square deviation between the rotation factors and the corresponding ternary quantized approximated rotation factors for different threshold values; Fig. 5 a mean square deviation between the rotation factors and the corresponding ternary quantized approximated rotation factors for different threshold values; Fig. 6 a hardware architecture that can be used in a circuit for the multiplication-free calculation of a binary approximated butterfly unit with a correction factor; Fig. 7 a hardware architecture that can be used in a circuit for the multiplication-free calculation of a ternary approximated butterfly unit with correction factor; Fig. 8 a hardware architecture that can be used in a circuit for the multiplication-free calculation of a binary approximated butterfly unit; Fig. 9 a hardware architecture that can be used in a circuit for the multiplication-free calculation of a ternary approximated butterfly unit; Fig. 10a schematic representation of a DIT radix-2 butterfly unit; Fig. 10b schematic representation of a DIF radix-2 butterfly unit; Fig. 11 schematic flow of an approximate convolution using AFFT between two 1D inputs; Fig. 12 schematic flow of an approximate convolution using 2D-AFFT between two 2D inputs; and Fig. 13 Schematic process of the 2D-AFFT.

[0028] Individual aspects of the invention described herein are described below in the Fig. 1 to 13. In summary, the Fig. 1 to 9 and 11 to 13 illustrate the principle of the present invention, while Fig. 10a and Fig. 10b shows a schematic representation of known butterfly units 500. In the present application, like reference numerals refer to like or equivalent elements, although not all reference numerals are shown again in all drawings if they are repeated.

[0029] All definitions provided in this application are applicable to the described methods, circuits, or computer program products. The definitions are not repeated frequently to avoid redundancy.

[0030] Here, the terms "input signal" are used synonymously with "input value" or "input data." The terms "quantization value" and "threshold value" are also used synonymously. The methods described initially require that a value / signal be made available for further calculation. The physical meaning of this value / signal can be determined by a person skilled in the art from the context in which the described methods are applied, or can be further understood from the further description in the context.

[0031] The present technical teaching comprises, on the one hand, a method for calculating the parameters necessary for the optimal approximation of the FFT, which is described in more detail in the flow chart according to Fig. 1. On the other hand, the present technical teaching comprises a hardware architecture for butterfly units, which is schematically shown in the Fig. 6 to 9 and can be implemented using a hardware description language on Field Programmable Gate Arrays (FPGAs), as an application-specific integrated circuit (ASIC), or as part of a System-on-Chip (SoC). Fig. The hardware structures illustrated in Figures 6 to 9 are thus a pictorial representation of a circuit proposed herein. Furthermore, based on the method for the approximate calculation of butterfly units of a Fourier transform of a signal, an improved method for training and / or executing a convolutional neural network (CNN) using an approximate fast Fourier transform (AFFT) can be provided, which is schematically illustrated in Figures Fig. 11 and Fig. 12 is outlined.

[0032] The described method for the approximate calculation of butterfly units of a Fourier transform of a signal comprises representing a number of butterfly units of a Fourier transform and subsequently approximating the number of butterfly units by quantizing rotation factors associated with the butterfly units, in particular actual ones, to obtain approximate rotation factors. A bit width of a quantized, approximate rotation factor is less than or equal to 8 bits. As can be seen from equation (3), a rotation factor comprises a real part and an imaginary part.

[0033] The present invention will be explained below using binary and ternary quantization of the butterfly units. However, the quantization described herein can also be applied to other quantizations, such as quaternary or quintary, etc.

[0034] The basis of the binary or ternary approximated butterfly unit is the approximation of the rotation factors WNk using binary or ternary quantization. Furthermore, a correction factor can further improve the approximation of the rotation factors.

[0035] In the flow chart after Fig. 1, at a start 110, input data 120 is initially input, which may comprise N values, where N is a natural number and specifies a number of input data. N can, for example, be a number of acquired data (samples) of an input signal. The following applies: N = number of input samples. The input values / signals 120 define the underlying discrete Fourier transform (DFT). The input values ​​120 are, in particular, acquired signals. The DFT is represented in a decomposition 130 into butterfly units in a butterfly graph or graph structure 140. The graph structure 140, which comprises a number of butterfly units 500 (see Fig. 10a, Fig. 10b) can be presented visually to a user. For example, a representation of the butterfly units 500, as shown in the Fig. 10a and Fig. 10b. In other words, first, a number of butterfly units of a Fourier transform are represented. The representation 130 is initially to be understood as decomposing 130 a matrix of the overall system into butterfly units (submatrices) so that further computational operations can be performed. Furthermore, the representation 130 can be understood as making it visually visible to a user, for example in the form of a graph structure 140. The butterfly units comprise rotation factors 150, which are to be approximated. For this purpose, the rotation factors are quantized, i.e., divided into sub-areas. Each rotation factor 150 belongs to a butterfly unit.

[0036] Below, an approximation 160 is discussed using the examples of binary quantization and ternary quantization (quantization type 190). The method described herein is preferably carried out using binary or ternary quantization. However, other quantizations / quantization types 190 are also possible.

[0037] In binary quantization, an interval [r min , r max ] divided into two sub-areas and a data point d i ∈ [r min , r max ] is coded or assigned according to its affiliation to one of the sub-areas, so that (d i ) B ∈ {-1, 1}.

[0038] In ternary quantization, an interval [r min , r max ] divided into three sub-areas and a data point d i ∈ [r min , r max ] is coded or assigned according to its affiliation to one of the sub-areas, so that (d i )T ∈ {-1, 0, 1}.

[0039] In the described procedure, a data point is generally assigned according to its affiliation to one of the P=2 (B-1) +1 sub-ranges are encoded. B is a natural number less than or equal to 8 and specifies the bit width.

[0040] To represent the two or three possible output values ​​of the quantization, one bit is required for binary quantization and two bits for ternary quantization. Binary and ternary quantization differ in the resulting accuracy, ie, the deviation from the data point d i . The data point d i is, for example, a quantization input. The quantization input includes a real part and an imaginary part of the rotation factor to be quantized. The selection of the quantization type 190, i.e. whether binary or ternary, according to the Fig. The method shown in Figure 1 can be performed by the user or by an estimation, which can be carried out by an algorithm. In the case of an estimation using an algorithm, a direct decision by the user is not necessary. To start a calculation of the estimation, the user enters a sample signal and a required accuracy guideline value into a program executing the algorithm. The program can then automatically estimate, in particular derive which type of quantization is appropriate. The user can also decide, or the estimation can be used to determine, whether a multiplication-free approximation 170 should be used, in which a correction factor α=1 applies to all rotation factors, or whether an approximation 180 with a reduced number of necessary multiplications should be used, in which an optimal value for the correction factor α= α opt for all rotation factors. Setting α= a optin step 180 of the Fig. 1 means, set α opt as a parameter in the calculation, which is to be determined within the framework of a minimization problem.

[0041] The quantization of the rotation factors 150 is applied to the real and imaginary parts, which, due to trigonometric relationships, both lie in the interval [-1, 1]. The quantization functions can generally be described with w∈{wr,Nk,wi,Nk} describe: qB(w)=(w)B={−1,w<0 1,w≥0 qT(w,t)=(w)T={−1w<−t 0|w|≤t 1,w>t

[0042] Equation (5a) describes the binary quantization, which in Fig. 2 is shown schematically. Equation (5b) describes the ternary quantization, which in Fig. 3 is shown schematically. In the Fig. 2 and Fig. Figure 3 shows the binary or ternary quantization of the imaginary part 215 and the real part 225 of the rotation factors 150, each in the interval [-1, 1], relative to a wave vector k. In ternary quantization, the parameter t ∈ [0, 1] describes a threshold value that divides the interval [-1, 1] into the three sub-ranges 301, 302, and 303 by applying it in the positive and negative ranges. Fig. 3, the threshold value t is shown as dashed lines 300 in the positive (t) and negative (-t) range. The dashed lines 300 run parallel to the k-axis. The first sub-range 301 contains the values ​​of the rotation factors wr / i,Nk, which corresponds to the half-open interval] t, 1] of the quantization function q T (w). In the second sub-area 302 are the values ​​of the rotation factors 150, which correspond to the half-open interval] -t, -1] of the quantization function q T(w). In the third sub-area 303 are the values ​​of the rotation factors 150, which correspond to the closed interval [-t, t] of the quantization function q T (w) are assigned. In Fig. 2, the two sub-areas 201 and 202 are to be assigned as follows. In the first sub-area 201, the values ​​of the rotation factors are wr / i,Nk, which corresponds to the closed interval [0 , 1] of the quantization function q B (w). In the second sub-area 202 lie the values ​​of the rotation factors 150, which correspond to the half-open interval ] 0, -1] of the quantization function q B (w). The Fig. 2 and Fig. 3 thus show the binary and ternary quantized rotation factors, which are described by equation (3).

[0043] In the described method, the quantization using N bits leads to a quantization of the rotation factors in P=2 (B-1)+ 1 sub-ranges, where B is a natural number less than or equal to 8 and B specifies the bit width. In binary quantization, where the bit width is one bit, i.e. B=1, the quantization thus leads to 2 (1-1) +1=2 0 +1=2 sub-ranges. In ternary quantization, where the bit width is two bits, i.e. B=2, the quantization thus leads to 2 (2-1) +1=2 1 +1 = 3 subranges. The value 0 (see equations (5b) or (6b)) is possible with ternary quantization. This uses so-called mid-tread quantization.

[0044] Using binary or ternary quantization, multiplication with the rotation factors can be replaced by a conditional decision: (w)B⋅x={−x(w)B=−1 x(w)B=1 (w)T⋅x={−x(w)T=−1 0,(w)T=0 x,(w)T=1

[0045] By replacing the multiplication by a conditional decision, the approximation 170 can be calculated without multiplication (see Fig. 1) or at least with a reduced number of multiplications 180. Equations (5a) and (5b) each give quantized rotation factors 192 (see Fig. 1) binary or ternary quantization.

[0046] In the described method, multiplication by the rotation factors during quantization into P sub-ranges is preferably replaced by a conditional decision. This can reduce the resource requirements of the described method. In the method, quantization is applied to a real part and an imaginary part of the real rotation factors.

[0047] In order to minimize the error between the approximated and actual rotation factors, a correction factor α can additionally be used. Preferably, the described method, in particular in the case of binary or ternary quantization, comprises minimizing an error between the approximated rotation factors and the actual rotation factors by using a correction factor α. Depending on the choice of the correction factor α, this can lead to a multiplication-free approximation 170 or to an approximation 180 with a reduced number of necessary multiplications. Here, “choice of the correction factor” refers to whether α=1 is set for all rotation factors, as in 170 of the Fig. 1, or whether α= a opt for all rotation factors, as in 180 of the Fig. 1 is specified.

[0048] If α=1 is set for all rotation factors according to step 170, and the quantization type 190 is selected as binary, an application 189 of the binary quantization q B (w) to all rotation factors. Here, the quantized rotation factors (w) B in step 192, ie, the approximate rotation factors. After determining the approximate rotation factors, the method for the approximate calculation of butterfly units of a Fourier transform of a signal is completed 194. The approximate rotation factors can then be used for further purposes, for example, in a subsequent method.

[0049] If α=1 is set for all rotation factors according to step 170, and the quantization type 190 is selected as ternary, an optimal threshold value t is first calculated according to step 185. The threshold value t divides the value range of the quantization functions in the ternary quantization into three sub-ranges. Subsequently, using the calculated threshold value t 191, an application 193 of the ternary quantization q T (w) to all rotation factors. Here, the quantized rotation factors (w) T in step 192, ie, the approximate rotation factors. After determining the approximate rotation factors, the method for the approximate calculation of butterfly units of a Fourier transform of a signal is completed 194. The approximate rotation factors can then be used for further purposes, for example, in a subsequent method.

[0050] If α= α optfor all rotation factors according to step 180, and the quantization type 190 is chosen as binary, an optimal correction factor α opt for all rotation factors in step 187. After calculating the correction factor 188, an application 189 of the binary quantization q B (w) to all rotation factors. Here, the quantized rotation factors (w) B in step 192 using the optimal correction factor α opt determined, ie, the approximate rotation factors are determined. After determining the approximate rotation factors, the method for the approximate calculation of butterfly units of a Fourier transform of a signal is complete 194. The approximate rotation factors can then be used for further purposes, for example, in a subsequent method.

[0051] If α= a optfor all rotation factors according to step 180, and the quantization type 190 is chosen as ternary, first an optimal threshold value t an optimal correction factor α opt for all rotation factors in step 186. After calculating the correction factor 188 and the threshold value 191, the ternary quantization q is applied 193 T (w) to all rotation factors. Here, the quantized rotation factors (w) T in step 192 using the optimal correction factor a opt and using the optimal threshold value t, ie, the approximate rotation factors are determined. After determining the approximate rotation factors, the method for the approximate calculation of butterfly units of a Fourier transform of a signal is completed 194. The approximate rotation factors can then be used for further purposes, for example, in a subsequent method.

[0052] The individual approximation steps are explained in detail below. The approximation of the quantized rotation factors can therefore be generally described as: WNk=wr,Nk−iwi,Nk≈α((wr,Nk)B / T−i(wi,Nk)B / T)=α(WNk)B / T

[0053] The correction factor α can be determined in such a way that the approximation of the rotation factors according to equation (7) is optimal. This means that the error between the, in particular the actual, rotation factor WNk and the approximation α(WNk)B / T is minimized. This can be described by the following optimization problem: minα|WNk−α(WNk)B / T|=minα|WNk−α(WNk)B / T|=minα|(wr,Nk−α(wr,Nk)B / T)−i (wi,Nk−α(wi,Nk)B / T)|=minα(wr,Nk−α(wr,Nk)B / T)2+(wi,Nk−α(wi,Nk)B / T)2

[0054] If, to solve the optimization problem, the derivative of the expression to be minimized is calculated according to equation (8) and set to 0, then, after equivalence transformation, one obtains for α: α=wr,Nk⋅(wr,Nk)B / T+wi,Nk⋅(wi,Nk)B / T((wr,Nk)B / T)2+((wi,Nk)B / T)2=αopt

[0055] In the case of ternary quantization, the threshold value t can also be chosen for any correction factor α such that the approximation becomes optimal, i.e., the error between an actual rotation factor and the corresponding approximated rotation factor is minimized. To do this, the mean square deviation between all rotation factors and their approximations must be minimized: mint1N∑k=0N−1|WNk−α⋅qT(WNk,t)|2

[0056] Since the quantization function q T (w, t) is only partially differentiable, the problem cannot be solved analytically. Numerical or graphical methods can be used for the solution. Fig. 4 and Fig. 5 show an example of the term to be optimized according to equation (10) (mean square deviation between actual and approximated rotation factor) for N = 1024 and α = 1 ( Fig. 4) and N = 1024 and α = α opt ( Fig. 5). The resulting mean square deviation 400 between the actual and approximated rotation factor is plotted against the threshold value t. The minimum of the function describing the mean square deviation between the actual and approximated rotation factor, and thus the optimal threshold values, are at t = 0.5 for α = 1 ( Fig. 4) and at t = 0.38 for α = α opt ( Fig. 5).

[0057] The described method therefore preferably comprises the steps of forming a derivative of the error to be minimized; and performing at least one equivalent transformation in order to obtain an expression for the correction factor α, in particular for an optimal correction factor α opt , to obtain. Furthermore, the described method preferably comprises, in particular in the case of ternary quantization, selecting the threshold value t to an arbitrary correction factor α.

[0058] Preferably, a threshold value or quantization values ​​for approximating the rotation factors are selected such that the approximated rotation factors can be written as a power of two or as a sum of powers of two.

[0059] Each butterfly unit of the number of butterfly units can have a different number of input values ​​or the same number of input values. Only the dimensions of the input values ​​must match.

[0060] Preferably, the method for the approximate calculation of butterfly units of a Fourier transform of a signal is based on the fast Fourier transform (FFT). The method can be implemented for 1D FFT or 2D FFT.

[0061] The multiplication with the rotation factors 150 within the radix-n butterfly units according to equation (4) can be approximated with the correction factor α as follows: a≈a*=(WNk)B / T⋅x=α((wr,Nk)B / T+i(wi,Nk)B / T)⋅(xr+ixi) =α((wr,Nk)B / T⋅xr−(wi,Nk)B / T⋅xi)+iα((wr,Nk)B / T⋅xi+(wi,Nk)B / T⋅xr)

[0062] The number of real multiplications is thus reduced from four (between the real and imaginary parts of WNk and x) to two, since only the real and imaginary parts of the result must be multiplied by the correction factor α. The correction factor α is an a-priori known constant. In this case, a constant known a-priori means that the correction factor α is known after application of the method but before application in the application (hardware / circuit 100). Multiplication by the correction factor 188, as in the Fig. 6 and Fig. 7, thus does not require a hardware multiplier.

[0063] Equation (11) can be used to derive corresponding hardware architectures for DIF / DIT radix-n butterfly units, which can be implemented using a hardware description language on FPGAs, as ASICs, or as part of systems-on-chips (SoCs). Fig. 6 and Fig. 7 shows an example of a template for implementing a hardware structure of a binary or ternary DIT radix-2 butterfly unit with correction factor α. The templates according to Fig. 6 and Fig. 7 are used to implement the hardware structure in a circuit for the approximate calculation of butterfly units of a Fourier transform of a signal. The circuit is preferably implemented on an FPGA, in particular as an ASIC or as part of a system-on-chip (SoC).

[0064] Fig. 6 and Fig. 7 show a hardware architecture that can be used in a circuit 100 for multiplication-free calculation of a binary ( Fig. 6) or ternary ( Fig. 7) approximated butterfly unit 500 with correction factor 188, wherein multiplexers (BMUX / TMUX) 600 are provided in the circuit 100. Fig. 8 and Fig. 9 show a hardware architecture that can be used in a circuit 100 for multiplication-free calculation of a binary ( Fig. 8) or ternary ( Fig. 9) approximated butterfly unit 500, wherein multiplexers (BMUX / TMUX) 600 are provided in the circuit 100. The Fig. 6 to 9 thus show the hardware architecture necessary to carry out steps 170 to 194 according to Fig. 1 to be realized.

[0065] The circuit for the approximate calculation of butterfly units of a Fourier transform of a signal comprises a number of M:1 multiplexers, where M=2, ..., 256 is a natural number. M specifies the number of inputs of the multiplexer(s). The circuit is designed to replace a multiplication based on a quantization of rotation factors associated with butterfly units, in particular actual ones, without an actual hardware multiplier before a signal flow by at least one multiplexer of the number of multiplexers. The multiplications with the rotation factors are replaced by an M:1, in particular a 2:1 or 3:1 multiplexer (BMUX or TMUX). The 2:1 or 3:1 multiplexers can be used in particular for binary or ternary quantization.

[0066] Subsequently, the real and imaginary parts can be multiplied by the correction factor α and the calculation with the second input value of the butterfly unit can be carried out, as is the case, for example, in Fig. 6 and Fig. 7. Therefore, the circuit is preferably designed to calculate an output signal at a multiplexer with a second input value. Furthermore, the circuit is preferably designed to calculate a real part and an imaginary part of the output signal at the multiplexer with a correction factor α before calculating the output signal with the second input value.

[0067] The real or imaginary part of the binary or ternary quantized rotation factors can be represented by one bit in the binary case and two bits in the ternary case. The bit width and representation format (integer, floating-point number) of the input values ​​can, in principle, be arbitrary. However, the blocks for addition, subtraction, sign inversion, and multiplication with reduced complexity should be adapted to the selected bit width and representation format (integer, floating-point) of the input values ​​in the case of quantization with a larger bit width.

[0068] For the case α = 1, a butterfly unit can be approximated without multiplication (see 170 in Fig. 1) and equation (4) can be further simplified to: a≈a**=(WNk)B / T⋅x=((wr,Nk)B / T+i(wi,Nk)B / T)⋅(xr+ixi) =((wr,Nk)B / T⋅xr−(wi,Nk)B / T⋅xi)+i((wr,Nk)B / T⋅xi+(wi,Nk)B / T⋅xr)

[0069] Equation (12) can be used to derive corresponding hardware architectures for DIF / DIT radix-n butterfly units. Fig. 8 and Fig. 9 show an example of a template for an implementation of a hardware structure of a multiplication-less binary or ternary DIT radix-2 butterfly unit.

[0070] Using the described method for the approximate calculation of butterfly units of a Fourier transform of a signal or the described circuit for the approximate calculation of butterfly units of a Fourier transform of a signal, multiplexer-based architectures for approximate butterfly units with purely real input values, more than two input values ​​(radix-n), and DIF partitioning can be constructed analogously to the hardware architectures shown in Figs. 6, 7, 8, and 9. The templates according to Fig. 8 and Fig. 9 are used to implement the hardware structure in a circuit for the approximate calculation of butterfly units of a Fourier transform of a signal. The circuit is preferably implemented on an FPGA, in particular as an ASIC or as part of a system-on-chip (SoC).

[0071] In any case, the circuit is designed to carry out the described method for the approximate calculation of butterfly units of a Fourier transform of a signal.

[0072] According to a further aspect, a computer program product is described which comprises instructions which, when executed by a computer, cause the computer to execute the method for the approximate calculation of butterfly units of a Fourier transform of a signal. The computer program product is preferably implemented in a described circuit for the approximate calculation of butterfly units of a Fourier transform of a signal.

[0073] The described method for the approximate calculation of butterfly units of a Fourier transform of a signal can significantly reduce the number of multiplications required for an FFT or iFFT, thus reducing the computational complexity and resource consumption of the transformation between the time and frequency domains, and increase the computational speed. This is an advantage over the state of the art. The described method thus enables the presented hardware architectures, which require either no or a reduced number of multiplications to calculate an FFT butterfly unit, but do not require hardware multipliers. This is accompanied by an increase in energy efficiency and performance.

[0074] The quantization of the rotation factors required to calculate the FFT also leads to a reduction in memory requirements. Since the described method for the approximate calculation of butterfly units of a Fourier transform of a signal and the associated optimization of the FFT are based on an approximate calculation, i.e., an approximation, which reduces the accuracy of the result, a further advantage of the described method is the optimal approximation of the rotation factors. This enables an optimal approximation of the result despite the strong quantization of the rotation factors.

[0075] Technical applications of the described method and the corresponding circuit can be found in all areas of digital signal processing. In the field of system condition monitoring, for example, the analysis of structure-borne sound signals plays a crucial role. In many cases, time-domain signals are recorded using acceleration or acoustic emission sensors. To extract relevant information, these discrete signals are then analyzed in the frequency domain or time-frequency domain using FFT-based methods. Sensor signals of other quantities, such as current or force, are also transformed into the frequency domain or time-frequency domain to extract relevant information.

[0076] Since the method for the approximate calculation of butterfly units of a Fourier transform of a signal enables a fast and approximate calculation of frequency spectra, relevant frequency bands can be quickly identified and extracted for compressed storage of information.

[0077] It is also conceivable to use non-optimal parameters, as described herein, to approximate the FFT in the described method. Furthermore, it is conceivable to use other hardware architectures to perform the approximate calculation of a butterfly unit.

[0078] Similar analysis methods are also used for processing audio signals. The described method allows for approximating all FFT-based methods. Since the 2D FFT can also be expressed using the 1D variant, the described method can also be applied to 2D input data, ie, to the FFT-based processing of, for example, image data.

[0079] Furthermore, the method for the approximate calculation of butterfly units of a Fourier transform of a signal can be used not only for signal analysis but also for signal manipulation by exploiting the convolution theorem, which states that convolutions in the time domain are equivalent to pointwise multiplication in the frequency domain. Thus, the described method can also be used in all application areas of discrete convolution, such as control systems or acoustics.

[0080] Convolution also forms the basis of convolutional neural networks (CNNs) in the field of machine learning, which are primarily used for real-time object recognition in autonomous driving and robotics. Applying the convolution theorem allows for a reduction in computational complexity and thus accelerated computation. Using the presented method, this approach can be significantly optimized and accelerated by reducing the computational complexity of the transformation. Another application of the invention is lossy data compression.

[0081] Based on the method for approximately calculating butterfly units of a Fourier transform of a signal, an improved method for training and / or executing a convolutional neural network (CNN) using an approximate fast Fourier transform (AFFT) can be provided. Executing a convolutional neural network uses inference, i.e., applying the trained network to obtain a conclusion or prediction for a given input. The convolutional computations of the convolutional neural network required for inference and training are approximated by the AFFT.

[0082] The further proposed method for training and / or executing a convolutional neural network using an approximate fast Fourier transform comprises providing at least two input signals. The input signals can be 1D or 2D signals. For example, they can be audio signals and / or image signals. Furthermore, the method for training and / or executing a convolutional neural network comprises performing a convolution.The convolution as such comprises approximating a Fourier transform for each of the at least two input signals to obtain at least two approximated fast Fourier transforms (AFFTs); calculating a Hadamard product of the at least two approximated fast Fourier transforms (AFFTs) to obtain an approximated convolution result in the frequency domain; and approximating an inverse Fourier transform to obtain an approximated inverse fast Fourier transform (iAFFT). Approximating an inverse Fourier transform corresponds to applying an inverse approximated fast Fourier transform (iAFFT) to the result of the Hadamard product.After performing the convolution, the method for training and / or executing a convolution-based neural network comprises outputting the inverse approximated fast Fourier transform (iAFFT) as an output signal, in particular as an approximated result of the convolution in the time domain. As proposed, the FFT required for the convolution of discrete-time signals in the frequency domain, or its inverse, is approximated. This has the consequence that the result of the convolution also represents an approximation. The FFT is approximated, as already described in connection with the method for the approximate calculation of butterfly units of a Fourier transform of a signal, preferably via a binary or ternary quantization of the rotation factors, in particular with a bit width B of one or two.However, approximations with higher bit widths are also conceivable, as also described in connection with the method for the approximate calculation of butterfly units of a Fourier transform of a signal. Further preferred is a subsequent calculation with the correction factor α. With the approximate FFT (AFFT), the number of arithmetic operations and memory accesses can be reduced. In particular, the number of energy-intensive multiplications can be significantly reduced, to the point where the FFT can be performed without multiplication. This advantage can then ultimately be transferred to convolution, so that the method for training and / or executing a convolutional neural network can also operate in a resource-optimized manner.

[0083] Preferably, the method for training and / or executing a convolutional neural network for approximating the Fourier transform for each of the at least two input signals comprises decomposing a Fourier transform of a signal into a number of butterfly units with at least two input values ​​and approximating the butterfly units by quantizing rotation factors associated with the butterfly units, in particular actual ones, in order to obtain approximated rotation factors. In other words, the method for the approximate calculation of butterfly units of a Fourier transform of a signal is used to approximate the Fourier transform of each of the at least two input signals.The above statements regarding the method for the approximate calculation of butterfly units of a Fourier transform of a signal thus also apply to the method for training and / or executing a convolutional neural network, to which reference is hereby made. Consequently, the fast Fourier transform is preferably approximated by quantizing rotation factors. When approximating the Fourier transform, multiplication by rotation factors is replaced by a conditional decision when quantizing into P sub-domains (see details above).

[0084] Preferably, one dimension of the input signals is arbitrary. However, the at least two input signals should have the same dimension, particularly preferably either 1D or 2D. The at least two input signals preferably have the same dimension, but can have different lengths with regard to their entries in one of the dimensions. The dimensions and thus also the length of the entries in the dimensions must be aligned. This can be achieved by inserting zeros (zero padding) in order to align the dimensions of the at least two input signals. For example, in the 1D case it is the length of the input signals that must be aligned. In the 2D case, for example, a height and a width of the input signals would have to be aligned. The terms filter kernel and convolution kernel are synonymous. This is a vector or a matrix that is convolved with an input signal.A CNN ultimately applies a large number of filters in the convolutional layers to an input using convolution. For example, convolution kernels typically have smaller dimensions than the input values, which should be adjusted to match each other before applying the AFFT, as just described.

[0085] Fig. 11 and Fig. 12 show the basic process of approximate convolution for 1D and 2D input signals. Fig. 11 and Fig. 12 represent the convolution after adjusting the dimensions of the two inputs. According to Fig. 11, two 1D input values ​​are convolved and Fig. 12 two 2D input values ​​are convolved. Both Fig. 11 and Fig. 12, after providing the input values ​​200, the approximate Fourier transform AFFT 210 is calculated, followed by a Hadamard product 220 and the approximate inverse fast Fourier transform (iAFFT) 230 is calculated. Finally, a single output signal 240 is output, which has the same dimension as the two input values ​​200.

[0086] Preferably, the convolution is calculated in a forward pass of the convolution-based neural network between at least one first input value (Input 1) of a neural layer of a first input signal 200a of the at least two input signals 200 and convolution kernels 200b of the neural layer. Convolution kernels are formed by a second input signal 200b of the at least two input signals 200 in the Fig. 11 and Fig. 12. Since the convolution kernels 200b typically have smaller dimensions than the first input signal 200a, the signals 200a and 200b must be aligned before applying the AFFT. This can be achieved by inserting zeros (zero padding).

[0087] Preferably, the convolution is calculated in a backward pass of the convolution-based neural network between input values ​​(Input 1) of a neural layer of a first input signal 200a of the at least two input signals 200 and error gradients 200b (Input 2) as well as the convolution between filter kernels 200a (Input 1) and the error gradients 200b (Input 2). Error gradients 200b are formed by a second input signal 200b of the at least two input signals 200 in the Fig. 11 and Fig. 12. The backward step consists of the convolution between the input data 200a of the respective layer (Input 1) and the error gradients 200b (Input 2), as well as the convolution between the filter kernels 200a (Input 1) and the error gradients 200b (Input 2). Here, too, an adjustment of the dimensions may be necessary.

[0088] Here, the same reference symbol is used for the terms convolution kernel 200b, error gradient 200b and second input value 200b in order to Fig. 11 and Fig. 12 shows that, depending on whether a backward pass or a forward pass of the convolutional neural network occurs, the second input signal 200b has a different physical meaning, but it is always an input signal 200. The same applies analogously to the terms filter kernel 200a, input data 200a, and first input signal 200a.

[0089] The folding itself is preferably carried out in one dimension (1D) (see Fig. 11) or in two dimensions (2D) (see Fig. 12). Dimensions higher than 2D would also be conceivable.

[0090] Preferably, in a two-dimensional (2D) convolution of the convolution-based neural network, the approximated fast Fourier transform 210 (AFFT) is first applied to all rows 310 of the two-dimensional input signal 200 and then to all columns 320 of an intermediate result. It is conceivable to use an overlap-and-save or an overlap-and-add convolution during the convolution. These convolutions involve decomposition of the input signal, application of the AFFT-based convolution to the segments and the filter kernel, and finally recombination using overlap-and-add or overlap-and-save. For 2D CNNs, a 2D AFFT is performed, which approximates a 2D FFT. The 2D AFFT is Fig. 13 realized by the ordinary AFFT. Fig. 13 shows the flow of the 2D-AFFT, which corresponds to the blocks 210 in Fig. 12 correspond.

[0091] The method for training and / or executing a convolutional neural network can also be implemented by a circuit for performing convolutions during the training and / or execution of a convolutional neural network. The circuit for performing convolutions during the training and / or execution of a convolutional neural network (CNN) using an approximate fast Fourier transform (AFFT), which is implemented on an FPGA, in particular as an ASIC or as part of a system-on-chip (SoC), is designed to perform the method for training and / or executing a convolutional neural network.In particular, the circuit for performing convolutions during the training and / or execution of a convolution-based neural network implements a circuit for the approximate calculation of butterfly units of a Fourier transform of a signal. The circuit for training and executing a convolution-based neural network also includes additional components, the basic functionalities of which should be familiar to those skilled in the art and will therefore not be described further.

[0092] A further aspect includes a computer program product comprising instructions that, when executed by a computer, cause the computer to perform the method for training and / or executing a convolutional neural network.

[0093] The described method for training and / or executing a convolutional neural network can significantly reduce the number of arithmetic operations required to calculate convolutional layers in 1D and 2D CNNs, thus significantly reducing the computational complexity and resource consumption of entire networks during inference and training, and increasing the computational speed. This represents a key advantage of the method for training and / or executing a convolutional neural network, or rather, the circuitry for performing convolutions during training and / or executing a convolutional neural network. The method can be implemented on software-programmable processors and in the form of dedicated hardware architectures on FPGAs or as ASICs. Furthermore, the method can be integrated into systems-on-chips (SoCs) in the form of software-programmable hardware acceleration.By applying the convolution theorem and calculating the approximate convolution using the AFFT, it is possible to implement the transformations between the time and frequency domains required for resource-efficient convolution in the frequency domain (Hadamard product = pointwise multiplication) with or without a reduced number of multiplications. Most importantly, hardware multipliers are not required. This increases energy efficiency and performance.

[0094] Technical applications of the method for training and / or executing a convolutional neural network can be found in all areas where CNNs are to be deployed on resource-constrained embedded and edge systems in the form of software, e.g., on microprocessors and embedded GPUs, or digital hardware, e.g., as ASICs or FPGAs. Integration as software-programmable hardware acceleration in SoCs is also conceivable. It is particularly noteworthy that the described method for training and / or executing a convolutional neural network can be used for both inference and training of CNNs.

[0095] The method for training and / or executing a convolutional neural network can be applied in areas where CNN inference plays a role, for example, in image processing, particularly in object recognition in autonomous driving or person tracking in camera systems, or in audio signal processing applications, particularly in natural language processing (NLP) for keyword recognition and voice assistance systems. The method for training and / or executing a convolutional neural network can also be beneficially used for intelligent sensor technology in the field of predictive maintenance with CNN-based signal processing in the sensor for diagnostic and prognostic tasks.

[0096] Furthermore, the method for training and / or executing a convolutional neural network enables resource-efficient training of CNNs, which can be used in the field of autonomous, self- or unsupervised learning systems. This can be used, for example, for trainable data compression using autoencoders.

[0097] One application area in the field of predictive maintenance is the autonomous learning of the prediction of the remaining service life of critical machine components, such as rolling bearings or tools in CNC machines. Data annotation can be performed autonomously by timestamping recorded data during the lifetime of the critical component by the embedded system and determining the end of the component's service life with the help of external information (e.g., from the machine control system) or unsupervised clustering methods. Since large amounts of data are recorded over the lifetime of the component, which cannot be efficiently cached or transmitted due to limited storage resources of embedded and edge systems, trainable data compression using CNN-based autoencoders can also be used here.

[0098] In the field of robotics, tasks and skills must also be learned and expanded adaptively. One example is a robot arm equipped with a camera for sorting objects based on adaptively learned object recognition, incorporating distance information acquired by additional distance sensors during operation.

[0099] Although some aspects have been described in the context of a method, it should be understood that these aspects also represent a description of a corresponding apparatus, so that a block or component of an apparatus can also be understood as a corresponding method step or as a feature of a method step, and vice versa. A representation of the present invention in terms of an apparatus is omitted here for reasons of redundancy. Some or all of the method steps could be performed by (or using) a hardware apparatus, such as a microprocessor, a programmable computer, or an electronic circuit. In some embodiments, some or more of the key method steps can be performed by such an apparatus.

[0100] In the foregoing Detailed Description, various features have been grouped together in examples in order to streamline the disclosure. This manner of disclosure should not be interpreted as intending that the claimed examples include more features than are expressly recited in each claim. Rather, as the following claims reflect, the subject matter may lie in fewer than all of the features of a single disclosed example. Accordingly, the following claims are hereby incorporated into the Detailed Description, with each claim being capable of standing as its own separate example.While each claim may stand as its own separate example, it should be noted that although dependent claims in the claims refer to a specific combination with one or more other claims, other examples also include a combination of dependent claims with the subject matter of any other dependent claim or a combination of any feature with other dependent or independent claims. Such combinations are intended to be encompassed unless it is stated that a specific combination is not intended. Furthermore, it is intended to encompass a combination of features of a claim with any other independent claim, even if that claim is not directly dependent on the independent claim.

[0101] Depending on specific implementation requirements, embodiments of the invention may be implemented in hardware or in software, or at least partially in hardware or at least partially in software. The implementation may be carried out using a digital storage medium, for example a floppy disk, a DVD, a Blu-ray disc, a CD, a ROM, a PROM, an EPROM, an EEPROM, or a FLASH memory, a hard disk, or other magnetic or optical storage device on which electronically readable control signals are stored that can interact or interact with a programmable computer system in such a way that the respective method is carried out. Therefore, the digital storage medium embodying the proposed teaching may be computer-readable.

[0102] Some embodiments according to the teachings described herein thus comprise a data carrier having electronically readable control signals capable of interacting with a programmable computer system such that one of the features described herein is performed as a method.

[0103] In general, embodiments of the teachings described herein may be implemented as a computer program product having program code, wherein the program code is operable to perform one of the methods when the computer program product is run on a computer.

[0104] The program code can, for example, also be stored on a machine-readable medium.

[0105] Other embodiments include the computer program for performing one of the features described herein as a method, wherein the computer program is stored on a machine-readable medium. In other words, one embodiment of the method according to the invention is thus a computer program that has program code for performing one of the methods described herein when the computer program is executed on a computer.

[0106] A further embodiment of a proposed method is thus a data carrier (or a digital storage medium or a computer-readable medium) on which the computer program for performing one of the features described herein is recorded as a method. The data carrier or the digital storage medium or the computer-readable medium is typically tangible and / or non-transitory.

[0107] A further embodiment of the proposed method is thus a data stream or a sequence of signals that represents the computer program for performing one of the methods described herein. The data stream or sequence of signals can be configured, for example, to be transferred via a data communication connection, for example, via the Internet.

[0108] A further embodiment comprises a processing device, for example a computer or a programmable logic device, which is configured or adapted to carry out a method for the system described herein.

[0109] A further embodiment comprises a computer on which the computer program for carrying out the method for the system described herein is installed.

[0110] A further embodiment according to the invention comprises a device or a system designed to transmit a computer program for performing at least one of the features described herein in the form of a method to a recipient. The transmission can be electronic or optical, for example. The recipient can be, for example, a computer, a mobile device, a storage device, or a similar device. The device or system can, for example, comprise a file server for transmitting the computer program to the recipient.

[0111] In some embodiments, a programmable logic device (e.g., a field-programmable gate array, an FPGA) may be used to perform some or all of the functionalities of the methods and devices described herein. In some embodiments, a field-programmable gate array may interact with a microprocessor to perform the method described herein. Generally, in some embodiments, the method is performed by any hardware device. This may be general-purpose hardware such as a computer processor (CPU) or method-specific hardware such as an ASIC.

[0112] The above-described embodiments are merely illustrative of the principles of the present invention. It is understood that modifications and variations of the arrangements and details described herein will be apparent to others skilled in the art. Therefore, it is intended that the invention be limited only by the scope of the following claims and not by the specific details presented in the description and explanation of the embodiments herein. State of the art [1] M. Horowitz, “1.1 Computing's Energy Problem (and what we can do about it),” 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014. [2] JG Proakis and DG Manolakis, Digital Signal Processing (3rd ed.): Principles, Algorithms, and Applications, Prentice-Hall, Inc., 1996. [3] J. W. Cooley und J. W. Tukey, „An Algorithm for the Machine Calculation of Complex Fourier Series,“ 1965. [4] J. W. Cooley, P. A. W. Lewis und P. D. Welch, „Historical Notes on the Fast Fourier Transform,“ 1967. [5] J. W. Cooley, P. A. W. Lewis und P. D. Welch, „The Fast Fourier Transform and its Applications,“ 1969. [6] W. Liu, Q. Liao, F. Qiao, W. Xia, C. Wang und F. Lombardi, „Approximate Designs for Fast Fourier Transform (FFT) With Application to Speech Recognition,“ IEEE Transactions on Circuits and Systems I: Regular Papers, 2019. [7] Q. Liao, W. Liu, F. Qiao, C. Wang und F. Lombardi, „Design of Approximate FFT with Bit-width Selection Algorithms,“ 2018 IEEE International Symposium on Circuits and Systems (ISCAS),, 2018. [8] R. Teymourzadeh, M. J. Abigo und M. V. Hoong, „Static quantised radix-2 fast Fourier transform (FFT) / inverse FFT processor for constraints analysis,“ International Journal of Electronics, 2013. [9] S. C. Chan und P. M. Yiu, „An efficient multiplierless approximation of the fast Fourier transform using sum-of-powers-of-two (SOPOT) coefficients,“ IEEE Signal Processing Letters, 2002.

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[27] T. Abtahi, C. Shea, A. Kulkarni und T. Mohsenin, „Accelerating Convolutional Neural Network with FFT on Embedded Hardware,“ 2018.

Claims

[1] Method for the approximate calculation of butterfly units of a Fourier transform of a signal in which a binary or ternary quantization is carried out, the method comprising: Representing a number of butterfly units of a Fourier transform; approximating the number of butterfly units by quantizing rotation factors associated with the butterfly units to obtain approximated rotation factors, wherein a bit width of a quantized, approximated rotation factor is less than or equal to 8 bits, wherein in a binary or ternary quantization the method comprises: minimizing an error between the approximated rotation factors and the rotation factors by using a correction factor α, wherein the correction factor α is an α-priori known constant not equal to 1. [2] Method according to claim 1, wherein in a ternary quantization a parameter t ∈ [0, 1] defines a threshold value which divides an interval [-1, 1] into three sub-ranges by application in the positive and negative range. [3] A method according to any one of claims 1 or 2, wherein the quantization is applied to a real part and an imaginary part of the rotation factors. [4] A method according to claim 1, which comprises: Forming a derivative of the error to be minimized; and Performing at least one equivalence transformation to obtain an expression for the correction factor α, in particular for an optimal correction factor α opt , to obtain. [5] A method according to any one of claims 1 or 4, comprising: selecting the threshold value t to an arbitrary correction factor α. [6] Method according to one of the preceding claims, wherein threshold values ​​or quantization values ​​for approximating the rotation factors are selected such that the approximated rotation factors can be written as a power of two or as a sum of powers of two. [7] A method according to any one of the preceding claims, wherein each butterfly unit of the plurality of butterfly units has a different number of input values ​​or an equal number of input values. [8] Method according to one of the preceding claims, wherein the method is carried out on the basis of the fast Fourier transform FFT. [9] Method according to one of the preceding claims, wherein the method is feasible for 1D-FFT or 2D-FFT. [10] Circuit for the approximate calculation of butterfly units of a Fourier transform of a signal, the circuit being designed to carry out a method according to one of claims 1 to 9, the circuit comprising: a number of M:1 multiplexers, where M=2, ..., 256 is a natural number, wherein the circuit is configured to replace a multiplication based on a quantization of rotation factors associated with butterfly units without actual hardware multipliers before a signal flow by at least one multiplexer of the number of multiplexers. [11] Circuit according to claim 10, which is designed to calculate an output signal at a multiplexer with a second input value. [12] Circuit according to claim 10 or 11, which is designed to calculate a real part and an imaginary part of the output signal at the multiplexer with a correction factor α before calculating it with the second input value. [13] Circuit according to one of claims 10 to 12, wherein a bit width of the input values ​​is arbitrary, in particular can be represented as an integer or as a floating point number. [14] Circuit according to one of claims 10 to 13, wherein the circuit is implemented as an FPGA, in particular as an ASIC or as part of a System on Chips (SoCs). [15] Circuit according to one of claims 10 to 14, wherein the circuit is designed to carry out a method according to one of claims 1 to 9. [16] A computer program product comprising instructions which, when executed by a computer, cause the computer to carry out the method according to any one of claims 1 to 9.

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