BALL GRID ARRANGEMENT FOR AN INTEGRATED SWITCHING DEVICE AND A SWITCHING PACKAGE SYSTEM AND METHOD TO DO THIS

Abstract

Integrated circuit device (100'), comprising: an integrated circuit (102) comprising at least one package substrate (202) and a silicon chip (204); and a sphere grid arrangement (104) arranged on the package substrate (202) of the integrated circuit, wherein the sphere grid arrangement (104) comprises the following: a first set of solder balls (502, 504, 506, 508, 522, 524, 526, 528) configured to provide electrical connections for communication channels associated with the silicon chip (204), and a second set of solder balls (510) associated with an electrical ground and / or electrical power for the silicon chip (204), where the electrical connections are the first electrical connections, and wherein the sphere grid arrangement (104) includes a third set of solder balls configured to provide secondary electrical connections for auxiliary signals associated with the silicon chip (204), and wherein at least one solder ball from the second set of solder balls (510) is arranged between the first set of solder balls (502, 504, 506, 508, 522, 524, 526, 528) and the third set of solder balls, and where the packet substrate (202) defines a first page, a second page, a third page and a fourth page, and wherein the first set of solder balls (502, 504, 506, 508, 522, 524, 526, 528) is arranged along the first side, the second side and the third side of the packet substrate (202), and wherein the third set of solder balls is arranged along the fourth side of the package substrate (202).

Description

TECHNOLOGICAL AREA

[0001] Embodiments of the present invention generally relate to a sphere grid arrangement pattern for an integrated circuit device and for an integrated circuit package system, as well as a method based thereon. BACKGROUND

[0002] A ball-grid array is a type of electrical interconnect for an integrated circuit (ICC) that is mounted on a surface (e.g., a substrate) of the IC. The solder balls of a ball-grid array are generally arranged in a grid pattern on the underside of the IC. However, conventional grid-arranged ball-grid arrays are generally prone to interference between the solder balls, inefficient performance for communication channel links associated with the array, and / or inefficient power consumption for the IC. Therefore, an improved ball-grid array for an IC is desirable. US 2014 / 0293566A1 refers to a printed circuit board (PCB) that includes a substrate, a first ground electrode group, and a first pair of signal electrodes.The first ground electrode group comprises a plurality of first ground electrodes, each of the plurality of first ground electrodes being located at a corresponding vertex of a first rectangular region on a surface of the substrate. The first pair of signal electrodes is located within the first rectangular region and is oriented in a first direction parallel to one side of the first rectangular region. US 2013 / 0 087 918 A1 relates to a system and method for allocating power and ground pins and one-sided or differential signal pairs for a ball grid array semiconductor package. US 2011 / 0 192 640 A1 relates to an interconnect pattern for high-power interfaces. US 2016 / 0 150 638 A1 relates to an interconnect array pattern with a 3:1 signal-to-ground ratio.US 2005 / 0040536A1 refers to a semiconductor chip package with reduced crosstalk between adjacent signals in a layer of a substrate. US 2018 / 0331035A1 refers to a microprocessor package with a first layer featuring a bump-ground web structure. BRIEF SUMMARY

[0003] The invention is defined by independent claims 1, 16 and 22. To illustrate the invention, aspects and embodiments that may or may not fall within the scope of the claims are described here.

[0004] Exemplary embodiments of the present invention relate generally to systems, methods, and devices for providing an improved sphere lattice arrangement pattern for an integrated circuit. Details of some embodiments of the subject matter described herein are set forth in the accompanying drawings and the following description. Further features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.

[0005] In one embodiment, an integrated circuit comprises an integrated circuit and a sphere grid arrangement. The integrated circuit comprises at least one package substrate and a silicon chip. Furthermore, the sphere grid arrangement is arranged on the package substrate of the integrated circuit. In one or more embodiments, the sphere grid arrangement comprises a first set of solder balls configured to provide electrical connections for communication channels associated with the silicon chip, and a second set of solder balls associated with an electrical ground and / or electrical power for the silicon chip.In one or more embodiments, the first set of solder balls comprises a first subset of solder balls configured in a first orientation and a second subset of solder balls configured in a second orientation that differs from the first orientation. In one or more embodiments, at least one solder ball from the second set of solder balls is positioned between the first subset of solder balls and the second subset of solder balls.

[0006] In one or more embodiments, the first set of solder balls also comprises a third subset of solder balls configured in the first orientation and a fourth subset of solder balls configured in the second orientation.

[0007] In one or more embodiments, at least one further solder ball from the second set of solder balls is arranged between the third subset of solder balls and the fourth subset of solder balls.

[0008] In one or more embodiments, at least one further solder ball from the second set of solder balls is arranged between the second subset of solder balls and the third subset of solder balls.

[0009] In one or more embodiments, the first and second sets of solder balls are associated with transmitter communication channels. Furthermore, in one or more embodiments, the third and fourth sets of solder balls are associated with receiver communication channels.

[0010] In one or more embodiments, the first set of solder balls is surrounded by solder balls from the second set of solder balls.

[0011] In one or more embodiments, the electrical connections are the first electrical connections. In one or more embodiments, the ball grid arrangement also includes a third set of solder balls configured to provide second electrical connections for a power supply associated with the silicon chip.

[0012] In one or more embodiments, at least one further solder ball from the second set of solder balls is arranged between the first set of solder balls and the third set of solder balls.

[0013] In one or more embodiments, the package substrate defines a first side, a second side, a third side, and a fourth side. Furthermore, in one or more embodiments, the first set of solder balls is arranged along the first side, the second side, and the third side of the package substrate. Additionally, in one or more embodiments, the third set of solder balls is arranged along the fourth side of the package substrate.

[0014] In one or more embodiments, the electrical connections are the first electrical connections. In one or more embodiments, the ball grid arrangement also includes a third set of solder balls configured to provide second electrical connections for auxiliary signals associated with the silicon chip.

[0015] In one or more embodiments, at least one further solder ball from the second set of solder balls is arranged between the first set of solder balls and the third set of solder balls.

[0016] In one or more embodiments, the package substrate defines a first side, a second side, a third side, and a fourth side. Furthermore, in one or more embodiments, the first set of solder balls is arranged along the first side, the second side, and the third side of the package substrate. Additionally, in one or more embodiments, the third set of solder balls is arranged along the fourth side of the package substrate.

[0017] In one or more embodiments, the second orientation, which is associated with the second subset of solder balls, is perpendicular to the first orientation, which is associated with the first subset of solder balls.

[0018] In one or more embodiments, the sphere grid arrangement is arranged between the package substrate and a printed circuit board.

[0019] In one or more embodiments, the integrated circuit is an integrated circuit of a network switch, wherein the sphere grid arrangement is arranged between the network switch and a carrier circuit board.

[0020] In one or more embodiments, the integrated circuit is an integrated circuit for a network adapter.

[0021] In one or more embodiments, the integrated circuit is configured as a graphics processing unit.

[0022] In another embodiment, an integrated circuit system comprises an integrated circuit, a printed circuit board, and a sphere grid arrangement. The integrated circuit comprises at least one package substrate and a silicon chip. Furthermore, the sphere grid arrangement is positioned between the package substrate of the integrated circuit and the printed circuit board. In one or more embodiments, the sphere grid arrangement comprises a first set of solder balls configured to provide electrical connections for communication channels associated with the silicon chip, and a second set of solder balls associated with an electrical ground and / or electrical power supply for the silicon chip.In one or more embodiments, the first set of solder balls associated with the communication channels comprises a first subset of solder balls configured in a first orientation and a second subset of solder balls configured in a second orientation that differs from the first orientation. In one or more embodiments, at least one solder ball from the second set of solder balls is positioned between the first subset of solder balls and the second subset of solder balls.

[0023] In one or more embodiments, the first set of solder balls comprises a third subset of solder balls configured in the first orientation and a fourth subset of solder balls configured in the second orientation.

[0024] In one or more embodiments, at least one further solder ball from the second set of solder balls is arranged between the third subset of solder balls and the fourth subset of solder balls.

[0025] In one or more embodiments, at least one further solder ball from the second set of solder balls is arranged between the second subset of solder balls and the third subset of solder balls.

[0026] In one or more embodiments, the first set of solder balls and the second set of solder balls are connected to transmitter communication channels. Furthermore, in one or more embodiments, the third set of solder balls and the fourth set of solder balls are connected to receiver communication channels.

[0027] In a further embodiment, a method is provided. The method involves configuring an electrical signal via a silicon chip of an integrated circuit.The method also provides for the transmission of the electrical signal to a printed circuit board via a sphere grid arrangement arranged on the integrated circuit, wherein the sphere grid arrangement comprises a first set of solder balls configured to provide electrical connections for communication channels associated with the silicon chip, and a second set of solder balls associated with an electrical ground and / or electrical power for the silicon chip, the first set of solder balls comprising a first subset of solder balls configured in a first orientation, and a second subset of solder balls configured in a second orientation that differs from the first orientation, and at least one solder ball from the second set of solder balls is arranged between the first subset of solder balls and the second subset of solder balls.

[0028] A ball lattice array pattern for an integrated circuit is disclosed. An example of an integrated circuit device includes an integrated circuit and a ball lattice array. The integrated circuit comprises at least one package substrate and a silicon chip. The ball lattice array is arranged on the package substrate of the integrated circuit. The ball lattice array includes a first set of solder balls configured to provide electrical connections for communication channels and a second set of solder balls associated with an electrical ground. The first set of solder balls includes a first subset of solder balls configured in a first orientation and a second subset of solder balls configured in a second orientation.Furthermore, at least one solder ball from the second set of solder balls is arranged between the first subset of solder balls and the second subset of solder balls.

[0029] Each feature of an aspect or embodiment can be applied to other aspects or embodiments in any suitable combination. In particular, each feature of a process aspect or embodiment can be applied to a device aspect or embodiment, and vice versa.

[0030] The above summary is intended only to provide a basic understanding of some aspects of the present invention. Accordingly, it should be noted that the embodiments described above are only examples and should not be interpreted as limiting the scope or spirit of the present invention in any way. It should be borne in mind that the scope of the present invention includes many possible embodiments in addition to those summarized here, some of which are described further below. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Following this general description of the revelation, reference is now made to the accompanying drawings, which are not necessarily to scale and in which the following revelation is depicted: Fig. Figure 1 shows an exemplary system in conjunction with an integrated circuit comprising a sphere grid arrangement according to one or more embodiments of the present disclosure; Fig. Figure 2 shows another exemplary system in conjunction with an integrated circuit comprising a sphere grid arrangement according to one or more embodiments of the present disclosure; Fig. Figure 3 shows an example of an integrated circuit package system according to one or more embodiments of the present disclosure; Fig. 4 shows an example of a sphere grid arrangement according to one or more embodiments of the present disclosure; Fig. 5 shows another example of a sphere lattice arrangement according to one or more embodiments of the present disclosure; Fig. 6 shows another example of a sphere lattice arrangement according to one or more embodiments of the present disclosure; Fig. 7 shows another example of a sphere lattice arrangement according to one or more embodiments of the present disclosure; Fig. Figure 8 shows another example of a sphere lattice arrangement according to one or more embodiments of the present disclosure; Fig. Figure 9 is a flowchart illustrating an exemplary method for facilitating the transmission of an electrical signal across a spherical grid arrangement, which shows part of one or more embodiments of the present disclosure; and Fig. Figure 10 shows an example of a computer system that can be embedded in an integrated circuit, in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0032] Exemplary embodiments are described in more detail below with reference to the accompanying drawings, which illustrate some, but not all, embodiments. The embodiments can, in fact, take many different forms and should not be understood as limited to those presented here. The same reference numbers refer to the same elements throughout. The terms "exemplary" and "example" used here are not intended to make a qualitative assessment but merely to illustrate an example. Therefore, the use of such terms should not be understood as limiting the core and scope of the embodiments of the present invention.

[0033] A ball grid array is a type of electrical interconnect for an integrated circuit that is mounted on a surface (e.g., a substrate) of the integrated circuit. The solder balls of a ball grid array are generally arranged in a grid pattern on the bottom of the integrated circuit. In a conventional ball grid array, for example, the grounded solder balls are arranged in parallel rows and columns between the pairs of solder balls associated with the communication channel connections. However, conventional, grid-arranged ball grid arrays are generally prone to interference between the solder balls, inefficient performance for the communication channel connections associated with the ball grid array, and / or inefficient power consumption for an integrated circuit associated with the ball grid array.

[0034] In one embodiment relating to high-speed communication systems (e.g., servers in data centers), a ball grid array can be used to connect an integrated circuit of a switch (e.g., a network switch, an optical switch, etc.) to a carrier printed circuit board. Furthermore, the ball grid array can provide contacts for transmitted channel signals, received channel signals, power, and / or auxiliary connections such as Peripheral Component Interphase Express (PCIE) connectors. However, the arrangement of solder balls in a conventional ball grid array used to connect an integrated circuit of a switch to a carrier printed circuit board generally results in interference and / or crosstalk between one or more signals transmitted via the ball grid array.

[0035] To solve these and / or other problems, an improved ball grid array for an integrated circuit (e.g., an integrated switch) is disclosed herein. In one or more embodiments disclosed herein, a ball grid array pattern is provided that offers effective differential interference suppression between one or more signals transmitted via the ball grid array. In one or more embodiments, a ball grid array pattern disclosed herein is an array of solder balls that connects an integrated circuit (e.g., a switch or other type of networked integrated circuit) to a carrier printed circuit board to provide an optimal ball grid array package for the integrated circuit.According to various embodiments of the sphere grid array pattern disclosed herein, the performance of communication channels (e.g., high-speed communication channels) of an integrated circuit and / or the power management of an integrated circuit is improved compared to a conventional integrated circuit using a conventional sphere grid array. Thus, in one or more embodiments, improved performance and / or improved efficiency of an integrated circuit is provided. For example, in one or more embodiments, an integrated circuit is provided with improved electrical connections, improved signal integrity, reduced crosstalk between signals, improved DC power integrity, and / or improved AC power integrity.Furthermore, in one or more embodiments, the sphere grid arrangement pattern disclosed herein enables a cost reduction for an integrated circuit and / or a switch housing by reducing the number of printed circuit board layers and / or by increasing the sphere grid arrangement density.

[0036] Fig. Figure 1 shows a system 100 that incorporates an integrated circuit with a ball lattice array according to one or more embodiments of the present disclosure. In one or more embodiments, the system 100 is a package system for integrated circuits. The system 100 comprises an integrated circuit 102. The integrated circuit 102 can, for example, be an integrated circuit of a switch. The integrated circuit 102 can, for example, be an integrated circuit of a network switch, an optical switch, or another type of switch. In one example, the integrated circuit can be an application-specific integrated circuit of an Ethernet switch. However, in certain embodiments, the integrated circuit 102 can also be a different type of integrated circuit for a different type of technical application associated with a ball lattice array.In one or more embodiments, the system 100 can, for example, be an integrated circuit package system for a network adapter. In one example, the integrated circuit 102 can be connected to a network adapter. Alternatively, in one or more embodiments, the system 100 can be an integrated circuit package system for a graphics processing unit (GPU). For example, the integrated circuit 102 can be connected to a GPU and / or configured as a GPU.

[0037] The integrated circuit 102 comprises a sphere grid array 104. In one or more embodiments, the sphere grid array 104 is arranged, for example, on the integrated circuit 102 to facilitate electrical connections for the integrated circuit 102. The sphere grid array 104 can be configured in a sphere grid array pattern to enable interference suppression (e.g., reduction of crosstalk) between electrical signals transmitted via the sphere grid array 104. In one embodiment, the sphere grid array 104 can be arranged on the integrated circuit 102 using a fluxed sphere grid array mounting technique combined with flux adhesive, a solder paste sphere grid array mounting technique combined with solder paste, and / or another type of sphere grid array mounting technique combined with an adhesive.For example, in one embodiment, the solder balls of the ball grid arrangement 104 can be placed on corresponding adhesive deposits (e.g., flux deposits, solder paste deposits, etc.) applied to the integrated circuit 102. However, it is understood that in certain embodiments, a different type of ball grid arrangement technique can be used to arrange the ball grid arrangement 104 on the integrated circuit 102.

[0038] Fig. Figure 2 shows a system 100' that provides an integrated circuit with a sphere grid array according to one or more embodiments of the present disclosure. In one or more embodiments, the system 100' is an alternative embodiment of the system 100. The system 100' comprises the integrated circuit 102 and the sphere grid array 104. Furthermore, in one embodiment, the integrated circuit 102 comprises a packet substrate 202 and a silicon chip 204. The silicon chip 204 can be configured for network communication (e.g., optical communication, Ethernet, InfiniBand, etc.), Ethernet switching, Internet Protocol (IP) switching, sender communication, receiver communication, cloud computing, high-performance computing, machine learning, data storage, enterprise data centers, network security, network detection and response, network power distribution, and / or one or more technologies.Furthermore, the silicon chip 204 can include one or more processing units for the integrated circuit 102, such as one or more processor cores of the integrated circuit, one or more integrated circuit chips, one or more data processing units, one or more processors, one or more central processing units, one or more microprocessors, and / or one or more other processing units. In one or more embodiments, the silicon chip 204 can be configured for one or more integrated circuit applications (e.g., one or more high-speed integrated circuit applications) to provide a larger number of serial signals (e.g., high-speed serial signals) to be transmitted with improved signal integrity.

[0039] In one or more embodiments, the sphere grid arrangement 104 can be arranged on the package substrate 202 of the integrated circuit 102 to facilitate electrical connections for the silicon chip 204 of the integrated circuit 102. In one or more embodiments, the sphere grid arrangement 104 can be arranged on the package substrate 202 of the integrated circuit 102 to facilitate electrical connections for communication channels associated with the silicon chip 204. For example, the sphere grid arrangement 104 can be arranged on the package substrate 202 of the integrated circuit 102 to facilitate electrical connections for transmitter communication channels (e.g., send-side communication channels) associated with the silicon chip 204 and / or receiver communication channels (e.g., receiver-side communication channels) associated with the silicon chip 204.Additionally or alternatively, the sphere grid arrangement 104 can be arranged on the package substrate 202 of the integrated circuit 102 to facilitate electrical connections for the electrical ground of the silicon chip 204. Additionally or alternatively, the sphere grid arrangement 104 can be arranged on the package substrate 202 of the integrated circuit 102 to facilitate electrical connections for the power supply associated with the silicon chip 204. Additionally or alternatively, the sphere grid arrangement 104 can be arranged on the package substrate 202 of the integrated circuit 102 to facilitate electrical connections for auxiliary signals (e.g., PCIE connections) associated with the silicon chip 204. In certain embodiments, the package substrate 202 can have one or more vias (e.g.,The package substrate 202 may contain one or more electrical via connections, one or more through-holes through the silicon, one or more microvias, etc., to enable one or more electrical connections between the sphere grid assembly 104 and the silicon chip 204. Additionally or alternatively, the package substrate 202 may have one or more electrical conductors on one or more surfaces of the package substrate 202 to facilitate one or more electrical connections between the sphere grid assembly 104 and the silicon chip 204.

[0040] In one embodiment, the ball grid assembly 104 can be arranged on the package substrate 202 using a flux-adhesive-associated fluxing ball grid assembly technique, a solder paste-associated solder paste ball grid assembly technique, and / or another type of ball grid assembly technique associated with an adhesive. For example, in one embodiment, the solder balls of the ball grid assembly 104 can be placed on corresponding adhesive deposits (e.g., flux deposits, solder paste deposits, etc.) on the package substrate 202.

[0041] In certain embodiments, the silicon chip 204 can be mounted on the package substrate 202 via a first-level interconnect (FLI) 203, which mechanically and / or electrically connects the silicon chip 204 to the package substrate 202. In one or more embodiments, the FLI 203 can be a flip-chip FLI. In one embodiment, the FLI 203 can include a set of solder balls that establish a connection between a set of metal contacts on the silicon chip 204 and a set of metal contacts on the package substrate 202. In another embodiment, the FLI 203 can be attached to the package substrate 202 and / or the silicon chip 204 by means of a flux, solder paste, and / or another type of adhesive. For example, in one embodiment, the solder balls of the FLI 203 can be pressed onto appropriate adhesive deposits (e.g., flux deposits, solder paste deposits, etc.).) are placed on the package substrate 202 and / or the silicon chip 204. In certain embodiments, the integrated circuit 102 may additionally include an underfill section 205 configured to distribute the thermal expansion differences between the silicon chip 204 and the package substrate 202. In one or more embodiments, the underfill section 205 includes an epoxy polymer that fills one or more spaces between the silicon chip 204 and the package substrate 202.

[0042] Fig. Figure 3 shows a system 300, which is an integrated circuit package system according to one or more embodiments of the present disclosure. In one or more embodiments, the system 300 can be an integrated circuit package system. The system 300 comprises the integrated circuit 102, the sphere grid arrangement 104, and a printed circuit board 302. In certain embodiments, the integrated circuit 102 comprises the package substrate 202 and the silicon chip 204. In one embodiment, the integrated circuit 102 can be attached to the printed circuit board 302 via the sphere grid arrangement 104. For example, the sphere grid arrangement 104 can be arranged between the integrated circuit 102 (e.g., the package substrate 202 of the integrated circuit 102) and the printed circuit board 302. In one aspect, the sphere grid arrangement 104 can establish one or more electrical connections between the integrated circuit 102 and the printed circuit board 302.In certain embodiments, the printed circuit board 302 can be a carrier board for the integrated circuit 102. For example, the printed circuit board 302 can be a network switch board and / or a network router board (e.g., an Ethernet switch board and / or an Ethernet router board). In another example, the printed circuit board 302 can be a network adapter board. In another embodiment, the printed circuit board 302 can be a transceiver board. In yet another example, the printed circuit board 302 can be a board for a network adapter. In yet another example, the printed circuit board 302 can be a board for a GPU. However, it should be understood that in certain embodiments, the printed circuit board 302 can be a different type of printed circuit board. In one or more embodiments, the printed circuit board 302 can carry one or more electrical signals from the integrated circuit 102 (e.g.,from the silicon chip 204) via the spherical grid arrangement 104. Additionally or alternatively, in one or more embodiments, the printed circuit board 302 can transmit one or more electrical signals via the spherical grid arrangement 104 to the integrated circuit 102 (e.g., to the silicon chip 204). The one or more electrical signals transmitted between the integrated circuit 102 and the printed circuit board 302 via the spherical grid arrangement 104 can include one or more electrical signals associated with communication channels, one or more electrical signals associated with transmitter communication channels (e.g., transmitter-side communication channels), one or more electrical signals associated with receiver communication channels (e.g., receiver-side communication channels), or one or more electrical signals associated with auxiliary connections (e.g.,PCIE connections), one or more electrical signals associated with data, and / or one or more other electrical signals. In one or more embodiments, one or more modulated data signals can be transmitted between the integrated circuit 102 and the printed circuit board 302 via one or more communication channels connected to the sphere grid arrangement 104. For example, in one embodiment, one or more PAM data signals (e.g., one or more PAM2 data signals, one or more PAM4 data signals, etc.) can be transmitted between the integrated circuit 102 and the printed circuit board 302 via one or more communication channels connected to the sphere grid arrangement 104.It is also understood that in certain embodiments one or more other types of modulation data signals can alternatively be transmitted between the integrated circuit 102 and the printed circuit board 302 via one or more communication channels connected to the sphere grid arrangement 104.

[0043] Fig. Figure 4 shows an embodiment of the ball grid arrangement 104 according to one or more embodiments of the present disclosure. For example, a layout of solder balls for the ball grid arrangement 104 according to the one shown in Fig. The embodiment shown in Figure 4 can be configured. In one or more embodiments, the sphere grid arrangement 104 can be mounted on the integrated circuit 102 (e.g., the package substrate 202 of the integrated circuit 102) according to the embodiment shown in Figure 4. Fig. The configuration shown in section 4 is arranged. In one or more embodiments, the integrated circuit 102 (e.g., the package substrate 202 of the integrated circuit 102) defines a first page (e.g., FIRST PAGE in Fig. 4), a second page (e.g. SECOND PAGE in Fig. 4), a third page (e.g. THIRD PAGE in Fig. 4) and a fourth page (e.g. FOURTH PAGE in Fig. 4) In one embodiment, a set of solder balls of the ball grid arrangement 104 can be arranged along the first side, the second side, and the third side. Furthermore, another set of solder balls of the ball grid arrangement 104, different from the set of solder balls arranged along the first, second, and third sides, can be arranged along the fourth side.

[0044] In one embodiment, the solder balls for high-speed channels are arranged on three outer sides of a surface of the integrated circuit 102 (e.g., a surface of the package substrate 202 of the integrated circuit 102). Furthermore, solder balls for power supply and / or auxiliary signals can occupy a fourth side of the surface of the integrated circuit 102 (e.g., a surface of the package substrate 202 of the integrated circuit 102). As shown in Fig. As shown in Figure 4, the areas of the sphere grid arrangement 104 labeled "T" and "R" contain solder balls for connecting various signal pairs of transmitter communication channels (e.g., transmitter-side communication channels) and receiver communication channels (e.g., receiver-side communication channels). It is understood, however, that the positions of the T and R pairs can be interchanged. Furthermore, the areas labeled "A" of the sphere grid arrangement 104 may contain solder balls corresponding to auxiliary signals, the area labeled "B" may contain solder balls corresponding to power supply signals, and the area labeled "C" may contain solder balls corresponding to another type of electrical connection.In certain embodiments, the area designated “D” of the spherical grid arrangement 104 can contain solder balls corresponding to one or more electrical connections for a component layer of the printed circuit board 302. In certain embodiments, area “D” can be implemented without vias, since the solder balls for the power supply are located approximately in a central part of the spherical grid arrangement 104, thereby improving the performance of the integrated circuit 102.

[0045] Fig. Figure 5 shows an example of a sphere grid arrangement 104' according to one or more embodiments of the present disclosure. The sphere grid arrangement 104' can correspond to at least a part of the sphere grid arrangement 104. In one embodiment, the sphere grid arrangement 104' can represent an interference cancellation pattern associated with at least a part of the sphere grid arrangement 104. For example, the solder balls associated with the communication channels can be arranged in an interference cancellation pattern, thereby improving the performance of the communication channels and / or the integrated circuit 102.In one or more embodiments, the sphere grid arrangement 104' comprises a solder ball 502 associated with a communication channel such as a transmitter communication channel T1+, a solder ball 504 associated with a communication channel such as a transmitter communication channel T1-, a solder ball 506 associated with a communication channel such as a transmitter communication channel T2+, and a solder ball 508 associated with a communication channel such as a transmitter communication channel T2-. For example, the T1+ associated solder ball 502 and the T1- associated solder ball 504 can be differential pairs associated with communication channels connected to a transmitter. Furthermore, the solder ball 506 associated with T2+ and the solder ball 508 associated with T22- can additionally or alternatively be differential pairs associated with communication channels associated with a transmitter.Additionally or alternatively, in a further embodiment, the sphere grid arrangement 104' comprises a solder ball 522 associated with a communication channel such as a receiver communication channel R1+, a solder ball 524 associated with a communication channel such as a receiver communication channel R1-, a solder ball 526 associated with a communication channel such as a receiver communication channel R2+, and a solder ball 528 associated with a communication channel such as a receiver communication channel R2-. For example, the solder ball 522 associated with R1+ and the solder ball 524 associated with R1- can be differential pairs associated with communication channels assigned to a receiver. Furthermore, the solder ball 526 associated with R2+ and the solder ball 528 associated with R2- can additionally or alternatively be differential pairs associated with communication channels assigned to a receiver.The sphere grid arrangement 104' can also include a set of solder balls associated with electrical ground, such as the solder balls 510a-z.

[0046] In one or more embodiments, as in Fig. As shown in Figure 5, a first set of solder balls (e.g., solder ball 502, solder ball 504, solder ball 506, solder ball 508, solder ball 522, solder ball 524, solder ball 526, and / or solder ball 528) of the sphere grid arrangement 104' is configured to provide electrical connections for communication channels connected to the silicon chip 204. Furthermore, a second set of solder balls (e.g., one or more solder balls from the solder balls 510a-z) of the sphere grid arrangement 104' is connected to an electrical ground and / or electrical power for the silicon chip 204. In certain embodiments, the first set of solder balls is surrounded by one or more solder balls (e.g., one or more solder balls from the solder balls 510e-z) from the second set of solder balls.

[0047] In one embodiment, the first set of solder balls comprises a first subset of solder balls (e.g., solder ball 502 and solder ball 504) configured in a first orientation (e.g., in a vertical direction) and a second subset of solder balls (e.g., solder ball 506 and solder ball 508) configured in a second orientation (e.g., in a horizontal direction) that differs from the first orientation. In one embodiment, the second orientation associated with the second subset of solder balls (e.g., solder ball 506 and solder ball 508) can be perpendicular or nearly perpendicular with respect to the first orientation associated with the first subset of solder balls (e.g., solder ball 502 and solder ball 504). For example, in one embodiment, the first subset of solder balls (e.g., solder ball 502 and solder ball 504) can be positioned substantially along a first axis on the package substrate 202, and the second subset of solder balls (e.g.,Solder ball 506 and solder ball 508 can be positioned on the package substrate 202 substantially along a second axis, wherein the first and second axes are configured in different orientations with respect to the package substrate 202 (e.g., where the second axis is perpendicular or nearly perpendicular with respect to the first axis). Additionally, at least one solder ball (e.g., solder ball 510a) from the second set of solder balls is arranged between the first subset of solder balls (e.g., solder ball 502 and solder ball 504) and the second subset of solder balls (e.g., solder ball 506 and solder ball 508).

[0048] In another embodiment, the first set of solder balls comprises a third subset of solder balls (e.g., solder ball 522 and solder ball 524) configured in the first orientation (e.g., the vertical orientation) and a fourth subset of solder balls (e.g., solder ball 526 and solder ball 528) configured in the second orientation (e.g., the horizontal orientation). Furthermore, at least one additional solder ball (e.g., solder ball 510b) from the second set of solder balls is arranged between the third subset of solder balls (e.g., solder ball 522 and solder ball 524) and the fourth subset of solder balls (e.g., solder ball 526 and solder ball 528). In one embodiment, the second orientation, which is associated with the fourth subset of solder balls (e.g. solder ball 526 and solder ball 528), can be perpendicular or approximately perpendicular with respect to the first orientation, which is associated with the third subset of solder balls (e.g. solder ball 522 and solder ball 524).For example, in one embodiment, the third set of solder balls (e.g., solder ball 522 and solder ball 524) can be positioned on the package substrate 202 substantially along a third axis, and the fourth set of solder balls (e.g., solder ball 526 and solder ball 528) can be positioned on the package substrate 202 substantially along the second axis, wherein the second and third axes are configured in different orientations with respect to the package substrate 202 (e.g., wherein the second axis is perpendicular or nearly perpendicular with respect to the third axis). In one or more embodiments, the second set of solder balls (e.g., solder ball 506 and solder ball 508) and the fourth set of solder balls (e.g., solder ball 526 and solder ball 528) can be arranged on the package substrate 202 substantially along the same axis (e.g., the second axis). Furthermore, in one or more embodiments, an axis (e.g.,The first axis, which is connected to the first set of solder balls (e.g., solder ball 502 and solder ball 504), is essentially parallel to an axis (e.g., the third axis) that is connected to the third set of solder balls (e.g., solder ball 522 and solder ball 524). Additionally, in certain embodiments, at least one further solder ball (e.g., solder ball 510c and / or solder ball 510d) from the second set of solder balls is arranged between the second set of solder balls (e.g., solder ball 506 and solder ball 508) and the third set of solder balls (e.g., solder ball 522 and solder ball 524).

[0049] In certain embodiments, the first subset of solder balls (e.g., solder ball 502 and solder ball 504) and the second subset of solder balls (e.g., solder ball 506 and solder ball 508) can be associated with transmitter communication channels, and the third subset of solder balls (e.g., solder ball 522 and solder ball 524) and the fourth subset of solder balls (e.g., solder ball 526 and solder ball 528) can be associated with receiver communication channels. Alternatively, in certain embodiments, the first set of solder balls (e.g., solder ball 502 and solder ball 504) and the second set of solder balls (e.g., solder ball 506 and solder ball 508) can be connected to receiver communication channels, and the third set of solder balls (e.g., solder ball 522 and solder ball 524) and the fourth set of solder balls (e.g., solder ball 526 and solder ball 528) can be connected to transmitter communication channels. In certain embodiments, the first set of solder balls (e.g.,Solder balls 502 and 504) and the second set of solder balls (e.g., solder balls 506 and 508) are surrounded by one or more solder balls (e.g., solder balls 510e-o) from the second set of solder balls. Additionally or alternatively, the third set of solder balls (e.g., solder balls 522 and 524) and the fourth set of solder balls (e.g., solder balls 526 and 528) are surrounded by one or more solder balls (e.g., solder balls 510p-z) from the second set of solder balls.

[0050] In certain embodiments, a third set of solder balls can be configured to provide secondary electrical connections for power supply and / or auxiliary signals in conjunction with the silicon chip 204. In certain embodiments, the package substrate 202 defines a first side, a second side, a third side, and a fourth side. The first set of solder balls can be arranged along the first, second, and third sides of the substrate. Furthermore, the third set of solder balls can be arranged along the fourth side of the package substrate 202.

[0051] Fig. Figure 6 shows an example of a sphere grid arrangement 104" according to one or more embodiments of the present disclosure. The sphere grid arrangement 104" can correspond to at least a portion of the sphere grid arrangement 104 and / or the sphere grid arrangement 104'. In one embodiment, the sphere grid arrangement 104" is arranged in an interference cancellation pattern that is associated with at least a portion of the sphere grid arrangement 104 and / or the sphere grid arrangement 104'. For example, solder balls associated with the communication channels can be arranged in an interference cancellation pattern for signals associated with the solder balls, thereby improving the performance of the communication channels and / or the integrated circuit 102.In one or more embodiments, the sphere grid arrangement 104" comprises the soldering sphere 502, the soldering sphere 504, the soldering sphere 506, the soldering sphere 508, the soldering sphere 510a, the soldering sphere 510c, the soldering sphere 510e, the soldering sphere 510f, the soldering sphere 510g, the soldering sphere 510h, the soldering sphere 510i, the soldering sphere 510j, the soldering sphere 510k, the soldering sphere 510l, the soldering sphere 510m, the soldering sphere 510n and the soldering sphere 510o.

[0052] In one embodiment, the solder ball 510a (e.g., G0) together with the solder ball 506 (e.g., 2+) and the solder ball 508 (e.g., 2-) form one long leg of a "T"-shaped configuration, and the solder ball 502 (e.g., 1+) ​​and the solder ball 504 (e.g., 1-) form the crossbar of the "T". In certain embodiments, solder ball 502 and solder ball 504 can be surrounded by eight solder balls (e.g., solder ball 510a, solder balls 510e-g, and solder balls 5101-n corresponding to G0-G7) that are connected to the electrical ground. In certain embodiments, the solder ball 506 and the solder ball 508 can also be surrounded by eight solder balls (e.g., solder ball 510a and solder balls 510g-1 corresponding to G0, G4, G5, and G8-G12) connected to electrical ground. In one aspect, the T-shaped configuration can provide differential interference suppression for the sphere grid arrangement 104".It goes without saying that the specific number of solder balls assigned to the communication channels and / or electrical ground can vary, and that similar configurations can be used to achieve a similar effect of differential interference suppression.

[0053] Fig. Figure 7 shows an example of a spherical grid arrangement 104''' according to one or more embodiments of the present disclosure. The spherical grid arrangement 104''' can correspond to at least a part of the spherical grid arrangement 104, the spherical grid arrangement 104', and / or the spherical grid arrangement 104''. In one embodiment, the spherical grid arrangement 104''' can represent an interference cancellation pattern associated with at least a part of the spherical grid arrangement 104, the spherical grid arrangement 104', and / or the spherical grid arrangement 104''. For example, the T-shaped configuration can provide differential interference suppression and thus improve the performance of the communication channels and / or the integrated circuit 102.

[0054] In one aspect, differential-differential coupling can depend on the distances between adjacent pairs of solder balls (e.g., solder balls connected to communication channels) and can be represented by the following equation: Coupling=[(1 P→2 P)−(1 N→2P)]−[(1 P→2 N)−(1 N→2 N)] where the number 1 represents a first pair of solder balls connected to communication channels, the number 2 represents a second pair of solder balls connected to communication channels, the letter N represents a negative contact of each pair of solder balls, the letter P represents a positive contact of each pair of solder balls, and the arrows → represent distance.

[0055] In Fig. In section 7, the letters next to the arrows represent the distances between two solder balls, and the circle with an "X" in the middle represents a solder ball connected to ground. Substituting these lengths into the equation above, we get... Fig. 7 shows that the coupling cancels out. For example, the coupling = [(a - a) - (b - b)] = 0 when one considers the Fig. The T-shaped configuration shown in section 7 is used.

[0056] Fig. Figure 8 shows an example of a sphere grid arrangement 104'''' according to one or more embodiments of the present disclosure. The sphere grid arrangement 104'''' can correspond to at least a part of the sphere grid arrangement 104. In one embodiment, the sphere grid arrangement 104'''' can represent an interference cancellation pattern associated with at least a part of the sphere grid arrangement 104.

[0057] In one aspect, it compares Fig. Figure 8 schematically shows the areas for solder balls connected to signal channels and the surrounding solder balls connected to electrical ground. Fig. 8. The unshaded circles can represent solder balls connected to electrical ground, and the shaded circles can represent solder balls connected to a signal (e.g., a communication channel, power supply, auxiliary connection, another type of signal, etc.). In another aspect, Fig. 8 schematically a section of the Fig. Figure 4 shows the sphere grid arrangement 104, wherein the area contains solder balls for 16 pairs of communication channels and corresponds to an area of ​​89.6 mm². In certain embodiments, the size of the sphere grid arrangement 104 can be about 7% smaller than conventional sphere grid arrangements, thereby allowing additional communication channels and / or other components to be added to the integrated circuit 102 and / or reducing the size of the package substrate 202.

[0058] Embodiments of the present disclosure are described below with reference to block diagrams and flowchart figures. It should therefore be understood that each block of the block diagrams and flowchart figures can be implemented in the form of a computer program product, a complete hardware implementation, a combination of hardware and computer program products and / or devices, systems, computing devices / units, computing units, and / or the like, which execute instructions, operations, steps, and similar interchangeable terms (e.g., the executable instructions, instructions for execution, program code, and / or the like) on a computer-readable storage medium. For example, the fetching, loading, and execution of code can be sequential, such that one instruction is fetched, loaded, and executed at a time.In some embodiments, fetching, loading, and / or execution can occur in parallel, allowing multiple instructions to be fetched, loaded, and / or executed simultaneously. Such embodiments can thus produce specifically configured machines that perform the steps or operations specified in the block diagrams and flowcharts. Accordingly, the block diagrams and flowchart illustrations support various combinations of embodiments for performing the specified instructions, operations, or steps.

[0059] Fig. Figure 9 is a flowchart illustrating an exemplary method 900 for facilitating the transmission of an electrical signal across a sphere grid arrangement according to one or more embodiments of the present disclosure. It is understood that each block of the flowcharts and combinations of blocks in the flowcharts can be implemented by various means. In some embodiments, certain operations described herein may be modified or extended as described below. Furthermore, some embodiments may also include additional optional operations. It should be noted that each of the modifications, optional additions, or extensions described herein may be included with the operations described herein either alone or in combination with other features described herein. The Fig. The 9 operations shown can be performed, for example, by an exemplary computer system 1000 (shown in Fig. 10) is implemented, which is embedded in an integrated circuit (e.g., the integrated circuit 102) and / or a silicon chip (e.g., the silicon chip 204). In some embodiments, the computer system 1000 is a firmware computer system embedded in an integrated circuit (e.g., the integrated circuit 102) and / or a silicon chip (e.g., the silicon chip 204). In one or more embodiments, one or more of the Fig. The operations shown in Figure 9 can be performed, for example, by an integrated circuit (e.g., the integrated circuit 102) and / or a silicon chip (e.g., the silicon chip 204). In one or more embodiments, the computer system 1000 configures an electrical signal via a silicon chip of an integrated circuit in operation 902.In one or more embodiments, during operation 904, the computer system 1000 transmits the electrical signal to a printed circuit board via a sphere grid arrangement located on the integrated circuit, wherein the sphere grid arrangement comprises a first set of solder balls configured to provide electrical connections for communication channels connected to the silicon chip, and a second set of solder balls connected to an electrical ground and / or electrical power for the silicon chip, the first set of solder balls comprising a first subset of solder balls configured in a first orientation, and a second subset of solder balls configured in a second orientation that differs from the first orientation, and at least one solder ball from the second set of solder balls is arranged between the first subset of solder balls and the second subset of solder balls.

[0060] Fig.Figure 10 illustrates the computer system 1000, which may be embedded in an integrated circuit system and / or an integrated circuit package system. In some cases, the computer system 1000 may be a firmware computer system that is communicatively coupled to one or more circuit modules and configured to control one or more circuit modules connected to an integrated circuit (e.g., the integrated circuit 102). For example, the computer system 1000 may be a firmware computer system and / or a controller computer system that is communicatively connected to one or more circuit modules, such as an integrated circuit (e.g., the integrated circuit 102). The computer system 1000 may include or otherwise be interconnected with a processor 1010, a memory circuit 1020, and a communication circuit 1030.In some embodiments, the processor 1010 (which may include multiple or co-processors or other processing circuits connected to the processor) may be interconnected with the memory circuit 1020. The memory circuit 1020 may comprise a non-transient memory circuit and include one or more volatile and / or non-volatile memories. In some examples, the memory circuit 1020 may be an electronic storage device (e.g., a computer-readable storage medium) configured to store data that can be retrieved by the processor 1010. In some examples, the data stored in the memory 1020 may include signal data, communication channel data, communication protocol data, or the like, to enable the device to perform various functions or procedures in accordance with the embodiments of the present invention described herein.

[0061] In some examples, the 1010 processor can be implemented in various ways. For instance, the processor can be implemented as one or more of the following hardware processing elements, such as a silicon chip, a microprocessor, a coprocessor, a digital signal processor (DSP), a GPU, a controller, or a processing element with or without an accompanying DSP. The 1010 processor can also be incorporated into various other processing circuits, including integrated circuits such as an FPGA (field-programmable gate array), a microcontroller unit (MCU), an ASIC (application-specific integrated circuit), a hardware accelerator, or a specialized electronic chip. Furthermore, in some embodiments, the processor can include one or more processing cores configured to operate independently.A multi-core processor can enable multiprocessing within a single package. Additionally or alternatively, the processor can include one or more processors configured in tandem over the bus to allow independent instruction execution, pipelining, and / or multithreading. In some embodiments, the 1010 processor is a microprocessor.

[0062] In one embodiment, the processor 1010 can be configured to execute instructions, such as computer program code or instructions stored in the memory circuit 1020 or otherwise accessible to the processor 1010. Alternatively or additionally, the processor 1010 can be configured to execute hard-coded functions. Regardless of whether it is configured by hardware or software instructions, or by a combination thereof, the processor 1010 can represent an arithmetic unit (e.g., physically embodied in a circuit) configured to perform operations according to an embodiment of the present invention described herein. For example, if the processor 1010 is implemented as an ASIC, FPGA, or the like, the processor can be configured as hardware to perform the operations of an embodiment of the invention.Alternatively, if the processor 1010 is configured to execute software or computer program instructions, it can be specifically configured by those instructions to perform the algorithms and / or operations described herein when the instructions are executed. In some cases, however, the processor 1010 may be a device processor (e.g., a mobile device or a stationary computer) specifically configured for use in an embodiment of the present invention by further configuring the processor using instructions to perform the algorithms and / or operations described herein. The processor 1010 may include, among other things, a clock, an arithmetic logic unit (ALU), and logic gates configured to support the operation of the processor 1010.

[0063] The Computer System 1000 can optionally include the Communication Circuit 1030. The communication circuit can be any means, either hardware-based or a combination of hardware and software, configured to receive and / or transmit data to / from a network and / or another device or module that communicates with the Computer System 1000. In this respect, the communication interface can include, for example, supporting hardware and / or software to enable communication. Thus, the Communication Circuit 1030 can include, for example, a communication modem and / or other hardware / software to support communication via cable, a universal serial bus (USB), an integrated receiver circuit, or other mechanisms.

[0064] Many modifications and other embodiments of the present inventions set forth herein will occur to a person skilled in the art in the field to which these inventions belong when considering the teachings set forth in the foregoing descriptions and the accompanying drawings. It is therefore self-evident that the present inventions are not limited to the specific embodiments disclosed. Although the foregoing descriptions and the accompanying drawings describe exemplary embodiments in connection with certain example combinations of elements and / or functions, it should be borne in mind that other combinations of elements and / or functions can be provided by alternative embodiments.In this respect, other combinations of elements and / or functions besides those expressly described above are conceivable, as can be set out in some of the appended claims. Although specific terms are used here, they are used only in a general and descriptive sense and not for the purpose of limitation.

[0065] It is understood that the aspects and embodiments described above are only examples.

[0066] Each device, method and feature disclosed in the description and (where applicable) in the claims and drawings can be provided independently or in any suitable combination.

Claims

[1] Integrated circuit device (100') comprising: an integrated circuit (102) comprising at least one package substrate (202) and a silicon chip (204); and a sphere grid arrangement (104) arranged on the package substrate (202) of the integrated circuit, wherein the sphere grid arrangement (104) comprises the following: a first set of solder balls (502, 504, 506, 508, 522, 524, 526, 528) configured to provide electrical connections for communication channels associated with the silicon chip (204), and a second set of solder balls (510) associated with an electrical ground and / or electrical power for the silicon chip (204), where the electrical connections are the first electrical connections, and wherein the sphere grid arrangement (104) includes a third set of solder balls configured to provide secondary electrical connections for auxiliary signals associated with the silicon chip (204), and wherein at least one solder ball from the second set of solder balls (510) is arranged between the first set of solder balls (502, 504, 506, 508, 522, 524, 526, 528) and the third set of solder balls, and where the packet substrate (202) defines a first page, a second page, a third page and a fourth page, and wherein the first set of solder balls (502, 504, 506, 508, 522, 524, 526, 528) is arranged along the first side, the second side and the third side of the packet substrate (202), and wherein the third set of solder balls is arranged along the fourth side of the package substrate (202). [2] Integrated circuit device (100') according to claim 1, wherein the first set of solder balls comprises a first subset (502, 504) of solder balls configured in a first orientation, and a second subset (506, 508) of solder balls configured in a second orientation which differs from the first orientation, and wherein at least one solder ball (510a) from the second set of solder balls (510) is arranged between the first subset (502, 504) of solder balls and the second subset (506, 508) of solder balls. [3] Integrated circuit device (100') according to claim 2, wherein the first set of solder balls further comprises a third subset (522, 524) of solder balls configured in the first orientation and a fourth subset (526, 528) of solder balls configured in the second orientation. [4] Integrated circuit device (100') according to claim 3, wherein at least one further solder ball (510b) from the second set of solder balls (510) is arranged between the third subset (522, 524) of solder balls and the fourth subset (526, 528) of solder balls. [5] Integrated circuit device (100') according to claim 3 or 4, wherein at least one further solder ball (510c, 510d) from the second set of solder balls (510) is arranged between the second subset (506, 508) of solder balls and the third subset (522, 524) of solder balls. [6] Integrated circuit device (100') according to one of claims 3, 4 or 5, wherein the first subset (502, 504) of solder balls and the second subset (506, 508) of solder balls are connected to transmitter communication channels, and wherein the third subset (522, 524) of solder balls and the fourth subset (526, 528) of solder balls are associated with receiver communication channels. [7] Integrated circuit device (100') according to one of the preceding claims, wherein the first set of solder balls (502, 504, 506, 508, 522, 524, 526, 528) is surrounded by solder balls from the second set of solder balls (510). [8] Integrated circuit device (100') according to one of the preceding claims, wherein the electrical connections are first electrical connections and wherein the ball grid arrangement (104) comprises a third set of solder balls configured to provide second electrical connections for a power supply connected to the silicon chip (204). [9] Integrated circuit device (100') according to claim 8, wherein at least one further solder ball from the second set of solder balls (510) is arranged between the first set of solder balls (502, 504, 506, 508, 522, 524, 526, 528) and the third set of solder balls. [10] Integrated circuit device (100') according to any one of claims 2 to 6, wherein the second orientation associated with the second subset (506, 508) of solder balls is perpendicular to the first orientation associated with the first subset (502, 504) of solder balls. [11] Integrated circuit device (100') according to one of the preceding claims, wherein the sphere grid arrangement (104) is arranged between the package substrate (202) and a printed circuit board (302). [12] Integrated circuit device (100') according to any one of claims 1 to 10, wherein the integrated circuit is an integrated circuit (102) of a network switch and wherein the ball grid arrangement (104) is arranged between the network switch and a carrier circuit board. [13] Integrated circuit device (100') according to any one of claims 1 to 10, wherein the integrated circuit is an integrated circuit (102) for a network adapter. [14] Integrated circuit device (100') according to any one of claims 1 to 10, wherein the integrated circuit (102) is configured as a graphics processing unit. [15] Integrated circuit package system (300), comprising: An integrated circuit (102) comprising at least one package substrate (202) and a silicon chip (204); a printed circuit board (302); and a sphere grid arrangement (104) which is arranged between the package substrate (202) of the integrated circuit (102) and the printed circuit board (302), wherein the sphere grid arrangement (104) comprises a first set of solder balls (502, 504, 506, 508, 522, 524, 526, 528) configured to provide electrical connections for communication channels associated with the silicon chip (204), and a second set of solder balls (510) associated with an electrical ground and / or electrical power for the silicon chip (204), where the electrical connections are the first electrical connections, and wherein the sphere grid arrangement (104) includes a third set of solder balls configured to provide secondary electrical connections for auxiliary signals associated with the silicon chip (204), and wherein at least one solder ball from the second set of solder balls (510) is arranged between the first set of solder balls (502, 504, 506, 508, 522, 524, 526, 528) and the third set of solder balls, and where the packet substrate (202) defines a first page, a second page, a third page and a fourth page, wherein the first set of solder balls (502, 504, 506, 508, 522, 524, 526, 528) is arranged along the first side, the second side and the third side of the packet substrate (202), and wherein the third set of solder balls is arranged along the fourth side of the package substrate (202). [16] Integrated circuit package system (300) according to claim 15, wherein the first set of solder balls (502, 504, 506, 508, 522, 524, 526, 528) associated with the communication channels comprises a first subset (502, 504) of solder balls configured in a first orientation and a second subset (506, 508) of solder balls configured in a second orientation which differs from the first orientation, and wherein at least one solder ball (510a) from the second set of solder balls (510) is arranged between the first subset (502, 504) of solder balls and the second subset (506, 508) of solder balls. [17] Integrated circuit package system (300) according to claim 16, wherein the first set of solder balls (502, 504, 506, 508, 522, 524, 526, 528) comprises a third subset (522, 524) of solder balls configured in the first orientation and a fourth subset (526, 528) of solder balls configured in the second orientation. [18] Integrated circuit package system (300) according to claim 17, wherein at least one further solder ball (510b) from the second set of solder balls (510) is arranged between the third subset (522, 524) of solder balls and the fourth subset (526, 528) of solder balls. [19] Integrated circuit package system (300) according to claim 17 or 18, wherein at least one further solder ball (510c, 510d) from the second set of solder balls (510) is arranged between the second subset (506, 508) of solder balls and the third subset (522, 524) of solder balls. [20] Integrated circuit package system (300) according to claim 17, 18 or 19, wherein the first subset (502, 504) of solder balls and the second subset (506, 508) of solder balls are connected to transmitter communication channels, and wherein the third subset (522, 524) of solder balls and the fourth subset (526, 528) of solder balls are connected to receiver communication channels. [21] Procedures, including: Configuring an electrical signal via a silicon chip (204) of an integrated circuit (102) with at least one package substrate (202); and Transmission of the electrical signal to a printed circuit board (302) via a sphere grid arrangement (104) arranged on the integrated circuit, wherein the sphere grid arrangement (104) comprises a first set of solder balls (502, 504, 506, 508, 522, 524, 526, 528) configured to provide electrical connections for communication channels associated with the silicon chip (204), and a second set of solder balls (510) associated with an electrical ground and / or electrical power for the silicon chip (204), where the electrical connections are the first electrical connections; the ball grid arrangement (104) includes a third set of solder balls configured to provide secondary electrical connections for a power supply connected to the silicon chip (204) or for auxiliary signals associated with the silicon chip (204); and wherein at least one solder ball from the second set of solder balls (510) is arranged between the first set of solder balls (502, 504, 506, 508, 522, 524, 526, 528) and the third set of solder balls, and wherein the package substrate (202) defines a first side, a second side, a third side and a fourth side; and wherein the first set of solder balls (502, 504, 506, 508, 522, 524, 526, 528) is arranged along the first side, the second side and the third side of the package substrate; and the third set of solder balls is arranged along the fourth side of the package substrate.

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