DEVICE STRUCTURE AND RESISTIVE RANDOM ACCESS MEMORY DEVICE WITH RESISTIVE STORAGE CELL USING AN INTERFACIAL TRANSITION METAL COMPOSITION LAYER AND METHOD FOR MAKING THEM

Abstract

Device structure comprising a resistive memory cell, wherein the resistive memory cell comprises: a lower electrode (130, 130C) comprising at least: a lower metallic barrier layer (134, 134C), a lower metal layer (136, 136C) comprising a first metal having a melting point of more than 2000 degrees Celsius, and a transition metal compound layer (138, 138C) comprising an oxide or nitride of a transition metal selected from Ti, Ta and W; a resistive transition metal oxide layer (140, 140C) comprising a conductive filament-forming dielectric oxide of at least one transition metal and located on the transition metal compound layer (138, 138C); and an upper electrode (150, 150C) having an upper metal layer (152, 152C) having a second metal, and at least one upper metallic barrier layer (154, 154C, 156, 156C) where: the lower metallic barrier layer (134, 134C) has a lower vertical stack comprising, from bottom to top, a first lower tantalum nitride layer (131, 131C), a lower tantalum layer (132, 132C), and a second lower tantalum nitride layer (133, 133C); and the at least one upper metallic barrier layer (154, 154C, 156, 156C) having an upper vertical stack comprising, from bottom to top, an upper tantalum nitride layer (154, 154C) and a titanium nitride layer (156, 156C).

Description

BACKGROUND

[0001] A resistive memory cell has a resistive storage element in which a data bit can be encoded as either a low-impedance or a high-impedance state. Multiple resistive memory cells can be arranged as a two-dimensional or three-dimensional array to provide a random-access resistive memory array. The reliability of a resistive memory cell depends on how well it maintains its original device characteristics after repeated programming, erase, and read operations.

[0002] German patent application DE 10 2019 100 488 A1 describes chips with an RRAM device that has a diffusion barrier layer located between a lower electrode and a data storage layer. German patent application US 2020 / 0 203 603 A1 describes an RRAM device that has a lower electrode over a substrate, a first switching layer over the lower electrode, a second switching layer containing aluminum on the first switching layer, and an upper electrode. German patent application DE 10 2019 103 777 A1 This document describes methods for manufacturing memory cells separated by a void-free dielectric structure. German patent application US 2020 / 0381622A1 describes RRAM cells that include, among other things, a first electrode formed by a first opening in a dielectric layer. German patent application DE 102013104112A1 describes devices that have a dielectric intermediate layer and, above it, a first metallization layer, wherein the first metallization layer comprises a first metal conductor and, above it, a dielectric layer. Furthermore, conductive linings are described as barrier layers comprising individual layers of Ta, TaN, WN, WSi, TiN, Ru, and combinations thereof. German patent application DE 102019107906A1 relates to lower electrode structures in memory devices. The objective is to increase the reliability of the memory devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with common practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily enlarged or reduced for the clarity of the discussion. Fig. Figure 1 is a vertical cross-sectional view of an exemplary structure after the formation of complementary metal-oxide-semiconductor (CMOS) transistors, metal interconnect structures embedded in dielectric material layers, and a lower dielectric interconnect via layer according to an embodiment of the present disclosure. Fig. Figure 2 is a vertical cross-sectional view of the exemplary structure after the formation of an arrangement of lower interconnection via structures according to an embodiment of the present disclosure. Fig. Figure 3 is a vertical cross-sectional view of a memory cell region of the exemplary structure after the formation of a dielectric etch stop layer according to an embodiment of the present disclosure. Fig. Figure 4 is a vertical cross-sectional view of a memory cell region of the exemplary structure after the formation of a layer stack comprising at least one continuous lower metallic barrier layer, a continuous lower metal layer, a continuous transition metal compound layer, a continuous resistive transition metal oxide layer, a continuous upper metal layer, at least one continuous upper metallic barrier layer and a continuous dielectric cover layer, according to an embodiment of the present disclosure. Fig. Figure 5 is a vertical cross-sectional view of a memory cell region of the exemplary structure after structuring the dielectric cover layer, the at least one continuous upper metallic barrier layer and the continuous upper metal layer according to an embodiment of the present disclosure. Fig. Figure 6 is a vertical cross-sectional view of a memory cell region of the exemplary structure after the formation of a dielectric spacer according to an embodiment of the present disclosure. Fig. Figure 7 is a vertical cross-sectional view of a memory cell region of the exemplary structure after structuring the continuous resistive transition metal oxide layer, the continuous transition metal compound layer, the continuous lower metal layer and the at least one continuous lower metallic barrier layer according to an embodiment of the present disclosure. Fig. Figure 8 is a vertical cross-sectional view of a memory cell region of the exemplary structure after the formation of an etching mask structure, a dielectric lining and a dielectric material layer on the top level according to an embodiment of the present disclosure. Fig. Figure 9 is a vertical cross-sectional view of a memory cell region of the exemplary structure after the formation of upper interconnect via structures and upper interconnect metal leads according to an embodiment of the present disclosure. Fig. Figure 10 is a vertical cross-sectional view of the exemplary structure during the processing steps of Fig. 9. Fig. Figure 11 is a flowchart illustrating a sequence of processing steps for manufacturing a resistive storage device of the present disclosure. DETAILED DESCRIPTION

[0004] The aforementioned problem is solved by the device structure according to claim 1, the resistive random access memory device according to claim 13, and the method according to claim 15. Further embodiments are described in the dependent claims. The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting.For example, the formation of a first feature above or on top of a second feature in the following description may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition serves the purpose of simplicity and clarity and does not in itself prescribe a relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass various orientations of the device used or operated, in addition to the orientation shown in the figures. The device can be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptions used herein can be interpreted accordingly.

[0006] In general, the structures and methods of the present disclosure can be used to form a memory cell that provides improved durability for a resistive storage element while minimizing any adverse effect on the resistance of a lower electrode. In particular, an interfacial transition metal compound layer can be provided between a highly conductive metal of a lower metal layer in a lower electrode and a resistive transition metal oxide layer, which has at least two resistive states providing different electrical resistances.The resistive transition metal oxide layer can comprise a filament-forming dielectric metal oxide material, and permanent structural damage to the resistive transition metal oxide layer due to repeated formation and quenching of conductive filaments within the resistive transition metal oxide layer can be delayed by using the interfacial transition metal compound layer between the lower metal layer and the resistive transition metal oxide layer. Aspects of various embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0007] Fig. Figure 1 is a vertical cross-sectional view of an exemplary structure after the formation of complementary metal-oxide-semiconductor (CMOS) transistors, metal interconnect structures formed within dielectric material layers at the lower level, and a dielectric interconnect via layer according to an embodiment of the present disclosure. The exemplary structure comprises complementary metal-oxide-semiconductor (CMOS) transistors and metal interconnect structures formed within dielectric material layers. In particular, the exemplary structure includes a substrate 9, which may be a semiconductor substrate such as a commercially available silicon wafer. Shallow trench insulation structures 720, comprising a dielectric material such as silicon oxide, may be formed in an upper section of the substrate 9.Suitable doped semiconductor wells, such as p-type and n-type wells, can be formed within any region, which may be laterally enclosed by a section of the flat trench insulation structures 720. Field-effect transistors can be formed above the top surface of the substrate 9. For example, each field-effect transistor may have a source region 732, a drain region 738, a semiconductor channel 735 having a surface section of the substrate 9 extending between the source region 732 and the drain region 738, and a gate structure 750. Each gate structure 750 may have a gate dielectric 752, a gate electrode 754, a gate cover dielectric 758, and a dielectric gate spacer 756.A source-side metal-semiconductor alloy region 742 can be formed on any source region 732, and a drain-side metal-semiconductor alloy region 748 can be formed on any drain region 738. Although planar field-effect transistors are illustrated in the drawings, embodiments in which the field-effect transistors may additionally or alternatively include fin field-effect transistors (FinFETs), gate-all-around field-effect transistors (GAA-FETs), or any other type of field-effect transistor (FET).

[0008] The exemplary structure can have a memory arrangement area 100 in which an arrangement of memory elements can subsequently be formed, and a peripheral area 200 in which logic devices supporting the operation of the arrangement of memory elements can be formed. In one embodiment, devices (such as field-effect transistors) in the memory arrangement area 100 can include bottom-electrode-access transistors that provide access to the bottom electrodes of memory cells to be formed subsequently. Top-electrode-access transistors that provide access to the top electrodes of memory cells to be formed subsequently can be formed in the peripheral area 200 during this processing step.Devices (such as field-effect transistors) in the peripheral area 200 can provide functions that may be required to operate the array of memory cells to be subsequently formed. In particular, devices in the peripheral area can be configured to control the programming, erasing, and read / write operations of the array of memory cells. For example, the devices in the peripheral area can include a read / write circuit and / or an upper electrode bias circuit. The devices formed on the upper surface of the substrate 9 can include complementary metal-oxide-semiconductor (CMOS) transistors and optionally additional semiconductor devices (such as resistors, diodes, capacitors, etc.) and are collectively referred to as the CMOS circuit 700.

[0009] Various metal interconnect structures embedded in dielectric material layers can subsequently be formed over the substrate 9 and the devices (such as field-effect transistors). The dielectric material layers can, for example, include a dielectric material layer at contact level 601, a first dielectric material layer at metal conduction level 610, a second dielectric material layer at conduction and via level 620, a third dielectric material layer at conduction and via level 630, and a fourth dielectric material layer at conduction and via level 640. The metal interconnect structures can include device contact via structures 612 formed in the dielectric material layer at contact level 601, which contact a respective component of the CMOS circuit 700, and first metal conduction structures 618.which are formed in the first dielectric material layer at the metal conduction level 610, first metal via structures 622 formed in a lower section of the second dielectric material layer at the conduction and via level 620, second metal conduction structures 628 formed in an upper section of the second dielectric material layer at the conduction and via level 620, second metal via structures 632 formed in a lower section of the third dielectric material layer at the conduction and via level 630, third metal conduction structures 638 formed in an upper section of the third dielectric material layer at the conduction and via level 630, third metal via structures 642 formed in a lower section of the fourth dielectric material layer at the conduction and via level 640,and fourth metal conductor structures 648, which are formed in an upper section of the fourth dielectric material layer at the conductor and via level 640. In one embodiment, the second metal conductor structures 628 can have source conductors that are connected to a source-side power supply for an array of storage elements. The voltage provided by the source conductors can be applied to the lower electrodes by the access transistors provided in the storage array area 100.

[0010] Each of the dielectric material layers (601, 610, 620, 630, 640) can comprise a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) can comprise at least one conductive material, which may be a combination of a metallic lining layer (such as a metallic nitride or a metallic carbide) and a metallic filler material. Each metallic lining layer can comprise TiN, TaN, WN, TiC, TaC, and WC, and each metallic filler material section can comprise W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable materials may also be used.In one embodiment, the first metal via structures 622 and the second metal conductor structures 628 can be formed as integrated conductor and via structures by a dual damascene process, the second metal via structures 632 and the third metal conductor structures 638 can be formed as integrated conductor and via structures, and / or the third metal via structures 642 and the fourth metal conductor structures 648 can be formed as integrated conductor and via structures.Although the present disclosure is described using an embodiment in which an arrangement of memory cells is formed above the fourth dielectric material layer on the conduction and via plane 640, embodiments in which the arrangement of memory cells can be formed on another metal interconnection plane are expressly considered herein.

[0011] The dielectric material layers (601, 610, 620, 630, 640) can be located at a lower level relative to an array of memory cells to be subsequently formed. As such, the dielectric material layers (601, 610, 620, 630, 640) are referred to herein as lower-level dielectric material layers, i.e., dielectric material layers located at lower levels relative to the array of memory cells to be subsequently formed. The metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) are referred to herein as lower-level metal interconnect structures.A subset of the metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) features lower-level metal conductors (such as the fourth metal conductor structure 648) embedded in the lower-level dielectric layers, with top surfaces within a horizontal plane that includes the uppermost surface of the lower-level dielectric layers. In general, the total number of metal conductor levels within the lower-level dielectric layers (601, 610, 620, 630, 640) can range from 1 to 10.

[0012] A dielectric cover layer 108 and a lower dielectric interconnect via layer 110 can be formed sequentially over the metal interconnect structures and the dielectric material layers. The continuous dielectric cover layer 108 and the lower dielectric interconnect via layer 110 can be additional dielectric material layers at a lower level. For example, the dielectric cover layer 108 can be formed on the top surfaces of the fourth metal conductor structures 648 and on the top surface of the fourth dielectric conductor and via layer 640. The dielectric cover layer 108 has a dielectric cover material that can protect underlying metal interconnect structures such as the fourth metal conductor structures 648. In one embodiment, the dielectric cover layer 108 can have a material that can provide high etch resistance, i.e.,a dielectric material, and can also act as an etch stop material during a subsequent anisotropic etching process that etches the lower dielectric interconnect via layer 110. For example, the dielectric cover layer 108 can be silicon carbide or silicon nitride and can have a thickness in the range of 5 nm to 30 nm, although smaller and larger thicknesses can also be used.

[0013] The lower dielectric interconnect via layer 110 can be made of any material suitable for the dielectric material layers (601, 610, 620, 630, 640). For example, the lower dielectric interconnect via layer 110 can be undoped silicate glass or doped silicate glass deposited by decomposition of tetraethyl orthosilicate (TEOS). The thickness of the lower dielectric interconnect via layer 110 can be in the range of 50 nm to 200 nm, although thinner and thicker thicknesses are also possible. The dielectric top layer 108 and the lower dielectric interconnect via layer 110 can be formed as planar top layers (unstructured layers), each having a planar top surface and a planar bottom surface extending through the memory arrangement area 100 and the peripheral area 200.

[0014] Fig. Figure 2 is a vertical cross-sectional view of the exemplary structure after the formation of an array of lower interconnect via structures 120 according to an embodiment of the present disclosure. Via cavities can be formed through the lower dielectric interconnect via plane 110 and the dielectric cover layer 108 of the exemplary structure. For example, a photoresist layer (not shown) can be applied over the lower dielectric interconnect via plane 110 and can be structured to form an opening within regions of the memory array area 100 that lie above each of the fourth metal conductor structures 648. Anisotropic etching can be performed to transfer the structure in the photoresist layer through the lower dielectric interconnect via plane 110 and the dielectric cover layer 108.The via cavities formed by the anisotropic etching process are referred to herein as bottom-electrode via cavities, since bottom-electrode via structures are subsequently formed within these cavities. The bottom-electrode via cavities may have tapered sidewalls exhibiting a taper angle (within a given vertical direction) ranging from 1 degree to 10 degrees. A top surface of a fourth metal conductor structure 648 may be physically exposed at the bottom of each bottom-electrode via cavity. The photoresist layer may subsequently be removed, for example, by ashing.

[0015] A metallic barrier layer can be formed as a single layer of material. The metallic barrier layer can cover physically exposed top surfaces of the fourth metal conduction structures 648, tapered sidewalls of the bottom-electrode vias, and the top surface of the lower dielectric interconnect via plane 110 without a hole passing through it. The metallic barrier layer can consist of a conductive metallic nitride such as TiN, TaN, and / or WN. Other suitable materials can also be used. The thickness of the metallic barrier layer can range from 3 nm to 20 nm, although thinner and thicker thicknesses are also possible.

[0016] A metallic filler material, such as tungsten or copper, can be deposited in the remaining volumes of the bottom-electrode vias. Sections of the metallic filler material and the metallic barrier layer that overlie the horizontal plane, including the top surface of the bottom dielectric via layer 110, can be removed by a planarization process, such as chemical-mechanical planarization. Each remaining section of the metallic filler material located in a given via cavity has a metallic via filler section 124. Each remaining section of the metallic barrier layer in a given via cavity has a metallic barrier layer 122.Each combination of a metallic barrier layer 122 and a metallic via-filler section 124 that fills a via cavity constitutes a lower interconnect via structure 120. An array of lower interconnect via structures 120 can be formed in the lower dielectric interconnect via layer 110 on underlying metal interconnect structures. The array of lower interconnect via structures 120 can contact top surfaces of a subset of the fourth metal conductor structures 648. In general, the array of lower interconnect via structures 120 contacts top surfaces of a subset of lower-level metal conductors located on the topmost layer of the lower-level dielectric layers (601, 610, 620, 630, 640).

[0017] With reference to Fig. Figure 3 illustrates a memory cell region of the exemplary structure after the formation of a dielectric etch stop layer 112. The dielectric etch stop layer 112 can comprise a dielectric material that can be used as an etch stop structure during a subsequent anisotropic etching process. For example, the dielectric etch stop layer 112 can comprise a dielectric material such as silicon carbide, silicon carbide nitride, silicon nitride, silicon oxynitride, or a dielectric metal oxide such as aluminum oxide, lanthanum oxide, or titanium oxide. Other suitable dielectric materials are possible. The dielectric etch stop layer 112 can be deposited by chemical vapor deposition or atomic layer deposition. The thickness of the dielectric etch stop layer 112 can be in the range of 3 nm to 100 nm, such as 10 nm to 50 nm, although smaller and larger thicknesses can also be used.

[0018] A photoresist layer (not shown) can be applied over the dielectric etch stop layer 112 and can be lithographically structured to form an array of openings. Each opening can have a periphery that is laterally offset inward from a periphery of an underlying lower interconnect via structures 120 in a top view. In other words, the area of ​​each opening within the photoresist layer can be entirely within the area of ​​an underlying lower interconnect via structure 120. The structure in the photoresist layer can be transferred through the dielectric etch stop layer 112 by an anisotropic etching process that incorporates an etching chemistry which selectively etches the material of the dielectric etch stop layer 112 to the metallic materials of the lower interconnect via structures 120.The photoresist layer can then be removed, for example, by ashing.

[0019] In general, a dielectric etch stop layer 112, having an array of openings, can be formed over the array of lower interconnect via structures 120 above the dielectric material layers at the lower level (601, 610, 620, 630, 640). The horizontal cross-sectional shape of each opening through the dielectric etch stop layer 112 can be a circle, an ellipse, a rectangle, a rounded rectangle, or any two-dimensional curved shape with a closed periphery. The maximum lateral dimension (such as a diameter or principal axis) of each opening through the dielectric etch stop layer 112 can be in a range of 10 nm to 100 nm, such as 20 nm to 50 nm, although smaller and larger maximum lateral dimensions can also be used.

[0020] With reference to Fig. 4. A layer stack comprising at least one continuous lower metallic barrier layer 134C, one continuous lower metal layer 136C, one continuous transition metal compound layer 138C, one continuous resistive transition metal oxide layer 140C, one continuous upper metal layer 152C, at least one continuous upper metallic barrier layer (154C, 156C), and one continuous dielectric top layer 158C, can be deposited in an arrangement of openings on physically exposed surfaces of the lower interconnect via structures 120 and over the dielectric etch stop layer 112. The combination of the at least one continuous lower metallic barrier layer 134C, the continuous lower metal layer 136C, and the continuous transition metal compound layer 138C is subsequently used to structure lower electrodes and is thus referred to herein as continuous lower electrode material layers 130C.The combination of the continuous upper metal layer 152C and the at least one continuous upper metallic barrier layer (154C, 156C) is subsequently used to structure upper electrodes and is thus referred to herein as continuous upper electrode material layers 150C.

[0021] According to the invention, the at least one continuous lower metallic barrier layer 134C comprises a plurality of continuous lower metallic barrier layers, in particular a stack comprising, from bottom to top, a first continuous lower metallic barrier layer 131C, a second continuous lower metallic barrier layer 132C, and a third continuous lower metallic barrier layer 133C. The first continuous lower metallic barrier layer 131C comprises a first conductive metallic nitride material: tantalum nitride (TaN). The second continuous lower metallic barrier layer 132C comprises an elemental metal: tantalum (Ta). The third continuous lower metallic barrier layer 133C comprises a second conductive metallic nitride material: tantalum nitride (TaN).Each of the first continuous lower metallic barrier layer 131C, the second continuous lower metallic barrier layer 132C and the third continuous lower metallic barrier layer 133C can have a respective thickness in a range of 1 nm to 100 nm, such as 3 nm to 30 nm, although smaller and larger thicknesses can also be used.

[0022] Each of the first continuous lower metallic barrier layer 131C, the second continuous lower metallic barrier layer 132C, and the third continuous lower metallic barrier layer 133C can be deposited by a respective deposition process such as physical vapor deposition or chemical vapor deposition. The thickness of each of the first continuous lower metallic barrier layer 131C, the second continuous lower metallic barrier layer 132C, and the third continuous lower metallic barrier layer 133C can be in a range of 2 nm to 40 nm, such as 4 nm to 20 nm, although smaller and larger thicknesses can also be used.The atomic percentage of nitrogen atoms within each of the first continuous lower metallic barrier layer 131C and the third continuous lower metallic barrier layer 133C can be uniform or can be graded to decrease electrical resistance and increase electromigration resistance.

[0023] According to the invention, the continuous lower metal layer 136C comprises a first metal with a melting point of more than 2,000 degrees Celsius. For example, the continuous lower metal layer 136C can comprise hafnium, ruthenium, iridium, niobium, molybdenum, tantalum, osmium, rhenium, or tungsten. Other suitable metal materials are possible. In one embodiment, the continuous lower metal layer 136C can comprise an element of Group 8 (such as ruthenium or osmium) or an element of Group 9 (such as rhodium or iridium). In general, the use of a metal with a high melting point for the continuous lower metal layer 136C can be advantageous for the purpose of reducing or eliminating atoms of the first metal within lower electrodes during the operation of resistive memory cells. In one embodiment, the continuous lower metal layer 136C can comprise ruthenium.The continuous lower metal layer 136C can be deposited by physical vapor deposition or chemical vapor deposition. The thickness of the continuous lower metal layer 136C can be in a range of 1 nm to 100 nm, such as 3 nm to 30 nm and / or 6 nm to 20 nm, although smaller and larger thicknesses can also be used.

[0024] According to the invention, the continuous transition metal compound layer 138C comprises, and / or consists substantially of, an oxide or nitride of a transition metal selected from Ti, Ta, and W. In one embodiment, the continuous transition metal compound layer 138C comprises, and / or consists substantially of, a transition metal oxide material selected from titanium oxide and tantalum oxide. In one embodiment, the continuous resistive transition metal oxide layer 140C can be free of the metal contained in the continuous lower metal layer 136C. In this embodiment, the metal of the continuous lower metal layer 136C can be free of tantalum, titanium, or tungsten. In one embodiment, the continuous transition metal compound layer 138C can be formed by depositing a metallic compound material instead of depositing a metal followed by nitriding or oxidation.In one embodiment, the continuous transition metal compound layer 138C can have a uniform non-metallic atomic percentage throughout.

[0025] In one embodiment, the continuous transition metal compound layer 138C includes, and / or consists substantially of, titanium oxide. In this embodiment, the continuous transition metal compound layer 138C can have a uniform oxygen atom percentage or a uniform nitrogen atom percentage throughout.

[0026] In one embodiment, the titanium oxide material of the continuous transition metal compound layer 138C can be deposited by an atomic layer deposition process. In this embodiment, a titanium-containing precursor gas (such as tetrakis(dimethylamino)titanium (Ti(N(CH3)2)4; TDMAT), titanium tetrachloride (TiCl4), or titanium tetraisopropoxide (TTIP)) and an oxygen source gas (such as H2O, O3, or O2) can be alternately fed into a process chamber having the exemplary structure shown during the atomic layer deposition process. The process temperature can be in a range from 0°C to 400°C, such as from 10°C to 350°C, although lower and higher process temperatures can also be used.The flow rate for the titanium-containing precursor gas and the oxygen source gas can range from 40 standard cubic centimeters per minute (scm) to 1000 standard cubic centimeters per minute (scm), although lower and higher flow rates are also possible. The total number of cycles (i.e., the number of repetitions of the titanium-containing precursor gas and oxygen source gas streams) can range from 1 to 50, such as 3 to 20, although lower and higher numbers of cycles are also possible. The thickness of the continuous 138C transition metal compound layer can range from 0.5 nm to 10 nm, such as 1.5 nm to 4 nm, although lower and greater thicknesses are also possible.

[0027] In one embodiment, the continuous transition metal compound layer 138C comprises, and / or consists substantially of, tantalum oxide. In another embodiment, the tantalum oxide material of the continuous transition metal compound layer 138C can be deposited by an atomic layer deposition process. In this embodiment, a tantalum-containing precursor gas (such as Ta(OC2H5)5, Ta(N(CH3)2)5, TaCl5, TaI5, or tert-butylimido-tris-ethylmethylamido-tantalum) and an oxygen source gas (such as H2O, O3, or O2) can be alternately fed into a process chamber having the exemplary structure during the atomic layer deposition process. The process temperature can be in a range from 0°C to 400°C, such as from 20°C to 350°C, although lower and higher process temperatures can also be used.The flow rate for the tantalum-containing precursor gas and the oxygen source gas can range from 40 standard cubic centimeters per minute (scm) to 1000 standard cubic centimeters per minute (scm), although lower and higher flow rates are also possible. The total number of cycles (i.e., the number of repetitions of the tantalum-containing precursor gas and oxygen source gas streams) can range from 1 to 50, such as 3 to 20, although lower and higher numbers of cycles are also possible. The thickness of the continuous 138C transition metal compound layer can range from 0.5 nm to 10 nm, such as 1.5 nm to 4 nm, although lower and greater thicknesses are also possible.

[0028] In one embodiment, the continuous transition metal compound layer 138C comprises a transition metal nitride material, and / or consists substantially of a material selected from titanium nitride, tantalum nitride and tungsten nitride.

[0029] In one embodiment, the continuous transition metal compound layer 138C comprises, and / or consists substantially of, titanium nitride. In another embodiment, the titanium nitride material of the continuous transition metal compound layer 138C can be deposited by an atomic layer deposition process. In this embodiment, a titanium-containing precursor gas (such as tetrakis(dimethylamino)titanium (Ti(N(CH3)2)4; TDMAT), titanium tetrachloride (TiCl4), or titanium tetraisopropoxide (TTIP)) and a nitrogen source gas (such as NH3 or N2) can be alternately fed into a process chamber having the exemplary structure during the atomic layer deposition process. The process temperature can be in the range of 150°C to 400°C, such as 200°C to 350°C, although lower and higher process temperatures can also be used.The flow rate for the titanium-containing precursor gas and the nitrogen source gas can range from 40 standard cubic centimeters per minute (scm) to 1000 standard cubic centimeters per minute (scm), although lower and higher flow rates are also possible. The total number of cycles (i.e., the number of repetitions of the titanium-containing precursor gas and nitrogen source gas streams) can range from 1 to 50, such as 3 to 20, although lower and higher numbers of cycles are also possible. The thickness of the continuous 138C transition metal compound layer can range from 0.5 nm to 10 nm, such as 1.5 nm to 4 nm, although lower and greater thicknesses are also possible.

[0030] In one embodiment, the titanium nitride material of the continuous transition metal compound layer 138C can be deposited by physical vapor deposition in an ultra-high vacuum chamber. In this embodiment, at least one inert gas, such as nitrogen or argon, can be used as an ambient gas during the physical vapor deposition process. The flow rate of the nitrogen and / or the argon can range from 1 standard cubic centimeter per minute (sccm) to 300 standard cubic centimeters per minute (sccm), although lower and higher flow rates can also be used. The deposition temperature during the physical vapor deposition process can range from 0 degrees Celsius to 300 degrees Celsius, although lower and higher temperatures can also be used.The direct current power used during the physical vapor deposition process can range from 10 watts to 6,000 watts, for example, from 30 watts to 2,000 watts, although lower and higher power levels are also possible. The thickness of the continuous 138C transition metal compound layer can range from 0.5 nm to 10 nm, for example, from 1.5 nm to 4 nm, although lower and greater thicknesses are also possible.

[0031] In one embodiment, the titanium nitride material of the continuous transition metal compound layer 138C can be deposited by an atomic layer deposition process. In this embodiment, a titanium-containing precursor gas (such as tetrakis(dimethylamino)titanium (Ti(N(CH3)2)4; TDMAT), titanium tetrachloride (TiCl4), or titanium tetraisopropoxide (TTIP)) and a nitrogen source gas (such as NH3) can be alternately fed into a process chamber having the exemplary structure shown during the atomic layer deposition process. The process temperature can be in the range of 150°C to 600°C, such as 300°C to 550°C, although lower and higher process temperatures can also be used.The flow rate for the titanium-containing precursor gas and the nitrogen source gas can range from 1 standard cubic centimeter per minute (sccm) to 500 standard cubic centimeters per minute (sccm), although lower and higher flow rates are also possible. Optionally, a carrier gas, such as helium gas, can be introduced into the process chamber during the deposition process. The radio frequency (RF) power applied to generate plasmas of the titanium-containing precursor gas and the nitrogen source gas can range from 10 watts to 3,000 watts, for example, from 50 watts to 1,000 watts, although lower and higher RF powers are also possible. The thickness of the continuous 138C transition metal compound layer can range from 0.5 nm to 10 nm, for example, from 1.5 nm to 4 nm, although smaller and larger thicknesses are also possible.

[0032] In one embodiment, the tantalum nitride material of the continuous transition metal compound layer 138C can be deposited by physical vapor deposition in an ultra-high vacuum chamber. In this embodiment, at least one inert gas, such as nitrogen or argon, can be used as an ambient gas during the physical vapor deposition process. The flow rate of the nitrogen and / or the argon can range from 1 standard cubic centimeter per minute (sccm) to 300 standard cubic centimeters per minute (sccm), although lower and higher flow rates can also be used. The deposition temperature during the physical vapor deposition process can range from 0 degrees Celsius to 300 degrees Celsius, although lower and higher temperatures can also be used.The DC power used during the physical vapor deposition process can range from 10 watts to 6,000 watts, for example, from 30 watts to 2,000 watts, although lower and higher power levels are also possible. Optionally, coil power can be used during the physical vapor deposition process. In this embodiment, the coil power can range from 10 watts to 2,000 watts, although lower and higher values ​​are also possible. The thickness of the continuous 138C transition metal compound layer can range from 0.5 nm to 10 nm, for example, from 1.5 nm to 4 nm, although lower and higher thicknesses are also possible.

[0033] In one embodiment, the continuous transition metal compound layer 138C comprises, and / or consists substantially of, tungsten nitride. In another embodiment, the tungsten nitride material of the continuous transition metal compound layer 138C can be deposited by an atomic layer deposition process. In this embodiment, a tungsten-containing precursor gas (such as tungsten hexafluoride) and a nitrogen source gas (such as NH3 or N2) can be alternately fed into a process chamber comprising the exemplary structure during the chemical vapor deposition process. The process temperature can be in a range of 150°C to 600°C, such as 200°C to 500°C, although lower and higher process temperatures can also be used.The flow rate for the tungsten-containing precursor gas and the nitrogen source gas can range from 40 standard cubic centimeters per minute (scm) to 1000 standard cubic centimeters per minute (scm), although lower and higher flow rates are also possible. The total number of cycles (i.e., the number of repetitions of the tungsten-containing precursor gas and nitrogen source gas streams) can range from 1 to 50, such as 3 to 20, although lower and higher numbers of cycles are also possible. The thickness of the continuous 138C transition metal compound layer can range from 0.5 nm to 10 nm, such as 1.5 nm to 4 nm, although lower and greater thicknesses are also possible.

[0034] The continuous resistive transition metal oxide layer 140 contains, and / or consists substantially of, a conductive filament-forming dielectric oxide of at least one transition metal. A conductive filament-forming dielectric oxide refers to a dielectric oxide that can form conductive filaments through it when an electric field is applied. Examples of conductive filament-forming dielectric oxides include hafnium oxide, zirconium oxide, titanium oxide, hafnium zirconium oxide, and strontium cobalt oxide. The electrical resistance of the continuous resistive transition metal oxide layer 140 along the thickness direction (e.g., along the vertical direction) can change by at least one order of magnitude, such as two to six orders of magnitude, when conductive filaments are formed within it by applying an electrical bias.

[0035] In embodiments where the continuous resistive transition metal oxide layer 140 comprises hafnium oxide, a vertical electric field of approximately 2.6 MV / cm can be used to form conductive threads within it. An electric field of opposite polarity and of a lower magnitude can be applied to remove the conductive threads from within the continuous resistive transition metal oxide layer 140.

[0036] The continuous resistive transition metal oxide layer 140 can be deposited by atomic layer deposition, chemical vapor deposition, or physical vapor deposition. For example, if the continuous resistive transition metal oxide layer 140 contains hafnium oxide, atomic layer deposition can be performed using a hafnium-containing precursor gas (such as hafnium tetrachloride) and an oxygen source gas (such as H₂O, O₂, or O₃) alternately flowed into a process chamber containing the exemplary structure to deposit the continuous resistive transition metal oxide layer 140. The thickness of the continuous resistive transition metal oxide layer 140 can be in the range of 1 nm to 50 nm, such as 3 nm to 20 nm and / or 6 nm to 10 nm, although smaller and larger thicknesses can also be used.

[0037] The continuous upper metal layer 152C comprises, and / or consists substantially of, a second metal with a melting point above 2,000 degrees Celsius. For example, the continuous upper metal layer 152C may comprise hafnium, ruthenium, iridium, niobium, molybdenum, tantalum, osmium, rhenium, or tungsten. In general, the use of a metal with a high melting point for the continuous upper metal layer 152C is advantageous for the purpose of reducing or eliminating atoms of the first metal within lower electrodes during the operation of resistive memory cells. In one embodiment, the continuous upper metal layer 152C may comprise, and / or consist substantially of, a metal that is different from any component metal of the continuous resistive transition metal oxide layer 140. In one embodiment, the continuous resistive transition metal oxide layer 140 may consist substantially of tantalum.The continuous resistive transition metal oxide layer 140 can be deposited by physical vapor deposition or chemical vapor deposition. The thickness of the continuous top metal layer 152C can be in a range of 4 nm to 100 nm, such as 8 nm to 50 nm, although thinner and thicker thicknesses can also be used.

[0038] The at least one continuous upper metallic barrier layer (154C, 156C) comprises a plurality of continuous upper metallic barrier layers, in particular a stack comprising, from bottom to top, a first continuous upper metallic barrier layer 154C and a second continuous upper metallic barrier layer 156C. The first continuous upper metallic barrier layer 154C comprises a conductive metallic nitride material: tantalum nitride (TaN). The second continuous upper metallic barrier layer 156C comprises a different conductive metallic nitride material: titanium nitride (TiN).

[0039] Each of the first continuous upper metallic barrier layer 154C and the second continuous upper metallic barrier layer 156C can be deposited by a respective deposition process, such as physical vapor deposition or chemical vapor deposition. The thickness of each of the first continuous upper metallic barrier layer 154C and the second continuous upper metallic barrier layer 156C can be in the range of 1 nm to 100 nm, for example, from 3 nm to 30 nm, although smaller and larger thicknesses can also be used. The atomic percentage of nitrogen atoms within each of the first continuous upper metallic barrier layer 154C and the second continuous upper metallic barrier layer 156C can be uniform or can be graded to decrease electrical resistance and increase electromigration resistance.

[0040] The continuous dielectric cover layer 158C can be formed over the at least one continuous upper metallic barrier layer (154C, 156C). The continuous dielectric cover layer 158C comprises a dielectric material such as silicon oxide, silicon oxynitride, silicon carbide, or silicon carbide nitride. In one embodiment, the continuous dielectric cover layer 158C can consist essentially of silicon nitride. The continuous dielectric cover layer 158C can be deposited by a chemical vapor deposition process, such as a plasma-enhanced chemical vapor deposition process. The thickness of the continuous dielectric cover layer 158C over a planar section of the at least one continuous upper metallic barrier layer (154C, 156C) can be in the range of 10 nm to 500 nm, such as 30 nm to 100 nm, although smaller and larger thicknesses can also be used.

[0041] In general, the layer stack (130C, 140C, 150C, 158C) can be formed above the upper surface of the dielectric etch stop layer 112 and project into each opening through the dielectric etch stop layer 112. Each downward-projecting section of the layer stack (130C, 140C, 150C, 158C) fills a respective opening through the dielectric etch stop layer 112. A planar section of the layer stack (130C, 140C, 150C, 158C) overlaps the planar upper surface of the dielectric etch stop layer 112.

[0042] Within and around each opening in the dielectric etch stop layer 112, the continuous transition metal compound layer 138C has a lower surface comprising a planar central lower surface segment 381 located within the area of ​​the opening through the dielectric etch stop layer 112, a planar peripheral lower surface segment 382 located outside the area of ​​the opening through the dielectric etch stop layer 112, and a concave connecting lower surface segment 383 connecting the planar central lower surface segment 381 and the planar peripheral lower surface segment 382.Within and around each opening in the dielectric etch stop layer 112, the continuous transition metal compound layer 138C has an upper surface comprising a planar central upper surface segment 391 located within a region of the opening through the dielectric etch stop layer 112, a planar peripheral upper surface segment 392 located outside the region of the opening through the dielectric etch stop layer 112, and a convex connecting upper surface segment 393 connecting the planar central upper surface segment 391 and the planar peripheral upper surface segment 392.

[0043] With reference to Fig. 5. An etch mask layer 157 (such as a photoresist layer) can be applied over the layer stack (130C, 140C, 150C, 158C) and can be lithographically structured to form an array of structured etch mask sections. Each structured etch mask section can overlap and cover the area of ​​one of the openings in the dielectric etch stop layer 112. Each structured etch mask section can have a horizontal cross-sectional shape of a circle, an ellipse, a rectangle, a rounded rectangle, or any two-dimensional curved horizontal cross-sectional shape with a closed periphery.

[0044] A first anisotropic etching process can be performed to transfer the structure in the etch mask layer 157 through the continuous dielectric cover layer 158C and the continuous upper electrode material layers 150C. The etching chemistry of the first anisotropic etching process can be selected such that it etches through the materials of the continuous dielectric cover layer 158C and the continuous upper electrode material layers 150C. A subsequent step of the first anisotropic etching process can have an etching chemistry that is selective for the material of the continuous resistive transition metal oxide layer 140C.

[0045] Remaining structured sections of the continuous dielectric cover layer 158C have an arrangement of dielectric covers 158. Remaining structured sections of the second continuous upper metallic barrier layer 156C have an arrangement of second upper metallic barrier layers 156. Remaining structured sections of the first continuous upper metallic barrier layer 154C have an arrangement of first upper metallic barrier layers 154. Remaining structured sections of the continuous upper metal layer 152C have an upper metal layer 152. Within each memory cell region located above an opening in the dielectric etch stop layer 112, a stack of an upper metal layer 152, at least one upper metallic barrier layer (154, 156), and a dielectric cover 158 can be formed.The stack of the upper metal layer 152, the at least one upper metallic barrier layer (154, 156), and the dielectric cover 158 can have vertically coincident sidewalls, i.e., sidewalls that lie within the same vertical plane. Each contiguous combination of an upper metal layer 152 and at least one upper metallic barrier layer (154, 156) constitutes an upper electrode 150 of a memory cell, which is subsequently to be completed. The upper electrode 150 can have a lateral dimension in the range of 10 nm to 500 nm, such as 30 nm to 100 nm, although smaller and larger lateral dimensions can also be used. The etch mask layer 157 can subsequently be removed, for example, by ashing.

[0046] In general, the upper electrode 150 has an upper metal layer 152 comprising, and / or consisting substantially of, a second metal having a melting point above 2,000 degrees Celsius and at least one upper metallic barrier layer (154, 156). In one embodiment, the first metal of the continuous lower metal layer 136C comprises, and / or consists substantially of, an element selected from ruthenium, tantalum, tungsten, rhenium, niobium, molybdenum, osmium, and iridium, and the second metal of each upper metal layer 152 comprises, and / or consists substantially of, an element selected from ruthenium, tantalum, tungsten, rhenium, niobium, molybdenum, osmium, and iridium.

[0047] With reference to Fig. 6. A dielectric material layer can be conformally deposited by a conformal deposition process such as a chemical vapor deposition process. The dielectric material layer comprises, and / or consists substantially of, at least one dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, or a stack of layers thereof. The thickness of the dielectric material layer can be in the range of 4 nm to 200 nm, such as 8 nm to 100 nm, although smaller and larger thicknesses can also be used. In one embodiment, the material of the dielectric material layer can differ from the material of the dielectric covers 158.

[0048] A second anisotropic etching process can be performed to etch horizontal sections of the dielectric material layer. This second anisotropic etching process can be selective with respect to the material of the dielectric covers 158 and can optionally be selective with respect to the material of the continuous resistive transition metal oxide layer 140C. Each remaining vertically extending section of the dielectric material layer has a dielectric spacer 160 that laterally surrounds a respective stack of an upper electrode 150 and a dielectric cover 158. Each dielectric spacer 160 can contact side walls of a respective stack of an upper electrode 150 and a dielectric cover 158. Each dielectric spacer 160 can have a respective straight vertical inner side wall and a respective tapered convex outer side wall.The lateral distance between a straight vertical inner side wall and a tapered convex outer side wall can decrease with a vertical distance from the horizontal plane including the uppermost surface of the continuous resistive transition metal oxide layer 140C.

[0049] With reference to Fig. 7. A third anisotropic etching process can be carried out to etch sections of the continuous resistive transition metal oxide layer 140C and the continuous lower electrode material layers 130C using the combination of the dielectric covers 158 and the dielectric spacers 160 as an etching mask. The dielectric etch stop layer 112 can be used as an etch stop structure for the third anisotropic etching process.

[0050] Each structured section of the continuous resistive transition metal oxide layer 140C comprises a resistive transition metal oxide layer 140. Each structured section of the continuous transition metal compound layer 138C comprises a transition metal compound layer 138. Each structured section of the continuous lower metal layer 136C comprises a lower metal layer 136. Each structured section of the at least one continuous lower metallic barrier layer 134C comprises at least one lower metallic barrier layer 134. In one embodiment, the at least one lower metallic barrier layer 134 can have a stack of layers comprising, from bottom to top, a first lower metallic barrier layer 131, a second lower metallic barrier layer 132, and a third lower metallic barrier layer 133.The first lower metallic barrier layer 131 is a structured residual portion of the first continuous lower metallic barrier layer 131C. The second lower metallic barrier layer 132 is a structured residual portion of the second continuous lower metallic barrier layer 132C. The third lower metallic barrier layer 133 is a structured residual portion of the third continuous lower metallic barrier layer 133C. The first lower metallic barrier layer 131, the second lower metallic barrier layer 132, and the third lower metallic barrier layer 133 within each layer stack may have vertically coincident sidewalls.

[0051] Each connected combination of at least one lower metallic barrier layer 134, a lower metal layer 136, and a transition metal compound layer 138 constitutes a lower electrode 130. Each resistive transition metal oxide layer 140 can be formed between a respective underlying lower electrode 130 and a respective overlying upper electrode 150. Each connected combination of a lower electrode 130, a resistive transition metal oxide layer 140, an upper electrode 150, a dielectric spacer 160, and a dielectric cover 158 constitutes a resistive memory cell 101. The sidewalls of the lower electrode 130 and the resistive transition metal oxide layer 140 within each resistive memory cell can be vertically coincident.The sidewalls of the upper electrode 150 can be laterally recessed inwards with respect to the sidewalls of the lower electrode 130 and the resistive transition metal oxide layer 140 within each resistive memory cell. The lower electrode 130 can have a lateral dimension in the range of 15 nm to 1,000 nm, such as 40 nm to 150 nm, although smaller and larger lateral dimensions are also possible. The ratio of the lateral dimension of the lower electrode 130 to the lateral dimension of the upper electrode 130 can be in the range of 1.1 to 3, such as 1.2 to 2, although smaller and larger ratios are also possible.

[0052] In one embodiment, the lower electrode 130 comprises at least one lower metallic barrier layer 134, a lower metal layer 136 comprising a first metal with a melting point above 2,000 degrees Celsius, and a transition metal compound layer 138 comprising an oxide or nitride of a transition metal selected from Ti, Ta, and W. The resistive transition metal oxide layer 140 comprises a conductive, filament-forming dielectric oxide of at least one transition metal and is located on the transition metal compound layer 138. In one embodiment, the transition metal compound layer 138 comprises, and / or consists substantially of, a transition metal oxide material selected from titanium oxide and tantalum oxide, or a transition metal nitride material selected from titanium nitride, tantalum nitride, and tungsten nitride.

[0053] In one embodiment, the entire upper surface of the transition metal compound layer 138 can be in contact with the entire lower surface of the resistive transition metal oxide layer 140 within each resistive memory cell 101. In one embodiment, the conductive filament-forming dielectric oxide of the resistive transition metal oxide layer 140 comprises a material selected from hafnium oxide, zirconium oxide, titanium oxide, hafnium zirconium oxide, and strontium cobalt oxide. In one embodiment, each resistive memory cell 101 has a dielectric spacer 160 that laterally surrounds the upper electrode 150.

[0054] Within each resistive memory cell 101, the entire lower surface of the upper metal layer 152 can contact a central section of an upper surface of the resistive transition metal oxide layer 140, and the entire lower surface of the dielectric spacer 160 can contact a peripheral section of the upper surface of the resistive transition metal oxide layer 140. In one embodiment, each resistive memory cell 101 has a dielectric cover 158 that contacts an upper surface of the upper electrode 150. A periphery of the lower surface of the dielectric cover 158 coincides with a periphery of an upper surface of the upper electrode 150.

[0055] In one embodiment, the dielectric etch stop layer 112 has an opening beneath each resistive memory cell 101. For each resistive memory cell 101, a central section of the lower electrode 130 is located within an opening in the dielectric etch stop layer 112. A peripheral section of the lower electrode 130 is located outside the opening above an upper surface of the dielectric etch stop layer 112. A cylindrical connecting section of the lower electrode 130 contacts a side wall of the opening and extends vertically between the central section of the lower electrode 130 and the peripheral section of the lower electrode 130.

[0056] In one embodiment, the transition metal compound layer 138 has a lower surface comprising a planar central lower surface segment 381 located within a region of the opening through the dielectric etch stop layer 112, a planar peripheral lower surface segment 382 located outside the region of the opening through the dielectric etch stop layer 112, and a concave connecting lower surface segment 383 connecting the planar central lower surface segment 381 and the planar peripheral lower surface segment 382.In one embodiment, the transition metal compound layer 138 has an upper surface comprising a planar central upper surface segment 391 located within a region of the opening through the dielectric etch stop layer 112, a planar peripheral upper surface segment 392 located outside the region of the opening through the dielectric etch stop layer 112, and a convex connecting upper surface segment 393 connecting the planar central upper surface segment 391 and the planar peripheral upper surface segment 392.

[0057] In general, the layer stack comprising at least one continuous lower metallic barrier layer 134C, the continuous lower metal layer 136C, the continuous transition metal compound layer 138C, the continuous resistive transition metal oxide layer 140C, the continuous upper metal layer 152C, the at least one continuous upper metallic barrier layer (154C, 156C) and the continuous dielectric top layer 158C can be structured using at least one anisotropic etching process.Structured sections of the layer stack comprise: an upper electrode 150, which has structured sections of the at least one continuous upper metallic barrier layer (154C, 156C) and the continuous upper metal layer 152C; a resistive transition metal oxide layer 140, which has a structured section of the continuous resistive transition metal oxide layer 140C; and a lower electrode 130, which has structured sections of the at least one continuous lower metallic barrier layer 134C, the continuous lower metal layer 136C and the continuous transition metal compound layer 138C.

[0058] With reference to Fig. 8. An etch stop plate 162 can optionally be formed over each dielectric cover 158, for example, by depositing an etch stop material layer and structuring the etch stop material layer into an array of discrete etch stop plates 162. The etch stop material layer can be deposited by chemical vapor deposition or physical vapor deposition. For example, a photoresist layer can be applied over the etch stop material layer and can be lithographically structured to cover areas of the dielectric covers 158. An etching process can be performed to etch unmasked sections of the etch stop material layer using the structured photoresist layer as an etch mask. Remaining sections of the etch stop material layer feature the etch stop plates 162. The photoresist layer can subsequently be removed, for example, by ashing.

[0059] In one embodiment, the etch stop plates 162 can comprise a dielectric material such as a dielectric metal oxide. For example, the etch stop plate 162 can comprise aluminum oxide, hafnium oxide, lanthanum oxide, or another dielectric metal oxide material. In another embodiment, the etch stop plates 162 can comprise a metallic material such as a conductive metallic nitride material (e.g., tantalum nitride, titanium nitride, or tungsten nitride) or a conductive metal (e.g., titanium, tantalum, tungsten, ruthenium, molybdenum, or cobalt). The thickness of the etch stop plates 162 can be in the range of 4 nm to 100 nm, such as 8 nm to 50 nm, although smaller and larger thicknesses can also be used.

[0060] A dielectric lining 164 can optionally be deposited over the physically exposed surfaces of the dielectric etch stop layer 112, the resistive memory cells 101, and the etch stop plates 162. The dielectric lining 164 can comprise a non-porous dielectric material such as undoped silicate glass, doped silicate glass, silicon oxynitride, or silicon nitride. The dielectric lining 164 can be deposited by a conformal deposition process such as chemical vapor deposition. The thickness of the dielectric lining 164 can be in the range of 4 nm to 100 nm, such as 8 nm to 50 nm, although smaller and larger thicknesses can also be used.

[0061] A dielectric material layer can subsequently be deposited over the dielectric lining 164. The dielectric material layer is referred to herein as a top-level dielectric material layer 166. In one embodiment, the top-level dielectric material layer 166 can comprise a low-k dielectric material having a dielectric constant of less than 3.9. For example, the top-level dielectric material layer 166 can comprise non-porous organosilicate glass or porous organosilicate glass. Optionally, the top surface of the top-level dielectric material layer 166 can be planarized. The thickness of the top-level dielectric material layer 166, measured across the uppermost surfaces of the dielectric lining 164 that lie above the resistive memory cells 101, can be in a range from 50 nm to 1 nm.000 nm, such as from 100 nm to 500 nm, although smaller and larger thicknesses can also be used.

[0062] With reference to Fig. 9 and Fig. 10. A first photoresist layer can be applied over the upper surface of the dielectric material layer 166 at the top level and can be lithographically structured to form an array of openings. Each opening in the first photoresist layer can superimpose one of the resistive memory cells 101. In one embodiment, each opening in the first photoresist layer superimposed on a resistive memory cell 101 can have a periphery that is entirely within the periphery of an underlying upper electrode 150. An anisotropic etching process can be performed to transfer the structure of the openings in the first photoresist layer through the dielectric material layer 166 at the top level, the dielectric lining 164, the etch stop plates 162, and the dielectric covers 158.A via cavity can be formed by the dielectric material layer 166 at the top level, the dielectric lining 164, the etch stop plates 162, and the dielectric covers 158 over each resistive memory cell 101. The top surface of an upper electrode 150 can be physically exposed below each via cavity. The first photoresist layer can then be removed, for example, by ashing.

[0063] A second photoresist layer can be applied over the upper surface of the top-level dielectric material layer 166 and can be lithographically structured to form a line and spacer structure. Each spacer between a pair of line structures can superimpose a respective row of resistive memory cells 101 or a respective column of resistive memory cells 101. An anisotropic etching process can be performed to transfer the structure in the second photoresist layer into an upper section of the top-level dielectric material layer 166. The anisotropic etching process can be selective with respect to the material of the upper electrodes 150. Line trenches can be formed in the upper section of the top-level dielectric material layer 166. The line trenches laterally connect a respective row of vias or a respective column of vias.The second photoresist layer can then be removed, for example, by ashing.

[0064] At least one conductive material can be deposited in the through-hole plating cavities and line trenches. The at least one conductive material can comprise a metallic barrier liner 172 and a metallic filler section 174. The metallic barrier liner 172 can comprise a conductive metallic nitride material such as tantalum nitride, titanium nitride, or tungsten nitride. The metallic barrier liner 172 can be deposited by physical vapor deposition and / or chemical vapor deposition. The thickness of the metallic barrier liner 172 can be in the range of 4 nm to 50 nm, such as 8 nm to 25 nm, although smaller and larger thicknesses can also be used. The metallic filler section 174 comprises a metallic filler material such as copper, aluminum, tungsten, molybdenum, ruthenium, cobalt, or an alloy or stack of layers thereof.The metallic filler material section 174 can be deposited by physical vapor deposition, chemical vapor deposition, electroplating, electroless plating or a combination thereof.

[0065] Excessive sections of the metallic barrier lining 172 and the metallic filler section 174 above the horizontal plane, including the uppermost surface of the dielectric material layer 166, can be removed by a planarization process. The planarization process can, for example, employ a chemical-mechanical planarization process and / or a recess etching process. Each remaining structured section of the metallic barrier lining 172 and the metallic filler section 174, which fills a respective combination of a line trench and via cavities, constitutes an integrated line-and-via structure 170. Each integrated line-and-via structure 170 can include a respective upper interconnect metal conductor 170M and a respective one-dimensional array of upper interconnect via structures 170V.

[0066] Each lower via-connection via structure 120 can be used to provide an electrical connection to a lower electrode 130. Each upper via-connection via structure 170 can be used to provide an electrical connection to an upper electrode 150. Each upper via-connection via structure 170 can be formed on the upper surface of a respective upper electrode 150. In general, a dielectric material layer (such as the dielectric material layer 166 at the top level) surrounds the resistive memory cells 101 laterally.The dielectric material layer can have an upper surface located above the horizontal upper surfaces of the dielectric covers 158, and each upper interconnection via structure 170V can extend vertically through the dielectric material layer and a respective dielectric cover 158 and can contact an upper surface of a respective upper electrode 150.

[0067] Metal interconnect structures 666 at the storage level can be formed in the dielectric material layer 166 at the top level simultaneously with the formation of the integrated line-and-via structures 170. For example, additional via cavities in the peripheral area 200 can be formed simultaneously with the formation of via cavities in the storage arrangement area 100, and additional line trenches can be formed in the peripheral area 200 simultaneously with the formation of the line trenches in the storage arrangement area 100. The integrated line-and-via structures 170 and the metal interconnect structures 666 at the storage level feature metal interconnect structures (170, 666) at the top level, i.e., metal interconnect structures formed in an upper interconnect layer.Additional dielectric material layers (not shown) at the top level and additional metal interconnect structures (not shown) at the top level can be formed over the metal interconnect structures (170, 666) at the top level as required.

[0068] With reference to Fig. Figure 11 illustrates a flowchart of a sequence of processing steps for manufacturing a resistive storage device (such as a resistive memory cell 101) of the present disclosure.

[0069] With joint reference to Fig. 1 and Fig. 2 and step 1110 of Fig. 11 a lower interconnection via structure 120 can be formed by a dielectric material layer at the lower level, such as the lower dielectric interconnection via level 110.

[0070] With joint reference to Fig. 3 and Fig. 4 and step 1120 of Fig. 11. A layer stack comprising at least one continuous lower metallic barrier layer 134C, one continuous lower metal layer 136C, one continuous transition metal compound layer 138C, one continuous resistive transition metal oxide layer 140C, one continuous upper metal layer 152C, and at least one continuous upper metallic barrier layer (154C, 156C) can be formed over a substrate 9. The continuous lower metal layer 136C comprises, and / or consists substantially of, a first metal with a melting point above 2,000 degrees Celsius. The continuous transition metal compound layer 138C comprises, and / or consists substantially of, an oxide or nitride of a transition metal selected from Ti, Ta, and W. The continuous resistive transition metal oxide layer 140C has a conductive filament-forming dielectric oxide of at least one transition metal, and / or consists substantially of it.The continuous upper metal layer 152C contains a second metal with a melting point of more than 2,000 degrees Celsius, and / or consists essentially of it.

[0071] With joint reference to Fig. 5- Fig. 7 and step 1130 of Fig. 11. The layer stack can be structured using at least one anisotropic etching process. Structured sections of the layer stack comprise: an upper electrode 150, which has structured sections of the at least one continuous upper metallic barrier layer (154C, 156C) and the continuous upper metal layer 152C; a resistive transition metal oxide layer 140, which has a structured section of the continuous resistive transition metal oxide layer 140C; and a lower electrode 130, which has structured sections of the at least one continuous lower metallic barrier layer 134C, the continuous lower metal layer 136C, and the continuous transition metal compound layer 138C.

[0072] With joint reference to Fig. 8 and step 1140 of Fig. 11 a dielectric material layer 166 can be formed on the upper level around and above the resistive storage cell 101.

[0073] With joint reference to Fig. 9 and Fig. 10 and step 1150 of Fig. 11 an upper connection via structure 170V can be formed on the upper electrode 150 of the resistive memory cell 101.

[0074] With reference to all drawings and according to various embodiments of the present disclosure, a device structure comprising a resistive memory cell 101 is provided. The resistive memory cell 101 comprises: a lower electrode 130 having at least one lower metallic barrier layer 134, a lower metal layer 136 comprising a first metal having a melting point of more than 2,000 degrees Celsius, and a transition metal compound layer 138 comprising an oxide or nitride of a transition metal selected from Ti, Ta, and W; a resistive transition metal oxide layer 140 comprising a conductive thread-forming dielectric oxide of at least one transition metal and arranged on the transition metal compound layer; and an upper electrode 150 comprising an upper metal layer 152 and at least one upper metallic barrier layer 154, 156.

[0075] In one embodiment, the transition metal compound layer 138 comprises a transition metal oxide material and / or consists substantially of a material selected from titanium oxide and tantalum oxide. In another embodiment, the transition metal compound layer 138 comprises a transition metal nitride material and / or consists substantially of a material selected from titanium nitride, tantalum nitride, and tungsten nitride.

[0076] In one embodiment, an entire upper surface of the transition metal compound layer 138 is in contact with an entire lower surface of the resistive transition metal oxide layer 140. In one embodiment, the conductive thread-forming dielectric oxide comprises a material selected from hafnium oxide, zirconium oxide, titanium oxide, hafnium zirconium oxide, and strontium cobalt oxide.

[0077] In one embodiment, the resistive storage cell 101 has a dielectric spacer 160 that laterally surrounds the upper electrode 150. In another embodiment, an entire lower surface of the upper metal layer 152 contacts a central section of an upper surface of the resistive transition metal oxide layer 140; and an entire lower surface of the dielectric spacer 160 contacts a peripheral section of the upper surface of the resistive transition metal oxide layer 140.

[0078] In one embodiment, the resistive memory cell 101 has a dielectric cover 158 that contacts an upper surface of the upper electrode 150, wherein a periphery of a lower surface of the dielectric cover 158 coincides with a periphery of an upper surface of the upper electrode 150. In another embodiment, the device structure comprises: a dielectric material layer (such as a top-level dielectric material layer 166) that laterally surrounds the resistive memory cell 101 and has an upper surface that is located above a horizontal upper surface of the dielectric cover 158; and an upper interconnection via structure 170V that extends vertically through the dielectric material layer 166 and the dielectric cover 158 and contacts an upper surface of the upper electrode 150.

[0079] In one embodiment, the device structure has a dielectric etch stop layer 112 which has an opening. A central section of the lower electrode 130 is located inside the opening; a peripheral section of the lower electrode 130 is located outside the opening above an upper surface of the dielectric etch stop layer 112; and a cylindrical connecting section of the lower electrode 130 contacts a side wall of the opening and extends vertically between the central section of the lower electrode 130 and the peripheral section of the lower electrode 130.

[0080] In one embodiment, the transition metal compound layer 138 has a lower surface comprising a planar central lower surface segment 381 located within a region of the opening through the dielectric etch stop layer 112, a planar peripheral lower surface segment 382 located outside the region of the opening through the dielectric etch stop layer 112, and a concave connecting lower surface segment connecting the planar central lower surface segment 381 and the planar peripheral lower surface segment 382.In one embodiment, the transition metal compound layer 138 has an upper surface comprising a planar central upper surface segment 391 located within a region of the opening through the dielectric etch stop layer 112, a planar peripheral upper surface segment 392 located outside the region of the opening through the dielectric etch stop layer 112, and a convex connecting upper surface segment 393 connecting the planar central upper surface segment 391 and the planar peripheral upper surface segment 392.

[0081] In one embodiment, the first metal comprises an element selected from ruthenium, tantalum, tungsten, rhenium, niobium, molybdenum, osmium and iridium; and the second metal comprises an element selected from ruthenium, tantalum, tungsten, rhenium, niobium, molybdenum, osmium and iridium.

[0082] According to the invention, the at least one lower metallic barrier layer 134 has a lower vertical stack comprising, from bottom to top, a first lower tantalum nitride layer (comprising a first lower metallic barrier layer 131), a lower tantalum layer (comprising a second lower metallic barrier layer 132), and a second lower tantalum nitride layer (comprising a third lower metallic barrier layer 133); and the at least one upper metallic barrier layer (154, 156) has an upper vertical stack comprising, from bottom to top, an upper tantalum nitride layer (comprising a first upper metallic barrier layer 154) and a titanium nitride layer (comprising a second upper metallic barrier layer 156).

[0083] According to another aspect of the present disclosure, a plurality of resistive memory cells 101 can be arranged in a two-dimensional array. In this embodiment, the CMOS circuit 700 can include a peripheral circuit for operating the two-dimensional array of resistive memory cells 101. The CMOS circuit 700 can include a two-dimensional array of access transistors for programming, erasing, and reading each of the resistive memory cells 101. The lower-level metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) and the upper-level metal interconnect structures (170, 666) provide an electrical connection between the various nodes of the CMOS circuit and the lower electrodes 130 and the upper electrodes 150 of the resistive memory cells 101.

[0084] With reference to all drawings and according to various embodiments of the present disclosure, a random access resistive memory device (RRAM device) is provided, comprising: an arrangement of resistive memory cells 101 located above a substrate 9, each having a lower electrode 130, a resistive transition metal oxide layer 140, and an upper electrode 150; field-effect transistors located on the substrate 9; first metal interconnect structures (such as a subset of the lower metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648)) that electrically connect first nodes of the field-effect transistors to the lower electrodes 130 within the arrangement of resistive memory cells 101;and second metal interconnect structures (such as a subset of the lower metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) and the upper metal interconnect structures (170, 666) that electrically connect the second nodes of the field-effect transistors to the upper electrodes 150 within the arrangement of resistive memory cells 101. Each lower electrode 130 has at least one lower metallic barrier layer 134, a lower metal layer 136 comprising ruthenium, and a transition metal interconnect layer 138 comprising an oxide or nitride of a transition metal, and / or consisting substantially of, or consisting of, Ti, Ta, and W; each resistive transition metal oxide layer 140 comprising, and / or consisting substantially of, a conductive filament-forming dielectric oxide of at least one transition metal;and each upper electrode 150 has an upper metal layer comprising a second metal with a melting point of more than 2,000 degrees Celsius and at least one upper metallic barrier layer. According to the invention, the lower metallic barrier layer 134 has a lower vertical stack comprising, from bottom to top, a first lower tantalum nitride layer, a lower tantalum layer, and a second lower tantalum nitride layer; and the at least one upper metallic barrier layer 154, 156 has an upper vertical stack comprising, from bottom to top, an upper tantalum nitride layer and a titanium nitride layer.

[0085] In one embodiment, the transition metal compound layer 138 comprises: a transition metal oxide material selected from titanium oxide and tantalum oxide; or a transition metal nitride material selected from titanium nitride, tantalum nitride and tungsten nitride.

[0086] In an experiment designed to verify the effectiveness of an embodiment of the present disclosure, a device comprising an array of resistive memory cells 101 of the present disclosure was constructed. In this example, the lower metal layer 136 comprised ruthenium, and the transition metal compound layer 138 comprised 3.8 nm thick tantalum nitride deposited by physical vapor deposition or atomic layer deposition. Nitrogen treatment was performed after deposition of the tantalum nitride material. After a durability test of over 200,000 programming and erasing cycles, the failure rate of the resistive memory cells of the present disclosure was below the detection limit.Without wishing to be bound to any particular theory, it is assumed that the transition metal compound layer 138 reduces an interfacial surface roughness between the lower metal layer 136 and the resistive transition metal oxide layer 140, thereby increasing the durability of the resistive memory cell 101 of the present disclosure.

Claims

[1] Device structure comprising a resistive memory cell, wherein the resistive memory cell comprises: a lower electrode (130, 130C) comprising at least: a lower metallic barrier layer (134, 134C), a lower metal layer (136, 136C) comprising a first metal having a melting point of more than 2000 degrees Celsius, and a transition metal compound layer (138, 138C) comprising an oxide or nitride of a transition metal selected from Ti, Ta and W; a resistive transition metal oxide layer (140, 140C) comprising a conductive filament-forming dielectric oxide of at least one transition metal and located on the transition metal compound layer (138, 138C); and an upper electrode (150, 150C) having an upper metal layer (152, 152C) having a second metal, and at least one upper metallic barrier layer (154, 154C, 156, 156C) where: the lower metallic barrier layer (134, 134C) has a lower vertical stack comprising, from bottom to top, a first lower tantalum nitride layer (131, 131C), a lower tantalum layer (132, 132C), and a second lower tantalum nitride layer (133, 133C); and the at least one upper metallic barrier layer (154, 154C, 156, 156C) having an upper vertical stack comprising, from bottom to top, an upper tantalum nitride layer (154, 154C) and a titanium nitride layer (156, 156C). [2] Device structure according to claim 1, wherein the transition metal compound layer (138, 138C) comprises a transition metal oxide material selected from titanium oxide and tantalum oxide. [3] Device structure according to claim 1, wherein the transition metal compound layer (138, 138C) comprises a transition metal nitride material selected from titanium nitride, tantalum nitride and tungsten nitride. [4] Device structure according to one of the preceding claims, wherein an entirety of an upper surface of the transition metal compound layer (138, 138C) is in contact with an entirety of a lower surface of the resistive transition metal oxide layer (140, 140C). [5] Device structure according to one of the preceding claims, wherein the conductive thread-forming dielectric oxide comprises a material selected from hafnium oxide, zirconium oxide, titanium oxide, hafnium zirconium oxide and strontium cobalt oxide. [6] Device structure according to one of the preceding claims, wherein the resistive storage cell has a dielectric spacer (160) that laterally surrounds the upper electrode (150). [7] Device structure according to claim 6, wherein: a lower surface of the upper metal layer (152, 152C) contacts a middle section of an upper surface of the resistive transition metal oxide layer (140, 140C); and a totality of a lower surface of the dielectric spacer (160) contacts a peripheral section of the upper surface of the resistive transition metal oxide layer (140, 140C). [8] Device structure according to claim 6 or 7, wherein the resistive storage cell has a dielectric cover (158, 158C) which contacts an upper surface of the upper electrode (150, 150C), wherein a periphery of a lower surface of the dielectric cover (158, 158C) coincides with a periphery of an upper surface of the upper electrode (150, 150C). [9] Device structure according to claim 8, further comprising: a dielectric material layer (166) that laterally surrounds the resistive memory cell (101) and has an upper surface that is located above a horizontal upper surface of the dielectric cover (158); and an upper interconnection via structure (170) which extends vertically through the dielectric material layer (166) and the dielectric cover (158) and contacts an upper surface of the upper electrode (150, 150C). [10] Device structure according to one of the preceding claims, further comprising a dielectric etch stop layer (112) having an opening, wherein: a middle section of the lower electrode (130, 130C) is located within the opening; a peripheral section of the lower electrode (130, 130C) is located outside the opening above an upper surface of the dielectric etch stop layer (112); and a cylindrical connecting section of the lower electrode (130, 130C) contacts a side wall of the opening and extends vertically between the middle section of the lower electrode (130, 130C) and the peripheral section of the lower electrode (130, 130C). [11] Device structure according to claim 10, wherein the transition metal compound layer comprises (138, 138C): a lower surface comprising a planar central lower surface segment (381) located within a region of the opening through the dielectric etch stop layer (112), a planar peripheral lower surface segment (382) located outside the region of the opening through the dielectric etch stop layer (112), and a concave connecting lower surface segment (383) connecting the planar central lower surface segment (381) and the planar peripheral lower surface segment (382); and an upper surface comprising a planar central upper surface segment (391) located within a region of the opening through the dielectric etch stop layer (112), a planar peripheral upper surface segment (392) located outside the region of the opening through the dielectric etch stop layer (112), and a convex connecting upper surface segment (393) connecting the planar central upper surface segment (391) and the planar peripheral upper surface segment (392). [12] Device structure according to one of the preceding claims, wherein: the first metal contains an element selected from ruthenium, tantalum, tungsten, rhenium, niobium, molybdenum, osmium, and iridium; and the second metal contains an element selected from ruthenium, tantalum, tungsten, rhenium, niobium, molybdenum, osmium and iridium. [13] Resistive Random Access Memory device, comprising: an arrangement of resistive storage cells (101) located above a substrate (9) and comprising a respective lower electrode (130), a respective resistive transition metal oxide layer (140) and a respective upper electrode (150); Field-effect transistors located on the substrate (9); first metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) that electrically connect the first nodes of the field-effect transistors to the lower electrodes 130 within the arrangement of resistive memory cells (101); and second metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) that electrically connect the second node of the field-effect transistors to the upper electrodes within the arrangement of resistive memory cells (101), where: each lower electrode (130) shall have at least: a lower metallic barrier layer (134), a lower metal layer (136) comprising ruthenium, and a transition metal compound layer (138) comprising an oxide or nitride of a transition metal selected from Ti, Ta and W; each resistive transition metal oxide layer (140C) comprises a conductive thread-forming dielectric oxide of at least one transition metal; and each upper electrode (150) has an upper metal layer (152) comprising a second metal with a melting point of more than 2,000 degrees Celsius and at least one upper metallic barrier layer (154, 156), wherein: the lower metallic barrier layer (134) has a lower vertical stack comprising, from bottom to top, a first lower tantalum nitride layer (131), a lower tantalum nitride layer (132) and a second lower tantalum nitride layer (133); and the at least one upper metallic barrier layer (154, 156) having an upper vertical stack comprising, from bottom to top, an upper tantalum nitride layer (154) and a titanium nitride layer (156). [14] Resistive Random Access Memory device according to claim 13, wherein the transition metal compound layer (138) comprises: a transition metal oxide material selected from titanium oxide and tantalum oxide; or a transition metal nitride material selected from titanium nitride, tantalum nitride and tungsten nitride. [15] Method for forming a device structure comprising: Forming a layer stack comprising, from bottom to top: at least one continuous lower metallic barrier layer (134C), a continuous lower metal layer (136C), a continuous transition metal compound layer (138C), a continuous resistive transition metal oxide layer (140C), a continuous upper metal layer (152C), and at least one continuous upper metallic barrier layer (154C, 156C) over a substrate (9), wherein the at least one continuous lower metallic barrier layer (134C) comprises a lower vertical stack comprising, from bottom to top, a first lower tantalum nitride layer (131C), a lower tantalum layer (132C), and a second lower tantalum nitride layer (133C), the continuous lower metal layer (136C) comprises a first metal, and the continuous transition metal compound layer (138C) comprises an oxide or nitride of a transition metal selected from Ti, Ta, and W. is,the continuous resistive transition metal oxide layer (140C) comprises a conductive thread-forming dielectric oxide of at least one transition metal, the continuous upper metal layer (152C) comprises a second metal, and the at least one continuous upper metallic barrier layer (154C, 156C) comprises an upper vertical stack comprising, from bottom to top, an upper tantalum nitride layer (154) and a titanium nitride layer (156); and, Structuring the layer stack using at least one anisotropic etching process, wherein structured sections of the layer stack have: an upper electrode (150) having structured sections of the at least one continuous upper metallic barrier layer (154C, 156C) and the continuous upper metal layer (152C); a resistive transition metal oxide layer (140) which has a structured section of the continuous resistive transition metal oxide layer (140C); and a lower electrode (130) comprising structured sections of at least one continuous lower metallic barrier layer (134C), the continuous lower metal layer (136C) and the continuous transition metal compound layer (138C). [16] Method according to claim 15, wherein the continuous transition metal compound layer (138C) comprises: a transition metal oxide material selected from titanium oxide and tantalum oxide; or a transition metal nitride material selected from titanium nitride, tantalum nitride and tungsten nitride. [17] The method of claim 15 or 16, further comprising: Forming a continuous dielectric cover layer (158C) over the at least one continuous upper metallic barrier layer (154C, 156C); Forming an etch mask section (157) over the continuous dielectric cover layer (158C); and Transfer of a structure of the etch mask section through the continuous dielectric cover layer (158C), which includes at least one continuous upper metallic barrier layer (154C, 156C) and the continuous upper metal layer (152C), wherein a structured section of the continuous dielectric cover layer (158C) comprises a dielectric cover (158), a structured section of the at least one continuous upper metallic barrier layer (154C, 156C) comprises at least one upper metallic barrier layer (154, 156), and a structured section of the continuous upper metal layer (152C) comprises an upper metal layer (152). [18] The method of claim 17, further comprising: Forming a dielectric spacer (160) around the dielectric cover (158) and the upper electrode (150); and anisotropic etching of sections of the continuous resistive transition metal oxide layer (140C), the continuous transition metal compound layer (138C), the continuous lower metal layer (136C) and the at least one continuous lower metallic barrier layer (134C) using a combination of the dielectric cover (158) and the dielectric spacer (160) as an etching mask. [19] Method according to any one of claims 15 to 18, further comprising: Forming a lower interconnection via structure (120) embedded in a dielectric material layer (601, 610, 620, 630, 640) at a lower level above the substrate (9); Forming a dielectric etch stop layer (112) having an opening over the lower interconnect via structure (120) over the dielectric material layer at the lower level, wherein the layer stack is formed over the dielectric etch stop layer (112) and on a section of the lower interconnect via structure (120) which is located inside the opening in the dielectric etch stop layer (112); Forming a dielectric material layer (166) at the top level around the structured sections of the layer stack; and Forming an upper interconnection via structure (170) on an upper surface of the upper electrode (150).

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