LOCKING LAYER ON A PIEZOELECTRIC COMPONENT PAD AND MANUFACTURING METHOD

Abstract

IC chip (Integrated Circuit Chip), comprising: a substrate; a piezoelectric component that lies above the substrate; a pad that lies over the piezoelectric component; a via extending from the pad to the piezoelectric component; a barrier layer that lies above the pad; wherein the barrier layer is configured to block hydrogen ions from diffusing through the barrier layer from above the barrier layer to the piezoelectric device; and a trapping layer on the underside of the piezoelectric component and designed to trap hydrogen ions.

Description

BACKGROUND

[0001] Piezoelectric actuators and other suitable piezoelectric components can generate physical movement in response to an electrical signal. This physical movement can be used to control various types of mechanical and optical systems. For example, physical movement can be used to control the movement of a movable diaphragm to create a loudspeaker.

[0002] Prior art relating to the subject matter of the invention can be found, for example, in US 10 115 883 B2 and WO 2022 / 264 654 A1.

[0003] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 illustrates a cross-sectional view of some embodiments of an IC chip (integrated circuit chip) in which a barrier layer limits a pad of a piezoelectric device. Fig. Figure 2 illustrates an extended cross-sectional view of some embodiments of the IC chip from Fig. 1, in which the piezoelectric component surrounds a membrane. Fig. Figure 3 illustrates a top view of some embodiments of the IC chip of Fig. 2. Fig. 4A and Fig. Figure 4B illustrates top views of some alternative embodiments of the IC chip of Fig. 3. Fig. Figures 5A-5G illustrate cross-sectional views of some alternative embodiments of the IC chip. Fig. 2. Fig. 6, Fig. 7A, Fig. 7B, Fig. 8, Fig. 9A, Fig. 9B, Fig. 10, Fig. 11, Fig. 12A, Fig. 12B, Fig. 13, Fig. 14A, Fig. 14B, Fig. 15A, Fig. 15B, Fig. 16, Fig. 17A, Fig. 17B, Fig. 18, Fig. 19, Fig. 20A and Fig. Figure 20B illustrates a series of views of some embodiments of a method for forming an IC chip in which a barrier layer limits a pad of a piezoelectric device. Fig. Figure 21 illustrates a block diagram of some embodiments of the method of Fig. 6, Fig. 7A, Fig. 7B, Fig. 8, Fig. 9A, Fig. 9B, Fig. 10, Fig. 11, Fig. 12A, Fig. 12B, Fig. 13, Fig. 14A, Fig. 14B, Fig. 15A, Fig. 15B, Fig. 16, Fig. 17A, Fig. 17B, Fig. 18, Fig. 19, Fig. 20A and Fig. 20B. Fig. Figure 22 illustrates a cross-sectional view of some first alternative embodiments of the method of Fig. 6, Fig. 7A, Fig. 7B, Fig. 8, Fig. 9A, Fig. 9B, Fig. 10, Fig. 11, Fig. 12A, Fig. 12B, Fig. 13, Fig. 14A, Fig. 14B, Fig. 15A, Fig. 15B, Fig. 16, Fig. 17A, Fig. 17B, Fig. 18, Fig. 19, Fig. 20A and Fig. 20B. Fig. Figures 23-25 ​​illustrate a series of cross-sectional views of some second alternative embodiments of the method of Fig. 6, Fig. 7A, Fig. 7B, Fig. 8, Fig. 9A, Fig. 9B, Fig. 10, Fig. 11, Fig. 12A, Fig. 12B, Fig. 13, Fig. 14A, Fig. 14B, Fig. 15A, Fig. 15B, Fig. 16, Fig. 17A, Fig. 17B, Fig. 18, Fig. 19, Fig. 20A and Fig. 20B. Fig. 26 and Fig. Figure 27 illustrates a series of cross-sectional views of some third alternative embodiments of Fig. 6, Fig. 7A, Fig. 7B, Fig. 8, Fig. 9A, Fig. 9B, Fig. 10, Fig. 11, Fig. 12A, Fig. 12B, Fig. 13, Fig. 14A, Fig. 14B, Fig. 15A, Fig. 15B, Fig. 16, Fig. 17A, Fig. 17B, Fig. 18, Fig. 19, Fig. 20A and Fig. 20B. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments, or examples, for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first structural element over or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, such that the first and second structural elements might not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition serves the purpose of simplification and clarity and does not itself imply any relationship between the different embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative terms such as "underlying," "below," "under," "overlying," "above," and the like may be used herein to facilitate description and to describe the relationship of one element or structural element to another element(s) or structural element(s), as illustrated in the figures. These spatially relative terms are intended to encompass various orientations of the component in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0007] A piezoelectric actuator or other suitable piezoelectric device can comprise a bottom electrode, a piezoelectric layer above the bottom electrode, and a top electrode above the piezoelectric layer. A top electrode pad lies above the top electrode and is electrically coupled to it by a top electrode via extending from the top electrode pad to the top electrode. A bottom electrode pad lies above the bottom electrode and is electrically coupled to it by a bottom electrode via extending from the bottom electrode pad to the bottom electrode.

[0008] One challenge with piezoelectric devices is that hydrogen-ion-containing processes can be used after the piezoelectric layer has formed. Furthermore, the top-side and bottom-side vias can provide diffusion pathways for hydrogen ions from these processes to diffuse into the piezoelectric layer. Hydrogen ions diffusing into the piezoelectric layer can accumulate within it, causing delamination and fracture, which could lead to device failure.

[0009] Various embodiments of the present disclosure relate to an integrated circuit (IC) chip in which a pad barrier delimits a pad of a piezoelectric device. The pad barrier is configured to block hydrogen ions and / or other stray materials from diffusing to the piezoelectric layer. Without the pad barrier, hydrogen ions from hydrogen-containing processes performed after pad formation could diffuse along a via extending from the pad to the piezoelectric device. By blocking the diffusion of hydrogen ions and / or other stray materials to the piezoelectric device, the pad barrier can prevent delamination and fracture of the piezoelectric layer. Therefore, the pad barrier can prevent failure of the piezoelectric device.

[0010] In relation to Fig. Figure 1 shows a cross-sectional view 100 of some embodiments of an IC chip, in which a pad junction 102 delimits a pad 104 of a piezoelectric device 106. The piezoelectric device 106 is located above a substrate 108 and is separated from the substrate 108 by a dielectric substrate layer 110. Furthermore, the piezoelectric device 106 has a bottom electrode 112, a piezoelectric layer 114 located above the bottom electrode 112, and a top electrode 116 located above the piezoelectric layer 114. In some embodiments, the piezoelectric device 106 is an actuator, but other suitable types of piezoelectric devices are conceivable. In some embodiments, the piezoelectric device 106 can also be referred to as a metal-piezoelectric-metal structure (MPM structure) and / or a piezoelectric structure.

[0011] A barrier layer 118 and a dielectric layer 120 are located above the piezoelectric component 106 and are stacked between the piezoelectric component 106 and the pad 104. The barrier layer 118 separates the dielectric layer 120 from the piezoelectric component 106 and is designed to block hydrogen ions and / or other stray materials from diffusing from above the barrier layer 118 to the piezoelectric layer 114. In some embodiments, the barrier layer 118 can be considered a hydrogen barrier.

[0012] The pad 104 lies above the component barrier layer 118 and has a first end 104 fe and a second ending 104 se up. The first end 104 fe lies above the top electrode 116 and a via 122 extends from the first end 104 fe, through the component barrier layer 118 and the dielectric component layer 120 to the top electrode 116. In alternative embodiments, the via 122 extends to the bottom electrode 112 instead of the top electrode 116. The second end 104 se is distal to the first end 104 fe and offset laterally from the piezoelectric component 106.

[0013] The pad junction 102 delimits the pad 104, and a passivation layer 124 delimits the pad junction 102 and the dielectric component layer 120. Furthermore, a pad opening 126 extends through the pad junction 102 and the passivation layer 124 to the second end 104 seto expose the pad 104. Similar to the device barrier layer 118, the pad barrier layer 102 is configured to block hydrogen ions and / or other suitable stray materials from diffusing from above the pad 104 to the piezoelectric device 106. In some embodiments, the pad barrier layer 102 can be considered a hydrogen barrier layer. Without the pad barrier layer 102, hydrogen ions from the hydrogen-containing semiconductor fabrication processes, which are carried out after the formation of the pad 104, could diffuse along the via 122 to the piezoelectric layer 114.

[0014] Hydrogen ions diffusing to the piezoelectric layer 114 can accumulate within it, causing delamination and fracture of the layer, which can lead to the failure of the piezoelectric device 106. Therefore, by blocking the diffusion of hydrogen ions to the piezoelectric layer 114, the pad barrier 102 and the device barrier 118 can prevent delamination and fracture of the piezoelectric layer 114. Thus, the pad barrier 102 and the device barrier 118 can prevent the failure of the piezoelectric device 106.

[0015] Because the pad opening 126 extends through the pad barrier layer 102, hydrogen ions and / or other stray materials can extend through the pad barrier layer 102. However, because the pad opening 126 at the second end 104 seSince the pad 104 is offset laterally from the piezoelectric component 106, the diffusion path from the pad opening 126 to the piezoelectric layer 114 can be long. Therefore, the probability that hydrogen ions and / or other stray materials diffuse from the pad opening 126 to the piezoelectric layer 114 can be low.

[0016] In some embodiments, a thickness T pb The pad barrier layer 102 approximately 200-600 angstroms, approximately 200-400 angstroms, approximately 400-600 angstroms, or another suitable value. If the thickness T pb If the thickness T is too small (e.g., less than about 200 angstroms), the pad barrier layer 102 may be unable to block the diffusion of hydrogen ions and / or other stray materials through the pad barrier layer 102. pbIf the value is too large (e.g., more than about 600 angstroms), material may be wasted, and high topographic variation in the pad barrier layer 102 may present processing challenges that reduce manufacturing yields.

[0017] In some embodiments, the pad barrier layer 102 is crystalline and / or has a density greater than about 2 grams per cubic centimeter (g / cm³). 3 ), 2.6 g / cm³ 3 , 5 g / cm 3 or another suitable value. It was welcomed that such a density could block the diffusion of hydrogen ions and / or other stray materials through the pad barrier layer 102.

[0018] In some embodiments, the pad barrier 102 is a metal oxide or another suitable material. The metal oxide may be, for example, aluminum oxide (e.g., Al₂O₃), titanium oxide (e.g., TiO₂), iron oxide (e.g., Fe₂O₃), zirconium oxide (e.g., ZrO₂), zinc oxide (e.g., ZnO), copper oxide (e.g., CuO), tantalum oxide (e.g., Ta₂O₅), another suitable type of metal oxide, or any combination thereof. In some embodiments, the pad barrier 102 is dielectric. In some embodiments, during IC chip formation, the pad barrier 102 is deposited by a process that does not depend on hydrogen ions and / or other stray materials. For example, the pad barrier 102 may be deposited by physical vapor deposition (PVD) or another suitable type of deposition.

[0019] In some embodiments, the barrier layer 118 is made of the same material as the pad barrier layer 102. In other embodiments, the barrier layer 118 is made of a different material than the pad barrier layer 102. In some embodiments, the barrier layer 118 is crystalline and / or has a density greater than approximately 2 g / cm³. 3 , 2.6 g / cm³ 3 , 5 g / cm 3 or another suitable value. In some embodiments, the density is the same as that of the pad barrier layer 102. In some embodiments, the device barrier layer 118 is dielectric.

[0020] In some embodiments, the substrate 108 is a bulk substrate of silicon or another suitable type of semiconductor material. In other embodiments, the substrate 108 is a semiconductor-on-insulator (SOI) substrate or another suitable type of semiconductor substrate. To the extent that the substrate 108 is an SOI substrate, the semiconductor material of the SOI substrate may be silicon or another suitable type of semiconductor material.

[0021] In some embodiments, the dielectric substrate layer 110 is or contains silicon oxide and / or another suitable dielectric. In some embodiments, the dielectric component layer 120 is or contains silicon oxide and / or another suitable dielectric. In some embodiments, the dielectric substrate layer 110 and the dielectric component layer 120 are made of or contain the same material. In other embodiments, the dielectric substrate layer 110 and the dielectric component layer are made of or contain different materials. In some embodiments, the passivation layer 124 is or contains silicon nitride and / or another suitable dielectric.

[0022] In some embodiments, a diffusion rate of hydrogen ions through and / or into the pad barrier layer 102 is lower than: 1) a diffusion rate of hydrogen ions through and / or into the dielectric substrate layer 110; 2) a diffusion rate of hydrogen ions through and / or into the dielectric component layer 120; 3) a diffusion rate of hydrogen ions through and / or into the pad 104; 4) a diffusion rate of hydrogen ions through and / or into the passivation layer 124; or 5) any combination of the foregoing.Similarly, in some embodiments, the diffusion rate of hydrogen ions through and / or into the device barrier layer 118 is lower than: 1) a diffusion rate of hydrogen ions through and / or into the dielectric substrate layer 110; 2) a diffusion rate of hydrogen ions through and / or into the dielectric device layer 120; 3) a diffusion rate of hydrogen ions through and / or into the pad 104; 4) a diffusion rate of hydrogen ions through and / or into the passivation layer 124; or 5) any combination of the foregoing. The rates of the pad barrier layer 102 and / or the device barrier layer 118 can, for example, be zero or nearly zero.

[0023] In some embodiments, the piezoelectric layer 114 is or contains lead zirconium tanate (e.g., PZT) and / or another suitable piezoelectric material. In some embodiments, the bottom electrode 112 is or contains titanium oxide, platinum, another suitable metal or conductive material, or any combination thereof. In some embodiments, the top electrode 116 is or contains titanium oxide, platinum, another suitable metal or conductive material, or any combination thereof. In some embodiments, the bottom and top electrodes 112 and 116 are made of the same material. In other embodiments, the bottom and top electrodes 112 and 116 are made of different materials.

[0024] In some embodiments, the pad is or contains copper, aluminum copper, aluminum, another suitable metal or conductive material, or any combination thereof. In some embodiments, the barrier layer 118 is configured to block material from the pad 104 diffusing from the pad 104 to the piezoelectric component 106. Such material may, for example, be or contain copper and / or another suitable material.

[0025] In some embodiments, while not shown, a solder hill structure, a wire bond structure or another suitable type of conductive structure is formed in the pad opening 126 to electrically couple the pad 104 and thus the piezoelectric device 106 to another IC chip, printed circuit board (PCB), wiring layer structure or other suitable structure.

[0026] In relation to Fig. Figure 2 is an extended cross-sectional view of 200 of some embodiments of the IC chip from Fig. Figure 1 provides a piezoelectric element 106 surrounding a membrane 202. When a voltage is applied from the top electrode 116 to the bottom electrode 112, the piezoelectric element 106 vibrates, causing the membrane 202 to move within a sound aperture 204. Therefore, the membrane 202 and the piezoelectric element 106 together form a piezoelectric loudspeaker or other suitable structure.

[0027] A pair of pads 104 and a pair of vias 122 are electrically coupled to the piezoelectric device 106. The pair of pads 104 has a top electrode pad 104t and a bottom electrode pad 104b, and the pair of vias 122 has a top electrode via 122t and a bottom electrode via 122b. The top electrode pad 104t and the top electrode via 122t correspond to the pad 104 and the via 122, which are connected with respect to Fig. Figure 1 illustrates and describes the following. The bottom electrode pad 104b and the bottom electrode via 122b are located on opposite sides of the sound aperture 204 to the top electrode pad 104t and the top electrode via 122t. Furthermore, the bottom electrode via 122b extends from the bottom electrode pad 104b to the bottom electrode 112.

[0028] The pad barrier layer 102 delimits both pads 104 and has a top electrode barrier segment 102t and a bottom electrode barrier segment 102b. The top electrode barrier segment 102t delimits the top electrode pad 104t, whereas the bottom electrode barrier segment 102b delimits the bottom electrode pad 104b.

[0029] By confining the pads 104, the pad barrier 102 prevents hydrogen ions and / or other stray particles from diffusing from above the top electrode pad 104z and the bottom electrode pad 104b to the piezoelectric device 106. Without the pad barrier 102, hydrogen ions from the hydrogen-containing semiconductor fabrication processes performed after the formation of the top electrode pad 104t and the bottom electrode pad 104b could diffuse along the top electrode via 122t and / or along the bottom electrode via 122b to the piezoelectric layer 114. This can induce delamination and fracture of the piezoelectric layer 114, which can lead to the failure of the piezoelectric device 106. Therefore, by blocking diffusion of hydrogen ions to the piezoelectric layer 114, the pad barrier layer 102 can prevent failure of the piezoelectric device 106.

[0030] Each pair of pad openings 126 exposes the pads 104 at locations laterally offset from the piezoelectric device 106, allowing for long diffusion paths from the pad openings 126 to the piezoelectric layer 114. Because the diffusion paths can be long, the probability of hydrogen ions and / or other stray materials diffusing from the pad openings 126 to the piezoelectric layer 114 may be low.

[0031] The substrate 108 is an SOI substrate and comprises a lower semiconductor layer 1081, an insulating layer 108i above the lower semiconductor layer 1081, and an upper semiconductor layer 108u above the insulating layer 108i. In some embodiments, the insulating layer is or contains silicon oxide and / or another suitable dielectric. In some embodiments, the lower semiconductor layer 108l and the upper semiconductor layers 108u are or contain silicon and / or another suitable semiconductor.

[0032] The membrane 202 corresponds to a section of the upper semiconductor layer 108u and is connected to a remainder of the upper semiconductor layer 108u outside the cross-sectional view 200 of Fig. 2 connected. Furthermore, as previously described, the membrane 202 moves in the sound opening 204 in response to vibrations from the piezoelectric component 106. Therefore, the piezoelectric component 106 can also be considered a piezoelectric actuator or another suitable type of piezoelectric component, and the piezoelectric component 106 and the membrane 202 can together form a piezoelectric loudspeaker.

[0033] The sound opening 204 extends through the substrate 108, the dielectric substrate layer 110, the dielectric component layer 120, and the passivation layer 124. Furthermore, the substrate 108, the dielectric substrate layer 110, the dielectric component layer 120, and the passivation layer 124 form a common side wall in the sound opening 204. In alternative embodiments, the dielectric component layer 120 and / or the passivation layer 124 do not form the common side wall, and / or the component barrier layer 118 also forms the common side wall.

[0034] In relation to Fig. Figure 3 shows a top view of 300 of some embodiments of the IC chip from Fig. 2 provided. The cross-sectional view 200 of Fig. 2 can, for example, be taken along line A and the sections of the cross-sectional view 200 of Fig. The two illustrated IC chips correspond, for example, to continuous sections of line A.

[0035] The diaphragm 202 has a circular top surface geometry, and the sound opening 204 has six slot-shaped segments. The slot-shaped segments extend through the diaphragm 202 (see cross-sectional view 200 of Fig. 2) and are spaced regularly around the membrane 202 at 0 degrees, 60 degrees, 120 degrees, 180 degrees, 240 degrees, and 300 degrees. In other embodiments, the slot-shaped segments may be spaced irregularly around the membrane 202. Furthermore, in other embodiments, the sound opening 204 has more or fewer slot-shaped segments. For example, the sound opening 204 may have 8, 12, or another suitable number of slot-shaped segments.

[0036] The piezoelectric device 106 (parts of which are shown as shadows) has an annular top surface geometry that extends in a closed path around the membrane 202. In alternative embodiments, the piezoelectric device 106 has a different suitable top surface geometry. Furthermore, the top surface electrode pad 104t and the bottom surface electrode pad 104b (both shown as shadows) extend from the top surface electrode via 122t and the bottom surface electrode via 122b, respectively, to locations laterally offset from the piezoelectric device 106.

[0037] The top electrode and bottom electrode barrier segments 102t, 102b (collectively the barrier segments 102t, 102b) of the pad barrier layer 102 are individually designed for the top electrode pad 104t and the bottom electrode pad 104b, respectively, and overlap them. Furthermore, the barrier segments 102t, 102b have top surface geometric shapes that correspond to the top surface geometric shapes of the top electrode pad 104t and the bottom electrode pad 104b. For example, the barrier segments 102t, 102b, as well as the top electrode pad 104t and the bottom electrode pad 104b, can have L-shaped top surface geometric shapes or other suitable top surface geometric shapes. In alternative embodiments, the barrier segments 102t, 102b have top-side geometric shapes that differ from those of the top electrode pad 104t and the bottom electrode pad 104b.

[0038] While the sound opening 204 is illustrated with six slot-shaped segments spaced around the diaphragm 202, more or less slot-shaped segments are conceivable. For example, with regard to Fig. 4A and Fig. 4B are top views 400A, 400B of some alternative embodiments of the IC chip of Fig. Three were provided, in which the number of slit-shaped segments varied. In Fig. 4A has the sound opening 204 with eight slot-shaped segments. In Fig. 4B has the sound opening 204 with twelve slot-shaped segments.

[0039] In relation to Fig. 5A-5G are cross-sectional views 500A-500G of some alternative embodiments of the IC chip from Fig. 2 provided.

[0040] in Fig. 5A is the passivation layer 124 on the side walls of the diaphragm 202 and on a top surface of the diaphragm 202. Furthermore, the passivation layer 124 lines a common side wall formed by the upper semiconductor layer 108u, the dielectric substrate layer 110, and the dielectric component layer 120. This can modify the stiffness of the diaphragm 202, allowing the diaphragm 202 to vibrate differently during use of the piezoelectric loudspeaker, which is formed jointly by the diaphragm 202 and the piezoelectric component 106.

[0041] In Fig. 5B are both the passivation layer 124 and the pad barrier layer 102 on side walls of the diaphragm 202 and a top surface of the diaphragm 202. Furthermore, both the passivation layer 124 and the pad barrier layer 102 line a common side wall formed by the upper semiconductor layer 108u, the dielectric substrate layer 110, and the dielectric component layer 120. This can change the stiffness of the diaphragm 202, allowing the diaphragm 202 to vibrate differently during use of the piezoelectric loudspeaker formed jointly by the diaphragm 202 and the piezoelectric component 106. In some embodiments, the top electrode and bottom electrode barrier segments 102t, 102b of the pad barrier layer 102 are located outside the cross-sectional view 500B of Fig. 5B connected.

[0042] In Fig. 5C the top electrode 116 and the piezoelectric layer 114 form common side walls and share a common width that is less than that of the bottom electrode 112.

[0043] In Fig. In 5D, the bottom and top electrodes 112, 116 and the piezoelectric layer 114 form common sidewalls and share a common width. Furthermore, a trapping layer 502 separates the piezoelectric device 106 from the dielectric substrate layer 110 and has a greater width than the common width. The trapping layer 502 is configured to absorb hydrogen ions and / or other stray materials, thereby preventing them from diffusing to and accumulating in the piezoelectric layer 114. As previously described, hydrogen ions accumulating in the piezoelectric layer 114 can induce detachment and fracture of the piezoelectric layer 114, potentially leading to failure of the piezoelectric device 106. Accordingly, by absorbing hydrogen ions, the trapping layer 502 can prevent device failure.

[0044] In some embodiments, the dielectric substrate layer 110 contains hydrogen ions, which are absorbed by the trapping layer 502 to prevent the hydrogen ions from diffusing to the piezoelectric layer 114. For example, the dielectric substrate layer 110 may contain hydrogen ions in embodiments in which the dielectric substrate layer 110 is tetraethyl orthosilicate silicon dioxide (TEOS-SiO2), silane silicon dioxide (e.g., SiH4-SiO2), another suitable oxide or dielectric, or any combination thereof. In some embodiments, the trapping layer 502 is or contains titanium, barium, cerium, lanthanum, aluminum, magnesium, thorium, or another suitable conductive trapping material for hydrogen ions and / or other stray materials.

[0045] In Fig. In 5E, the bottom electrode 112 and the trapping layer 502 share a first common width and form first common sidewalls. Furthermore, the piezoelectric layer 114 and the top electrode 116 share a second common width, which is smaller than the first common width, and form second common sidewalls that are laterally offset from the first common sidewalls.

[0046] In Fig. 5F separates the in relation to Fig. The trapping layer 502 described in 5D separates the top electrode 116 from the device barrier layer 118 instead of separating the bottom electrode 112 from the dielectric substrate layer 110. Furthermore, the trapping layer 502 forms common side walls with the top electrode 116 and the piezoelectric layer 114 and shares a common width with the top electrode 116 and the piezoelectric layer 114.

[0047] In Fig. 5G is a top electrode trapping layer 502t on the top electrode 116, whereas a bottom electrode trapping layer 502b is on a bottom side of the bottom electrode 112. The bottom electrode trapping layer 502b and the bottom electrode trapping layer 502b are described with respect to Fig. 5EE and Fig. 5F described as their counterparts.

[0048] In relation to Fig. 6, Fig. 7A, Fig. 7B, Fig. 8, Fig. 9A, Fig. 9B, Fig. 10, Fig. 11, Fig. 12A, Fig. 12B, Fig. 13, Fig. 14A, Fig. 14B, Fig. 15A, Fig. 15B, Fig. 16, Fig. 17A, Fig. 17B, Fig. 18, Fig. 19, Fig. 20A and Fig. Figure 20B provides a series of views of some embodiments of a method for forming an IC chip in which a barrier layer delimits a pad of a piezoelectric device. Figures marked with a suffix "A" or no suffix correspond to cross-sectional views, and figures marked with a suffix "B" correspond to top views of similarly numbered figures with a suffix "A". The cross-sectional views of figures marked with a suffix "A" can be taken, for example, along line A or B (whichever is present) in the top views of corresponding figures marked with a suffix "B". The method is illustrated for forming an IC chip according to the embodiments of Fig. 2 and Fig. 3. However, the method can alternatively be used to form an IC chip according to other suitable embodiments.

[0049] As seen through a cross-sectional view 600 of Fig. As illustrated in Figure 6, a dielectric substrate layer 110 is deposited over a substrate 108. The substrate 108 is a SOI substrate and comprises a lower semiconductor layer 108l, an insulating layer 108i above the lower semiconductor layer 108l, and an upper semiconductor layer 108u above the insulating layer 108i. In alternative embodiments, the substrate 108 is a bulk semiconductor substrate or another suitable type of semiconductor substrate. In some embodiments, the dielectric substrate layer 110 and the insulating layer 108i are the same material. In other embodiments, the dielectric substrate layer 110 and the insulating layer 108i are different materials.

[0050] Also from the cross-sectional view 600 of Fig. As illustrated in Figure 6, a component film 602 is deposited over the dielectric substrate layer 110 and comprises a bottom electrode layer 1121, a piezoelectric layer 114 lying above the bottom electrode layer 1121, and a top electrode layer 1161 lying above the piezoelectric layer 114. In some embodiments, the bottom electrode layer 1121 and the top electrode layer 1161 are made of the same material. In other embodiments, the bottom electrode layer 1121 and the top electrode layer 1161 are made of different materials.

[0051] As seen in a cross-sectional view of 700A from Fig. 7A and a top view 700B of Fig. 7B illustrates the component film 602 (see e.g. Fig. 6) structured to form a piezoelectric device 106 having a ring-shaped top surface geometry (see e.g. Fig. 7B) and extends in a closed path around a central region 702. In alternative embodiments, the piezoelectric device 106 can have a different suitable top surface geometry extending in a closed path around the central region 702. The piezoelectric device 106 comprises a bottom electrode 112, a structured section of the piezoelectric layer 114 (hereinafter referred to simply as the piezoelectric layer 114) located above the bottom electrode 112, and a top electrode 116 located above the piezoelectric layer 114.

[0052] The bottom electrode 112 corresponds to a structured section of the bottom electrode layer 112l (see e.g. Fig. 6), whereas the top electrode 116 corresponds to a structured section of the top electrode 116l. The piezoelectric layer 114 has a narrower width than the bottom electrode 112 and furthermore has sidewalls that are laterally offset from the sidewalls of the bottom electrode 112. The top electrode 116 has a narrower width than the piezoelectric layer 114 and furthermore has sidewalls that are laterally offset from the sidewalls of the piezoelectric layer 114.

[0053] In some embodiments, the structuring process does not introduce hydrogen ions and / or other stray materials that could diffuse to the piezoelectric layer 114 and induce its failure. Hydrogen ions diffusing to the piezoelectric layer 114 can accumulate within it and induce delamination and fracture of the piezoelectric layer 114, potentially causing the piezoelectric device 106 to fail.

[0054] In some embodiments, a process for performing the structuring comprises: 1) performing a first photolithography / etching process into the top electrode layer 116l using a first mask to form the top electrode 116; 2) performing a second photolithography / etching process into the piezoelectric layer 114 using a second mask; and 3) performing a third photolithography / etching process into the bottom electrode layer 112l using a third mask to form the bottom electrode 112. In alternative embodiments, another suitable process for structuring is performed.For example, the top electrode layer 116l and the piezoelectric layer 114 can be patterned together using a common photolithography / etching process and a common mask, whereas the bottom electrode layer 1121 can be patterned using a different photolithography / etching process and a different mask. Alternatively, the top electrode layer 1161, the piezoelectric layer 114, and the bottom electrode layer 1121 can be patterned together using a common photolithography / etching process and a common mask. The two alternative examples use fewer masks and therefore reduce manufacturing costs.

[0055] As seen through a cross-sectional view 800 of Fig. As illustrated in Figure 8, a device barrier layer 118 is deposited, covering the piezoelectric device 106 and the dielectric substrate layer 110. The device barrier layer 118 is designed to block hydrogen and / or other suitable stray materials from diffusing from above the device barrier layer 118 to the piezoelectric layer 114. By blocking the diffusion of stray materials (e.g., hydrogen ions) to the piezoelectric layer 114, the pad barrier layer 102 can prevent failure of the piezoelectric device 106.

[0056] In some embodiments, the component barrier layer 118 is a metal oxide or another suitable material. The metal oxide can be, for example, aluminum oxide (e.g., Al₂O₃), titanium oxide (e.g., TiO₂), iron oxide (e.g., Fe₂O₃), zirconium oxide (e.g., ZrO₂), zinc oxide (e.g., ZnO), copper oxide (e.g., CuO), tantalum oxide (e.g., Ta₂O₅), another suitable type of metal oxide, or any combination thereof.

[0057] The barrier layer 118 is deposited by a process that does not expose the piezoelectric layer 114 to hydrogen ions and / or other suitable stray materials. For example, the barrier layer 118 can be deposited by physical vapor deposition (PVD), atomic layer deposition (ALD), or another suitable process.

[0058] As seen in a cross-sectional view of 900A from Fig. 9A and a top view 900B of Fig. Figure 9B illustrates how the barrier layer 118 is patterned to remove a central section of the barrier layer 118 surrounding the piezoelectric device 106. Furthermore, the patterning removes an edge section of the barrier layer 118 surrounding the piezoelectric device 106. Upon completion of the patterning, the piezoelectric device 106 remains covered by the barrier layer 118 (e.g., completely covered). The patterning can be performed, for example, by a photolithography / etching process or another suitable process.

[0059] As seen through a cross-sectional view of 1000 of Fig. As illustrated in Figure 10, a dielectric component layer 120 is deposited, covering the component barrier layer 118. The dielectric component layer 120 can be, for example, TEOS oxide and / or another suitable dielectric(s). In some embodiments, the dielectric component layer 120 is deposited by a deposition process that exposes the component barrier layer 118 to hydrogen ions and / or other stray materials. In such embodiments, the component barrier layer 118 blocks the stray material (e.g., the hydrogen ions) from accumulating in the piezoelectric layer 114. As described above, this can, for example, prevent failure of the piezoelectric component 106.

[0060] As seen in the cross-sectional view 1100 of Fig. As illustrated in Figure 11, the dielectric component layer 120 and the component barrier layer 118 are patterned to form a pair of vias 1102. The vias 1102 are individually for and expose the top electrode 116 and the bottom electrode 112. In some embodiments, the patterning is performed by a process that employs hydrogen ions and / or other stray materials that can diffuse to the piezoelectric layer 114 and induce its failure. In other embodiments, the patterning is performed by a photolithography / etching process or by another suitable patterning process.

[0061] As seen through a cross-sectional view 1200 of Fig. 12A and a top view 1200B of Fig. As illustrated in Figure 12B, a pair of pads 104 and a pair of vias 122 are formed. The pads 104 have first ends individually for the via openings 1102 (see, for example, Figure 12B). Fig. 11) and superimposed on these. Furthermore, the pads 104 have second ends offset distal to and laterally from the first ends. The vias 122 are individually designed for and fill the via openings 1102. The vias 122 also extend from the pads 104 to the top electrode 116 and the bottom electrode 112, respectively. In some embodiments, the pads 104 and the vias 122 are part of a common layer. In other embodiments, the pads 104 are part of a first layer, whereas the vias 122 are part of a second layer that differs from the first layer.

[0062] In some embodiments, the pads 104 and the vias 122 are formed by a process that does not employ hydrogen ions and / or other stray materials that could diffuse to the piezoelectric layer 114 and induce its failure. In some embodiments, a process for forming the pads 104 and the vias 122 comprises: 1) depositing a conductive layer that covers the dielectric component layer 120 and fills the vias 1102; and 2) performing a photolithography / etching process to pattern the conductive layer into the pads 104. In alternative embodiments, another suitable process for forming the pads 104 and the vias 122 is employed.

[0063] As seen through a cross-sectional view 1300 of Fig. As illustrated in Figure 13, a pad barrier layer 102 is deposited, covering the pads 104 and the dielectric component layer 120. The pad barrier layer 102 is designed to block hydrogen ions and / or other suitable stray materials from diffusing from above the pad 104 to the piezoelectric component 106.

[0064] Without the pad barrier 102, hydrogen ions from hydrogen-containing semiconductor fabrication processes performed after the formation of the pad 104 can diffuse along the vias 122 to the piezoelectric layer 114. As previously described, hydrogen ions diffusing to the piezoelectric layer 114 can accumulate within it and induce delamination and fracture of the piezoelectric layer 114, potentially leading to the failure of the piezoelectric device 106. Therefore, by blocking the diffusion of hydrogen ions to the piezoelectric layer 114, the device barrier 118 can prevent delamination and fracture of the piezoelectric layer 114. This, in turn, can prevent the failure of the piezoelectric device 106.

[0065] The pad barrier layer 102 is deposited by a process that does not expose the pads 104 to hydrogen ions and / or other suitable stray materials. For example, the pad barrier layer 102 can be deposited by PVD, ALD, or another suitable process.

[0066] In some embodiments, a thickness T pb The pad barrier layer 102 approximately 200-600 angstroms, approximately 200-400 angstroms, approximately 400-600 angstroms, or another suitable value. If the thickness T pb If the thickness T is too small (e.g., less than approximately 200 angstroms), the pad barrier layer 102 may be unable to block the diffusion of hydrogen ions and / or other stray materials through the pad barrier layer 102. pbIf the value is too large (e.g., more than about 600 angstroms), material may be wasted, and high topographic variation in the pad barrier layer 102 may present processing challenges that reduce manufacturing yields.

[0067] In some embodiments, the pad barrier layer 102 is crystalline and / or has a density greater than about 2 g / cm³. 3 , 2.6 g / cm³ 3 , 5 g / cm 3or another suitable value. It was welcomed that such a density can block diffusion of hydrogen ions and / or other stray materials through the pad barrier layer 102. In some embodiments, the pad barrier layer 102 is a metal oxide or another suitable material. The metal oxide can be, for example, aluminum oxide (e.g., Al₂O₃), titanium oxide (e.g., TiO₂), iron oxide (e.g., Fe₂O₃), zirconium oxide (e.g., ZrO₂), zinc oxide (e.g., ZnO), copper oxide (e.g., CuO), tantalum oxide (e.g., Ta₂O₅), another suitable type of metal oxide, or any combination thereof.

[0068] In some embodiments, the pad barrier layer 102 is made of the same material as the device barrier layer 118. In other embodiments, the pad barrier layer 102 is made of a different material than the device barrier layer 118. In some embodiments, the device barrier layer 118 is crystalline and / or has a density greater than approximately 2 g / cm³. 3 , 2.6 g / cm³ 3 , 5 g / cm 3 or another suitable value. In some embodiments, the density is the same as that of the pad barrier layer 102.

[0069] As seen in a cross-sectional view of 1400A from Fig. 14A and a top view 1400B of Fig. As illustrated in Figure 14B, the pad barrier layer 102 is structured to segment it. A bottom electrode barrier segment 102b lies over and at pad 104 at bottom electrode 112, and a top electrode barrier segment 102t lies over and at pad 104 at top electrode 116. Upon completion of the structuring, the pads 103 remain covered by the pad barrier layer 102 (e.g., completely covered). The structuring can be carried out, for example, by a photolithography / etching process or by another suitable process.

[0070] As seen in a cross-sectional view of 1500A from Fig. 15A and a top view 1500B of Fig. As illustrated in Figure 15B, the component and dielectric substrate layers 120, 110 and the upper semiconductor layer 108u are structured to form several slots 1502 at the central region 702, which is surrounded by the piezoelectric component 106. The slots 1502 lie above the insulating layer 108i and extend through the component and dielectric substrate layers 120, 110 and the upper semiconductor layer 108u to the insulating layer 108i. Furthermore, the slots 1502 are spaced around a circular region of the upper semiconductor layer 108u and extend laterally into it. The circular region is surrounded by the piezoelectric component (e.g., when viewed from above) and is subsequently referred to as a membrane 202.

[0071] In some embodiments, a process for forming the slots 1502 comprises: 1) forming a photoresist mask over the pad barrier layer 102 and the dielectric component layer 120; 2) performing dry etching into the component and dielectric substrate layers 120, 110, and the upper semiconductor layer 108u with the mask in place; and 3) performing plasma ashing to remove the photoresist mask. In alternative embodiments, another suitable process for forming the slots 1502 is performed. In some embodiments, the dry etching and / or plasma ashing expose the IC chip to be formed to hydrogen ions and / or other stray materials. In such embodiments, the pad barrier layer 102 and the component barrier layer 118 block the stray material (e.g., the hydrogen ions) from diffusing to and accumulating in the piezoelectric layer 114.As previously described, this can, for example, prevent failure of the piezoelectric component 106.

[0072] As seen through a cross-sectional view 1600 of Fig. As illustrated in Figure 16, a passivation layer 124 is deposited, covering the pad barrier layer 102, the dielectric component layer 120, and the membrane 202, and also lining the slots 1502. In some embodiments, the deposition exposes the IC chip to be formed to hydrogen ions and / or other stray materials. In such embodiments, the pad barrier layer 102 and the component barrier layer 118 block the stray material (e.g., the hydrogen ions) from diffusing to and accumulating in the piezoelectric layer 114.

[0073] As seen in a cross-sectional view of 1700A from Fig. 17A and a top view 1700B of Fig. As illustrated in Figure 17B, the passivation layer 124 and the pad barrier layer 102 are structured to form pad openings 126 at the ends of the pads 104 distal to the vias 122. Furthermore, the structuring removes the passivation layer 124 from the membrane 202 and the slots 1502. In alternative embodiments, the passivation layer 124 persists at the membrane 202 and the slots 1502 (e.g., to protect the IC chip according to the embodiments of Fig. 5A to form).

[0074] In some embodiments, a process for performing the structuring comprises: 1) forming a photoresist mask over the passivation layer 124; 2) performing dry etching into the passivation layer 124 and the pad barrier layer 102 with the mask in place; and 3) performing plasma ashing to remove the photoresist mask. In alternative embodiments, another suitable process is performed to form the pad openings 126.

[0075] In some embodiments, dry etching and / or plasma ashing expose the IC chip being formed to hydrogen ions and / or other stray materials. Because the pad openings 126 extend through the pad junction 102, hydrogen ions and / or other stray materials can extend through the pad junction 102. However, because the pad openings 126 are located at the ends of the pads 104 distal to the vias 122, the diffusion path from the pad openings 126 to the piezoelectric layer 114 can be long. Therefore, the probability of hydrogen ions and / or other stray materials diffusing to the piezoelectric layer 114 is low.

[0076] As seen in a cross-sectional view from 1800 Fig. As illustrated in Figure 18, a sacrificial layer 1802 is deposited, which covers the IC chip to be formed and the pad openings 126 (see e.g. Fig. 17A and Fig. 17B) and the slots 1502 (see e.g. Fig. 17A and Fig. 17B) fills. In some embodiments, the sacrificial layer is silicon oxide 1802 and / or another suitable dielectric(s).

[0077] As seen in a cross-sectional view from 1900 Fig. As illustrated in 19, the IC chip is made of Fig. The substrate 108 is vertically rotated and structured to form a sound opening 204 that lies above and exposes the membrane 202. The structuring can be carried out, for example, by a photolithography / etching process or by another suitable process.

[0078] As seen in a cross-sectional view 2000A from Fig. 20A and a top view 2000B of Fig. As illustrated in Figure 20B, the IC chip is turned vertically. Furthermore, the sacrificial layer 1802 is removed. This removal can be carried out, for example, by etching using an etchant with high selectivity for the sacrificial layer 1802 relative to the underlying structure (e.g., the passivation layer 124 and the membrane 202).

[0079] By removing the sacrificial layer 1802, the sound opening 204 divides the slots 1502 (see e.g. Fig. 17A and Fig. 17B) and therefore extends through the membrane 202. Furthermore, the membrane 202 is detached and can move within the sound aperture 204. In response to the application of a voltage across the piezoelectric layer 114, from the top electrode 116 to the bottom electrode 112, the piezoelectric element 106 can vibrate. The vibrations can travel to the membrane 202 and cause the membrane 202 to vibrate, generating sound waves in the sound aperture 204. Accordingly, the piezoelectric element 106 and the membrane 202 work together to form a piezoelectric loudspeaker.

[0080] While Fig. 6, Fig. 7A, Fig. 7B, Fig. 8, Fig. 9A, Fig. 9B, Fig. 10, Fig. 11, Fig. 12A, Fig. 12B, Fig. 13, Fig. 14A, Fig. 14B, Fig. 15A, Fig. 15B, Fig. 16, Fig. 17A, Fig. 17B, Fig. 18, Fig. 19, Fig. 20A and Fig. 20B, which is described in relation to a procedure, it will be welcomed that the structures shown in these figures are not limited to the procedure, but can stand separately from the procedure on their own. While Fig. 6, Fig. 7A, Fig. 7B, Fig. 8, Fig. 9A, Fig. 9B, Fig. 10, Fig. 11, Fig. 12A, Fig. 12B, Fig. 13, Fig. 14A, Fig. 14B, Fig. 15A, Fig. 15B, Fig. 16, Fig. 17A, Fig. 17B, Fig. 18, Fig. 19, Fig. 20A and Fig. While 20B is described as a series of actions, it is welcome that the order of the actions can be modified in other embodiments. Fig. 6, Fig. 7A, Fig. 7B, Fig. 8, Fig. 9A, Fig. 9B, Fig. 10, Fig. 11, Fig. 12A, Fig. 12B, Fig. 13, Fig. 14A, Fig. 14B, Fig. 15A, Fig. 15B, Fig. 16, Fig. 17A, Fig. 17B, Fig. 18, Fig. 19, Fig. 20A and Fig. While Article 20B illustrates and describes a specific set of actions, some of the actions illustrated and / or described may be omitted in other embodiments. Furthermore, actions not illustrated and / or described may be included in other embodiments.

[0081] In relation to Fig. 21 is a block diagram 2100 of some embodiments of the method of Fig. 6, Fig. 7A, Fig. 7B, Fig. 8, Fig. 9A, Fig. 9B, Fig. 10, Fig. 11, Fig. 12A, Fig. 12B, Fig. 13, Fig. 14A, Fig. 14B, Fig. 15A, Fig. 15B, Fig. 16, Fig. 17A, Fig. 17B, Fig. 18, Fig. 19, Fig. 20A and Fig. 20B provided.

[0082] In 2102, a component film is formed over a substrate, the component film comprising a bottom electrode layer, a piezoelectric layer above the bottom electrode layer, and a top electrode layer above the piezoelectric layer. See, for example, Fig. 6.

[0083] In 2104, the device film is structured to form a piezoelectric device that extends in a closed path around a central region. See, for example, Fig. 7A and Fig. 7B.

[0084] In 2106, a barrier layer is formed that covers the piezoelectric device, with the barrier layer being configured to block the diffusion of hydrogen ions and / or other stray materials. See, for example, Fig. 8, Fig. 9A and Fig. 9B.

[0085] In 2108, a dielectric component layer is deposited that covers the component barrier layer and the piezoelectric component, with the dielectric component layer blocking hydrogen ions and / or other stray materials from diffusing to the piezoelectric layer during deposition. See, for example, Fig. 10.

[0086] At 2110, a pair of pads is formed, wherein the pads have first ends that are located above a top electrode and a bottom electrode of the piezoelectric device, respectively, and are connected to them by vias, and wherein the pads have second ends that are distal to the first ends and laterally offset from the piezoelectric device. See, for example, Fig. 11, Fig. 12A and Fig. 12B.

[0087] At 2112, a pad barrier layer is formed that covers the pads, with the pad barrier layer being configured to block diffusion of hydrogen ions and / or other stray materials. See, for example, Fig. 13, Fig. 14A and Fig. 14B.

[0088] In 2114, the substrate is structured to form multiple slits in the central region, with the slits being spaced around a membrane of the substrate in the central region, and with the pad barrier layer blocking hydrogen ions and / or other stray materials from diffusing to the piezoelectric layer during slit formation. See, for example, Fig. 15A and Fig. 15B.

[0089] In 2116, a passivation layer is deposited that covers the pad barrier layer, with the pad barrier layer blocking hydrogen ions and / or other stray materials from diffusing to the piezoelectric layer during the passivation layer deposition. See, for example, Fig. 16.

[0090] In 2118, the pad barrier layer and the passivation layer are structured to form pad openings, each exposing the second ends of the pads. It is unlikely that hydrogen ions and / or other stray materials used during pad opening formation will diffuse through the pad openings to the piezoelectric layer because the second ends are distal to the vias. See, for example, Fig. 17A and Fig. 17B.

[0091] At 2120, a sound aperture is formed that extends through the substrate to the membrane on a side of the substrate opposite the piezoelectric element, whereby the formation of the sound aperture detaches the membrane to allow it to move. See, for example, Fig. 18, Fig. 19, Fig. 20A and Fig. 20B.

[0092] While the block diagram 2100 of Fig. 21. Where a sequence of actions or events is illustrated and described herein, it is appreciated that the illustrated sequence of such actions or events is not to be interpreted in a limiting sense. For example, some actions occur in different sequences and / or concurrently with other actions or events besides those illustrated and / or described herein. Furthermore, not all illustrated actions may be required to implement one or more aspects or embodiments of the description herein, and one or more of the actions depicted herein may be implemented in one or more separate actions and / or phases.

[0093] In relation to Fig. 22 shows a cross-sectional view of 2200 of some first alternative embodiments of the method of Fig. 6, Fig. 7A, Fig. 7B, Fig. 8, Fig. 9A, Fig. 9B, Fig. 10, Fig. 11, Fig. 12A, Fig. 12B, Fig. 13, Fig. 14A, Fig. 14B, Fig. 15A, Fig. 15B, Fig. 16, Fig. 17A, Fig. 17B, Fig. 18, Fig. 19, Fig. 20A and Fig. 20B provided, in which the passivation layer 124 persists on the membrane 202 after completion of the process.

[0094] As seen in the cross-sectional view 2200 of Fig. 22 illustrates the aspects relating to Fig. 6, Fig. 7A, Fig. 7B, Fig. 8, Fig. 9A, Fig. 9B, Fig. 10, Fig. 11, Fig. 12A, Fig. 12B, Fig. 13, Fig. 14A, Fig. 14B, Fig. 15A, Fig. 15B and Fig. The 16 described actions are carried out. Afterwards, this will be done in relation to Fig. 17A and Fig. The structuring described in 17B is carried out, except that the structuring does not remove the passivation layer 124 from the membrane 202 and the slots 1502. Instead, the structuring forms openings 2202, each extending through the passivation layer 124 at the slots 1502 to expose the insulator layer 108i. Then, the structuring is carried out with respect to Fig. 18, Fig. 19, Fig. 20A and Fig. The actions described in section 20B were carried out. The resulting IC chip can, for example, be used as described in section 20B. Fig. 5A is illustrated.

[0095] In relation to Fig. 23-25 ​​shows a series of cross-sectional views 2300-2500 of some second alternative embodiments of the method of Fig. 6, Fig. 7A, Fig. 7B, Fig. 8, Fig. 9A, Fig. 9B, Fig. 10, Fig. 11, Fig. 12A, Fig. 12B, Fig. 13, Fig. 14A, Fig. 14B, Fig. 15A, Fig. 15B, Fig. 16, Fig. 17A, Fig. 17B, Fig. 18, Fig. 19, Fig. 20A and Fig. 20B provided, in which the pad barrier layer 102 and the passivation layer 124 are on the membrane 202 after completion of the process.

[0096] As seen in the cross-sectional view 2300 of Fig. 23 illustrates the aspects relating to Fig. 6, Fig. 7A, Fig. 7B, Fig. 8, Fig. 9A, Fig. 9B, Fig. 10, Fig. 11, Fig. 12A and Fig. The actions described in section 12B are carried out. Furthermore, the actions relating to Fig. 15A and Fig. The actions described in section 15B are carried out thereafter. In particular, the actions relating to Fig. 13, Fig. 14A and Fig. The actions described in 14B were not carried out. Therefore, the pad barrier layer 102 is not formed prior to structuring to create the slots 1502.

[0097] As seen in the cross-sectional view 2400 of Fig. 24 illustrates the aspects relating to Fig. 13 and Fig. The 16 described actions are performed sequentially to deposit the pad barrier layer 102 and the passivation layer 124, respectively. Therefore, the pad barrier layer 102 and the passivation layer 124 are deposited after structuring to form the slots 1502.

[0098] As seen in the cross-sectional view 2500 of Fig. 25 illustrates this in relation to Fig. 17A and Fig. The structuring described in 17B is carried out, except that the structuring does not remove the pad barrier layer 102 and the passivation layer 124 from the membrane 202 and the slots 1502. Instead, the structuring forms openings 2502 that extend through the passivation layer 124 and the pad barrier layer 102, respectively, at the slots 1502, to expose the insulator layer 108i. Afterward, the following are carried out with respect to Fig. 18, Fig. 19, Fig. 20A and Fig. The actions described in section 20B were carried out. The resulting IC chip can, for example, be used as described in section 20B. Fig. 5B is illustrated.

[0099] In relation to Fig. 26 and Fig. 27 shows a series of cross-sectional views 2600 and 2700 of some third alternative embodiments of the method of Fig. 6, Fig. 7A, Fig. 7B, Fig. 8, Fig. 9A, Fig. 9B, Fig. 10, Fig. 11, Fig. 12A, Fig. 12B, Fig. 33, Fig. 14A, Fig. 14B, Fig. 15A, Fig. 15B, Fig. 16, Fig. 17A, Fig. 17B, Fig. 18, Fig. 19, Fig. 20A and Fig. 20B provided, in which a trapping layer 502 is on a base of the ground electrode 112.

[0100] As seen in the cross-sectional view 2600 of Fig. 26 illustrates the aspects relating to Fig. The actions described in section 6 are carried out, except that a trapping layer 502 is deposited between the deposition of the dielectric substrate layer 110 and the deposition of the device film 602. The trapping layer 502 is configured to absorb hydrogen ions and / or other stray materials, thereby preventing them from accumulating in the piezoelectric layer 114. Furthermore, the trapping layer 502 is conductive and may be, for example, titanium, barium, cerium, lanthanum, aluminum, magnesium, thorium, or another suitable conductive trapping material for hydrogen ions and / or other stray materials.

[0101] As seen in the cross-sectional view 2700 of Fig. 27 illustrates the aspects relating to Fig. 7A and Fig. The actions described in section 7B were carried out with a few exceptions. The ground electrode layer 112l (see e.g. Fig. 26), the piezoelectric layer 114 and the top electrode layer 116l (see e.g. Fig. 26) are structured with a common structure. Furthermore, the trapping layer 502 is structured with a structure that differs from the common structure. In some embodiments, the common structure is the same as that for the piezoelectric layer 114 in Fig. 7A and Fig. 7B illustrated and / or the different structure is the same as that for the bottom electrode layer 112l in Fig. 7A and Fig. 7B illustrated this. After that, the following will be discussed in relation to Fig. 8, Fig. 9A, Fig. 9B, Fig. 10, Fig. 11, Fig. 12A, Fig. 12B, Fig. 13, Fig. 14A, Fig. 14B, Fig. 15A, Fig. 15B, Fig. 16, Fig. 17A, Fig. 17B, Fig. 18, Fig. 19, Fig. 20A and Fig. The actions described in section 20B were carried out. The resulting IC chip can, for example, be used as described in section 20B. Fig. 5D illustration.

[0102] In some embodiments, the present disclosure provides an IC chip comprising: a substrate; a piezoelectric device located above the substrate; a pad located above the piezoelectric device; a via extending from the pad to the piezoelectric device; and a barrier layer located above the pad, wherein the barrier layer is configured to block hydrogen ions from diffusing through the barrier layer, from above the barrier layer, to the piezoelectric device. In some embodiments, the barrier layer comprises aluminum oxide, titanium oxide, iron oxide, zirconium oxide, zinc oxide, copper oxide, or tantalum oxide. In some embodiments, the barrier layer has a density of approximately 2 grams per cubic centimeter.In some embodiments, the IC chip further comprises a dielectric layer between the pad and the piezoelectric component, wherein the via extends through the dielectric layer and wherein the diffusion rate of hydrogen ions through the dielectric layer is greater than the diffusion rate of hydrogen ions through the barrier layer. In some embodiments, the IC chip further comprises a second barrier layer between the pad and the piezoelectric component, wherein the via extends through the second barrier layer and wherein the second barrier layer is configured to block hydrogen ions from diffusing through the second barrier layer, from above the second barrier layer, to the piezoelectric component.In some embodiments, the IC chip further comprises: a second pad having a first end located above the piezoelectric element; and a second via extending from the second pad to the piezoelectric element, the barrier layer being located above and flush with the second pad. In some embodiments, the IC chip further comprises a trap layer located on a bottom side of the piezoelectric element and configured to trap hydrogen ions.

[0103] In some embodiments, the present disclosure provides a further IC chip comprising: a substrate; a piezoelectric structure over the substrate, the piezoelectric structure comprising a bottom electrode, a piezoelectric layer over the bottom electrode, and a top electrode over the piezoelectric layer; a first hydrogen barrier layer over the piezoelectric structure; a pad having a first end and a second end, the first end being over the first hydrogen barrier layer and the piezoelectric structure and electrically coupled to the top or bottom electrode, and the second end being planar with the piezoelectric structure; and a second hydrogen barrier layer over the pad and the piezoelectric structure. In some embodiments, the second hydrogen barrier layer is a metal oxide.In some embodiments, the first hydrogen barrier layer extends along individual sidewalls of the bottom electrode, the top electrode, or the piezoelectric layer, respectively. In some embodiments, the first and second hydrogen barrier layers share a common density. In some embodiments, the substrate has a movable membrane at an opening extending through the substrate, with the piezoelectric structure extending in a closed path around the movable membrane. In some embodiments, the second hydrogen barrier layer is located on a sidewall of the movable membrane. In some embodiments, the IC chip further includes a passivation layer located above the second hydrogen barrier layer, with the passivation layer being located on a sidewall of the movable membrane and the second hydrogen barrier layer being spaced apart from the movable membrane.In some embodiments, the pad is continuously elongated from the first end of the pad to the second end of the pad, the second end being distal to the first end and laterally offset from the piezoelectric structure. In some embodiments, the IC chip further comprises a passivation layer located above the second hydrogen barrier layer, the passivation layer and the second hydrogen barrier layer forming a common sidewall at the second end of the pad, and the second end being distal to and laterally offset from the first end and the piezoelectric structure.

[0104] In some embodiments, the present disclosure provides a method comprising: forming a piezoelectric structure over a substrate and comprising a first electrode, a piezoelectric layer over the first electrode, and a second electrode over the piezoelectric layer; depositing a dielectric layer covering the piezoelectric structure; forming a pad and a via, wherein the pad is over the dielectric layer and the via extends through the dielectric layer from the pad to the piezoelectric structure; depositing a barrier layer covering the pad and the piezoelectric structure; and performing a semiconductor fabrication process after depositing the barrier layer, wherein the semiconductor fabrication process exposes the barrier layer to ions and the barrier layer blocks the ions from passing through the barrier layer.In some embodiments, the deposition of the barrier layer is performed without a hydrogen source, and the ions are hydrogen ions. In some embodiments, the piezoelectric structure extends laterally in a closed path around a central region, and the semiconductor fabrication process includes structuring the substrate to form multiple slots in the central region. In some embodiments, the semiconductor fabrication process includes: depositing a passivation layer covering the barrier layer; and structuring the passivation layer and the barrier layer to form a pad opening that exposes one end of the pad offset laterally from the piezoelectric structure.

Claims

[1] IC chip (Integrated-Circuit-Chip), comprising: a substrate; a piezoelectric component that lies above the substrate; a pad that lies over the piezoelectric component; a via extending from the pad to the piezoelectric component; a barrier layer that lies above the pad; wherein the barrier layer is configured to block hydrogen ions from diffusing through the barrier layer from above the barrier layer to the piezoelectric device; and a trapping layer on the underside of the piezoelectric component and designed to trap hydrogen ions. [2] IC chip according to claim 1, wherein the barrier layer contains aluminium oxide, titanium oxide, iron oxide, zirconium oxide, zinc oxide, copper oxide or tantalum oxide. [3] IC chip according to claim 1 or 2, wherein the barrier layer has a density of about 2 grams per cubic centimeter. [4] IC chip according to one of the preceding claims, further comprising: a dielectric layer between the pad and the piezoelectric device, wherein the via extends through the dielectric layer and wherein a diffusion rate of hydrogen ions through the dielectric layer is greater than a diffusion rate of hydrogen ions through the barrier layer. [5] IC chip according to one of the preceding claims, further comprising: a second barrier layer between the pad and the piezoelectric device, wherein the via extends through the second barrier layer and wherein the second barrier layer is configured to block hydrogen ions from diffusing through the second barrier layer from above the second barrier layer to the piezoelectric device. [6] IC chip according to one of the preceding claims, further comprising: a second pad having a first end located above the piezoelectric component; and a second via extending from the second pad to the piezoelectric component, with the barrier layer lying above the second pad and being flush with it. [7] IC chip (Integrated-Circuit-Chip), comprising: a substrate; a dielectric substrate layer above the substrate; a piezoelectric structure above the substrate and on the dielectric substrate layer, wherein the piezoelectric structure comprises a bottom electrode, a piezoelectric layer above the bottom electrode and a top electrode above the piezoelectric layer; a trapping layer between the dielectric substrate layer and the piezoelectric structure, wherein the trapping layer is configured to trap hydrogen ions; a first hydrogen barrier layer located above the piezoelectric structure; a pad having a first end and a second end, wherein the first end lies above the first hydrogen barrier layer and the piezoelectric structure and is electrically coupled to the top or bottom electrode, and wherein the second end is planar with the piezoelectric structure; and a second hydrogen barrier layer located above the pad and the piezoelectric structure. [8] IC chip according to claim 7, wherein the second hydrogen barrier layer is a metal oxide. [9] IC chip according to claim 7 or 8, wherein the first hydrogen barrier layer extends along individual side walls of the bottom electrode, the top electrode or the piezoelectric layer. [10] IC chip according to any one of the preceding claims 7 to 9, wherein the first and the second hydrogen barrier layer share a common density. [11] IC chip according to any one of the preceding claims 7 to 10, wherein the substrate has a movable membrane at an opening extending through the substrate, and wherein the piezoelectric structure extends in a closed path around the movable membrane. [12] IC chip according to claim 11, wherein the second hydrogen barrier layer is on a side wall of the movable membrane. [13] IC chip according to claim 11 or 12, further comprising: a passivation layer located above the second hydrogen barrier layer, wherein the passivation layer is on a side wall of the movable membrane and wherein the second hydrogen barrier layer is spaced away from the movable membrane. [14] IC chip according to any one of the preceding claims 7 to 13, wherein the pad is continuously elongated from the first end of the pad to the second end of the pad and wherein the second end is distal to the first end and is laterally offset from the piezoelectric structure. [15] IC chip according to any one of claims 7 to 14 above, further comprising: a passivation layer above the second hydrogen barrier layer, wherein the passivation layer and the second hydrogen barrier layer form a common side wall at the second end of the pad and wherein the second end is distal to the first end and the piezoelectric structure and laterally offset thereto. [16] Procedure, comprehensive: Forming a piezoelectric structure over a substrate and comprising a first electrode, a piezoelectric layer above the first electrode, and a second electrode above the piezoelectric layer; Deposition of a dielectric layer that covers the piezoelectric structure; Forming a pad and a via, wherein the pad lies above the dielectric layer and wherein the via extends through the dielectric layer from the pad to the piezoelectric structure; Deposition of a barrier layer covering the pad and the piezoelectric structure; and Performing a semiconductor manufacturing process after deposition of the junction, wherein the semiconductor manufacturing process exposes the junction to ions and wherein the junction blocks the ions from passing through the junction, wherein a dielectric substrate layer is deposited above the substrate and a trapping layer is deposited on the dielectric substrate layer, wherein the piezoelectric structure is formed on the trapping layer, wherein the trapping layer is configured to absorb hydrogen ions. [17] Method according to claim 16, wherein the deposition of the barrier layer is carried out without a hydrogen source and wherein the ions are hydrogen ions. [18] Method according to claim 16 or 17, wherein the piezoelectric structure extends laterally in a closed path around a central region and wherein the semiconductor manufacturing process comprises structuring the substrate to form multiple slots at the central region. [19] Method according to any one of claims 16 to 18 above, wherein the semiconductor manufacturing process comprises: Deposition of a passivation layer covering the barrier layer; and Structuring the passivation layer and the barrier layer to form a pad opening that exposes one end of the pad that is offset laterally from the piezoelectric structure.

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