Semiconductor device with contact pad structure and manufacturing method

Abstract

Semiconductor device (100), comprising: a contact pad structure (102) over a first surface (106) of a semiconductor body (108); and a dielectric structure (110) covering a sidewall (112) and a boundary region (114) on a top surface (116) of the contact pad structure (102), wherein the dielectric structure (110) includes a first liner dielectric (1102) covering the sidewall (112) and the boundary region (114) and a dielectric spacer (1101) on the first liner dielectric (1102) at the sidewall (112) of the contact pad structure (102), and the dielectric spacer (1101) is confined to the sidewall (112) of the contact pad structure (102) and has a different material composition than the first liner dielectric (1102).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device, particularly to a semiconductor device having a contact pad structure and a manufacturing method thereof. BACKGROUND

[0002] In semiconductor devices, a wiring region above an active chip region typically contains one or more wiring levels containing metal lines to enable electrical interconnection of transistors or other components within the chip or to enable electrical contact with components outside the chip, e.g., via a contact pad structure. For example, reference is made to the disclosures in US 2013 / 0 087 908 A1 and US 2017 / 0 005 034 A1. The metal lines in the wiring levels of a wiring region must typically fulfill many, sometimes conflicting, requirements to meet chip reliability specifications.These requirements may include, for example, suitability to prevent moisture ingress and subsequent corrosion that may lead to device failure, very good conductivity, chemical stability, electromigration resistance, low diffusivity in the substrate material, among others.

[0003] Thus, there is a need to provide a semiconductor device with improved reliability. SUMMARY

[0004] The invention is defined in the independent claims. Further developments are subject to the dependent claims. One example of the present disclosure relates to a semiconductor device. The semiconductor device includes a contact pad structure over a first surface of a semiconductor body. Furthermore, the semiconductor device includes a dielectric structure lining a sidewall and a boundary region on an upper surface of the contact pad structure. The dielectric structure includes a dielectric spacer on the sidewall of the contact pad structure.

[0005] Another example of the present disclosure relates to a method of manufacturing a semiconductor device. The method includes forming a contact pad structure over a first surface of a semiconductor body. Further, the method includes forming a dielectric structure covering a sidewall and a boundary region on a top surface of the contact pad structure. The dielectric structure includes a dielectric spacer on the sidewall of the contact pad structure.

[0006] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate examples of semiconductor devices and, together with the description, serve to explain principles of the examples. Further examples are described in the following detailed description and claims. Fig. 1 and Fig. 2 are partial cross-sectional views to illustrate examples of semiconductor devices including a contact pad structure and a dielectric spacer on a sidewall of the contact pad structure. Fig. 3 is an experimental image to illustrate an exemplary shape of a sidewall region of the contact pad structure of a semiconductor device. Fig. 4 is a partial cross-sectional view to illustrate another example of a semiconductor device including dielectric spacers on sidewalls of a gate runner line and a source or emitter runner line. Fig. 5A to 5D and Fig. 6A to 6C are schematic cross-sectional views to illustrate process features for manufacturing a semiconductor device. DETAILED DESCRIPTION

[0008] In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific examples of semiconductor devices. It is to be understood that other examples may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. For example, features illustrated or described for one example may be used in connection with other examples to arrive at yet another example. It is intended that the present disclosure cover such modifications and variations. The examples are described using specific language that should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only.Corresponding elements are designated by the same reference numerals in the various drawings unless otherwise stated.

[0009] The terms "have," "contain," "comprise," "have," and the like are open-ended terms. These terms indicate the presence of the identified structures, elements, or characteristics, but do not preclude the presence of additional elements or characteristics. The indefinite and definite articles are intended to include both the plural and the singular, unless the context clearly indicates otherwise.

[0010] The term "electrically connected" describes a permanent, low-resistance connection between electrically connected elements, for example, a direct contact between the elements in question or a low-resistance connection via a metal and / or a highly doped semiconductor material. The term "electrically coupled" encompasses that one or more intermediate elements suitable for signal and / or power transmission may be connected between the electrically coupled elements, for example, elements that are controllable to temporarily provide a low-resistance connection in a first state and a high-resistance electrical decoupling in a second state. An ohmic contact is a non-rectifying electrical junction.

[0011] Ranges specified for physical dimensions include the boundary values. For example, a range for a parameter y from a to b is read as a ≤ y ≤ b. The same applies to ranges with a boundary value such as "at most" and "at least."

[0012] The terms "on" and "over" should not be construed to mean only "directly on" and "directly above." Rather, if an element is positioned "on" or "over" another element (e.g., a layer is "on" or "over" another layer, or "on" or "over" a substrate), another component (e.g., another layer) may be positioned between the two elements (e.g., another layer may be positioned between a layer and a substrate if the layer is "on" or "over" the substrate).

[0013] An example of a semiconductor device may include a contact pad structure over a first surface of a semiconductor body. The semiconductor device may further include a dielectric structure covering a sidewall and a boundary region on a top surface of the contact pad structure. The dielectric structure may include a dielectric spacer on the sidewall of the contact pad structure.

[0014] The semiconductor device may, for example, be an integrated circuit or a discrete semiconductor device or a semiconductor module. The semiconductor device may be or may include a power semiconductor device, e.g., a vertical power semiconductor device with a load current flow between the first surface and the second surface. The semiconductor device may be used in automotive, industrial power control, power management, sensor solutions, and Internet of Things security applications. The semiconductor device may be a power semiconductor diode or a power semiconductor IGBT (insulated gate bipolar transistor) or a reverse conducting (RC) IGBT or a power semiconductor transistor such as a power semiconductor IGFET (insulated gate field effect transistor, e.g.,a metal-oxide-semiconductor field-effect transistor) or a JFET (junction field-effect transistor) or a HEMT (high electron mobility transistor). The power semiconductor device can be configured to conduct currents of more than 1 A or more than 10 A or even more than 30 A. To realize a desired maximum load current, the semiconductor device can be designed using a plurality of cells connected in parallel. The parallel-connected cells can, for example, be transistor or diode cells formed in the shape of a strip or a strip segment. Of course, the device cells can also have any other shape, e.g., circular, elliptical, polygonal, or octahedral. Furthermore, the semiconductor device can be configured to conduct voltages between load terminals, e.g.,between the emitter and collector of an IGBT or between the cathode and anode of a diode or between the drain and source of a MOSFET, in a range of a few tens or a few hundred or up to a few thousand volts, e.g., 30 V, 40 V, 60 V, 80 V, 100 V, 400 V, 650 V, 1.2 kV, 1.7 kV, 3.3 kV, 4.5 kV, 5.5 kV, 6 kV, 6.5 kV, 10 kV. The blocking voltage may, for example, correspond to a voltage class specified in a datasheet of the power semiconductor device. The semiconductor device may also be or may include a lateral semiconductor device, e.g., a lateral power semiconductor device, with a load current flow along a lateral direction, e.g., parallel to the first surface.

[0015] The semiconductor device can, for example, be realized monolithically using a mixed technology. Such mixed technologies can, for example, be used to form analog circuit blocks in a chip using the bipolar devices included in this technology to provide interfaces to digital systems, to form digital circuit blocks using the complementary metal-oxide-semiconductor (CMOS) devices included in this technology to provide signal processing, and to form low-, medium-, or high-voltage or power blocks using field-effect transistors included in this technology. Such mixed technologies are known, for example, as bipolar CMOS-DMOS, BCD technologies, or smart power technologies (SPT) and are used in a variety of application areas, e.g.in the fields of lighting, engine control, automotive electronics, power management for mobile devices, audio amplifiers, power supplies, hard drives, and printers. The semiconductor device can, for example, be part of a BCD or smart power chip in one of the above application areas.

[0016] The semiconductor body can be based on various semiconductor materials, for example, silicon (Si), silicon-on-insulator (SOI), silicon sapphire (SOS), silicon germanium, germanium, gallium arsenide, silicon carbide, gallium nitride, or other compound semiconductor materials. The semiconductor body can be a semiconductor substrate, for example, a semiconductor wafer, and can contain one or more epitaxial layers deposited thereon or can be back-thinned.

[0017] For example, the first surface may be a front surface or a top surface of the semiconductor body, and the second surface may be a rear surface or a back surface of the semiconductor body. For example, the semiconductor body may be attached to a lead frame via the second surface. Interconnects may be arranged on the contact pad structure above the first surface of the semiconductor body to electrically connect circuit elements in the semiconductor body to elements, e.g., other semiconductor devices, outside the semiconductor device.

[0018] The contact pad structure may be part of a wiring region above the semiconductor body. The wiring region may comprise one or more than one, e.g., two, three, four, or even more, wiring levels. Each wiring level may be formed by a single or a stack of conductive layers, e.g., metal layer(s). The wiring levels may, for example, be lithographically patterned. An interlayer dielectric structure may be arranged between stacked wiring levels. A contact plug(s) or contact line(s) may be formed in openings in the interlayer dielectric structure to electrically connect parts, e.g., metal lines or contact regions, of different wiring levels. The contact pad structure may be formed by one or more elements of the wiring region.For example, the contact pad structure may include parts of an outermost wiring level of the wiring region, e.g., the wiring level with the greatest vertical distance to the first surface of the semiconductor body. The contact pad structure may, for example, directly border the first surface of the semiconductor body. The edge or boundary region of the contact pad structure may be a peripheral part of the upper surface of the contact pad structure. The boundary region of the contact pad structure may partially or completely surround a central part of the contact pad structure. The central part of the contact pad structure may be a central part on the upper surface of the contact pad structure, where, for example, an interconnection directly borders the contact pad structure.

[0019] The dielectric spacer on the sidewall of the contact pad structure may, for example, differ in material composition from other parts of the dielectric structure. For example, parts of the dielectric structure may be formed using separate layer deposition processes. The dielectric spacer may also be fused to other dielectric parts of the same material composition, e.g., if a backside etch of a dielectric layer to form the dielectric spacer only partially removes the dielectric layer in regions close to the dielectric spacer. The dielectric structure may include a plurality of dielectric parts, e.g., stacked layers or spacers, that differ from one another in terms of material composition, dimensions (e.g., thickness), and function (e.g., electrical insulation, diffusion barrier, adhesion properties).The dielectric structure may include a variety of dielectric materials, including, but not limited to, oxides (e.g., silicate glass, deposited SiO2, thermal SiO2), nitrides (e.g., Si3N4), high-k dielectrics, low-k dielectrics, or any combination thereof. For example, the dielectric spacer may be formed as a silicate glass dielectric spacer.

[0020] By providing the dielectric spacer on the sidewall of the contact pad structure, the creation of weak points in the dielectric structure can be counteracted. For example, the generation of growth gaps or seamlines emanating from the lower edges of the contact pad structure can be avoided or reduced. This can enable an improvement in the reliability of the semiconductor device.

[0021] Furthermore, the semiconductor device may, for example, have an interconnect on the upper surface of the contact pad structure. The interconnect may, for example, directly adjoin the upper surface of the contact pad structure. The interconnect may, for example, be based on, among other things, clip bonding, nailhead or ball bonding, wedge bonding, soldering, sintering, tape bonding, or a combination thereof.

[0022] For example, a portion of the sidewall of the contact pad structure may have a convex shape. The convex shape may be due, for example, to the process technology. The convex shape on the sidewall of the contact pad structure may be present with respect to a portion of the contact pad structure having a similar material composition. The convex shape on the sidewall of the contact pad structure may result in a positive inclination of the sidewall with respect to a perpendicular to the first surface in a first portion of the contact pad structure and a negative inclination of the sidewall with respect to the perpendicular to the first surface in a second portion of the contact pad structure (e.g., between the first portion and the first surface). Since a variety of processes can be used to form the contact pad structure, other sidewall shapes, e.g., conical or vertical sidewalls, may also be present.

[0023] The contact pad structure may be, for example, a pad structure of a source contact or a pad structure of an emitter contact or a pad structure of a gate contact.

[0024] The dielectric spacer may, for example, be arranged between a first liner dielectric of the dielectric structure and a second liner dielectric of the dielectric structure. The dielectric spacer may be sandwiched between the first liner dielectric of the dielectric structure and the second liner dielectric of the dielectric structure. In other words, in a cross-sectional view, the first liner dielectric and the second liner dielectric may encapsulate or completely surround the dielectric spacer. The first liner dielectric may directly border the sidewall of the contact pad structure. For example, the first liner dielectric may also directly border the dielectric spacer on the opposite side, e.g., opposite the location where the first liner dielectric directly borders the sidewall of the contact pad structure.The second liner dielectric may directly border the dielectric spacer, e.g., opposite to where the first liner dielectric directly borders the dielectric spacer. The second liner dielectric may also directly border the first liner dielectric, e.g., in a region that laterally delimits the dielectric of the spacer. For a Cu-containing contact pad structure, the dielectric structure may include the first liner dielectric and the second liner dielectric in addition to the dielectric spacer. In other examples, the first liner dielectric is optional and may also be omitted, e.g., when the contact pad structure is formed by Al-based materials.

[0025] For example, the first liner dielectric may include a dielectric layer or a dielectric layer stack, e.g., a nitride liner or cover (e.g., SiN) or an oxide cover (e.g., Al2O3 or deposited or thermal SiO2), or a combination thereof. The first liner dielectric may, for example, comprise a stack of an Al2O3 layer and a SiN layer. The second liner dielectric may, for example, include a dielectric layer or a dielectric layer stack, e.g., a nitride cover (e.g., SiN) or an oxide cover (e.g., silicate glass or deposited SiO2), or a combination thereof. The second liner dielectric may, for example, comprise a SiN cover and silicate glass. The silicate glass may, for example, be arranged between the first liner dielectric and the SiN cover of the second liner dielectric.

[0026] Furthermore, the semiconductor device may include a polyimide resin on the second liner dielectric. The polyimide resin may serve as a chip passivation, for example, directly adjacent to the second liner dielectric. A portion of the polyimide resin may also, for example, be adjacent to the first liner dielectric or a portion thereof.

[0027] Furthermore, the semiconductor device may include at least one of a gate runner line or a gate finger line electrically connecting gate electrodes of transistor cells to a pad structure of a gate contact. The gate runner line may, for example, partially or completely surround a transistor cell array. The gate runner line may be arranged between an edge of the semiconductor body, e.g., a die, and the contact pad structure. The dielectric structure may extend between the contact pad structure and the gate runner line and may cover a sidewall and a top surface of the gate runner line. For example, the dielectric structure may include a second dielectric spacer on the sidewall of the gate runner line. The dielectric spacer on the sidewall of the contact pad structure and the second dielectric spacer may, for example, be formed simultaneously.In other words, a single spacer process can be used to form the dielectric spacer and the second dielectric spacer. In addition to the dielectric spacer and the second dielectric spacer, additional dielectric spacers can be formed simultaneously. The additional dielectric spacer can, for example, include spacers on opposite sidewalls of the contact pad structure and the gate runner line, respectively.

[0028] The semiconductor device may, for example, further comprise a source or emitter runner line that electrically connects source or emitter regions of transistor cells to the contact pad structure. The source or emitter runner line may be arranged between an edge of the semiconductor body and the contact pad structure, or partially between the edge of the semiconductor body and a gate runner line. The dielectric structure may extend between the contact pad structure and the source or emitter runner line and may cover a sidewall and a top surface of the source or emitter runner line. The source or emitter runner line may, for example, partially or completely surround a transistor cell array. The dielectric structure may, in addition to the first and an optional second dielectric spacer, comprise a third dielectric spacer on the sidewall of the source or emitter runner line.For example, the dielectric spacer, the second dielectric spacer, and the third dielectric spacer may be formed simultaneously.

[0029] The contact pad structure may, for example, contain at least one of the elements Cu, Au, AlCu, Ag, or alloys thereof. The at least one of the elements Cu, Au, AlCu, Ag, or their alloys contained in the contact pad structure may, for example, be selected and adjusted with regard to electrical conductivity. The contact pad structure may contain further structural elements, e.g., sublayers, that serve a different purpose. For example, the contact pad structure may contain at least one diffusion barrier layer(s) or adhesion layer(s). The diffusion barrier layer(s) may, for example, have a smaller thickness than the layer or layer stack containing the at least one of the elements Cu, Au, AlCu, Ag, or alloys thereof.Likewise, the adhesion barrier layer(s) may have a smaller thickness than the layer or layer stack containing at least one of the elements Cu, Au, AlCu, Ag, or alloys thereof. The diffusion barrier layer(s) may be disposed between the first surface and the layer or layer stack containing at least one of the elements Cu, Au, AlCu, Ag, or alloys thereof. Likewise, the adhesion barrier layer(s) may be disposed between the first surface and the layer or layer stack containing at least one of the elements Cu, Au, AlCu, Ag, or alloys thereof. The contact pad structure may include pad finishing for surface protection or special joining techniques such as soldering or sintering. For example, typical materials include NiP, NiMoP, Pd, Ag, Au as a single layer or layer stacks such as NiP / Pd / Au.

[0030] A vertical distance between the first surface and an upper surface of the contact pad structure may, for example, be in a range of 2 µm to 50 µm.

[0031] For example, a width of the spacer dielectric at a bottom side of the spacer dielectric may be greater than a thickness of the first liner dielectric at the top surface of the contact pad structure.

[0032] For example, a width of the spacer dielectric at a bottom side of the spacer dielectric may be less than a thickness of the second liner dielectric on the top surface of the contact pad structure. In some other examples, the width of the spacer dielectric at a bottom side of the spacer dielectric may also be greater than a thickness of the second liner dielectric on the top surface of the contact pad structure.

[0033] Functional and structural details described above with respect to the examples of a semiconductor device, e.g., material(s), dimension(s), purpose, are intended to apply equally to the examples of manufacturing the semiconductor device, which are further described below.

[0034] An example of a method for manufacturing a semiconductor device may include forming a contact pad structure over a first surface of a semiconductor body. The method may further include forming a dielectric structure covering a sidewall and a boundary region on a top surface of the contact pad structure. The dielectric structure may include a spacer dielectric on the sidewall of the contact pad structure.

[0035] Forming the dielectric structure may, for example, comprise forming a first liner dielectric of the dielectric structure on the sidewall and on the top surface of the contact pad structure. Furthermore, the method may comprise forming the dielectric spacer by means of a spacer etching process. The method may further comprise forming a second liner dielectric on the dielectric spacer and on the first liner dielectric. The spacer etching process may be performed by means of an anisotropic etching process, e.g., by means of an anisotropic dry etching process such as a reactive ion etching process.

[0036] Forming the dielectric spacer by means of a spacer etching process may, for example, comprise forming a dielectric processing layer over the first surface of the semiconductor body. The dielectric layer may be partially etched back such that a first portion of the dielectric processing layer remains as the spacer dielectric and a second portion of the dielectric processing layer remains over the first main surface of the semiconductor body. Thus, the first portion and the dielectric spacer may have the same material composition and be fused.

[0037] The examples and features described above and below can be combined.

[0038] Functional and structural details (e.g., materials, dimensions) described with respect to the examples above are intended to apply equally to the examples illustrated in the figures and described below.

[0039] Fig. 1 schematically and exemplarily shows a semiconductor device 100. The semiconductor device 100 includes a contact pad structure 102 above a first surface 106 of a semiconductor body 108. The semiconductor device 100 further includes a dielectric structure 110 covering a sidewall 112 and an edge or boundary region 114 on an upper surface 116 of the contact pad structure 102. The dielectric structure 110 includes a dielectric spacer 1101 on the sidewall 112 of the contact pad structure 102. The dielectric spacer 1101 is arranged between a first liner dielectric 1102 of the dielectric structure 110 and a second liner dielectric 1103 of the dielectric structure 110. The first liner dielectric 1102 directly adjoins the sidewall 112 of the contact pad structure 102, and the second liner dielectric 1103 directly adjoins the dielectric spacer 1101. In the cross-sectional view of Fig. 1, the first liner dielectric 1102 and the second liner dielectric 1103 enclose or completely surround the dielectric spacer 1101. The dielectric structure 110 further includes a dielectric portion 1108 directly adjacent to the first surface 106 of the semiconductor body 108. For example, the dielectric portion 1108 may include a gate dielectric (e.g., a gate oxide layer), a field dielectric (e.g., a field dielectric oxide), an intermediate dielectric (e.g., an intermediate oxide layer), or any combination thereof. The semiconductor device 100 further includes a polyimide resin 118 on the second liner dielectric 1103.

[0040] The semiconductor device may further include an interconnect 150 on the top surface 116 of the contact pad structure 102. Depending on the type of semiconductor device (e.g., integrated circuit, discrete semiconductor device, IGBT, FET, diode, thyristor) and depending on the type of contact pad structure (e.g., pad structure of a source contact, pad structure of an emitter contact, pad structure of an anode contact, gate runner line, source runner line, anode runner line), a device-specific arrangement of doped semiconductor regions (e.g., an n-doped source region and a p-doped body region for an n-channel FET, an n-doped emitter region and a p-doped body region for an n-channel IGBT, a p-doped anode region for a diode) and optional non-semiconductor regions (e.g., trench electrode structures) in the semiconductor body 108 (through an active device area 140 of the semiconductor body 108 in Fig. 1 illustrated in a simplified manner).

[0041] A vertical distance vd between the first surface 106 and a top surface 116 of the contact pad structure 102 may be in a range of 2 µm to 50 µm. A width w of the dielectric spacer 1101 at a bottom side of the dielectric spacer 1101 may be greater than a thickness t1 of the first liner dielectric 1102 on the top surface 116 of the contact pad structure 102. The width w of the dielectric spacer 1101 at a bottom side of the dielectric spacer 1101 may be less than a thickness t2 of the second liner dielectric 1103 on the top surface 116 of the contact pad structure 102. The width w of the dielectric spacer 1101 at a bottom side of the dielectric spacer 1101 may also be greater than or equal to a thickness t2 of the second liner dielectric 1103 on the top surface 116 of the contact pad structure 102.

[0042] In the schematic cross-sectional view of Fig. 2 illustrates another example of a semiconductor device 100. The Fig. 2 is based on the semiconductor device 100 shown in Fig. 1, but differs in that the first dielectric liner or cap 1102 and the dielectric spacer 1101 are formed from a common dielectric processing layer 1100, i.e., have a similar material composition. For example, during a spacer etching process applied to the dielectric processing layer 1100, a back etch of the dielectric processing layer 1100 to form the spacer dielectric 1101 may not completely remove the dielectric processing layer 1100 in regions 1107 adjacent to the dielectric spacer 1101, but may only partially remove it.

[0043] The cross-sectional view of Fig. 3 illustrates an image based on an experimental analysis of a semiconductor device sample prepared using the focused ion beam (FIB) technique. A portion 1121 of the sidewall 112 of the contact pad structure 102 is illustrated. The sidewall 112 of the contact pad structure 102 of the illustrated sample has a convex shape. Other examples may have a different sidewall shape, e.g., concave or non-conical or conical, but share the dielectric spacer 1101 on (e.g., directly adjacent to or near) the sidewall 112 of the contact pad structure 102 to reduce or suppress the generation of seam lines.

[0044] In the schematic cross-sectional view of Fig. 4 illustrates another example of a semiconductor device 100. The Fig. 4 is based on the semiconductor device 100 of Fig. 1 and further includes a gate runner line 120 that electrically connects gate electrodes of transistor cells to a pad structure of a gate contact. The gate runner line 120 is arranged between an edge of the semiconductor body 108 and the contact pad structure 102. The dielectric structure 110 extends between the contact pad structure 102 and the gate runner line 120 and covers a sidewall 124 and a top surface 126 of the gate runner line 120. The dielectric structure 110 further includes a second dielectric spacer 1104 on the sidewall 124 of the gate runner line 120. Furthermore, the semiconductor device 100 comprises a source or emitter runner line 128 that electrically connects source or emitter regions of transistor cells to the contact pad structure 102. The source or emitter runner line 128 is arranged between an edge of the semiconductor body 108 and the contact pad structure 102.The dielectric structure 110 extends between the contact pad structure 102 and the source or emitter runner line 128 and covers a sidewall 130 and a top surface 132 of the source or emitter runner line 128. The dielectric structure 110 includes a third dielectric spacer 1105 on the sidewall 130 of the source or emitter runner line 120.

[0045] The aspects and features mentioned and described together with one or more of the previously described examples and figures may also be combined with one or more of the other examples to replace a similar feature of the other example or to additionally introduce the feature into the other example.

[0046] The schematic cross-sectional views of the Fig. 5A to 5D illustrate exemplary features of a method for manufacturing a semiconductor device 100.

[0047] Referring to the schematic cross-sectional view of Fig. 5A, a dielectric portion 1108 of a dielectric structure 110 is formed and directly adjoins a first surface 106 of the semiconductor body 108. A contact pad structure 102 is formed over the first surface 106 of the semiconductor body 108. A first liner dielectric 1102 of the dielectric structure 110 is formed on the sidewall 112 and on the top surface 116 of the contact pad structure 102.

[0048] Referring to the schematic cross-sectional view of Fig. 5B, a spacer etching process is performed by forming a dielectric processing layer 1100 on the first liner dielectric 1102. Referring to the schematic cross-sectional view of Fig. 5C, the dielectric processing layer 1100 is etched back such that a dielectric spacer 1101 remains on the sidewall 112 of the contact pad structure 102. Referring to the schematic cross-sectional view of Fig. 5D, a second liner dielectric 1103 is formed on the dielectric spacer 1101 and on the first liner dielectric 1102.

[0049] The schematic cross-sectional views of the Fig. 6A to 6C illustrate further exemplary features of a method for manufacturing a semiconductor device 100.

[0050] Referring to the schematic cross-sectional view of Fig. 6A, a dielectric portion 1108 of a dielectric structure 110 is formed and directly adjoins a first surface 106 of the semiconductor body 108. A contact pad structure 102 is formed over the first surface 106 of the semiconductor body 108. A spacer etch process is performed by forming a dielectric processing layer 1100 on the dielectric portion 1108 and on the contact pad structure 102. Referring to the schematic cross-sectional view of Fig. 6B, the dielectric processing layer 1100 is partially etched back such that the dielectric spacer 1101 and a portion of the dielectric processing layer 1100 remain in regions 1107 adjacent to the dielectric spacer 1101 above the first surface 106 of the semiconductor body 108. Referring to the schematic cross-sectional view of Fig. 6C, a second liner dielectric 1103 is formed on the dielectric spacer 1101 and on the first liner dielectric 1102. Referring to the schematic cross-sectional view of Fig. 6C, a second liner dielectric 1103 is formed on the remainder of the dielectric processing layer 1100.

[0051] Another example is based on the Fig. 6A to 6C, but includes prior to forming the dielectric processing layer as shown in Fig. 6A, further illustrates the process for forming the first dielectric cover 1102 as shown in Fig. 5B is illustrated.

Claims

[1] A semiconductor device (100), comprising: a contact pad structure (102) over a first surface (106) of a semiconductor body (108); and a dielectric structure (110) covering a sidewall (112) and a boundary region (114) on a top surface (116) of the contact pad structure (102), wherein the dielectric structure (110) includes a first liner dielectric (1102) covering the sidewall (112) and the boundary region (114) and a dielectric spacer (1101) on the first liner dielectric (1102) at the sidewall (112) of the contact pad structure (102), and the dielectric spacer (1101) is confined to the sidewall (112) of the contact pad structure (102) and has a different material composition than the first liner dielectric (1102). [2] The semiconductor device (100) of the preceding claim, further comprising an interconnect on the upper surface (116) of the contact pad structure (102). [3] The semiconductor device (100) according to any one of the preceding claims, wherein a part (1121) of the sidewall (112) of the contact pad structure (102) has a convex shape. [4] The semiconductor device (100) according to any one of the preceding claims, wherein the contact pad structure (102) is a pad structure of a source contact, a pad structure of an emitter contact, or a pad structure of a gate contact. [5] Semiconductor device (100) according to one of the preceding claims, wherein the dielectric spacer (1101) is arranged between the first liner dielectric (1102) of the dielectric structure (110) and a second liner dielectric (1103) of the dielectric structure (110). [6] Semiconductor device (100) according to the preceding claim, wherein the first liner dielectric (1102) directly adjoins the sidewall (112) of the contact pad structure (102) and the second liner dielectric (1103) directly adjoins the dielectric spacer (1101). [7] The semiconductor device (100) according to any one of claims 5 to 6, wherein the first liner dielectric (1102) comprises a SiN coating and the second liner dielectric (1103) comprises a SiN coating and a silicate glass, the silicate glass being disposed between the first liner dielectric (1102) and the SiN coating of the second liner dielectric (1103). [8] The semiconductor device (100) according to any one of claims 5 to 7, further comprising a polyimide resin (118) on the second liner dielectric (1103). [9] Semiconductor device (100) according to one of the preceding claims, further comprising at least one of a gate runner line (120) or a gate finger line electrically connecting gate electrodes of transistor cells to a pad structure of a gate contact, wherein the gate runner line (120) is arranged between an edge of the semiconductor body (108) and the contact pad structure (102) and the dielectric structure (110) extends between the contact pad structure (102) and the gate runner line (120) and covers a sidewall (124) and a top surface (126) of the gate runner line (120). [10] The semiconductor device (100) of the preceding claim, wherein the dielectric structure (110) includes a second dielectric spacer (1104) on the sidewall (124) of the gate runner line (120). [11] Semiconductor device (100) according to one of the preceding claims, further comprising a source or emitter runner line (128) electrically connecting source or emitter regions of transistor cells to the contact pad structure (102), wherein the source or emitter runner line (128) is arranged between an edge of the semiconductor body (108) and the contact pad structure (102) and the dielectric structure (110) extends between the contact pad structure (102) and the source or emitter runner line (128) and covers a sidewall (130) and a top surface (132) of the source or emitter runner line (128). [12] Semiconductor device (100) according to the preceding claim, wherein the dielectric structure (110) includes a third dielectric spacer (1105) on the sidewall (130) of the source or emitter runner line (128). [13] Semiconductor device (100) according to one of the preceding claims, wherein the contact pad structure (102) contains at least one of the elements Cu, Au, AlCu, Ag or alloys thereof. [14] The semiconductor device (100) according to any one of the preceding claims, wherein a vertical distance (vd) between the first surface (106) and a top surface (116) of the contact pad structure (102) is in a range of 2 µm to 50 µm. [15] The semiconductor device (100) of any preceding claim, wherein a width (w) of the dielectric spacer (1101) at a bottom side of the dielectric spacer (1101) is greater than a thickness (t1) of the first liner dielectric (1102) on the top surface (116) of the contact pad structure (102). [16] The semiconductor device (100) according to any one of claims 5 to 15, wherein a width (w) of the dielectric spacer (1101) at a bottom side of the dielectric spacer (1101) is smaller than a thickness (t2) of the second liner dielectric (1103) on the top surface (116) of the contact pad structure (102). [17] A method of manufacturing a semiconductor device (100), comprising: forming a contact pad structure (102) over a first surface (106) of a semiconductor body (108); and forming a dielectric structure (110) covering a sidewall (112) and a boundary region (114) on a top surface (116) of the contact pad structure (102), wherein the dielectric structure (110) includes a first liner dielectric (1102) covering the sidewall (1102) and the boundary region (114), and a dielectric spacer (1101) on the first liner dielectric (1102) on the sidewall (112) of the contact pad structure (102), and the dielectric spacer (1101) is confined to the sidewall (112) of the contact pad structure (102) and has a different material composition than the first liner dielectric (1102), and wherein forming the dielectric structure includes forming a first liner dielectric (1102) of the dielectric structure (110) on the side wall (112) and on the upper surface (116) of the contact pad structure (102),forming the dielectric spacer (1101) by means of a spacer etching process and forming a second liner dielectric (1103) on the dielectric spacer (1101) and on the first liner dielectric (1102).

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