DYNAMIC PREFEELING OF DATA FROM A STORAGE

Abstract

A non-transitory machine-readable storage medium (400) comprising instructions that, when executed, cause a system to: dynamically adjust (402) a prefetching load with respect to a prefetch cache based on a measure (120) of past uses of the prefetch cache and based on a measure of contention for accesses to prefetched data in the prefetch cache, wherein the prefetching load is to prefetch data from a memory (106) into the prefetch cache, and wherein the measure of contention for accesses to the prefetched data in the prefetch cache is based on a set of events in which one or more entities are unable to obtain locks to access the prefetch cache.

Description

background

[0001] A system can contain different types of memory. The first type of memory is persistent memory, which is used to store a relatively large amount of data. Persistent memory can be implemented using storage devices such as disk-based storage devices, solid-state drives, etc. Another type of memory that can be included in the system is smaller, but faster memory, which can be used to temporarily store a portion of the data stored in persistent memory. The faster, smaller memory can be implemented using storage devices such as dynamic random-access memory (DRAM), static random-access memory (SRAM), flash memory, etc.

[0002] US 2013 / 0013867 A1 relates to a data prefetcher comprising a controller for controlling the operation of the data prefetcher. The controller receives data related to cache misses and data related to events not related to a prefetch function of the data prefetcher. The data prefetcher further comprises a counter for maintaining a count associated with the data prefetcher. The count is adjusted in a first direction in response to the detection of a cache miss and in a second direction in response to the detection of an event not related to the prefetch function. The controller disables the prefetch function when the counter reaches a threshold.

[0003] US 2011 / 0 113 199 A1 refers to an optimization of a prefetch in a processor. Short description

[0004] A non-transitory machine-readable storage medium according to claims 1 to 11, a system according to claims 12 to 16 and a method according to claims 17 to 20 are disclosed. Brief description of the drawings

[0005] Some embodiments of the present disclosure are described with reference to the following figures. Fig. is a block diagram of an arrangement including a memory system with a dynamic prefetching engine according to some examples. Fig. is a flowchart of a process of a dynamic prefetching engine according to some examples. Fig. is a block diagram of an arrangement in which a dynamic prefetching engine can control a set of prefetch threads, according to some examples. Fig. is a block diagram of a storage medium that stores machine-readable instructions according to some examples. Fig. is a block diagram of a system according to some examples. Fig. is a flowchart of a method according to some examples.

[0006] In the drawings, identical reference numbers indicate similar, but not necessarily identical, elements. The illustrations are not necessarily to scale, and the size of some parts may be exaggerated to better illustrate the example shown. Furthermore, the drawings contain examples and / or embodiments consistent with the description; however, the description is not limited to the examples and / or embodiments shown in the drawings. Detailed description

[0007] In this disclosure, the use of the term "a" or "a" or "the" includes the plural forms unless the context clearly indicates otherwise. Likewise, the term "comprises," "including," or "have," when used in this disclosure, specifies the presence of the specified elements but does not preclude the presence or addition of other elements.

[0008] Data may be prefetched from memory (implemented with one or more storage devices, which may include a mix of different types of storage devices) into a cache to improve access speeds for later-arriving requests, which may be satisfied by retrieving the data from the cache. In some examples, the memory may be implemented with slower storage devices (e.g., disk-based storage devices, solid-state drives, etc.), while the cache may be implemented with faster storage devices (e.g., DRAM devices, SRAM devices, flash memory devices, etc.).

[0009] More generally, a "cache" can refer to any type of storage that can be used to store a copy of data present in another storage. In other examples, a "cache" can store data that isn't present in another storage. A "prefetch cache" can refer to a cache used to store prefetched data retrieved from another storage. It should be noted that a cache can be used for a variety of purposes, including storing prefetched data as well as other forms of cached data.

[0010] Prefetching data from memory can refer to retrieving data from memory that is not currently the subject of a requester's access request. An access request can refer to a read or write request. A "requester" can refer to any entity capable of requesting read or write access to data. The requester can be, for example, a program or a machine. Another example is a user as a requester.

[0011] The data is prefetched based on a judgment that, given a current pattern of data accesses from memory, the prefetched data is likely to be the subject of subsequent requests in the relatively near future. Prefetching data from memory into the cache allows a requester's later access request to be satisfied using the prefetched data in the cache. To satisfy an access request, data in the cache is accessed. If the requested data is not present in the cache when an access request for that data is received, the requested data is fetched from memory into the cache and then retrieved from the cache.If the requested data is among the data already in the cache when the access request is received, the requested data can be accessed more quickly than if the same data were first retrieved from memory in response to the access request and then retrieved from the cache. The cache also generally has a faster access speed than memory.

[0012] In some examples, access to data may be sequential. For example, a series of access requests from a requester (or multiple requesters) may be requests for successive portions of data in memory. Consecutive chunks of data in memory may refer to chunks with consecutive physical or logical addresses, block numbers, page numbers, or other identifiers that represent an order in which the chunks of data are received or stored by the system. In response to an initial access request, a prefetching process may prefetch additional chunks of data (that are part of the consecutive chunks of data) into the cache, expecting that subsequently received requests have a high probability of involving the prefetched data.

[0013] However, prefetching data requires the use of resources, including memory resources (for storing the prefetched data), processing resources (for implementing the logic to decide which data to prefetch), and communication resources (for transferring the prefetched data from memory to the cache). If the prefetched data is not used before it is evicted from the cache (e.g., to free up space for other I / O operations), the resource consumption associated with fetching the data into the cache would be wasted. The likelihood of prefetched data being evicted from the cache is higher when the system's I / O load is relatively high and the cache is full or nearly full.

[0014] Furthermore, resource contention can occur between the prefetching process and another process that can share the cache. For example, the prefetching process can prefetch data into parts of the cache that another process can also access. In some examples, a cache can be organized into data pages, with each "page" of data having a specific size (the specific size can be fixed or adjustable).

[0015] Resource contention can occur in the form of lock contention. For example, to access a specific page of the cache, the requesting entity (e.g., the prefetching process) must acquire a lock, which may prevent another entity (e.g., a requestor) from accessing the specific page because the other entity would be unable to acquire the lock for the specific page.

[0016] When resource contention related to cache accesses occurs at a high frequency, this can lead to reduced system performance because prefetching processes can prevent other requesters from completing their input / output (I / O) operations quickly, or I / O operations from other requesters can delay the completion of prefetching operations.

[0017] Resource contention can reduce the benefit associated with prefetching data into the cache, especially when the memory is implemented using storage devices with relatively fast access speeds. In such examples, when the system's I / O load is relatively high and the likelihood of resource contention when accessing the cache is relatively high, overall system performance can be improved by avoiding data prefetching. The disadvantage associated with retrieving data from memory (rather than from the cache) is reduced when the memory is implemented using faster storage devices.

[0018] It can be difficult to determine when to turn prefetching on or off because the system's I / O load can change rapidly over time.

[0019] In accordance with some implementations of the present disclosure, a prefetching load is dynamically adjusted based on one or more metrics, including a measure of past usage of a prefetch cache and / or a measure of access contention during accesses to the prefetch cache. A "prefetching load" generally refers to a set of prefetch operations occurring or scheduled in a system.

[0020] Fig. is a block diagram of an example arrangement including a storage system 102 with a front end 104 and a memory 106, which can be considered part of a back end of the storage system 102. The "front end" of the storage system 102 refers to a collection of components of the storage system 102 that interact with requestors 108 over a network and perform operations to manage access to data in the memory 106 in response to requests from the requestors 108.

[0021] The "backend" of storage system 102 refers to the storage infrastructure that stores data. Storage 106 includes a collection of storage devices 118 (one or more storage devices).

[0022] In the examples according to Fig. The frontend 104 includes a memory controller 110 that manages access to memory 106 in response to requests from requesters. The memory controller 110 can receive a request from a requester 108, e.g., a write or read request. In response to the request, the memory controller 110 can send commands to the memory 106 via a communication link 116 to perform the writing or reading of data.

[0023] The frontend 104 also includes a dynamic prefetching engine 112 according to some implementations of the present disclosure. The dynamic prefetching engine 112 is capable of dynamically adjusting the prefetching load of the storage system 102 based on certain criteria (discussed further below).

[0024] As used herein, an "engine" may refer to hardware processing circuitry, which may include any one or a combination of a microprocessor, a core of a multi-core microprocessor, a microcontroller, a programmable integrated circuit, a programmable gate array, or other hardware processing circuitry. Alternatively, an "engine" may refer to a combination of hardware processing circuitry and machine-readable instructions (software and / or firmware) executable on the hardware processing circuitry.

[0025] The frontend 104 also includes a cache 114, which can be used to store data, such as a copy of the data stored in memory 106 or other data. In some examples, the dynamic prefetching engine 112 can prefetch data from memory 106 into the cache 114. Thus, the cache 114 can store both prefetched data and other data. The cache 114 can be implemented using a collection of storage devices (one storage device or multiple storage devices).

[0026] In some examples, there may be multiple I / O operations initiated by requesters 108 and / or other devices that may include storing corresponding data in cache 114. The multiple I / O operations may include reads of sequential data streams from memory 106, random reads of data from memory 106, writes of data to memory 106, and so on. A "sequential data stream" may refer to a series of data chunks stored in consecutive physical locations in memory 106. A "random read" of data may refer to a read that may access data from any location in memory 106, as indicated by a memory address.

[0027] The numerous I / O operations may compete with the dynamic prefetching engine 112 in accessing the cache 114 (a shared resource), which may result in resource contention in the cache 114, particularly when the I / O load in the storage system 102 is relatively high.

[0028] As previously mentioned, resource contention may occur due to lock contention when entities attempt to acquire locks to write to pages in cache 114. While one entity (e.g., dynamic prefetching engine 112) holds a lock on a page in cache 114 to perform a prefetch operation, another entity cannot access the same page, which may delay an I / O operation by the other entity.

[0029] As another example, after data has been prefetched into cache 114 by dynamic prefetching engine 112, a subsequent I / O operation may cause some or all of the prefetched data to be removed from cache 114, for example, when cache 114 is full. As a result, the prefetched data in cache 114 may be deleted before the prefetched data is even read, resulting in wasted resource utilization associated with prefetching data.

[0030] To address the aforementioned problems, the dynamic prefetching engine 112 may dynamically adjust the prefetching load based on one or more metrics, including a metric 120 of past usage of a prefetch cache and / or a metric 122 of resource contention during accesses to the cache 114.

[0031] Measures 120 and 122 may be stored in a memory 124 of storage system 102. Storage 124 may be implemented by a collection of storage devices (one or more storage devices). In other examples, measures 120 and 122 may be stored in cache 114 or another storage location.

[0032] In some examples, the storage system 102 includes a monitoring engine 126 capable of monitoring accesses to the cache 114 to derive the measures 120 and 122.

[0033] The prefetch cache historical usage metric 120 refers to how effective the prefetch cache has been used in the past, e.g., over a particular time interval (e.g., last hour, last 24 hours, last week, etc.). In some examples, the prefetch cache historical usage metric 120 may be a prefetch cache utilization (P). Note that the "prefetch cache" may refer to any cache or a portion of a cache used by the dynamic prefetching engine 112 to store prefetch data. In some examples, P may be expressed as a percentage, such as the percentage of reads of data stored in the prefetch cache that resulted in a prefetch cache hit. A "prefetch cache hit" occurs when a read from the prefetch cache was successful.P The "prefetch cache hit" can be expressed as the percentage of all accesses to the prefetch cache (in a given time interval) that resulted in a cache hit. The monitoring engine 126 can derive the prefetch cache utilization (P) based on monitoring the accesses to the prefetch cache in the given time interval and determine which of these accesses resulted in a cache hit.

[0034] In other examples, the measure 120 of past prefetch cache usage may be expressed by other parameters, such as the number of cache hits per unit time, etc.

[0035] The measure 122 for resource contention during accesses to the cache 114 provides an indication of the extent of contention resulting from accesses to the cache 114 by different units. For example, the measure 122 may be based on a number of events in which one or more units are unable to access the cache 114 (e.g., a unit cannot obtain a lock to access a page of the cache 114 because the lock is held by another unit, such as the dynamic prefetching engine 112). The measure 122 is also referred to as the resource contention measure (C). For example, the measure 122 may be based on a number of read conflicts when accessing pages of prefetched data in the cache 114, e.g., due to an inability to obtain a lock.As another example, the measure 122 may be based on a ratio between a number of accesses to prefetched data in the cache 114 that resulted in a conflict and the total number of accesses to the prefetched data in the cache 114.

[0036] The monitoring engine 126 may derive the measure 122 (or C) based on observing accesses to the prefetched data in the cache 114 that resulted in, for example, a lock contention.

[0037] Fig. is a flowchart of a process performed by the dynamic prefetching engine 112 according to some examples. Although in Fig. the tasks are presented in a particular order, it is pointed out that in other examples the tasks may be performed in a different order and that some of the tasks may be omitted and others added.

[0038] The dynamic prefetching engine 112 receives (at 202) the prefetch cache utilization measure (P) and receives (at 204) the resource contention measure (C), which is a measure of resource contention during accesses to prefetched data in the cache. The dynamic prefetching engine 112 can receive P and C by retrieving the measures, for example, from memory 124.

[0039] The dynamic prefetching engine 112 then decides whether to adjust the prefetching load based on the prefetch cache utilization measure (P) and the resource contention measure (C). Adjusting the prefetching load may involve either increasing the prefetching load or decreasing the prefetching load.

[0040] To decide whether to increase or decrease the prefetching load, the dynamic prefetching engine 112 compares the values ​​of P and C with the scale-up thresholds (TP-up and TC-up) and the scale-down thresholds (TP-down and TC-down). The values ​​of P and C are compared with the scale-up thresholds (TP-up and TC-up) to determine whether the prefetching load should be increased, and the values ​​of P and C are compared with the scale-down thresholds (TP-down and TC-down) to determine whether the prefetching load should be decreased. In some examples, the values ​​of TP-down and TP-up may be different, and the values ​​of TC-down and TC-up may be different. In other examples, the values ​​of TP-down and TP-up may be equal and / or the values ​​of TC-down and TC-up may be equal.

[0041] Specifically, the dynamic prefetching engine 112 (at 206) determines whether P < TP-down or C > TC-down. A value of P less than TP-down indicates that prefetch cache usage is sufficiently low, so the prefetching load should be reduced. A value of C greater than TC-down indicates that resource contention associated with accessing prefetched data is sufficiently high, so the prefetching load should be reduced.

[0042] In response to determining that P < TP-down or C > TC-down, the dynamic prefetching engine 112 (at 208) decreases the prefetching load. In another example, the prefetching load is decreased in response to determining both P < TP-down and C > TC-down.

[0043] Assuming that none of the conditions checked at 206 are true, the dynamic prefetching engine 112 determines (at 210) whether P > TP-up and C < TC-up. P being greater than TP-up indicates that prefetch cache utilization is high, and C being less than TC-up means that resource contention related to accesses to prefetched data is low. If both conditions checked at 210 are true, the dynamic prefetching engine 112 (at 212) increases the prefetching load.

[0044] If the P > TP-up and C < TC-up condition is not met, the dynamic prefetching engine 112 does not change the prefetching load and returns to task 202.

[0045] As in Fig. As shown, in some examples, a prefetching load may be shared by a number of prefetch threads 304-1, 304-2, ..., 304-N (N ≥ 1) that are actively prefetching data from memory 106 into cache 114, also referred to as the "prefetch cache" because cache 114 stores prefetched data (as well as other data types).

[0046] The dynamic prefetching engine 112 may start a prefetch thread for each I / O operation that the dynamic prefetching engine 112 has determined would benefit from prefetching data. An example of such an I / O operation is an I / O operation that retrieves chunks of data from memory 106 one at a time. Different I / O operations may be initiated by different requestors 108 or other entities. An I / O operation may result in data being retrieved from memory 106 in an I / O traffic stream.

[0047] A "prefetch thread" may refer to a corresponding prefetch operation initiated by the dynamic prefetching engine 112 for a corresponding I / O operation initiated by an entity, such as a requestor 108. The dynamic prefetching engine 112 may perform separate prefetch operations (in the form of prefetch threads) in response to different I / O operations.

[0048] Fig. shows N prefetch threads 304-1, 304-2, ..., 304-N that are actively fetching data into the prefetch cache. In some examples, there may be a maximum number of prefetch threads that can be active at a given time; in other words, the dynamic prefetching module 112 may not start more than the maximum number of prefetch threads.

[0049] To dynamically adjust the prefetching load, the dynamic prefetching engine 112 may increase or decrease the number (N) of prefetch threads. Adjusting the number (N) of prefetch threads may be based on the prefetch cache utilization measure (P) and the resource contention measure (C), as described above.

[0050] A dynamic decrease in the number of prefetch threads (N) can be calculated using the following equation: N=N(100−PK+1)⋅D(Step), where K is a constant (e.g., 10 or another constant) and D (Step) represents the number of threads that are decremented at each iteration. For example, D (Step) can be 1, 2, 3, and so on. Equation 1 is used when P < TP-down or C > TC-down, as in 206 in Fig. Equation 1 gradually decreases the number of prefetch threads.

[0051] A dynamic increase in the number of prefetch threads (N) can be calculated using the following equation: N=N+I(Step), where I(Step) represents the number of threads to increment in each iteration. For example, I(Step) can be 1, 2, 3, and so on.

[0052] Equation 2 is used when P > TP-up and C < TC-up, as in 210 in Fig. Equation 2 gradually increases the number of prefetch threads.

[0053] Fig. is a block diagram of a non-transitory machine-readable or computer-readable storage medium 400 having machine-readable instructions stored thereon that, when executed, cause a system to perform various tasks.

[0054] The machine-readable instructions include instructions 402 for dynamically adjusting the prefetching load to determine a prefetching load with respect to a prefetch cache based on a measure (e.g., P) of past uses of the prefetch cache, the prefetching load being to prefetch data from memory into the prefetch cache.

[0055] In some examples, the prefetching load is dynamically adjusted by selecting a number of prefetching threads (e.g., 304-1 to 304-N in Fig. ) that are designed to prefetch data from memory into the prefetch cache.

[0056] In some examples, the machine-readable instructions are to dynamically adjust the prefetching load based on a measure (e.g., C) of contention for accesses to prefetched data in the prefetched cache.

[0057] In some examples, the level of contention for accessing the prefetched data in the prefetch cache is based on a number of events where one or more devices cannot access the prefetch cache.

[0058] In some examples, the level of contention for accessing the prefetched data in the prefetch cache is based on the number of read conflicts when accessing the prefetch cache.

[0059] In some examples, the level of contention for accessing the prefetch data in the prefetch cache is based on a number of events where one or more entities cannot obtain locks to access the prefetch cache.

[0060] In some examples, the measurement of past prefetch cache usage is based on a percentage of the prefetch data stored in the prefetch cache that has been accessed.

[0061] In some examples, the measure of past prefetch cache usage is based on a percentage of reads of data stored in the prefetch cache that resulted in a cache hit.

[0062] In some examples, the machine-readable instructions are to dynamically adjust the prefetching load by gradually decreasing the prefetching load when the amount of past prefetch cache usage meets a threshold (e.g., P < TP-down).

[0063] In some examples, the machine-readable instructions are to dynamically adjust the prefetching load by gradually increasing the prefetching load when the amount of past prefetch cache usage meets a threshold (e.g., P > TP-up).

[0064] In some examples, the machine-readable instructions are to dynamically adjust the prefetching load by gradually reducing the prefetching load in response to the measure of past uses of the prefetch cache satisfying the first threshold (e.g., P < TP-down), and gradually increasing the prefetching load in response to the measure of past uses of the prefetch cache satisfying a second threshold that is different from the first threshold (e.g., P > TP-up).

[0065] In some examples, the machine-readable instructions are to further dynamically adjust the prefetching load based on a measure of contention for accesses to prefetched data in the prefetch cache, wherein the dynamic adjustment of the prefetching load includes gradually decreasing the prefetching load in response to the measure of past uses of the prefetch cache meeting a first scale-down threshold or the measure of contention for accesses to the prefetched data in the prefetch cache meeting a second scale-down threshold (e.g., P < TP-down or C > TC-down), and gradually increasing the prefetching load in response to the measure of past uses of the prefetch cache reaching a first scale-up threshold and the measure of contention for accesses to the prefetched data in the prefetch cache meeting a second scale-up threshold (e.g., P > TP-up and C < TC-up).

[0066] Fig. is a block diagram of a system 500 (e.g., the memory system 102 of Fig. or another computer system).

[0067] The system 500 includes a cache 502 for storing data prefetched from memory. The system 500 includes a prefetch controller 504 (e.g., the dynamic prefetch engine 112) for dynamically adjusting a prefetching load on the cache 502 based on a measurement (506) of resource contention during accesses to the cache, where the prefetching load consists of prefetching data from memory into the cache 502.

[0068] In some examples, the prefetch controller 504 dynamically adjusts the prefetching load based on a measure of past usage of prefetched data in the cache.

[0069] Fig.is a flowchart of a process 600 according to some examples. Process 600 may be performed in a system with a hardware processor. A hardware processor may include a microprocessor, a core of a multi-core microprocessor, a microcontroller, a programmable integrated circuit, a programmable gate array, or other hardware processing circuitry.

[0070] Process 600 includes receiving (at 602) a measure of past usage of a cache that stores data previously fetched from memory. The measure of past usage may be fetched from memory, for example.

[0071] Process 600 includes receiving (at 604) a measure of resource contention during accesses to the prefetched data in the cache. The measure of resource contention may be retrieved, for example, from memory.

[0072] The process 600 includes dynamically adjusting (at 606) a prefetching load with respect to the prefetch cache based on the level of past usage and the level of resource contention, where the prefetching load is to prefetch data from memory into the cache.

[0073] In the foregoing description, numerous details are set forth to provide an understanding of the subject matter disclosed herein. However, implementations may be practiced without some of these details. Other implementations may include modifications and variations from the details described above. The appended claims are intended to cover such modifications and variations.

Claims

[1] A non-transitory machine-readable storage medium (400) comprising instructions that, when executed, cause a system to: dynamically adjust (402) a prefetching load with respect to a prefetch cache based on a measure (120) of past uses of the prefetch cache and based on a measure of contention for accesses to prefetched data in the prefetch cache, wherein the prefetching load is to prefetch data from a memory (106) into the prefetch cache, and wherein the measure of contention for accesses to the prefetched data in the prefetch cache is based on a set of events in which one or more entities are unable to obtain locks to access the prefetch cache. [2] The non-transitory machine-readable storage medium of claim 1, wherein the instructions are to dynamically adjust the prefetching load by dynamically adjusting a set of prefetching threads (304-1 to 304-N) that are to prefetch the data from the memory (106) into the prefetch cache. [3] The non-transitory machine-readable storage medium of claim 1, wherein the events in which the one or more entities are unable to obtain the locks to access the prefetch cache include events of read conflicts in accessing the prefetch cache. [4] The non-transitory machine-readable storage medium of claim 1, wherein a lock contention occurs when a first entity is unable to acquire a lock on a portion of the prefetch cache because a second entity holds a lock on the portion of the prefetch cache. [5] The non-transitory machine-readable storage medium of claim 1, wherein the measure (120) of past uses of the prefetch cache is based on a percentage of the prefetch data stored in the prefetch cache that has been accessed. [6] The non-transitory machine-readable storage medium of claim 1, wherein the measure (120) of past uses of the prefetch cache is based on a percentage of reads of data stored in the prefetch cache that resulted in a cache hit. [7] The non-transitory machine-readable storage medium of claim 1, wherein the instructions are to dynamically adjust the prefetching load in response to a comparison of the measure (120) of past uses of the prefetch cache with a threshold. [8] The non-transitory machine-readable storage medium of claim 7, wherein the instructions are to dynamically adjust the prefetching load by gradually decreasing the prefetching load in response to the measure (120) of past uses of the prefetch cache reaching a threshold. [9] The non-transitory machine-readable storage medium of claim 7, wherein the instructions are to dynamically adjust the prefetching load by incrementally increasing the prefetching load in response to the measure (120) of past uses of the prefetch cache reaching a threshold. [10] The non-transitory machine-readable storage medium of claim 7, wherein the threshold is a first threshold, and wherein the instructions are to dynamically adjust the prefetching load by: the prefetching load is gradually reduced in response to the measure (120) of past uses of the prefetch cache reaching the first threshold; and the prefetching load is gradually increased in response to the measure (120) of past uses of the prefetch cache reaching a second threshold that is different from the first threshold. [11] The non-transitory machine-readable storage medium of claim 1, wherein the instructions are to dynamically adjust the prefetching load by: the prefetching load is gradually reduced in response to the measure (120) of past uses of the prefetch cache reaching a first scale-down threshold or the measure of conflicts in accesses to the prefetched data in the prefetch cache reaching a second scale-down threshold; and the prefetching load is gradually increased in response to the measure (120) of past uses of the prefetch cache reaching a first scale-up threshold and the measure of contention in accesses to the prefetched data in the prefetch cache reaching a second scale-up threshold. [12] A system (500) comprising: a cache (114; 502) for storing data previously retrieved from a memory (106); and a prefetch controller (504) to: dynamically adjusting a prefetching load with respect to the cache (114; 502) based on a measure (122) of resource contention during accesses to the cache (114; 502), wherein the prefetching load serves to prefetch data from the memory (106) into the cache (114; 502), and wherein the measure (122) of resource contention during accesses to the cache (114; 502) is based on a set of events in which one or more entities are unable to obtain locks for accessing the cache (114; 502). [13] The system (500) of claim 12, wherein the prefetch controller (504) is to: dynamically adjust the prefetching load based on a measure (120) of past usage of prefetched data in the cache (114; 502). [14] The system (500) of claim 13, wherein the prefetch controller (504) is to: dynamically adjust the prefetching load based on a comparison of the measure (122) of resource contention with a first threshold and a comparison of the measure (120) of past uses of the prefetched data in the cache (114; 502) with a second threshold. [15] The system (500) of claim 14, wherein the first threshold is a first scale-down threshold and the second threshold is a second scale-down threshold, and wherein the prefetch controller (504) is to dynamically adjust the prefetching load by gradually reducing the prefetching load. [16] The system (500) of claim 14, wherein the first threshold is a first scale-up threshold and the second threshold is a second scale-up threshold, and wherein the prefetch controller (504) is to dynamically adjust the prefetching load by gradually increasing the prefetching load. [17] A method (600) performed in a system comprising a hardware processor, comprising: Receiving (602) a measure (120) of past uses of a cache (114; 502) that stores data prefetched from a memory (106) by a prefetcher; Receiving (604) a measure (122) of resource contention upon access to the prefetched data in the cache (114; 502), wherein the measure (122) of resource contention is based on a set of events in which one or more entities are unable to access the cache (114; 502) due to an access by the prefetcher; and dynamically adjusting (606) a prefetching load with respect to the cache (114; 502) based on the measure (120) of past usage and the measure (122) of resource contention, the prefetching load being for prefetching data from the memory (106) into the cache (114; 502). [18] The method (600) of claim 17, wherein dynamically adjusting the prefetching load comprises adjusting a set of prefetch threads (304-1 to 304-N) to prefetch data from the memory (106) into the cache (114; 502). [19] The method (600) of claim 17, wherein the set of events where the one or more entities cannot access the cache (114; 502) comprises a set of events where the one or more entities are unable to obtain locks to access the cache (114; 502). [20] The method (600) of claim 19, wherein the one or more entities are unable to obtain locks to access the cache (114; 502) because the prefetcher holds a lock on the cache (114; 502).

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