Area segmentation for analog cam storage with improved accuracy

Abstract

A circuit (600), comprising: a first aCAM sub-circuit (601) which is electrically connected to a matching line; and a second aCAM sub-circuit (602) which is electrically connected to the matching line; where the circuit is executed upon receiving a digital input signal (x): converts the digital input signal (x) into a first analog voltage signal (V(x)) and a second analog voltage signal (V(x-PL1)), wherein the first analog voltage signal (V(x)) is received by the first aCAM sub-circuit and the second analog voltage signal (V(x-PL1)) is received by the second aCAM sub-circuit, wherein: the first analog voltage signal (V(x)) is an analog voltage signal that represents the digital input signal (x), and the second analog voltage signal (V(x-PL1)) is an analog voltage signal representing a version of the digital input signal (x) reduced according to a number of programmable levels of the first aCAM sub-circuit; and only provides a match along the match line if the first analog voltage signal (V(x)) is within a programmed voltage range of the first aCAM sub-circuit and the second analog voltage signal (V(x-PL1)) is within a programmed voltage range of the second aCAM sub-circuit.

Description

background

[0001] A content-addressable memory ("CAM") is a type of computer memory in which stored data is searched for by its content rather than its location. When a "word" is entered into a CAM, the CAM searches for that word in its contents. If the CAM finds the word (i.e., "matches"), it returns the address of the location where the found word is located.

[0002] Analog CAMs ("aCAMs") are special types of CAMs that can store and search ranges of values ​​(unlike more traditional digital-based CAMs, which can only store / search zeros and ones) using the programmable conductance of memristors. For example, in a given aCAM cell, the conductance of a first memristor can be programmed to specify the lower limit of a range, and the conductance of a second memristor can be programmed to specify an upper limit of the range. The aCAM cell can perform a search to determine if an input signal (e.g., an analog input voltage signal) falls within the programmed range defined by the conductance of the first and second memristors. If the input falls within the programmed range, the aCAM cell returns a match.If the input is outside the programmed range, the aCAM cell returns a mismatch.

[0003] Individual aCAM cells can be arranged in aCAM arrays consisting of rows and columns of aCAM cells. Words can be stored along the rows of the aCAM array (the rows of an aCAM array can be referred to as "match lines"), with each aCAM cell of a particular row storing one entry of the stored word. When the aCAM array receives an input word (e.g., a series of analog voltage signals, each representing one entry of the input word), the aCAM array can search for the input word along the columns of the aCAM array (e.g., a first entry of the input word can be searched for in a first column of the CAM array, a second entry of the input word can be searched for in a second column of the CAM array, etc.). The aCAM array "finds" the input word in a given row if all aCAM cells of the given row provide a match for their respective entries of the input word.

[0004] LI, C.; GRAVES, CE; SHENG, X. et al.: “Analog content-addressable memories with memristors” Nature Communications, No. 11, 1638 (2020), 02.04.2020, pages 1 - 8, describes a content-addressable memory that compares an input search word with all stored rows of words in an array in a highly parallel manner. Short description of the drawings

[0005] The present disclosure will now be described in detail in accordance with one or more various examples with reference to the following figures. The figures are for illustrative purposes only and show examples only. Fig. 1 shows an example of an aCAM cell according to examples of the technique disclosed herein. Fig. 2 shows an example of a voltage domain diagram according to examples of the presently disclosed technique. Fig.3 shows another example of a voltage domain diagram according to examples of the presently disclosed technique. Fig. 4 shows an example of a conceptual diagram in accordance with examples of the presently disclosed technique. Fig. 5 shows a circuit example according to examples of the presently disclosed technique. Fig. 6 shows a circuit example according to examples of the presently disclosed technique. Fig. 7 shows a circuit example according to examples of the presently disclosed technique. Fig. 8 shows a circuit example according to examples of the presently disclosed technique. Fig. 9 shows an example of a subtraction subcircuit according to examples of the presently disclosed technique. Fig.10 shows an example of a computer system that may be used to perform signal adjustments, according to examples of the present technique. Fig. 11 shows a block diagram of an example computer system in which various of the examples described herein may be implemented.

[0006] The figures are not exhaustive and do not limit the present disclosure to the precise form disclosed. Detailed description

[0007] By performing native search and matching operations between an input word and internally stored words / patterns, an aCAM array can be used to perform calculations for various applications. The more complex matching operations the aCAM array can perform, the more complex calculations it can perform at a high level.

[0008] The complexity of the search and match operations that an aCAM array can perform (and hence the complexity of the calculations that can be performed on it) is limited by the number of unique values ​​that the cells that comprise it can store or search for. The number of unique values ​​that an aCAM cell can store or search for can be referred to as the number of programmable levels for the aCAM cell or the accuracy level for the aCAM cell. A high-precision aCAM (i.e., an aCAM with a higher number of programmable levels) can perform more complex calculations than a low-precision aCAM (i.e., an aCAM with a lower number of programmable levels).

[0009] A major limitation of aCAMs is that their accuracy is limited by intrinsic structural constraints of their analog memory elements (i.e., the programmable conductance memristors). In particular, memristors used in aCAMs can only be programmed to a finite / discrete number of conductance states due to intrinsic structural limitations / imperfections (i.e., an M-bit memristor has 2 Mdiscrete / finite programmable conductance states). For example, two-bit memristors, which are commonly used in aCAMs, have four programmable conductance states (and two programmable bits). As described above, the programmed conductances of two memristors can be used to specify a lower and upper limit of a stored range for an aCAM cell (here, the stored range can represent one entry of a stored word). Due to their limited programmability, memristors can only be used to specify range limits in a finite / discrete manner. This means that a typical aCAM cell has a discrete / finite number of programmable levels. For example, a typical aCAM cell with two 2-bit memristors has only 2 M =2 = 4 programmable levels.

[0010] As mentioned earlier, due to their limited accuracy, conventional aCAMs are limited in their ability to perform calculations requiring a higher degree of complexity, thus limiting their practical applicability. In other words, conventional aCAMs have generally been incapable of performing complex calculations that require searching for an input using a large number of programmable levels (e.g., 16 levels, 32 levels, 64 levels, etc.).

[0011] Against this backdrop, examples of the presently disclosed technique provide novel circuits that increase the accuracy of aCAMs by leveraging the concept of range segmentation to representatively store an analog voltage range across multiple aCAM cells / subcircuits (here, the representatively stored analog voltage range may correspond to a word entry). In this way, for a circuit of the presently disclosed technique, accuracy can be increased linearly with each aCAM cell / subcircuit added to the circuit (e.g., the number of programmable levels that can be used to store a word entry and / or the number of programmable levels by which an input signal can be searched).Circuits of the presently disclosed technique can accordingly be used to perform more complex calculations than conventional aCAMs - and can thus be used in a wider range of computing applications.

[0012] Through "range segmentation," examples can representatively store an analog voltage range across multiple aCAM cells / subcircuits—where each aCAM cell / subcircuit representatively stores a segment of the representatively stored analog voltage range. As described in more detail below, such range segmentation may require strategic programming of the lower and upper boundary thresholds for each aCAM cell / subcircuit to ensure that the combination of aCAM cells / subcircuits is capable of representatively storing an analog voltage range that none of the aCAM cells / subcircuits could store individually.

[0013] To complement the range segmentation / programming used to store an analog voltage range across multiple aCAM cells / subcircuits, examples also employ strategic signal adaptations that allow a circuit to search for a digital input signal (x) based on the (large) analog voltage range representatively stored across the multiple aCAM cells / subcircuits. Such signal adaptations may include providing a particular aCAM cell / subcircuit with a version of the digital input signal (x) reduced according to a total number of programming levels of the aCAM cells / subcircuits that precede it in an ordered representational level arrangement (the term "ordered representational level arrangement" as used herein may refer to an ordered logic arrangement of aCAM subcircuits used to store representative levels for a circuit).As described below, such signal conditioning / reduction can be used to accommodate structural / programmability constraints of the individual aCAM cells / subcircuits of the circuit. Such signal conditioning allows the circuit to seek received input signal values ​​that exceed the restrictive programmability limits of the aCAM cells / subcircuits that comprise the circuit.

[0014] Fig. Figure 1 shows an example of an aCAM cell 100 that can be used to implement circuits of the technique disclosed herein. As described above, the aCAM cell 100 can search for an input signal (e.g., an analog input voltage signal (V(x))) using a stored analog voltage range.

[0015] The aCAM cell 100 includes a match line (i.e., ML 102) that can be precharged to a high voltage. As described further below, the aCAM cell 100 "provides a match" when the voltage on the ML 102 remains high and "a mismatch" when the voltage on the ML 102 is discharged. As described above, in various examples, the aCAM cell 100 may be an aCAM cell in a row of an aCAM array. In certain examples, the match / mismatch result for the entire row (of which the aCAM cell 100 is a part) may be output to other circuitry (e.g., a resistive random access memory array) for further processing / classification.

[0016] The aCAM cell 100 also includes two data lines: DL1 106 and DL2 108 (in the example from Fig.1 running vertically), both electrically connected to an input data line: DL 104. The aCAM cell 100 can receive an analog input voltage signal (V(x)) along the DL 104 (here, the analog input voltage signal (V(x)) can be an analog voltage signal converted from a digital input signal (x)). As shown, DL1 106 and DL2 108 are both electrically connected to DL 104 and electrically connected in parallel with each other. Accordingly, an analog input voltage signal (V(x)) can be applied along DL1 106 and DL2 108, respectively. As previously mentioned, if the analog input voltage signal (V(x)) is outside the analog voltage range programmed into the aCAM cell 100, the analog input voltage signal (V(x)) will eventually discharge ML 102.Here, the analog voltage range stored by the aCAM cell 100 is set / defined by the programmed conductances of the memristors M1 and M2, whereby the programmed conductance of the memristor M1 sets / defines the lower limit of the stored analog voltage range and the programmed conductance of the memristor M2 sets / defines the upper limit of the stored analog voltage range (see e.g. . Fig. 2).

[0017] As shown, the aCAM cell 100 includes a "lower limit side" 110 and an "upper limit side" 120 because the memristors M1 and M2 are programmed to define the lower limit and the upper limit, respectively, of the analog voltage range stored by the aCAM cell 100.

[0018] The lower barrier 110 includes a transistor T1 and a memristor M1 electrically connected in series. The memristor M1, in conjunction with the transistor T1, forms a voltage divider subcircuit 112. As shown, the voltage divider subcircuit 112 generates a gate voltage (G1) across the pull-down transistor T2. When the gate voltage (G1) across the pull-down transistor T2 exceeds a threshold, the pull-down transistor T2 is turned on / activated, and the voltage across the ML 102 is "pulled down" (i.e., discharged), providing a mismatch. As described above, the voltage across the pull-down transistor T2 can be influenced by: (1) the programmed conductance of the memristor M1 and (2) the analog input voltage signal (V(x)). In particular, the transistor T1 becomes more conductive when the analog input voltage signal (V(x)) is greater than or equal to a threshold voltage (ZB (T L)) (the programmed conductance of the memristor M1 remains the same during the search process), and thus the voltage between SL_hi and SL_lo (typically at ground (GND)) drops across the memristor M1, resulting in a small gate voltage (G1) that does not turn on / activate the pull-down transistor T2, giving a consistent result for the lower limit side 110. Here, the value of (T L ) (i.e., the threshold voltage that causes transistor T1 to become more conductive relative to memristor M1) can be programmed by programming the conductance of memristor M1. In this way, the programmed conductance of memristor M1 can be used to set the lower limit of the voltage range stored by aCAM cell 100.

[0019] Similar to the lower limit side 110, the upper limit side 120 comprises a transistor T3 and a memristor M2 electrically connected in series. The memristor M2, together with the transistor T3, forms a voltage divider subcircuit 122. The upper limit side 120 differs slightly from the lower limit side 110 in that the voltage divider subcircuit 122 is electrically connected to an input of an inverter 124 (here, the series-connected transistors T4 and T5 work together to form the inverter 124). The inverter 124 serves to invert the voltage output by the voltage divider subcircuit 122. Since the pull-down transistor T6 is electrically connected to the output of the inverter 124, the inverted voltage output by the inverter 124 controls the gate voltage (G2) on the pull-down transistor T6.When the gate voltage (G2) on pull-down transistor T6 exceeds a threshold, pull-down transistor T6 turns on / activates and "pulls" (i.e., discharges) the voltage on ML 102, creating a mismatch. As described above, the voltage on pull-down transistor T6 can be affected by: (1) the programmed conductance of memristor M2 and (2) the analog input voltage signal (V(x)). In particular, when the analog input voltage signal (V(x)) is less than or equal to a threshold voltage (e.g., (T H)), the transistor T3 is not highly conductive (e.g., with a conductance on the order of 10 nS compared to a higher conductance state of, e.g., 10 mS), and thus the voltage between SL_hi and SL_lo (typically at GND) remains high across the transistor T3, resulting in a high output voltage for the voltage divider subcircuit 122. However, when this high voltage is inverted by the inverter 124, the inverted (now low) voltage causes a low gate voltage (G2), which does not turn on / activate the pull-down transistor T6, thus giving a consistent result for the upper limit side 120. Here, the value of (T H) (i.e., the threshold voltage that causes transistor T3 to be non-conductive relative to memristor M2) can be programmed by programming the conductance of memristor M2. In this way, the programmed conductance of memristor M2 can be used to set the upper limit of the voltage range stored by a CAM cell 100.

[0020] Fig.Figure 2 shows an example diagram illustrating how memristors M1 and M2 of aCAM cell 100 can be used to set the lower voltage limit 202 and the upper voltage limit 204 of a stored voltage range for aCAM cell 100. As shown, aCAM cell 100 provides a match for an analog input voltage signal (V(x)) when the analog input voltage signal (V(x)) is within the voltage range defined by the lower voltage limit 202 and the upper voltage limit 204. If the analog input voltage signal (V(x)) is outside the voltage range defined by the lower voltage limit 202 and the upper voltage limit 204, aCAM cell 100 provides a mismatch. As described above, the conductance of the memristors M1 and M2 can be programmed to set / define the lower limit voltage 202 and the upper limit voltage 204.

[0021] As described above, the accuracy of aCAM cells (including the aCAM Cell100) is limited because the memristors they use to define range limits can only be programmed to a discrete / finite number of conductance states. Referring to the diagram in Fig.2 to illustrate the concept, this means that the lower limit voltage 202 and the upper limit voltage 204 can only be placed at a discrete / finite number of locations (represented by the vertical dashed lines to illustrate the concept). This, in turn, limits the number of programmable levels that an aCAM cell (e.g., aCAM cell 100) can store / search. As described above and further explained below, examples of the presently disclosed technique provide new circuits that increase the number of programmable levels for aCAMs by utilizing the concept of range segmentation to representatively store an analog voltage range across multiple aCAM cells / subcircuits (here, the representatively stored analog voltage range may correspond to one entry of a stored word). In this way, a circuit of the presently disclosed technique can increase the accuracy (i.e.,The number of programmable levels (i.e., the number of programmable levels for the circuit) can increase linearly with each aCAM cell / subcircuit added to the circuit. Accordingly, circuits of the presently disclosed technique can be used to perform more complex calculations than conventional aCAMs—and can thus be used in a wider range of computing applications.

[0022] Fig.3 shows an example diagram illustrating how memristors M1 and M2 of aCAM cell 100 can be programmed to store an open voltage range for aCAM cell 100 (i.e., a stored voltage range that is unlimited at at least one end). As shown, aCAM cell 100 returns a match for an analog input voltage signal (V(x)) when the analog input voltage signal (V(x)) is greater than or equal to a lower limit voltage 302 set by memristor M1. In other words, CAM cell 100 only reports a mismatch when the analog input voltage signal (V(x)) is less than the lower limit voltage 302. As described above, the conductance of memristor M1 can be programmed to set the lower limit voltage 302.

[0023] This is where Fig. 3 of Fig.2, because the conductance of memristor M2 has been programmed to a "wildcard" value (sometimes called a "don't care" value) that virtually always provides a match for the upper limit side 120 of the aCAM cell 100 (i.e., a match for the upper limit side 120 of the aCAM cell 100 for any value of the analog input voltage signal (V(x)) that would be received by the aCAM cell 100 in practice). In general, deep conductance states of memristors can be used as placeholder values ​​that establish virtually unlimited lower and upper limits for an aCAM cell. These deep conductance states (e.g., a deep low conductance state (DLCS) for a lower wildcard lower limit value and a deep high conductance state (DHCS) for a wildcard upper limit value) are well outside the reliably programmable conductance ranges of the memristors.For example, if the memristors of a CAM cell 100 are programmed in the range [1uS, 100uS], deep conductance states of, for example, 0.01uS and 1000uS can be used for wildcard values, which set practically open lower and upper limits for the aCAM cell 100. These deep conductance states are generally difficult to program reliably and are therefore reserved for wildcard values ​​where a programming error of, for example, 10% is acceptable. By programming the memristors of the aCAM cell 100 to wildcard values ​​ / deep conductance states, deep lower and upper voltage limits can be set in examples that are practically unlimited.In other words, since in practice the input / search voltage values ​​received by an aCAM cell / subcircuit generally always lie within the lower and upper low-state voltage limits set by programming the memristors of an aCAM cell / subcircuit to wildcard values, it can generally be stated that programmed wildcard values ​​always provide a match.

[0024] In Fig.3, memristor M2 thus effectively sets an open "upper limit" for the analog voltage range stored by CAM cell 100. It should be understood that in other examples, the conductance of memristor M2 may be programmed to specify a "true" upper limit voltage (i.e., an upper limit voltage that effectively defines a "less than or equal to" condition at the upper limit) and the conductance of memristor M1 may be programmed to a "wildcard" value that practically always provides a match for the lower limit side 110 of CAM cell 100 (i.e., such programming can effectively store an open voltage range that is practically limited only at the upper end). Likewise, in certain examples, the conductances of both memristors M1 and M2 may be programmed to "wildcard" values ​​so that CAM cell 100 practically always provides a match (i.e.,for each value of the analog input voltage signal (V(x)) that the CAM cell 100 would receive in practice).

[0025] As described in detail below, examples may use “wildcard” programming to store open voltage ranges for individual aCAM cells / subcircuits, which are used in combination with other aCAM cells / subcircuits to representatively store a (larger) analog voltage range.

[0026] Fig. Figure 4 shows an example of a conceptual diagram that can be used to illustrate the concept of area division. In particular, Fig.4 illustrates how an example circuit 400 may be used to represent a large range 450 from 2-10 (integer values ​​are used here for illustrative purposes, but it should be understood that circuit 400 may representatively store an analog voltage range corresponding to the stored integer range of 2-10). The large range 450 may correspond to a word entry (i.e., circuit 400 may representatively store a word entry corresponding to or represented by the large range 450 by representatively storing the large range 450).

[0027] As described above, examples can use “region segmentation” to representatively store a region across multiple aCAM cells / subcircuits - where each aCAM cell / subcircuit representatively stores a segment of the (larger) representatively stored region.

[0028] The term "representatively stores" is used here because the range for which a particular aCAM cell / subcircuit is actually programmed may differ from the segment it representatively stores. This is partly because a typical aCAM cell / subcircuit can only be programmed to store ranges with a minimum possible lower bound of 1 and a maximum possible upper bound of 2. M where “M” represents the number of programmable bits of the aCAM cell / subcircuit (as well as the number of programmable bits of the memristors used in the aCAM cell / subcircuit), and “2 M“ represents the number of programmable levels of the aCAM cell / subcircuit (it is understood that in certain examples where “0” instead of 1 is the lowest programmable level of the aCAM cell / subcircuit, the aCAM cell / subcircuit may have ranges with a minimum possible lower limit of 0 and a maximum possible upper limit (2 M -1). However, by segmenting the ranges, the example circuits can also store ranges whose upper or lower limit is higher than 2 M For example, a circuit according to examples of the presently disclosed technique consisting of “N” aCAM cells / subcircuits may have regions with a maximum possible upper limit of N*2 M (or a maximum possible lower limit of (N*2 M-1)) representatively store - although the aCAM cells / subcircuits that form the circuit are only designed to store areas with a maximum possible upper or lower limit of 2 M can be programmed. As will be described later, examples use strategic programming of limit values ​​within the individual aCAM cells / subcircuits so that the individual aCAM cells / subcircuits can store representative segments that contain values ​​greater than 2 M contain.

[0029] Again with reference to Fig. 4, the example circuit 400 comprises four aCAM subcircuits (i.e., the aCAMs 401-404) connected along a match line (not shown) such that they perform Boolean "AND" operations with respect to each other. Here, each aCAM subcircuit of the circuit 400 may be the same / similar to the aCAM cell 100 of Fig. 1, although this does not have to be the case.

[0030] As in Fig. 4, each aCAM subcircuit of circuit 400 has four programmable levels (i.e., programmable levels 1, 2, 3, and 4 - the programmable levels of the aCAM subcircuits of circuit 400 are shown in Fig. 4 below). Through region segmentation and strategic programming, examples can use the four aCAM subcircuits of circuit 400 to represent regions across 16 representation levels (the representation levels of the aCAM subcircuits of circuit 400 are shown in Fig. 4 shown above).

[0031] The ordered logic arrangement of the aCAM subcircuits used to store the representation levels for circuit 400 may be referred to herein as an ordered arrangement of representation levels for circuit 400. Accordingly, each aCAM subcircuit of circuit 400 may be assigned a placement in the ordered representation level arrangement for circuit 400. For example, aCAM 401 may be assigned a first placement in the ordered representation level arrangement (i.e., representation levels 1-4), aCAM 402 may be assigned a second placement in the ordered representation level arrangement (i.e., representation levels 5-8), aCAM 403 may be assigned a third placement in the ordered representation level arrangement (i.e., representation levels 9-12), and aCAM 404 may be assigned a fourth placement in the ordered representation level arrangement (i.e., representation levels 13-16).Furthermore, it can be said that: (1) the aCAMs 401-403 are located before the aCAM 404 in the ordered representation level arrangement; (2) the aCAMs 401-402 are located before the aCAM 403 in the ordered representation level arrangement; and (3) the aCAM 401 is located before the aCAM 402 in the ordered representation level arrangement. As described below, the placement of a particular aCAM subcircuit in the ordered representation level arrangement of circuit 400 can determine which version of a matched input signal the given aCAM subcircuit receives.

[0032] Again with reference to Fig.4, and in particular on aCAM 401, it can be seen that the programmable levels of the aCAM 401 (i.e., programmable levels 1-4) and the representation levels assigned to the aCAM 401 (i.e., representation levels 1-4) are identical. This is because the representation levels assigned to aCAM 401 can all be programmed directly in the aCAM 401.

[0033] However, the programmable levels and the representation levels of the aCAM 402 are different from each other. In particular, a particular representation level of the aCAM 402 (e.g., representation level 5) is equivalent to the corresponding programmable level, increased by the number of programmable levels of the aCAM subcircuit that precedes the aCAM 402 in the ordered arrangement of representation levels of the circuit 400 (i.e., the number of programmable levels of the aCAM 401). For example, the representation level 5 of the aCAM 402 corresponds to the corresponding programmable level 1 of the aCAM 402, increased by the number of programmable levels (4) of the aCAM 401. As described above, the aCAM 402 cannot be directly programmed to set upper or lower limits higher than 4 because it is only a two-bit aCAM subcircuit with four programmable levels.Through strategic programming in combination with the signal adjustments associated with . Fig. 5, the aCAM 402 can, however, be programmed to representatively store / search for an upper or lower limit higher than 4 - namely at representation levels 5-8.

[0034] Likewise, the programmable levels and the representation levels of the aCAM 403 are different from each other. In particular, a particular representation level of the aCAM 403 (e.g., representation level 10) is equivalent to the corresponding programmable level increased by the number of programmable levels of the two aCAM subcircuits preceding the aCAM 403 in the ordered representation level arrangement of the circuit 400 (e.g., the combined number of programmable levels of aCAM 401 and aCAM 402). For example, the representation level 10 of the aCAM 403 is equivalent to the corresponding programmable level 2 of the aCAM 403, increased by the combined number of programmable levels (8) of the aCAMs 401 and 402. As described above, the aCAM 403 cannot be directly programmed to set upper or lower limits higher than 4 because it is only a two-bit aCAM subcircuit with four programmable levels.Through strategic programming in combination with the signal adjustments associated with . Fig. 5, the aCAM 403 can, however, be programmed to store or search for an upper or lower limit higher than 4 - namely at representation levels 9-12.

[0035] The programmable levels and the representation levels of the aCAM 404 also differ from each other. In particular, a given representation level of the aCAM 404 (e.g., representation level 15) is equivalent to the corresponding programmable level increased by the number of programmable levels of the three aCAM subcircuits preceding the aCAM 404 in the representation level arrangement of the circuit 400 (e.g., the combined number of programmable levels of the aCAMs 401-403). For example, representation level 15 of the aCAM 404 corresponds to the corresponding programmable level 3 of the aCAM 404 increased by the combined number of programmable levels (12) of the aCAMs 401-403. As described above, the aCAM 404 cannot be directly programmed to set upper or lower limits higher than 4, as it is only a two-bit aCAM subcircuit with four programmable levels.Through strategic programming in combination with the signal adjustments associated with . Fig. 5, the aCAM 404 can, however, be programmed to store / search for an upper or lower limit higher than 4 - namely at representation levels 13-16.

[0036] As is clear from the examples of the presently disclosed technique, by segmenting regions and strategically programming thresholds within each aCAM subcircuit, the four aCAM subcircuits of circuit 400 can be used in combination to represent and store regions with a maximum possible upper limit of 16. Thus, the four aCAM subcircuits of circuit 400 can be used in combination to representatively store the large region 450, which ranges from 2 to 10. In particular, each of the aCAMs 401-403 can representatively store a segment of the large region 450, so that in combination they representatively store the large region 450 in its entirety.

[0037] As in Fig.4 (and Table 1 below), the aCAM 401 stores a first segment 461 (here, the first segment 461 covers a range of 2-4), the aCAM 402 stores a second segment 462 (here, the second segment 462 covers a range of 5-8), and the aCAM 403 stores a third segment 463 (here, the third segment 463 covers a range of 9-10). In the specific example of Fig. 4, the aCAM 404 does not representatively store any segment of the large area 450. Again, the term "representatively stores" is used because the area a particular aCAM subcircuit is programmed to store may differ from the area that the particular aCAM cell / subcircuit representatively stores. For illustrative purposes, Table 1 below compares the areas that the aCAMs 401-404 are programmed to store with the segments of the large area 450 that the aCAMs 401-404 representatively store. Table 1 aCAM 401 aCAM 402 aCAM 403 aCAM 404 Programmed lower limit 2 Open - i.e. "wildcard" Open - i.e. "wildcard" Open - i.e. "wildcard" Programmed upper limit Open - i.e. "wildcard" Open - i.e. "wildcard" 2 Open - i.e. "wildcard" Lower limit representation segment 2 5 9 N / A Upper limit representation segment 4 8 10 N / A

[0038] As shown in Table 1, to representatively store a range of 2 to 10: (1) the lower limit of the aCAM 401 is programmed to a value of 2 and the upper limit of the aCAM 401 is programmed to an open / "wildcard" value that virtually always yields a match; (2) the lower limit of the aCAM 402 is programmed to an open / "wildcard" value that virtually always yields a match, and the upper limit of the aCAM 402 is programmed to an open / "wildcard" value that virtually always yields a match; (3) the lower limit of the aCAM 403 is programmed to an open / "wildcard" value that virtually always yields a match, and the upper limit of the aCAM 403 is programmed to a value of 2;and (4) the lower limit of the aCAM 404 is programmed to an open / "wildcard" value that virtually always yields a match, and the upper limit of the aCAM 404 is programmed to an open / "wildcard" value that virtually always yields a match. As discussed in connection with ; Fig. As described in Section 1, the lower and upper limits of the individual aCAM subcircuits (including the “wildcard” values) can be programmed by programming the conductances of memristors included in the individual aCAM subcircuits.

[0039] Here, the programmed lower limit of the aCAM 401 (i.e., programmable level 2) sets the lower limit (i.e., representation level 2) of the large range 450, as representatively stored by the circuit 400. The programmed upper limit of the aCAM 403 (i.e., programmable level 2) sets the upper limit (i.e., representation level 10) of the large range 450, as representatively stored by the circuit 400. Since the other programmable lower / upper limits of the aCAMs 401-404 are not used to set representation limits for the large analog voltage range 450, they are programmed to "wildcard" values ​​that virtually always provide a match. This strategic programming, as well as the signal reduction / adaptation required to search for an input signal (x) using such a representatively stored range, is discussed below in connection with Fig.5. However, at a high level, such strategic programming and signal conditioning is intended to account for the fact that the programmable levels and the representation levels of the aCAMs 402-404 differ from each other. As described above, the programmable levels and the representation levels of the aCAMs 402-404 differ from each other due to the programmability limitations of the aCAM subcircuits—namely, that they cannot be directly programmed to set lower or upper limits above 4.

[0040] Fig.5 shows an example circuit 500 according to examples of the presently disclosed technique. Circuit 500 includes four aCAM subcircuits (i.e., aCAMs 501-504) connected along a match line such that they perform Boolean "AND" operations with respect to one another. Each aCAM subcircuit of circuit 500 may be the same / similar to aCAM cell 100, although this need not be the case. Circuit 500 also includes four digital-to-analog converters (DACs) (i.e., DACs 511-514) and a controller 520.

[0041] Like the aCAM subcircuits of circuit 400, each aCAM subcircuit of circuit 500 has four programmable levels. Through range segmentation and strategic programming, in examples, the four aCAM subcircuits of circuit 500 can be used to store analog voltage ranges across 16 representation levels. Here, circuit 500 can have the same / similar ordered arrangement of representation levels as circuit 400, with aCAM 501 assigned a first placement in the ordered arrangement of representation levels (i.e., representation levels (V(1))-(V(4))), aCAM 502 assigned a second placement in the ordered arrangement of representation levels (i.e., representation levels (V(5))-(V(8))), aCAM 503 assigned a third placement in the ordered arrangement of representation levels (i.e.,Representation levels (V(9))-(V(12))) and the aCAM 504 is assigned a fourth placement in the ordered arrangement of representation levels (i.e., representation levels (V(13))-(V(16))). Where "V" can represent a function or group of functions used by DACs 511-514 to convert digital integer values ​​to analog voltage values.

[0042] As shown, the controller 520 receives a digital input signal (x). As mentioned above, the integer value of the digital input signal (x) can be any value between 1 and 16, since the circuit 500 has (4*2 M=2=16) representation levels (in various examples, such an integer value can be represented bitwise). Accordingly, an analog signal (V(x)) representing the digital input signal (x) can be any value from (V(1)) to (V(16)) (where "V" can represent a function or group of functions used by DACs 511-514 to convert digital integer values ​​to analog voltage values).

[0043] It should be understandable why a digital input signal (x) with a value greater than (4) might pose a challenge for examples of the presently disclosed technique. As described above, the aCAMs 501-504 each have only 4 programmable levels and can therefore only be programmed to set limits up to (V(4)).

[0044] Thus, for example, if circuit 500 were programmed to representatively store an analog voltage range of (V(2))-(V(10)), the representative upper limit of (V(10)) would have to be set by programming the upper limit of aCAM 503 to (V(2)) (this is analogous here to setting the representative upper limit of 10 for the large range 450 by programming the upper limit of aCAM 403 to a value of 2).

[0045] Now assume that the received analog signal (V(x)) is equal to (V(9)). In this case, if (V(x))=(V(9)) is fed to the aCAM 503 without any reductions / adjustments, the aCAM 503 returns a mismatch because (V(x))=(V(9)) is not less than or equal to the programmed upper limit for aCAM 503 of (V(2)). Since the aCAMs 501-504 are connected along a match line such that they perform Boolean AND operations with respect to each other, the circuit 500 returns a mismatch if any of the aCAM subcircuits (including aCAM 503) returns a mismatch. If circuit 500 were to produce a mismatch at (V(x))=(V(9)), this would be a problem because circuit 500 is designed to representatively store an analog voltage range of (V(2))-(V(10)) in which (V(9)) lies.To avoid such an erroneous result, examples of the presently disclosed technique utilize strategic signal adaptations that involve providing a particular aCAM subcircuit with a version of the analog voltage signal (V(x)) that is reduced according to a total number of programmable levels of the aCAM cells / subcircuits preceding the particular aCAM subcircuit in an ordered representational level arrangement. As described above, such signal adaptation / reduction may accommodate the structural / programmability limitations of the individual aCAM subcircuits of circuit 500—namely, that they cannot be directly programmed to set lower or upper limits above (V(4)). For this reason, the programmable levels and the representation levels of the aCAMs 502-504 are distinct from each other.As described below, this difference can be taken into account by signal adaptation / reduction.

[0046] As in Fig. 5, the controller 520 performs the signal adjustments / reductions described above. In the specific example of Fig. 5, such signal adjustments are performed in the digital domain (i.e., before versions of the digital input signal (x) are converted into analog voltage signals), but in other examples, such signal adjustments may be performed in the analog domain (i.e., after the digital input signal (x) has been converted into an analog voltage signal).

[0047] As shown, control unit 520 supplies an unadjusted version of the digital input signal (x) to DAC 511 (which is electrically connected to aCAM 501). Here, no reduction is required for the signal supplied to DAC 511 / aCAM 501 because aCAM 501 is first in the ordered representation level arrangement of circuit 500. Accordingly, all representation levels assigned to aCAM 501 can be programmed directly in aCAM 501. In other words, aCAM 501 will never set a representation limit higher than (V(4))—which would be used to search for the analog voltage signal (V(x)).

[0048] In contrast, the controller 520 feeds a reduced version of the digital input signal (x) to the DAC 512 (which is electrically connected to the aCAM 502). The analog signal fed to the aCAM 502 (i.e., the analog signal (V(x-4))) has thus been reduced (in the digital domain) according to the number of programmable levels of the aCAM 501 (i.e., 4 programmable levels). Such signal reduction is used to account for the difference between the representation levels of the aCAM 502 (i.e., (V(5))-(V(8))) and the programmable levels of the aCAM 502 (i.e., (V(1))-(V(4))). Here too, the analog signal supplied to the aCAM 502 (ie the analog signal (V(x-4))) is searched directly based on the programmable levels of the aCAM 402 (ie (V(1))-(V(4)).

[0049] Likewise, the control unit 520 supplies a reduced version of the digital input signal (x) to the DAC 513 (which is electrically connected to the aCAM 503). Thus, the analog signal supplied to the aCAM 503 (i.e., the analog signal (V(x-8))) (in the digital domain) has been reduced according to a combined number of programmable levels of the aCAMs 501 and 502 (i.e., 8 programmable levels). Such signal reduction is used to account for the difference between the representation levels of the aCAM 503 (i.e., (V(9))-(V(12))) and the programmable levels of the aCAM 503 (i.e., (V(1))-(V(4))). Here too, the analog signal supplied to the aCAM 503 (ie the analog signal (V(x-8)) is searched directly based on the programmable levels of the aCAM 503 (ie (V(1))-(V(4)).

[0050] Likewise, controller 520 supplies a reduced version of the digital input signal (x) to DAC 514 (which is electrically connected to aCAM 504). Thus, the analog signal supplied to aCAM 504 (i.e., the analog signal (V(x-12))) (in the digital domain) has been reduced according to a combined number of programmable levels of aCAMs 501-503 (i.e., 12 programmable levels). Such signal reduction is used to account for the difference between the representation levels of the aCAM 404 (i.e., (V(13))-(V(16))) and the programmable levels of the aCAM 504 (i.e., (V(1))-(V(4))), against which the signal fed to the aCAM 504 (i.e., the analog signal (V(x-12))) is searched. Again, the analog signal fed to the aCAM 504 (i.e., the analog signal (V(x-12))) is searched directly against the programmable levels of the aCAM 504 (i.e., (V(1))-(V(4)).

[0051] As described above, through region segmentation and strategic signal adjustments, circuit 500 can combine commonly used aCAM cells to representatively store a much wider variety of analog voltage ranges than conventional aCAMs. In this way, circuit 500 can linearly increase accuracy with each aCAM cell / subcircuit added to the circuit (e.g., the number of programmable levels / representation levels that can be used to store a word entry and / or the number of programmable levels / representation levels by which an input signal can be searched). Accordingly, circuit 500 can perform more complex calculations than conventional aCAMs—and can therefore be used in a wider range of computing applications.

[0052] Fig.6 shows an example circuit 600 according to examples of the presently disclosed technique. Specifically, circuit 600 represents an abstract / generic circuit design from which circuits 400 and 500 can be derived.

[0053] As shown, circuit 600 includes four aCAM subcircuits (i.e., aCAMs 601-604) connected along a match line to perform Boolean "AND" operations with respect to each other. Each aCAM subcircuit of circuit 600 may be the same / similar to aCAM cell 100 of Fig. 1, although this need not be the case. While circuit 600 includes four aCAM subcircuits, it should be understood that in other examples, circuit 600 may generally include two or more aCAM subcircuits (e.g., a first aCAM subcircuit, a second subcircuit, etc.). Circuit 600 also includes a signal conversion segment 620.

[0054] As in connection with the Fig. 4-5, the circuit 600 may include an ordered arrangement of representation levels, wherein each aCAM subcircuit of the circuit 600 is assigned a placement in the ordered arrangement of representation levels (such placement assignment determines which analog voltage signal is supplied to each aCAM subcircuit). For example, the aCAM 601 may be assigned a first placement in the ordered representation level arrangement comprising representation levels consisting of integer values ​​from (1) to (2 M ), where "M" represents the number of programmable bits of the aCAM 601. The aCAM 602 may be assigned a second placement in the ordered representation level arrangement, which includes representation levels consisting of integer values ​​of (2 M +1) to (2 M + 2 N), where "N" represents the number of programmable bits of the aCAM 602. Likewise, the aCAM 603 may be assigned a third placement in the ordered representation level arrangement, which includes representation levels consisting of integer values ​​of (2 M + 2 N + 1) to (2 M + 2 N +2 P ), where “P” represents the number of programmable bits of the aCAM 603, and so on. In the specific example of Fig.6, the aCAM 601 may be assigned the first placement of the ordered representation level arrangement for the circuit 600, the aCAM 602 may be assigned the second placement of the ordered representation level arrangement for the circuit 600, the aCAM 603 may be assigned the third placement of the ordered representation level arrangement for the circuit 600, and the aCAM 604 may be assigned the fourth placement of the ordered representation level arrangement for the circuit 600. Assuming that each aCAM subcircuit of the circuit 600 has “M” programmable bits, the number of representation levels / programmable levels for the circuit 600 may be (4*2 M ).

[0055] Taking advantage of the ordered representation level arrangement described above, two or more of the aCAM subcircuits of circuit 600 can be used in combination to represent an analog voltage range, with a particular aCAM subcircuit representing a segment of the (larger) represented analog voltage range. Thus, in a first example, an analog voltage range could be representatively stored across aCAMs 601 and 602; in a second example, an analog voltage range could be representatively stored across aCAMs 601-603; in a third example, an analog voltage range could be representatively stored across aCAMs 601-604; in a fourth example, an analog voltage range could be representatively stored across aCAMs 602 and 603; in a fifth example, an analog voltage range could be representatively stored across aCAMs 602-604; and so on.In each example, the representatively stored analog voltage can represent an entry of a word.

[0056] As described above, each aCAM subcircuit of circuit 600 may include two memristors that may be programmed to representatively store segments of the (larger) analog voltage range. For example, aCAM 601 may include a first memristor and a second memristor, aCAM 602 may include a third memristor and a fourth memristor, aCAM 603 may include a fifth memristor and a sixth memristor, and aCAM 604 may include a seventh memristor and an eighth memristor.

[0057] In extension of the second example above (i.e., where the analog voltage range is representatively stored across the aCAMs 601-603), the first memristor of the aCAM 601 can be used to representatively set a lower limit for the analog voltage range that is representatively stored across the aCAMs 601-603. In particular, the first memristor of the aCAM 601 can be programmed to set a lower limit threshold voltage (V 1TL ) for the aCAM 601, which representatively sets the lower limit for the (larger) analog voltage range. The sixth memristor of the aCAM 603 can be used to representatively set an upper limit for the analog voltage range that is representatively stored across the aCAMs 601-603. In particular, the sixth memristor of the aCAM 603 can be programmed to set an upper limit threshold voltage (V 3TH) for the aCAM 603, which can set the upper limit for the (larger) analog voltage range in a representative manner.

[0058] As described above, the memristors of circuit 600 that are not used to define representation limits for the (larger) analog voltage range can be programmed to "wildcard" values ​​that virtually always match their respective circuit segments. For example, the second memristor (of the aCAM 601) can be programmed to define an open-ended upper-limit threshold voltage (V 1TH=„wildcard" ) for the aCAM 601 so that the aCAM 601 provides a match along the match line unless the analog voltage signal received by the aCAM 601 is less than (V 1TL ). Similarly, the fifth memristor (of the aCAM 603) can be programmed to provide an open-circuit lower threshold voltage (V 3TL=„wildcard") for aCAM 603 so that aCAM 603 provides a match along the match line unless the analog voltage signal received by aCAM 603 is greater than (V 3TH ). Related to this, the third memristor (of the aCAM 602) can be programmed to provide an open lower threshold voltage (V 2TL=„wildcard" ) for the aCAM 602, and the fourth memristor (of the aCAM 602) can be programmed to set an open upper limit threshold voltage (V 2TH=„wildcard" ) for the aCAM 602 so that the aCAM 602 will provide a match for virtually any analog voltage signal it receives (i.e., any analog voltage signal within the low voltage limits defined by the third and fourth memristors). Similarly, the seventh memristor (of the aCAM 604) can be programmed to provide an open-loop low-limit threshold voltage (V 4TL=„wildcard") for the aCAM 604, and the eighth memristor (of the aCAM 604) can be programmed to set an open upper limit threshold voltage (V 4TH=„wildcard" ) for the aCAM 604 so that the aCAM 604 will provide a match for virtually any analog voltage signal value it receives (i.e., any analog voltage signal within the low voltage limits defined by the seventh and eighth memristor).

[0059] With reference to the signal adjustments performed by circuit 600, as illustrated, circuit 600 receives a digital input signal (x) via signal conversion segment 620. Signal conversion segment 620 then converts the digital input signal (x) into: (1) a first analog voltage signal (V(x)) supplied to aCAM 601; (2) a second analog voltage signal (V(x-PL1)) supplied to aCAM 602; (3) a third analog voltage signal (V(x-PL 1 / 2)), which is fed to the aCAM 603; and (4) a fourth analog voltage signal (V(x-PL 1 / 2 / 3 )) which is supplied to the aCAM 604. It is understood that the signal conversion segment 620 may comprise various types and combinations of circuit elements (e.g., controllers, digital-to-analog converters, signal subtraction subcircuits, etc.). Non-exhaustive examples of the signal conversion segment 620 are described in connection with the Fig. 7-9. However, the components of the signal conversion segment 620 are less important than its overall function, which is to implement the Fig.5 - namely, to supply a particular aCAM subcircuit with an analog voltage signal representing a version of a received digital input signal (x) reduced according to a total number of programmable levels of aCAM subcircuits preceding the particular aCAM subcircuit in an ordered representation level arrangement for the circuit.

[0060] Accordingly, the first analog voltage signal (V(x)) supplied to the aCAM 601 may comprise an analog voltage signal representing the digital input signal (x) originally received by the circuit 600. The aCAM 601 only provides a match for the first analog voltage signal (V(x)) if the first analog voltage signal (V(x)) is within a programmed voltage range of the aCAM 601—defined by programmed conductances of the memristors comprising the aCAM 601 (i.e., the first memristor and the second memristor). For example, if the first memristor (of the aCAM 601) is programmed to have a lower limit threshold voltage (V 1TL ) for the aCAM 601, and the second memristor (of aCAM 601) is programmed to set an open upper limit threshold voltage (V 1TH=„wildcard") for the aCAM 601, the aCAM 601 will deliver a match unless the first analog voltage signal (V(x)) is less than (V 1TL ).

[0061] The second analog voltage signal (V(x-PL1)) supplied to the aCAM 602 may comprise an analog voltage signal representing a version of the digital input signal (x) reduced according to a number of programmable levels of the aCAM 601 (i.e., PL1). As described above, such signal conditioning is required to compensate for a difference between the programmable levels of the aCAM 602 (e.g., programmable levels (1) to (2 N ), where “N” represents the number of programmable bits for aCAM 602) and the representation levels assigned to the aCAM 602 for storage (e.g. representation levels (2 M +1) to (2 M + 2 N), where "M" is the number of programmable bits of the aCAM 601). Therefore, the aCAM 602 only provides a match for the second analog voltage signal (V(x-PL1)) if the second analog voltage signal (V(x-PL1)) is within a programmed voltage range of the aCAM 602 - defined by the programmed conductances of the memristors that make up the aCAM 602 (i.e., the third memristor and the fourth memristor). For example, if the third memristor (of the aCAM 602) is programmed to provide an open-loop lower-bound threshold voltage (V 2TL=„wildcard" ) for the aCAM 602, and the fourth memristor (of the aCAM 602) is programmed to set an open upper limit threshold voltage (V 2TH=„wildcard") for the aCAM 602, the aCAM 602 provides a match for virtually any value of the second analog voltage signal (V(x-PL1)) (i.e., for any value of the second analog voltage signal (V(x-PL1)) within the low voltage limits defined by the third and fourth memristor).

[0062] The third analog voltage signal (V(x-PL 1 / 2 )) supplied to the aCAM 603 may comprise an analog voltage signal representing a version of the digital input signal (x) that corresponds to the total number of programmable levels of the aCAMs 601 and 602 (i.e., PL 1 / 2 ) is reduced. As described above, such signal conditioning is required to compensate for a difference between the programmable levels of the aCAM 603 (e.g. programmable levels (1) to (2 P), where “P” stands for the number of programmable bits for the aCAM 603) and the representation levels assigned to the aCAM 603 for storage (e.g. representation level (2 M + 2 N +1) to (2 M + 2 N + 2 P )). Therefore, the aCAM 603 only provides a match for the third analog voltage signal (V(x-PL 1 / 2 )) when the third analog voltage signal (V(x-PL 1 / 2 )) is within a programmed voltage range of the aCAM 603 - defined by the programmed conductances of the memristors that make up the aCAM 603 (i.e., the fifth and sixth memristors). For example, if the fifth memristor (of the aCAM 603) is programmed to have an open-circuit lower threshold voltage (V 3TL=„wildcard" ) for the aCAM 603, and the sixth memristor (of the aCAM 603) is programmed to set an (actual) upper limit threshold voltage (V 3TH) for the aCAM 603, the aCAM 603 returns a match unless (V(x-PL 1 / 2 )) exceeds the upper limit threshold voltage (V 3TH ) for the aCAM 603.

[0063] The fourth analog voltage signal (V(x-PL 1 / 2 / 3 )) supplied to the aCAM 604 may comprise an analog voltage signal representing a version of the digital input signal (x) corresponding to a total number of programmable levels of the aCAMs 601-603 (i.e., PL 1 / 2 / 3 ) is reduced. As described above, such signal conditioning is required to compensate for a difference between the programmable levels of the aCAM 603 (e.g. programmable levels (1) to (2 9 ), where “Q” represents the number of programmable bits for aCAM 604) and the representation levels assigned to aCAM 604 for storage (e.g. representation levels (2 M + 2 N + 2 P +1) to (2 M + 2 N + 2P +2 Q )). Therefore, the aCAM 604 only provides a match for the fourth analog voltage signal (V(x-PL 1 / 2 / 3 )) when the fourth analog voltage signal (V(x-PL 1 / 2 / 3 )) is within a programmed voltage range of the aCAM 604 - defined by the programmed conductances of the memristors that make up the aCAM 604 (i.e., the seventh and eighth memristors). For example, if the seventh memristor (of the aCAM 604) is programmed to have an open-circuit lower threshold voltage (V 4TL=„wildcard" ) for the aCAM 604, and the eighth memristor (of the aCAM 604) is programmed to set an open upper limit threshold voltage (V 4TH=„wildcard" ) for the aCAM 604, the aCAM 604 provides for virtually any value of the fourth analog voltage signal (V(x-PL 1 / 2 / 3 )) a match (ie for each value of the fourth analog voltage signal (V(x-PL 1 / 2 / 3)) within the low voltage limits defined by the seventh and eighth memristor).

[0064] As described above, the circuit 600 may receive a digital input signal (x) having an integer value between (1) and (2 M + 2 N + 2 P +2 Q ) (or an integer value between (0) and (2 M + 2 N + 2 P +2 Q - 1)) receive / process and search for this digital input signal (x) using analog voltage ranges that are representative over up to (2 M + 2 N + 2 P +2 Q) programmable levels / representation levels are stored. If the aCAMs 601-604 are each 2-bit aCAM cells (i.e., M=N=P=Q=2), this means that the circuit 600 can receive a digital input signal (x) that can have an integer value from (1) to (4*22 = 16), and search this digital input signal (x) against analog voltage ranges stored in up to (4*22=16) programmable / representation levels. In contrast, a conventional 2-bit aCAM cell could only receive / process a digital input signal (x) with an integer value between (1) and (4) and search this digital input signal (x) against analog voltage ranges stored across up to 4 programmable levels. Through range segmentation and strategic signal adjustments, the circuit can combine 600 commonly used aCAM cells to represent far more diverse analog voltage ranges than conventional aCAMs.In this way, circuit 600 can linearly increase accuracy with each aCAM cell / subcircuit added to the circuit (e.g., the number of programmable levels / representation levels that can be used to store a word entry and / or the number of programmable levels / representation levels by which an input signal can be searched). Accordingly, circuit 600 can perform more complex calculations than conventional aCAMs—and can therefore be used in a wider range of computing applications.

[0065] Fig.7 shows an example circuit 700 according to examples of the presently disclosed technique. Circuit 700 may be the same / similar to circuit 600, with digital-to-analog converters (DACs) 711-714 and controller 720 comprising signal conversion segment 620 of circuit 600. Controller 720 (which may be various types of controllers used to adjust digital or analog signals) is electrically connected to each of DACs 711-714 (DACs 711-714 may be various types of digital-to-analog converters used to convert digital signals to analog signals). The DAC 711 is electrically connected to the controller 720 and the aCAM 701, the DAC 712 is electrically connected to the controller 720 and the aCAM 702, the DAC 713 is electrically connected to the controller 720 and the aCAM 703, and the DAC 714 is electrically connected to the controller 720 and the aCAM 704. The specific example from Fig.Although FIG. 7 shows four DACs and four aCAM subcircuits, in other examples, circuit 700 may include two or more DACs, each electrically connected to two or more aCAM subcircuits (i.e., two or more DAC-aCAM subcircuit branches).

[0066] As shown, the controller 720 can perform the functions associated with Fig. 6 described signal adaptation in the digital domain. In particular, the control unit 720 converts a digital input signal (x) received by the circuit 700 into: (1) a first reduced digital signal (x-PL1) which is supplied to the DAC 712; (2) a second reduced digital signal (x-PL 1 / 2 ) which is fed to the DAC 713; and (3) a third reduced digital signal (x-PL 1 / 2 / 3 ), which is fed to the DAC 714. The controller 720 can feed an unadjusted version of the digital input signal (x) to the DAC 711.

[0067] As in connection with Fig. 6, the first reduced digital signal (x-PL1) may comprise a version of the digital input signal (x) reduced according to a number of programmable levels of aCAM 701 (i.e., PL1). The second reduced digital signal (x-PL 1 / 2 ) may comprise a version of the digital input signal (x) corresponding to a number of programmable levels of the aCAMs 701 and 702 (ie PL 1 / 2 ) is reduced. The third reduced digital signal (x-PL 1 / 2 / 3 ) may comprise a version of the digital input signal (x) corresponding to a number of programmable levels of the aCAMs 701-703 (ie PL 1 / 2 / 3 ) is reduced.

[0068] As shown, each DAC of circuit 700 converts the digital signal it receives into an analog voltage signal. The analog voltage signals from Fig. 7 can be used to analog voltage signals from Fig.6 be the same / similar and can be processed by the aCAMs 701-704 in the same / similar way.

[0069] In various examples, the controller 720 can be used to program the conductances of the memristors of the circuit 700 and thus also the upper and lower limit voltages of the aCAMs 701-704. In certain examples, such programming can transition the circuit 700 from a first (high-precision) operating mode, in which a (larger) analog voltage range is stored representatively across two or more aCAM subcircuits of the circuit 700, to a second (low-precision) operating mode, in which each aCAM subcircuit of the circuit 700 stores its own individual (small) analog voltage range. In the first (high-precision) operating mode, the (larger) analog voltage range can represent a word entry stored with high precision.In contrast, in the second operating mode (low precision), each of the individual (small) analog voltage ranges may represent individual word entries stored with a lower precision. Thus, in the first (high-precision) operating mode, the circuit 700 could store one word entry with high precision. In contrast, in the second operating mode (low precision), the circuit 700 could store four word entries with a lower precision. In this case, the controller 720 may only perform signal adjustments / reductions in the first (high-precision) operating mode. The controller 720 may automatically switch between the first (high-precision) operating mode and the second operating mode (low precision) depending on the type of calculations the circuit 700 is performing. For example, a complex calculation (e.g.Random forests), which require searching an input through a larger number of levels, may require operation in the first (high-precision) mode of operation. In contrast, a less complex computation may not require operation in the first (high-precision) mode of operation. Accordingly, circuit 700 can be better utilized for the less complex computation by storing / searching four word entries at the lower precision level.

[0070] Fig. 8 shows an example circuit 800 according to examples of the presently disclosed technique. Circuit 800 may be the same as / similar to circuit 600, with a digital-to-analog converter (i.e., DAC 810) and three subtractor subcircuits (i.e., SUBs 831-833) comprising signal conversion segment 620 of circuit 600.

[0071] In contrast to circuit 700, in which the signal conditioning is performed in the digital domain, the signal conditioning in circuit 800 is performed in the analog domain (i.e., after a digital input signal (x) has been converted into an analog voltage signal (V(x)) representing the digital input signal (x)). Furthermore, instead of a controller, circuit 800 uses subtractor subcircuits to perform signal conditioning (for further details, see, e.g., Fig. 9). By using subtractor subcircuits to perform signal conditioning in the analog domain, circuits of the present technique can use a single DAC, which is often complex to design and power and area intensive. A potential disadvantage is that this single DAC may require higher accuracy because it is used to convert more digital signals.

[0072] As in Fig.As shown in Figure 8, the DAC 810 is electrically connected to a first aCAM subcircuit (i.e., the aCAM 801) and a first subtractor subcircuit (i.e., the SUB 831). SUB 831 is electrically connected to the DAC 810, a second aCAM subcircuit (i.e., the aCAM 802), and a second subtractor subcircuit (i.e., the SUB 832). SUB 832 is electrically connected to SUB 831, a third aCAM subcircuit (i.e., the aCAM 803), and a third subtractor subcircuit (i.e., the SUB 833). SUB 833 is electrically connected to SUB 832 and a fourth aCAM subcircuit (i.e., the aCAM 804).

[0073] The DAC 810 can receive a digital input signal (x) and convert it into a first analog voltage signal (V(x)) that represents the digital input signal (x). The DAC 810 can then transmit the first analog voltage signal (V(x)) to the aCAM 801 and the SUB 831. The aCAM 801 can process the first analog voltage signal (V(x)) in the same / similar manner as described in connection with the Fig. 6-7 described.

[0074] The SUB 831 can convert the first analog voltage signal (V(x)) into a second analog voltage signal (V(x-PL1)), which can be defined in the same / similar way as in connection with Fig. 6. The SUB 831 can then transmit the second analog voltage signal (V(x-PL1)) to aCAM 802 and SUB 832. The aCAM 802 can process the second analog voltage signal (V(x-PL1)) in the same / similar manner as described in connection with the Fig. 6-7 described.

[0075] The SUB 832 can convert the second analog voltage signal (V(x-PL1)) into a third analog voltage signal (V(x-PL 1 / 2 ) which can be defined in the same / similar way as in the context of Fig. 6. The SUB 832 can output the third analog voltage signal (V(x-PL 1 / 2 ) is then transmitted to the aCAM 803 and the SUB 833. The aCAM 803 can receive the third analog voltage signal (V(x-PL 1 / 2 ) in the same / similar manner as in connection with the Fig. 6-7 described.

[0076] The SUB 833 can provide the third analog voltage signal (V(x-PL 1 / 2 ) into a fourth analog voltage signal (V(x-PL 1 / 2 / 3 ) which can be defined in the same / similar way as in the context of Fig. 6. The SUB 833 can then provide the fourth analog voltage signal (V(x-PL 1 / 2 / 3 ) to the aCAM 804.

[0077] The aCAM 804 can measure the fourth analog voltage signal (V(x-PL 1 / 2 / 3 ) in the same / similar manner as in connection with the Fig. 6-7 described.

[0078] Fig. 9 shows an example of a subtractor subcircuit 900 according to examples of the presently disclosed technique. The subtractor subcircuit 900 is based on a negative feedback operational amplifier, with an input voltage Vin applied to the negative input via a fixed resistor R. A reference voltage -V_ref is applied to the positive input via a fixed resistor R. The current flowing into the feedback resistor (also R) is equal to V_in / R - V_ref / R, and the output voltage is thus V_out = R(V_in / R - V_ref / R) = V_in - V_ref.

[0079] Fig.10 shows an example of a computer system 1000 that may be used to perform signal adjustments in accordance with various examples of the presently disclosed technique. In various examples, the computer system 1000 may be incorporated in the controller 520 of Fig. 5, in the signal conversion segment 620 from Fig. 6 and / or in the controller 720 Fig. 7. More generally, computer system 1000 may be implemented as part of a circuit described herein. As described above, such a circuit may include at least two aCAM subcircuits used in combination to represent and store an analog voltage range.

[0080] As in Fig. 10, the computer component 1010 may be, for example, a server computer, a controller, or other similar computer component that can process data. In the example embodiment of Fig.10, the computer component 1010 includes a hardware processor 1012 and a machine-readable storage medium 1014.

[0081] The hardware processor 1012 may be one or more central processing units (CPUs), semiconductor-based microprocessors, and / or other hardware devices capable of fetching and executing instructions stored in the machine-readable storage medium 1014. The hardware processor 1012 may fetch, decode, and execute instructions, such as instructions 1016-1020, to control processes or operations for burst preloading to estimate available bandwidth. Alternatively, or in addition to fetching and executing instructions, the hardware processor 1012 may include one or more electronic circuits containing electronic components for performing the functionality of one or more instructions, such as a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or other electronic circuitry.

[0082] A machine-readable storage medium, such as machine-readable storage medium 1014, may be any electronic, magnetic, optical, or other physical storage device that contains or stores executable instructions. For example, machine-readable storage medium 1014 may be random access memory (RAM), non-volatile RAM (NVRAM), electrically erasable programmable read-only memory (EEPROM), a storage device, an optical disk, or the like. In some examples, machine-readable storage medium 1014 may be a non-transitory storage medium, where the term "non-transitory" does not include transitory propagation indicators. As described in detail below, machine-readable storage medium 1014 may be encoded with executable instructions, for example, instructions 1016-1020.

[0083] As described above, computer system 1000 may be implemented as part of a circuit described in connection with the preceding FIGS. Such a circuit may include at least two aCAM subcircuits (i.e., at least a first aCAM subcircuit and a second aCAM subcircuit) used in combination to representatively store an analog voltage range. Within the circuit, the first aCAM subcircuit may have a first placement in an ordered representational level arrangement for the circuit, and the second aCAM subcircuit may have a second placement in the ordered representational level arrangement for the circuit. The circuit may also include digital-to-analog converters (DACs) (i.e., a first DAC and a second DAC) that convert digital signals to analog signals. Within the circuit, computer system 1000 may be electrically connected to the first and second DACs.The first DAC may be electrically connected to the first aCAM subcircuit, and the second DAC may be electrically connected to the second aCAM subcircuit. As described above and further explained below, the hardware processor 1012 / computer system 1000 may transmit a separate version of a received digital input signal (x) to the first and second DACs, respectively. Each DAC may then convert the digital signal it receives into an analog voltage signal and transmit the analog voltage signals to the first aCAM subcircuit and the second aCAM subcircuit, respectively, for processing.

[0084] As described above, the hardware processor 1012 may execute instruction 1016 to receive a digital input signal (x).

[0085] Hardware processor 1012 may execute instruction 1018 to convert digital input signal (x) into a reduced digital input signal (x-PL1). As described above, the reduced digital input signal (x-PL1) may comprise a version of digital signal (x) reduced according to a number of programmable levels of the first aCAM subcircuit.

[0086] The hardware processor 1012 may execute instruction 1020(a) to transmit the digital input signal (x) to the first DAC (which is electrically connected to the first aCAM subcircuit). Accordingly, the first DAC may convert the digital input signal (x) into a first analog voltage signal (V(x)) representing the digital input signal (x). Here, the hardware processor 1012 may transmit the digital input signal (x) to the first DAC / first aCAM subcircuit because the first aCAM subcircuit is the first in the ordered representation-level arrangement for the circuit in which the hardware processor 1012 / computer system 1000 is implemented.

[0087] The hardware processor 1012 may execute instruction 1020(b) to transfer the reduced digital input signal (x-PL1) to the second DAC (which is electrically connected to the second aCAM subcircuit). Accordingly, the second DAC may convert the reduced digital input signal (x-PL1) into a second analog voltage signal (V(x-PL1)) representing the reduced digital input signal (x-PL1). Here, the hardware processor 1012 may transfer the reduced digital input signal (x-PL1) to the second DAC / second aCAM subcircuit because the second aCAM subcircuit is the second in the ordered representation-level arrangement for the circuit in which the hardware processor 1012 / computer system 1000 is implemented.

[0088] After receiving the first analog voltage signal (V(x)) or the second analog voltage signal (V(x-PL1)), the first aCAM subcircuit and the second aCAM subcircuit can process the analog voltage signals in the same / similar manner as described in connection with the previous figures.

[0089] Fig. 11 shows a block diagram of an example computer system 1100 in which various examples described herein may be implemented. For example, the computer system 1100 may be configured to implement the controller 520 of Fig. 5, of the controller 720 Fig. 7, of the computer system 1000 Fig. 10 and / or as part of the signal conversion segment 620 from Fig. 6 can be used.

[0090] Computer system 1100 includes a bus 1112 or other communication mechanism for transmitting information, and one or more hardware processors 1104 connected to bus 1112 for processing information. For example, hardware processor(s) 1104 may be one or more general-purpose microprocessors.

[0091] Computer system 1100 also includes main memory 1106, such as random access memory (RAM), a cache, and / or other dynamic storage devices, connected to bus 1112 for storing information and instructions to be executed by processor 1104. Main memory 1106 may also be used to store temporary variables or other intermediate information during the execution of instructions to be executed by processor 1104. When such instructions are stored in storage media accessible to processor 1104, computer system 1100 becomes a special-purpose machine adapted to perform the operations specified in the instructions.

[0092] Computer system 1100 also includes a read-only memory (ROM) 908 or other static storage device connected to bus 1112 for storing static information and instructions for processor 1104. A storage device 1110, such as a magnetic disk, an optical disk, or a USB flash drive, etc., is provided and connected to bus 1112 for storing information and instructions.

[0093] Computer system 1100 may be connected to a display 1112, such as a liquid crystal display (LCD) (or a touch screen), via bus 1112 to display information to a computer user. An input device 1114, including alphanumeric and other keys, is coupled to bus 1112 to communicate information and command selections to processor 904. Another type of user input device is cursor control 1116, such as a mouse, trackball, or cursor direction keys, for communicating direction information and command selections to processor 904 and controlling cursor movement on display 1112. In some embodiments, the same direction information and command selections as with cursor control may be implemented via receiving touches on a touchscreen without a cursor.

[0094] Computer system 1100 may include a user interface module for implementing a graphical user interface, which may be stored on a mass storage device in the form of executable software code executed by the computing device(s). This and other modules may include, for example, components such as software components, object-oriented software components, class components and task components, processes, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables.

[0095] Generally, the term "component", "engine", "system", "database", "data store" and the like, as used herein, may refer to logic embodied in hardware or firmware, or to a collection of software instructions that may have entry and exit points and be written in a programming language such as Java, C, or C++. A software component may be compiled and linked into an executable program, installed in a dynamic link library, or written in an interpreted programming language such as BASIC, Perl, or Python. It is understood that software components may be callable by other components or by themselves, and / or may be called in response to detected events or interrupts. Software components configured to run on computing devices may be embodied on a computer-readable medium, such asa compact disc, digital video disc, flash drive, magnetic disk, or other tangible medium, or as a digital download (and may be originally stored in a compressed or installable format that must be installed, decompressed, or decrypted prior to execution). Such software code may be stored partially or entirely in a memory of the executing computing device for execution by the computing device. Software instructions may be embedded in firmware, such as an EPROM. In addition, the hardware components may consist of interconnected logic units such as gates and flip-flops and / or programmable units such as programmable gate arrays or processors.

[0096] Computer system 1100 may implement the techniques described herein using custom hard-wired logic, one or more ASICs or FPGAs, firmware, and / or program logic that, in combination with the computer system, makes or programs computer system 1100 into a special-purpose machine. According to one implementation, the techniques described herein are performed by computer system 1100 in response to processor(s) 904 executing one or more sequences of one or more instructions contained in main memory 906. Such instructions may be read into main memory 906 from another storage medium, such as storage device 1110. Execution of the instruction sequences contained in main memory 906 causes processor(s) 904 to perform the process steps described herein.In alternative implementations, hard-wired circuits may be used instead of or in combination with software instructions.

[0097] The term "non-transitory media" and similar terms as used herein refer to any media that stores data and / or instructions that cause a machine to operate in a particular manner. Such non-transitory media may include non-volatile media and / or volatile media. Examples of non-volatile media include optical or magnetic disks, such as storage device 1110. Volatile media includes dynamic memory, such as main memory 906. Common forms of non-volatile media include, for example, floppy disks, flexible disks, hard disks, solid-state drives, magnetic tape or other magnetic data storage media, CD-ROMs, other optical data storage media, physical media with hole patterns, RAM, PROM and EPROM, FLASH EPROM, NVRAM, other memory chips or cartridges, and networked versions thereof.

[0098] Non-transitory media are distinct from transmission media but can be used in conjunction with them. Transmission media are involved in the transfer of information between non-transitory media. Examples of transmission media include coaxial cable, copper wire, and fiber optic cable, including the wires that make up bus 1112. Transmission media can also take the form of sound or light waves, such as those generated in data communications via radio and infrared.

[0099] Computer system 1100 also includes a communications interface 1118 connected to bus 1112. Network interface 1118 establishes a two-way data communications connection to one or more network connections connected to one or more local area networks. For example, communications interface 1118 may be an Integrated Services Digital Network (ISDN) card, a cable modem, a satellite modem, or a modem for establishing a data communications connection to a corresponding type of telephone line. As another example, network interface 1118 may be a Local Area Network (LAN) card for establishing a data communications connection to a compatible LAN (or a WAN component for communicating with a WAN). Wireless connections may also be implemented.In each of these embodiments, the network interface 1118 sends and receives electrical, electromagnetic, or optical indicators that carry digital data streams containing various types of information.

[0100] A network connection typically enables data communication over one or more networks to other data devices. For example, a network connection may establish a connection over a local area network to a host computer or data devices operated by an Internet service provider (ISP). The ISP, in turn, provides data communication services over the worldwide packet data communication network, now commonly referred to as the "Internet." Both the local area network and the Internet use electrical, electromagnetic, or optical indicators that transmit digital data streams. The indicators in the various networks and the indicators in the network connection and in the communication interface 1118 that transmit the digital data to and from the computer system 1100 are examples of transmission media.

[0101] Computer system 1100 can send messages and receive data, including program code, over the network(s), the network connection, and the communications interface 1118. Using the Internet as an example, a server could transmit requested code for an application program over the Internet, the ISP, the local area network, and the communications interface 1118.

[0102] The received code may be executed by processor 904 upon receipt and / or stored in storage device 1110 or other non-volatile memory for later execution.

[0103] All of the processes, methods, and algorithms described in the preceding sections may each be embodied in code components executed by, and fully or partially automated by, one or more computer systems or computer processors comprising computer hardware. The one or more computer systems or computer processors may also be operated to support the performance of the corresponding operations in a cloud computing environment or as software as a service (SaaS). The processes and algorithms may be partially or fully implemented in application-specific circuitry. The various features and methods described above may be used independently of one another or combined in various ways.Various combinations and subcombinations are intended to be within the scope of this disclosure, and certain method or process blocks may be omitted in some implementations. The methods and processes described herein are also not limited to any particular order, and the associated blocks or states may be executed in other suitable orders, in parallel, or otherwise. Blocks or states may be added to or removed from the disclosed examples. The execution of certain operations or processes may be distributed among computer systems or computer processors located not only on a single machine, but across a number of machines.

[0104] As used herein, a circuit may be implemented in any form of hardware, software, or a combination thereof. For example, one or more processors, controllers, ASICs, PLAs, PALs, CPLDs, FPGAs, logic components, software routines, or other mechanisms may be implemented to form a circuit. In implementation, the various circuits described herein may be implemented as discrete circuits, or the described functions and features may be distributed, in part or in whole, among one or more circuits. Even though various features or functional elements are individually described or claimed as separate circuits, those features and functions may be shared by one or more common circuits, and such description is not intended to assume or imply that separate circuits are required to implement those features or functions.If a circuit is implemented in whole or in part with software, that software may be implemented to operate with a computer or processing system capable of performing the described functionality, such as computer system 1100.

[0105] As used here, a dataset can refer to an ordered collection of data. As described above, a dataset can be a data-related product of a data processing pipeline.

[0106] As used here, data analytics (which may be implemented using machine learning and / or artificial intelligence) can refer to techniques that make predictive statements, e.g., about modeled scenarios and systems. As described above, analytics models derived from data are common data-related products of data processing pipelines.

[0107] The term machine learning used here can refer to processes that, through the use of algorithms, are capable of automatically transforming data sets into analytical models. These analytical models, in turn, are capable of making predictions based on patterns or inferences derived from other data / data sets. The implementation of machine learning in enterprise environments, e.g., in companies, has been promoted so that these institutions can use machine learning to offer their customers better services and products, make their operations more efficient, etc. The implementation of machine learning in an enterprise context, also known as operationalization, can involve the deployment (and management) of analytical models, i.e., the introduction of analytical models into production.

[0108] As used here, metadata can refer to data that provides information about other data. Within a data processing pipeline, each data-related product and each processing step can be associated with metadata. Metadata for a dataset can include, for example, textual documentation for the dataset, names of tables / columns / features within the dataset, descriptions of content contained within the dataset, data sizes within the dataset, data distributions within the dataset, etc.Examples of metadata for a processing step might include the language in which the processing step / program is written, information about the input fields used for the processing step, the contents of the associated documentation for the processing step, the class of the algorithm used for the processing step, the staging or quality assurance (QA) status for the processing step, the names of the developers / data scientists involved in the processing step, etc.

Claims

[1] A circuit (600) comprising: a first aCAM subcircuit (601) electrically connected to a match line; and a second aCAM subcircuit (602) electrically connected to the match line; where the circuit when receiving a digital input signal (x): converting the digital input signal (x) into a first analog voltage signal (V(x)) and a second analog voltage signal (V(x-PL1)), wherein the first analog voltage signal (V(x)) is received by the first aCAM subcircuit and the second analog voltage signal (V(x-PL1)) is received by the second aCAM subcircuit, wherein: the first analog voltage signal (V(x)) is an analog voltage signal representing the digital input signal (x), and the second analog voltage signal (V(x-PL1)) is an analog voltage signal representing a version of the digital input signal (x) reduced according to a number of programmable levels of the first aCAM subcircuit; and only provides a match along the match line if the first analog voltage signal (V(x)) is within a programmed voltage range of the first aCAM subcircuit and the second analog voltage signal (V(x-PL1)) is within a programmed voltage range of the second aCAM subcircuit. [2] A circuit according to claim 1, wherein: the first aCAM subcircuit comprises a first memristor and a second memristor; the second aCAM subcircuit comprises a third memristor and a fourth memristor and the first four memristors each have (M) programmable bits, wherein the (M) programmable bits of a given memristor are programmed by tuning the conductance of the given memristor. [3] Circuit according to claim 2, wherein the circuit comprises at least 2*2 M programmable levels for representatively storing an analog voltage range across at least the first aCAM subcircuit and the second aCAM subcircuit. [4] The circuit of claim 2, wherein an analog voltage range representatively stored across at least the first aCAM subcircuit and the second aCAM subcircuit represents an entry of a word. [5] A circuit according to claim 4, wherein: the first memristor is programmed to provide a lower threshold voltage (V 1TL ) for the first aCAM subcircuit; and the lower limit threshold voltage (V 1TL) of the first aCAM subcircuit sets a representative lower limit for the analog voltage range which is stored representatively at least across the first aCAM subcircuit and the second aCAM subcircuit. [6] A circuit according to claim 5, wherein: the second memristor is programmed to provide an upper limit threshold voltage (V 1TH=„wildcard" ) for the first aCAM subcircuit such that the first aCAM subcircuit provides a match along the match line when the first analog voltage signal (V(x)) received by the first aCAM subcircuit is greater than or equal to the lower limit threshold voltage (V 1TL ) of the first aCAM subcircuit and less than or equal to the upper limit threshold voltage (V 1TH=„wildcard" ) is. [7] A circuit according to claim 2, further comprising: a third aCAM subcircuit (603) electrically connected to the match line; and a fourth aCAM subcircuit (604) electrically connected to the match line; where the circuit upon receiving the digital input signal (x): the digital input signal (x) into the first analog voltage signal (V(x)), the second analog voltage signal (V(x-PL1)), a third analog voltage signal (V(x-PL 1 / 2 )) and a fourth analog voltage signal (V(x-PL 1 / 2 / 3 ), wherein the first analog voltage signal (V(x)) is received by the first aCAM subcircuit, the second analog voltage signal V(x-PL1) is received by the second aCAM subcircuit, the third analog voltage signal V(x-PL 1 / 2 ) is received by the third aCAM subcircuit and the fourth analog voltage signal V(x-PL 1 / 2 / 3 ) is received by the fourth aCAM subcircuit, where: the third analog voltage signal (V(x-PL 1 / 2)) is an analog voltage signal representing the digital input signal (x) reduced according to a total number of programmable levels for the first and second aCAM subcircuits, and the fourth analog voltage signal (V(x-PL 1 / 2 / 3 )) is an analog voltage signal representing a version of the digital input signal (x) reduced according to a total number of programmable levels for the first to third aCAM subcircuits; and only provides a match along the match line if the first analog voltage signal (V(x)) is within a programmed voltage range of the first aCAM subcircuit and the second analog voltage signal (V(x-PL1)) is within a programmed voltage range of the second aCAM subcircuit and the third analog voltage signal (V(x-PL 1 / 2)) is within a programmed voltage range of the third aCAM subcircuit and the fourth analog voltage signal (V(x-PL 1 / 2 / 3 )) is within a programmed voltage range of the fourth aCAM subcircuit. [8] A circuit according to claim 7, wherein: the third aCAM subcircuit comprises a fifth memristor and a sixth memristor; the fourth aCAM subcircuit comprises a seventh memristor and an eighth memristor and the first to eighth memristor each have (M) programmable bits, wherein the (M) programmable bits of a given memristor are programmed by tuning the conductance of the given memristor. [9] Circuit according to claim 8, wherein the circuit comprises at least 4*2 M programmable levels for representatively storing an analog voltage range across at least two of the first to fourth aCAM subcircuits. [10] A circuit according to claim 8, wherein: an analog voltage is stored representatively across the first to third aCAM subcircuits; the sixth memristor is programmed to provide an upper limit threshold voltage (V 3TH ) for the third aCAM subcircuit; the upper limit threshold voltage (V 3TH ) sets a representative upper limit of the analog voltage range for the third aCAM subcircuit, which is stored representatively across the first to third aCAM subcircuits; and the fifth memristor is programmed to provide an open lower limit threshold voltage (V 3TL=„wildcard" ) for the third aCAM subcircuit, so that the third aCAM subcircuit always provides a match along the match line when the third analog voltage signal (V(x-PL 1 / 2)) received by the third aCAM subcircuit is less than or equal to the upper limit threshold voltage (V 3TH ) for the third aCAM subcircuit. [11] A circuit according to claim 10, wherein: the third memristor is programmed to provide an open lower limit threshold voltage (V 2TL=„wildcard" ) for the second aCAM subcircuit, and the fourth memristor is programmed to set an open upper limit threshold voltage (V 2TH=„wildcard" ) for the second aCAM subcircuit such that the second aCAM subcircuit provides a match along the match line for each value of the second analog voltage signal (V(x-PL1)); and the seventh memristor is programmed to provide an open lower limit threshold voltage (V 4TL=„wildcard" ) for the fourth aCAM subcircuit, and the eighth memristor is programmed to set an open upper limit threshold voltage (V 4TH=„wildcard") for the fourth aCAM subcircuit, so that the fourth aCAM subcircuit sets a match along the match line for each value of the fourth analog voltage signal (V(x- PL 1 / 2 / 3)) delivers. [12] A circuit (700) comprising: a controller (720); a first digital-to-analog converter (711) electrically connected to the controller and a first aCAM subcircuit (701); a second digital-to-analog converter (712) electrically connected to the controller and a second aCAM subcircuit (702); wherein the first aCAM subcircuit is electrically connected to the first digital-to-analog converter and a match line, and the second aCAM subcircuit is electrically connected to the second digital-to-analog converter and the match line; where when receiving a digital input signal (x): the controller transmits the digital input signal (x) to the first digital-to-analog converter and transmits a reduced digital input signal (x-PL1) to the second digital-to-analog converter, wherein the reduced digital input signal (x-PL1) comprises a version of the digital input signal (x) reduced according to a number of programmable levels for the first aCAM subcircuit; the first digital-to-analog converter converts the digital input signal (x) into a first analog voltage signal (V(x)) representing the digital input signal (x) and transmits the first analog voltage signal (V(x)) to the first aCAM subcircuit; the second digital-to-analog converter converts the reduced digital input signal (x-PL1) into a second analog voltage signal (V(x-PL1)) representing the reduced digital input signal (x-PL1) and transmits the second analog voltage signal (V(x-PL1)) to the second aCAM subcircuit, the circuit provides a match if the first analog voltage signal (V(x)) is within a programmed voltage range of the first aCAM subcircuit and the second analog voltage signal (V(x-PL1)) is within a programmed voltage range of the second aCAM subcircuit. [13] A circuit according to claim 12, wherein: the first aCAM subcircuit comprises a first memristor and a second memristor; the second aCAM subcircuit comprises a third memristor and a fourth memristor and the first to fourth memristor each have (M) programmable bits, wherein the (M) programmable bits of a given memristor are programmed by tuning the conductance of the given memristor. [14] Circuit according to claim 13, wherein the circuit comprises at least 2*2 Mprogrammable levels for representatively storing an analog voltage range across at least the first and second aCAM subcircuits. [15] The circuit of claim 13, wherein an analog voltage range representatively stored across at least the first and second aCAM subcircuits represents an entry of a word. [16] A circuit (800) comprising: a digital-to-analog converter (810) electrically connected to a first aCAM subcircuit (801) and a first subtractor subcircuit (831); wherein the first subtractor subcircuit is electrically connected to the digital-to-analog converter and a second aCAM subcircuit (802); the first aCAM subcircuit is electrically connected to the digital-to-analog converter and a match line, and the second aCAM subcircuit is electrically connected to the first subtractor subcircuit and the match line; where when receiving a digital input signal (x): the digital-to-analog converter: converts the digital input signal (x) into a first analog voltage signal (V(x)) representing the digital input signal (x), and transmits the first analog voltage signal (V(x)) to the first aCAM subcircuit and the first subtractor subcircuit; the first subtractor subcircuit: converting the first analog voltage signal (V(x)) into a second analog voltage signal (V(x-PL1)) representing a version of the digital input signal (x) reduced according to a number of programmable levels for the first aCAM subcircuit, and transmits the second analog voltage signal (V(x-PL1)) to the second aCAM subcircuit, and the circuit provides a match if the first analog voltage signal (V(x)) is within a programmed voltage range of the first aCAM subcircuit and the second analog voltage signal (V(x-PL1)) is within a programmed voltage range of the second aCAM subcircuit. [17] A circuit according to claim 16, further comprising: a second subtractor subcircuit (832) electrically connected to the first subtractor subcircuit, a third subtractor subcircuit (833) and a third aCAM subcircuit (803); wherein the third subtractor subcircuit is electrically connected to the second subtractor subcircuit and a fourth aCAM subcircuit (804); the third aCAM subcircuit is electrically connected to the second subtractor subcircuit and the match line, and the fourth aCAM subcircuit is electrically connected to the third subtractor subcircuit and the match line; where when receiving the digital input signal (x): the first subtractor subcircuit: converts the first analog voltage signal (V(x)) into the second analog voltage signal (V(x-PL1)) representing the version of the digital input signal (x) reduced according to the number of programmable levels for the first aCAM subcircuit, and transmits the second analog voltage signal (V(x-PL1)) to the second aCAM subcircuit and the second subtractor subcircuit, the second subtractor subcircuit: the second analog voltage signal (V(x-PL1)) into a third analog voltage signal (V(x-PL 1 / 2)) representing a version of the digital input signal (x) reduced according to a total number of programmable levels for the first and second aCAM subcircuits, and the third analog voltage signal V(x-PL 1 / 2 ) to the third aCAM subcircuit and the third subtractor subcircuit, the third subtractor subcircuit: the third analog voltage signal (V(x-PL 1 / 2 )) into a fourth analog voltage signal (V(x-PL 1 / 2 / 3 )) representing a version of the digital input signal (x) reduced according to a total number of programmable levels for the first to third aCAM subcircuits, and the fourth analog voltage signal (V(x-PL 1 / 2 / 3 )) to the fourth aCAM subcircuit, and the circuit only provides a match if the first analog voltage signal (V(x)) is within a programmed voltage range of the first aCAM subcircuit and the second analog voltage signal (V(x-PL1)) is within a programmed voltage range of the second aCAM subcircuit and the third analog voltage signal (V(x-PL 1 / 2 )) is within a programmed voltage range of the third aCAM subcircuit and the fourth analog voltage signal (V(x-PL 1 / 2 / 3 )) is within a programmed voltage range of the fourth aCAM subcircuit. [18] A circuit according to claim 17, wherein: the first aCAM subcircuit comprises a first memristor and a second memristor; the second aCAM subcircuit comprises a third memristor and a fourth memristor; the third aCAM subcircuit comprises a fifth memristor and a sixth memristor; the fourth aCAM subcircuit comprises a seventh memristor and an eighth memristor and the first to eighth memristor each have (M) programmable bits, wherein the (M) programmable bits of a given memristor are programmed by tuning the conductance of the given memristor. [19] Circuit according to claim 18, wherein the circuit comprises at least 4*2 M programmable levels for representatively storing an analog voltage range across at least two of the first to fourth aCAM subcircuits. [20] The circuit of claim 18, wherein an analog voltage range representatively stored across at least two of the first to fourth aCAM subcircuits represents an entry of a word.

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