Semiconductor devices with embedded filler particles and associated manufacturing processes

Abstract

Semiconductor device, comprising: a chip carrier (2); a semiconductor chip (4) arranged on the chip carrier (2); an intermediate layer (16) arranged between the chip carrier (2) and the semiconductor chip (4); an encapsulation material (12) that at least partially encapsulates the semiconductor chip (4); and Filler particles (18) embedded in the intermediate layer (16), wherein the filler particles (18) are homogeneously and completely distributed over the entire intermediate layer (16), and wherein the filler particles (18) comprise a semiconductor material with a band gap in a range of 2.3 eV to 3.6 eV.

Description

Technical field

[0001] The present disclosure relates to semiconductor devices with embedded filler particles and associated manufacturing processes. background

[0002] High electrical voltage differences can occur between individual components in semiconductor devices during operation. For example, increased electrical potential differences can arise in a current sensor between a busbar and a sensor chip positioned above it. Depending on material properties and the relative arrangement of the device components, these increased voltage differences can lead to extremely high electric field strengths in certain areas of the device. Device components located in these areas can be subject to wear due to the high electric field strengths, which in the worst case can lead to device failure. Manufacturers and developers of semiconductor devices are constantly striving to improve their products. Extending the lifespan of the devices and ensuring their continuous, reliable operation can be of particular interest.

[0003] Publication US 2021 / 0057298A1 relates to a semiconductor device with a semiconductor chip embedded in an encapsulation material. The encapsulation material contains a base material with embedded filler particles. Publication JP 2021-52195A relates to a semiconductor device with a single-polarity logic circuit. Publication US 2013 / 0062789A1 relates to a method for filling a gap area with filler particles. Publication DE 102018109013A1 relates to a semiconductor arrangement with a molding compound. The molding compound contains a matrix and a filler with filler particles. Brief description

[0004] Several aspects pertain to a semiconductor device. The semiconductor device comprises a chip carrier and a semiconductor chip arranged on the chip carrier. The semiconductor device further comprises an intermediate layer arranged between the chip carrier and the semiconductor chip, and an encapsulation material that at least partially encapsulates the semiconductor chip. The semiconductor device also includes filler particles embedded in the intermediate layer. The filler particles are homogeneous and completely distributed throughout the entire intermediate layer. The filler particles comprise a semiconductor material with a band gap in the range of 2.3 eV to 3.6 eV.

[0005] Several aspects pertain to a semiconductor device. The semiconductor device comprises a chip carrier and a semiconductor chip arranged on the chip carrier. The semiconductor device further comprises an intermediate layer arranged between the chip carrier and the semiconductor chip, and an encapsulation material that at least partially encapsulates the semiconductor chip. The semiconductor device also comprises filler particles embedded in the intermediate layer. The filler particles are designed to reduce the electrical conductivity of the intermediate layer to a range of 10 when the electric field strength increases to a value greater than 5 V / µm. -16 S / m up to 10 -2 S / m to increase. The filler particles are homogeneous and completely distributed over the entire intermediate layer.

[0006] Several aspects concern a semiconductor device. The semiconductor device comprises a chip carrier and a semiconductor chip arranged on the chip carrier. The semiconductor device further comprises an intermediate layer arranged between the chip carrier and the semiconductor chip and an encapsulation material that at least partially encapsulates the semiconductor chip. The semiconductor device further comprises filler particles embedded in the encapsulation material, wherein the filler particles are made of a semiconductor material with a band gap in the range of 2.3 eV to 3.6 eV, and wherein the filler particles are designed to reduce the electrical conductivity of the encapsulation material to a range of 10 when the electric field strength increases to a value greater than 5 V / µm. -16 S / m up to 10 -2 to increase S / m, and wherein the filler particles have maximum dimensions in a range of about 30 pm to about 100 µm.

[0007] Several aspects relate to a method for fabricating a semiconductor device. The method comprises placing an interlayer on a chip substrate and placing a semiconductor chip on the interlayer. The method further comprises encapsulating the semiconductor chip with an encapsulation material. Filler particles are embedded in the interlayer. The filler particles comprise a semiconductor material with a band gap in the range of 2.3 eV to 3.6 eV. The filler particles are homogeneously and completely distributed over the entire interlayer (16).

[0008] Several aspects concern a method for manufacturing a semiconductor device. The method includes placing an interlayer on a chip substrate and placing a semiconductor chip on the interlayer. The method further includes encapsulating the semiconductor chip with an encapsulation material. Filler particles are embedded in the interlayer. The filler particles are designed to reduce the electrical conductivity of the interlayer to a range of 10 when the electric field strength increases to a value greater than 5 V / µm. -16 S / m up to 10 -2 S / m to increase. The filler particles are homogeneous and completely distributed over the entire intermediate layer.

[0009] Several aspects concern a method for manufacturing a semiconductor device. The method comprises placing an interlayer on a chip substrate and placing a semiconductor chip on the interlayer. The method further comprises encapsulating the semiconductor chip with an encapsulation material, wherein filler particles are embedded in the encapsulation material. These filler particles are made of a semiconductor material with a band gap in the range of 2.3 eV to 3.6 eV, and are designed to reduce the electrical conductivity of the encapsulation material to a range of 10 when the electric field strength increases to a value greater than 5 V / µm. -16 S / m up to 10 -2 to increase S / m, and wherein the filler particles have maximum dimensions in a range of about 30 µm to about 100 µm. Brief description of the drawings

[0010] Devices and methods according to the disclosure are explained in more detail below with reference to the drawings. The elements shown in the drawings are not necessarily drawn to scale relative to one another. Identical reference numerals may denote identical components. Fig. Figure 1 schematically shows a perspective view of a semiconductor device 100. Fig. Figure 2 schematically shows a cross-sectional side view of a semiconductor device 200 as well as field lines of an electric field occurring in the semiconductor device 200. Fig. Figure 3 schematically shows a cross-sectional side view of a semiconductor device 300 according to the disclosure. Fig. Figure 4 schematically shows a cross-sectional side view of a semiconductor device 400 according to the disclosure. Fig. Figure 5 schematically shows a cross-sectional side view of a semiconductor device 500 according to the disclosure. Fig. Figure 6 shows a flowchart of a process for manufacturing a semiconductor device according to the disclosure. Fig. Figure 7 shows a flowchart of a process for manufacturing a semiconductor device according to the disclosure. Fig. Figure 8 illustrates the electrical conductivities of a material containing embedded silicon carbide filler particles as a function of an electric field. The electrical conductivities of the material are shown for different weight percentages of the filler particles. Fig. Figure 9 illustrates electric current densities in a material containing embedded zinc oxide filler particles as a function of an electric field. The electric current densities are shown for different weight percentages of the filler particles. Fig. Figure 10 illustrates electric current densities in different materials containing embedded zinc oxide filler particles as a function of an electric field. The electric current densities are shown for different sizes and shapes of the filler particles. Detailed description

[0011] The following description refers to the accompanying drawings. The drawings illustrate specific embodiments in which the present disclosure can be implemented in practice by way of example. The following detailed description is not to be understood in a limiting sense.

[0012] The Fig. 1 and Fig. 2 and its description are intended to qualitatively and exemplarily illustrate a technical problem underlying the present disclosure. However, the present disclosure is not limited to the problems described in the Fig. 1 and Fig. limited to the two device types shown.

[0013] The semiconductor device 100 of the Fig. 1 can have a chip carrier 2 and a semiconductor chip 4 arranged above it. The semiconductor chip 4 can, for example, be a magnetic field sensor chip with at least one sensor element. In the specific example of the Fig. 1 The semiconductor chip 4 can correspond to a differential magnetic field sensor chip with two Hall sensor elements 6A, 6B.

[0014] The electrically conductive chip carrier 2 can function as a current rail and be designed to carry an electrical measuring current 8. In the example shown, the chip carrier 2, or the current rail it forms, can have two indentations, allowing the measuring current 8 to follow an S-shaped path around the two sensor elements 6A and 6B. The measuring current 8 can induce a magnetic field at the locations of the sensor elements 6A and 6B. The semiconductor chip 4 can be designed to detect the induced magnetic field at the positions of the sensor elements 6A and 6B. Based on the detected magnetic field (or based on an associated differential measurement signal), the magnitude of the measuring current 8 can be determined. For this reason, the semiconductor chip 4 or the semiconductor device 100 can also be referred to as a current sensor.

[0015] The semiconductor device 200 of the Fig. 2 can be one or more features of the semiconductor device 100 of the Fig. The semiconductor device 200 can include a chip carrier 2 and a semiconductor chip 4 arranged above the chip carrier 2. A stack of dielectric layers 10 can be arranged between the chip carrier 2 and the semiconductor chip 4. In the example shown, the layer stack can have two dielectric layers 10A, 10B. The device components mentioned can be at least partially encapsulated by an encapsulation material 12.

[0016] During operation of the semiconductor device 200, large electrical potential differences can occur between the chip carrier 2 and the semiconductor chip 4. For example, such voltage differences can reach values ​​exceeding 1000 volts. Galvanic isolation between the chip carrier 2 and the semiconductor chip 4 can be provided by the dielectric layers 10A, 10B arranged between them. Since the dielectric layers 10A, 10B exhibit electrical insulating properties, high electric field strengths can build up in certain spatial regions of the semiconductor device 200. Fig. Figure 2 illustrates an electric field occurring within the semiconductor device 200 by electric field lines.

[0017] In the case shown, for example, a concentration of electric field lines can occur in a (spatial) region 14 where the semiconductor chip 4, the encapsulation material 12, and the upper dielectric layer 10B are adjacent. In other words, comparatively high electric field strengths can occur in region 14. Materials located in region 14 can be subjected to considerable stress due to these high electric field strengths, which can be particularly problematic for materials with limited insulating properties. For example, an adhesive layer based on epoxy, silicone, or acrylate located between the top surface of the upper dielectric layer 10B and the bottom surface of the semiconductor chip 4 may not necessarily be designed for strong electrical insulation.The described stress can then lead to accelerated aging of the materials, which can result in unwanted electrical discharges within the device and, in the worst case, a failure of the device.

[0018] The following describes exemplary semiconductor devices according to the disclosure, as well as methods for manufacturing such semiconductor devices. These semiconductor devices can provide reduced internal electric field strengths and thus contribute, at least partially, to solving the previously described technical problem.

[0019] The semiconductor device 300 of the Fig. 3 can have one or more features of previously described semiconductor devices. The semiconductor device 300 can have a chip carrier 2 and a semiconductor chip 4 arranged on the chip carrier 2. An intermediate layer 16 can be arranged between the chip carrier 2 and the semiconductor chip 4. In the example shown, the intermediate layer 16 can have one or more dielectric layers 26. Filler particles 18 can be embedded in the intermediate layer 16. The aforementioned device components can be at least partially encapsulated by an encapsulation material 12.

[0020] The filler particles 18 can contain or be made of a semiconductor material with a band gap in the range of approximately 2.3 eV to approximately 3.6 eV. In this context, the filler particles 18 can, for example, contain at least one of zinc oxide or silicon carbide.

[0021] The electrical conductivity of the intermediate layer 16 can depend on and be adjusted according to the content of filler particles 18 in the intermediate layer 16. Generally, the proportion of filler particles 18 in the intermediate layer 16 can range from approximately 1 wt% to approximately 99 wt%. Preferably, the proportion of filler particles 18 in the intermediate layer 16 can range from approximately 15 wt% to approximately 60 wt%. In other examples, the proportion of filler particles 18 in the intermediate layer 16 can be selected differently. In these cases, the proportion can lie within a range with a lower limit and an upper limit, where the lower limit can be approximately 5, 10, 15, 20, 25, or 30 wt% and the upper limit approximately 50, 60, 70, 80, or 90 wt%.

[0022] The electrical conductivity of the intermediate layer 16 can also depend on and be adjusted according to the maximum dimensions of the filler particles 18. For example, with substantially spherical filler particles 18, a maximum dimension can correspond to a maximum diameter of the filler particles 18. In general, the filler particles 18 can have maximum dimensions in a range of approximately 1 µm to approximately 300 µm. Preferably, the filler particles can have maximum dimensions in a range of approximately 30 µm to approximately 100 µm. In other examples, the maximum dimensions of the filler particles 18 can also be selected differently. The maximum dimensions can lie within a range with a lower limit and an upper limit, where the lower limit can be approximately 10, 20, 30, 40, or 50 µm and the upper limit approximately 75, 100, 150, 200, or 250 µm.

[0023] The filler particles 18 can generally have any geometric shape. In a preferred example, the filler particles 18 can be essentially spherical. In other examples, the filler particles 18 can be irregularly shaped.

[0024] The filler particles 18 can be designed to increase the electrical conductivity of the intermediate layer 16 to a range of approximately 10 when the electric field strength increases to a value of more than about 5 V / µm. -16 S / m up to about 10 -2 to increase S / m. Preferably, the filler particles 18 can be designed to increase the electrical conductivity of the intermediate layer 16 to a range of approximately 10 when the electric field strength increases in this way. -12 S / m up to about 10 -6to increase S / m. In other examples, the values ​​mentioned can be chosen differently. The previously given exemplary value of the electric field strength of more than approximately 5 V / µm can be replaced in other examples by a value of more than approximately 6, 7, 8, 9, or 10 V / µm. Furthermore, the electrical conductivity of the intermediate layer 16 can be increased to a range with a lower limit and an upper limit, where the lower limit can assume a value of approximately 10 -16 , 10 -15 , 10 -11 , 10 -11 , 10 -12 , 10 -11 , 10 -10 or 10 -9 S / m and the upper limit can assume a value of approximately 10 -7 , 10 -6 , 10 -5 , 10 -4 , 10 -3 or 10 -2 S / m. In the Fig. 8, Fig. 9 to Fig. Figure 10 shows exemplary electrical conductivities of materials with embedded filler particles as a function of electric field strengths. However, it should be noted that the present disclosure is not limited to the values ​​given therein.

[0025] In the example shown, the filler particles 18 can be embedded in the dielectric layer 26 or in a stack of several dielectric layers. The dielectric layer 26 can be designed to provide galvanic isolation between the chip carrier 2 and the semiconductor chip 4. In one example, the dielectric layer 26 can contain or be made of an inorganic material. The inorganic material can, for example, comprise at least one component of a glass or ceramic material. Alternatively or additionally, the dielectric layer 26 can contain or be made of an organic material. The organic material can, for example, comprise at least one component of a polymer, a polyimide, an epoxy, or a silicone.

[0026] The chip carrier 2 is not limited to a specific carrier type. In particular, the chip carrier 2 can be made at least partially of an electrically conductive material, so that galvanic isolation between the chip carrier 2 and the semiconductor chip 4 may be necessary. In the example shown, the chip carrier 2 can be a lead frame, which can be made at least partially of a metal or a metal alloy. The lead frame can have one or more die pads 20 and one or more leads 22. In the side view of the Fig. 3. Further connection conductors can be arranged behind and concealed by the illustrated connection conductors 22. The semiconductor chip 4 can be mounted on the top of the die pad 20. The conductor frame or the die pad 20 can be designed as a busbar, as already mentioned in connection with the Fig. 1 described.

[0027] The encapsulation material 12 can contain or be made of an electrically insulating material. One or more components of the semiconductor device 300 can be encapsulated by the encapsulation material 12 and thereby protected against external influences, such as moisture or mechanical shocks. The encapsulation material 12 can form a housing, so that the semiconductor device 300 can also be referred to as a semiconductor housing or semiconductor package. The encapsulation material 12 can comprise at least one of a mold compound, an epoxy, an imide, a thermoplastic, a thermosetting polymer, a polymer mixture, a glob-top material, a laminate, etc.Various techniques can be used to manufacture the housing formed by the encapsulation material 12, for example at least one of compression molding, injection molding, powder molding, liquid molding, map molding, lamination, etc.

[0028] In addition to the components already mentioned, the semiconductor device 300 can optionally have one or more electrical connecting elements (e.g., bond wires) 28 that can electrically connect the semiconductor chip 4 to the connecting conductors 22. The connecting conductors 22 can be at least partially uncovered by the encapsulation material 12, so that the semiconductor chip 4 can be electrically contacted from outside the housing.

[0029] As already mentioned in connection with the Fig. As described in Figure 2, during operation of the semiconductor device 300, electrical voltage differences occurring between the chip carrier 2 and the semiconductor chip 4 can lead to locally increased electric field strengths within the semiconductor device 300. The filler particles 18 can be designed to at least partially reduce these increased electric field strengths. Due to the increased electrical conductivity of the intermediate layer 16 caused by the filler particles 18, a localized displacement of charge carriers can occur in the intermediate layer 16 or at the positions of the filler particles 18. This displacement of charge carriers can at least partially reduce the aforementioned voltage differences and the resulting increased electric field strengths in the corresponding spatial regions. The displacement of charge carriers can establish a new equilibrium in which previously dense electric field lines are diluted.

[0030] In this context, it should be noted that the previously described charge carrier displacement does not necessarily affect, nor can it affect, the fundamental insulating properties of the intermediate layer 16. This means that, despite the charge carrier displacement, the intermediate layer 16, or rather the dielectric layer 26, can still act as a dielectric and provide sufficient galvanic isolation between the chip carrier 2 and the semiconductor chip 4. While the electrical conductivity of the intermediate layer 16 can be increased by the filler particles 18 at sufficiently high electric field strengths, it can still be several orders of magnitude lower than the electrical conductivity of an electrical conductor, which is typically above 10 6S / m can be located. Therefore, the charge carrier displacement cannot, for example, bridge an insulation path provided by the intermediate layer 16 between the chip carrier 2 and the semiconductor chip 4. Furthermore, the charge carrier displacement cannot lead to undesired electrical currents occurring within the semiconductor device 300.

[0031] As previously described, the electric field strength can be reduced, particularly at certain positions of the filler particles 18, by using the filler particles 18. The filler particles 18 can therefore preferably be arranged in a spatial region where the electric field strength may be increased due to a geometric shape of at least one of the semiconductor chip 4, the intermediate layer 16, the chip carrier 2, or the encapsulation material 12. In one example, the filler particles 18 can be arranged at at least one of an edge or a tip of the semiconductor chip 4. There, the electric field lines may be compressed, resulting in high electric field strengths. In a specific example, the filler particles 18 can be arranged in a region where the semiconductor chip 4, the encapsulation material 12, and the intermediate layer 16 are adjacent to one another. Such a region is associated with the Fig. 2 described.

[0032] In one example, the filler particles 18 can be arranged only at positions within the intermediate layer 16 where increased electric field strengths may occur. Preferably, however, the filler particles 18 can be distributed homogeneously and completely over the entire intermediate layer 16. Compared to a locally limited arrangement of the filler particles 18 within the intermediate layer 16, a homogeneous distribution of the filler particles 18 over the entire intermediate layer 16 can be more cost-effective and easier to implement.

[0033] The semiconductor devices described herein, according to the disclosure, can provide, in addition to the reduction of electric field strength already described, the technical effects described below. By way of example only, the semiconductor device 300 of the Fig. 3. Reference is made to this. However, it is clear that the aforementioned technical effects can also be provided by any other semiconductor device described herein.

[0034] The use of filler particles 18 and the resulting reduction of electric field strength within the semiconductor device 300 can prevent wear of device components. This prevents premature aging of the components and increases their service life. The risk of failure of the semiconductor device 300 can thus be reduced. Furthermore, the extended service life allows for savings in energy and material resources.

[0035] By reducing the electric field strengths, electrical discharges, partial discharges, and / or air breakdowns within the semiconductor device 300 can be prevented. Due to aging processes, air volumes or air bubbles may form in the device, for example, at an interface between the encapsulation material 12 and the interlayer 16. The reduced electric field strengths can reduce the risk of discharges along air gaps within these air volumes.

[0036] By reducing the electric field strengths, additional components for improved galvanic isolation within the semiconductor device or in a higher-level system can be dispensed with. The necessary galvanic isolation can be provided completely in the semiconductor devices according to the disclosure, and in particular by the use of the filler particles 18. The devices described herein therefore represent simplified and cost-effective solutions.

[0037] Due to the achieved reduction of electric field strengths, insulation standards specified by industry standards can be met. The relevant industry standards at the time of this disclosure are IEC 60664 and IEC 60747-17. However, it should be noted that this disclosure is in no way limited to the aforementioned standards or related types of devices. The concepts described herein can naturally also be applied in other technical fields or devices.

[0038] The semiconductor devices described herein can be used, for example, in highly efficient, resource-saving electric drives. Electric drives can contribute, at least in part, to reducing global carbon dioxide emissions. The semiconductor devices described herein can therefore contribute, at least indirectly, to green technology solutions, i.e., climate-friendly solutions that provide reduced energy and material consumption.

[0039] The semiconductor device 400 of the Fig. 4 can exhibit one or more features of previously described semiconductor devices. In contrast to the Fig. 3. The filler particles 18 can be embedded in the encapsulation material 12 of the semiconductor device 400. In the example shown, the filler particles 18 can be homogeneously and completely distributed over the entire encapsulation material 12. By analogy to Fig. 3. The filler particles can be 18 in the Fig. 4. designed to increase the electrical conductivity of the encapsulation material 12 to a specific range when the electric field strength rises to a certain value. All related statements in connection with the Fig. 3 can also refer to the example of the Fig. 4. In particular, all statements regarding the filler particles 18, their properties, their technical effects, etc., can be applied analogously to the semiconductor device 400 of the Fig. 4 apply. For the sake of simplicity, reference is made to the description of the Fig. 3 referred.

[0040] The semiconductor device 500 of the Fig. The semiconductor device 500 can have one or more features of previously described semiconductor devices. In the semiconductor device 500, the intermediate layer 16 can contain one or more adhesive layers (or adhesive layers) 24, which may, among other things, be designed to attach the semiconductor chip 4 to the chip carrier 2. In the case shown, the intermediate layer can, by way of example, have two adhesive layers 24A, 24B. The lower adhesive layer 24A can attach the underside of a dielectric layer 26 to the top side of the chip carrier 2, while the upper adhesive layer 24B can attach a top side of the dielectric layer 26 to the underside of the semiconductor chip 4. The adhesive layers 24A, 24B can, in particular, contain or be made of an electrically insulating material.

[0041] In contrast to the examples of Fig. 3 and Fig. 4. The filler particles 18 can be embedded in at least one of the adhesive layers 24A, 24B in the semiconductor device 500. In the example shown, the filler particles 18 can be homogeneously and completely distributed over the total volumes of the adhesive layers 24A, 24B. By analogy to the examples of Fig. 3 and Fig. 4 the filler particles 18 of the Fig. 5. designed to increase the electrical conductivity of the adhesive layers 24A, 24B to a specific range when the electric field strength rises to a certain value. All related statements in connection with the Fig. 3 and Fig. 4 can naturally also affect the filler particles 18 of the Fig. 5 apply.

[0042] In the examples described above, Fig. 3, Fig. 4 to Fig. In 5, the filler particles 18 were each embedded in a single component of the respective semiconductor device. For example, in the example of the Fig. 4 only contained in the encapsulation material 12. In this context, however, it should be noted that features of the Fig. 3, Fig. 4 to Fig. 5 can be combined arbitrarily in further examples. In general, the filler particles 18 can therefore be contained in at least one of the intermediate layer 16, the dielectric layer 26, the adhesive layer 24, or the encapsulation material 12. For the sake of simplicity, not all possible combinations of features are explicitly shown and described here. However, it is clear to those skilled in the art that a reduction of increased electric field strengths can also be achieved by using the filler particles 18 in more than one single component.

[0043] Furthermore, it should be noted that the filler particles 18 described herein can be used in different types of devices and their use is not limited to a specific device type. For example, the filler particles 18 can be used in a current sensor, such as the one described in the Fig. 1 is described. This means that a semiconductor device according to the disclosure can be part of a current sensor. In another example, the filler particles 18 can be used in a semiconductor device according to the disclosure, which can be part of a gate driver or a discrete component. In particular, the use of the filler particles 18 can be advantageous in such devices designed to provide certain isolation functions, such as the galvanic isolation already described between a busbar and a semiconductor chip arranged above it.

[0044] The Fig. 6 and Fig. Figure 7 shows flowcharts for processes for manufacturing semiconductor devices according to the disclosure. The illustrated processes can be used, for example, to manufacture one of the semiconductor devices described above and can thus be read in conjunction with the preceding figures. The processes are presented in general terms to qualitatively describe aspects of the disclosure. Each of the processes may have further aspects. For example, a process may be extended to include one or more of the aspects mentioned in connection with other examples described herein.

[0045] In the process of Fig. In 30, an intermediate layer can be arranged on a chip carrier. In 32, a semiconductor chip can be arranged on the intermediate layer. In 34, the semiconductor chip can be encapsulated with an encapsulation material. Filler particles comprising a semiconductor material with a band gap in the range of approximately 2.3 eV to approximately 3.6 eV can be embedded in at least one of the intermediate layers or the encapsulation material.

[0046] In the process of Fig. In 36, an intermediate layer can be arranged on a chip carrier. In 38, a semiconductor chip can be arranged on the intermediate layer. In 40, the semiconductor chip can be encapsulated with an encapsulation material. Filler particles can be embedded in at least one of the intermediate layer or the encapsulation material. The filler particles can be designed to, when an electric field strength increases to a value greater than approximately 5 V / µm, reduce the electrical conductivity of at least one of the intermediate layer or the encapsulation material to a range of approximately 10. -16 S / m up to about 10 -2 to increase S / m.

[0047] The Fig. Section 8 concerns the electrical properties of a material containing embedded silicon carbide filler particles. In the exemplary representation of the Fig. Figure 8 shows the conductivity of the material (in S / m) against the strength of an applied electric field (in kV / mm) for different filler particle concentrations (in wt.%). Fig. Figure 8 shows five curves for filler particle contents of 0, 10, 30, 50 and 100 percent by weight.

[0048] From the Fig. Figure 8 shows that the electrical conductivity of the material increases significantly above a certain electric field strength. For example, the electrical conductivity of a material with a filler particle content of approximately 30% by weight increases significantly above an electric field strength of approximately 4 kV / mm. The higher the filler particle content, the lower the electric field strength at which the electrical conductivity of the material increases significantly.

[0049] The Fig. Section 9 concerns the electrical properties of a material containing embedded zinc oxide filler particles. In the exemplary representation of the Fig. 9 represents a current density J of a current flowing through the material (in A / cm²) for different filler particle concentrations (in %). 2 ) plotted against the strength of an existing electric field E (in MV / cm). An increased current density J can be due to an increased electrical conductivity of the material. Fig. Figure 9 shows four curves for filler particle contents of 15, 20, 25, and 30 percent, respectively. Analogous to the Fig. 8 exits the curves of the Fig. 9 highlights that an increased filler particle content provides an increase in material conductivity at lower electric field strengths.

[0050] The Fig. Section 10 concerns the electrical properties of different materials containing embedded zinc oxide filler particles. In the exemplary representation of the Fig. 10 is a current density J of a current flowing through the material (in mA / cm²) for different dimensions (in µm) and different geometric shapes (cf. “spherical” and “irregular”) of the filler particles. 2 or ∝ A / cm 2 ) plotted against the strength of an existing electric field E (in V / mm). From the Fig. 10 shows, among other things, that filler particles with larger dimensions provide an increase in current density at lower electric field strengths.

[0051] The Fig. Figure 10 shows three groups of curves. The first group concerns an epoxy filled with zinc oxide filler particles and contains four thin curves relating to (especially maximum) dimensions of the filler particles in the ranges of 50 µm to 100 µm, 100 µm to 150 µm, 150 µm to 200 µm, and 200 µm to 300 µm. The current density on the left side of the diagram is given in units of mA / cm². 2 specified.

[0052] The second group concerns a silicone rubber (or silicone rubber) filled with zinc oxide filler particles and contains four curves relating to filler particles with (especially maximum) dimensions in the ranges of 50 µm to 75 µm, 75 µm to 100 µm, 100 µm to 125 µm, and 125 µm to 150 µm. Here, the current density J is shown on the right-hand side of the diagram in units ∝ A / cm². 2 specified.

[0053] The third group concerns a silicone rubber filled with zinc oxide filler particles and contains eight thick curves. Four curves relate to spherical filler particles with (especially maximum) dimensions in the ranges of 50 µm to 75 µm, 75 µm to 100 µm, 100 µm to 125 µm, and 125 µm to 150 µm. Four further curves relate to irregularly shaped filler particles with (especially maximum) dimensions in the ranges of 20 µm to 35 µm, 35 µm to 50 µm, 50 µm to 75 µm, and 75 µm to 125 µm. Here, the current density J is shown on the right-hand side of the diagram in units ∝ A / cm². 2 specified. Examples

[0054] The following section explains semiconductor devices and associated manufacturing processes using examples.

[0055] Example 1 is a semiconductor device comprising: a chip carrier; a semiconductor chip arranged on the chip carrier; an intermediate layer arranged between the chip carrier and the semiconductor chip; an encapsulation material encapsulating the semiconductor chip at least partially; and filler particles embedded in at least one of the intermediate layer or the encapsulation material, wherein the filler particles comprise a semiconductor material having a band gap in the range of 2.3 eV to 3.6 eV.

[0056] Example 2 is a semiconductor device according to Example 1, wherein the filler particles comprise at least one of zinc oxide or silicon carbide.

[0057] Example 3 is a semiconductor device according to Example 1 or 2, wherein the filler particles are designed to, when an electric field strength increases to a value greater than 5 V / µm, at least one of the electrical conductivities of the interlayer or of the encapsulation material is reduced to a range of 10 -16 S / m up to 10 -2 to increase S / m.

[0058] Example 4 is a semiconductor device according to Example 3, wherein the increase in electrical conductivity is designed to reduce the electric field strength at certain positions of the filler particles.

[0059] Example 5 is a semiconductor device according to one of the preceding examples, wherein a proportion of the filler particles in at least one of the interlayer or encapsulation material has a value in the range of 1 wt% to 99 wt%.

[0060] Example 6 is a semiconductor device according to one of the preceding examples, wherein the filler particles have maximum dimensions in a range of 1 µm to 300 µm.

[0061] Example 7 is a semiconductor device according to any of the preceding examples, wherein the filler particles are arranged in a region where an electric field strength is increased due to a geometric shape of at least one of the semiconductor chip, the intermediate layer, the chip carrier or the encapsulation material.

[0062] Example 8 is a semiconductor device according to one of the preceding examples, wherein the filler particles are arranged at at least one of an edge or a tip of the semiconductor chip.

[0063] Example 9 is a semiconductor device according to one of the preceding examples, wherein the filler particles are arranged in a region where the semiconductor chip, the encapsulation material and the intermediate layer are adjacent to each other.

[0064] Example 10 is a semiconductor device according to one of the preceding examples, wherein the filler particles are homogeneously and completely distributed over the entire encapsulation material.

[0065] Example 11 is a semiconductor device according to one of the preceding examples, wherein the filler particles are homogeneously and completely distributed over the entire interlayer.

[0066] Example 12 is a semiconductor device according to any of the preceding examples, wherein: the intermediate layer comprises a dielectric layer designed to provide galvanic isolation between the chip carrier and the semiconductor chip, and the filler particles are embedded in the dielectric layer.

[0067] Example 13 is a semiconductor device according to any of the preceding examples, wherein: the intermediate layer comprises an adhesive layer designed to attach the semiconductor chip to the chip carrier, and the filler particles are embedded in the adhesive layer.

[0068] Example 14 is a semiconductor device according to any of the preceding examples, wherein the encapsulation material comprises at least one of a mold compound, an epoxy, an imide, a thermoplastic, a thermosetting polymer, a polymer mixture, a glob-top material or a laminate.

[0069] Example 15 is a semiconductor device according to any of the preceding examples, wherein: the chip carrier comprises a current conductor designed to carry a measuring current, and the semiconductor chip is part of a current sensor designed to detect an magnitude of the measuring current.

[0070] Example 16 is a semiconductor device according to one of the preceding examples, wherein the semiconductor chip is part of a gate driver.

[0071] Example 17 is a semiconductor device comprising: a chip carrier; a semiconductor chip arranged on the chip carrier; an intermediate layer arranged between the chip carrier and the semiconductor chip; an encapsulation material encapsulating the semiconductor chip at least partially; and filler particles embedded in at least one of the intermediate layers or the encapsulation material, which are designed to shift, upon an increase in electric field strength to a value greater than 5 V / µm, at least one of the electrical conductivities of the intermediate layer or the encapsulation material to a range of 10 -16 S / m up to 10 -2 to increase S / m.

[0072] Example 18 is a semiconductor device according to Example 17, wherein the filler particles comprise a semiconductor material with a band gap in the range of 2.3 eV to 3.6 eV.

[0073] Example 19 is a method for manufacturing a semiconductor device, the method comprising: arranging an intermediate layer on a chip carrier; arranging a semiconductor chip on the intermediate layer; and encapsulating the semiconductor chip with an encapsulation material, wherein at least one of the intermediate layer or the encapsulation material contains embedded filler particles comprising a semiconductor material having a band gap in the range of 2.3 eV to 3.6 eV.

[0074] Example 20 is a method for manufacturing a semiconductor device, the method comprising: arranging an interlayer on a chip substrate; arranging a semiconductor chip on the interlayer; and encapsulating the semiconductor chip with an encapsulation material, wherein at least one of the interlayer or the encapsulation material contains embedded filler particles designed to reduce the electrical conductivity of at least one of the interlayer or the encapsulation material to a range of 10 when an electric field strength increases to a value greater than 5 V / µm. -16 S / m up to 10 -2 to increase S / m.

[0075] Although specific embodiments are presented and described herein, it is obvious to the person skilled in the art that a multitude of alternative and / or equivalent implementations can replace the specific embodiments shown and described without departing from the scope of this disclosure. This application is intended to cover all adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this disclosure is limited only to the claims and their equivalents.

Claims

[1] Semiconductor device comprising: a chip carrier (2); a semiconductor chip (4) arranged on the chip carrier (2); an intermediate layer (16) arranged between the chip carrier (2) and the semiconductor chip (4); an encapsulation material (12) that at least partially encapsulates the semiconductor chip (4); and Filler particles (18) embedded in the intermediate layer (16), wherein the filler particles (18) are homogeneously and completely distributed over the entire intermediate layer (16), and wherein the filler particles (18) comprise a semiconductor material with a band gap in a range of 2.3 eV to 3.6 eV. [2] Semiconductor device according to claim 1, wherein the filler particles (18) comprise at least one of zinc oxide or silicon carbide. [3] Semiconductor device according to claim 1 or 2, wherein the filler particles (18) are designed to increase the electrical conductivity of the intermediate layer (16) to a range of 10 when the electric field strength increases to a value of more than 5 V / µm. -16 S / m up to 10 -2 to increase S / m. [4] Semiconductor device according to claim 3, wherein the increase in electrical conductivity is designed to reduce the electric field strength at positions of the filler particles (18). [5] Semiconductor device according to one of the preceding claims, wherein a proportion of the filler particles (18) in the intermediate layer (16) has a value in the range of 1 weight percent to 99 weight percent. [6] Semiconductor device according to one of the preceding claims, wherein the filler particles (18) have maximum dimensions in a range of 1 µm to 300 µm. [7] Semiconductor device according to one of the preceding claims, wherein the filler particles (18) are arranged in a region in which an electric field strength is increased due to a geometric shape of at least one of the semiconductor chip (4), the intermediate layer (16), the chip carrier (2) or the encapsulation material (12). [8] Semiconductor device according to one of the preceding claims, wherein the filler particles (18) are arranged at at least one of an edge or a tip of the semiconductor chip (4). [9] Semiconductor device according to one of the preceding claims, wherein the filler particles (18) are arranged in a region where the semiconductor chip (4), the encapsulation material (12) and the intermediate layer (16) are adjacent to each other. [10] Semiconductor device according to any one of the preceding claims, wherein: the intermediate layer (16) comprises a dielectric layer (26) designed to provide galvanic isolation between the chip carrier (2) and the semiconductor chip (4), and the filler particles (18) are embedded in the dielectric layer (26). [11] Semiconductor device according to any one of the preceding claims, wherein: the intermediate layer (16) comprises an adhesive layer (24) designed to attach the semiconductor chip (4) to the chip carrier (2), and the filler particles (18) are embedded in the adhesive layer (24). [12] Semiconductor device according to any of the preceding claims, wherein the encapsulation material (12) comprises at least one of a mold compound, an epoxy, an imide, a thermoplastic, a thermosetting polymer, a polymer mixture, a glob-top material or a laminate. [13] Semiconductor device according to any one of the preceding claims, wherein: the chip carrier (2) comprises a current conductor designed to carry a measuring current, and the semiconductor chip (4) is part of a current sensor designed to detect the magnitude of the measuring current. [14] Semiconductor device according to one of the preceding claims, wherein the semiconductor chip (4) is part of a gate driver. [15] Semiconductor device comprising: a chip carrier (2); a semiconductor chip (4) arranged on the chip carrier (2); an intermediate layer (16) arranged between the chip carrier (2) and the semiconductor chip (4); an encapsulation material (12) that at least partially encapsulates the semiconductor chip (4); and Filler particles (18) embedded in the intermediate layer (16) are designed to increase the electrical conductivity of the intermediate layer (16) to a range of 10 when the electric field strength increases to a value greater than 5 V / µm. -16 S / m up to 10 -2 to increase S / m, wherein the filler particles (18) are homogeneously and completely distributed over the entire intermediate layer (16). [16] Semiconductor device according to claim 15, wherein the filler particles (18) comprise a semiconductor material having a band gap in a range of 2.3 eV to 3.6 eV. [17] Semiconductor device comprising: a chip carrier (2); a semiconductor chip (4) arranged on the chip carrier (2); an intermediate layer (16) arranged between the chip carrier (2) and the semiconductor chip (4); an encapsulation material (12) that at least partially encapsulates the semiconductor chip (4); and Filler particles (18) embedded in the encapsulation material (12), wherein the filler particles (18) are made of a semiconductor material with a band gap in the range of 2.3 eV to 3.6 eV, wherein the filler particles (18) are designed to increase the electrical conductivity of the encapsulation material (12) to a range of 10 when the electric field strength increases to a value of more than 5 V / µm -16 S / m up to 10 -2 to increase S / m, and the filler particles have maximum dimensions in a range of approximately 30 µm to approximately 100 µm. [18] Method for manufacturing a semiconductor device, the method comprising: Arranging an intermediate layer (16) on a chip carrier (2); Arranging a semiconductor chip (4) on the intermediate layer (16); and Encapsulation of the semiconductor chip (4) with an encapsulation material (12), wherein filler particles (18) comprising a semiconductor material with a band gap in a range of 2.3 eV to 3.6 eV are embedded in the intermediate layer (16), wherein the filler particles (18) are homogeneously and completely distributed over the entire intermediate layer (16). [19] Method for manufacturing a semiconductor device, the method comprising: Arranging an intermediate layer (16) on a chip carrier (2); Arranging a semiconductor chip (4) on the intermediate layer (16); and Encapsulation of the semiconductor chip (4) with an encapsulation material (12), wherein filler particles (18) are embedded in the intermediate layer (16) which are designed to increase the electrical conductivity of the intermediate layer (16) to a range of 10 when the electric field strength increases to a value of more than 5 V / µm -16 S / m up to 10 -2to increase S / m, wherein the filler particles (18) are homogeneously and completely distributed over the entire intermediate layer (16). [20] Method for manufacturing a semiconductor device, the method comprising: Arranging an intermediate layer (16) on a chip carrier (2); Arranging a semiconductor chip (4) on the intermediate layer (16); and Encapsulation of the semiconductor chip (4) with an encapsulation material (12), wherein filler particles (18) are embedded in the encapsulation material (12) which are made of a semiconductor material with a band gap in the range of 2.3 eV to 3.6 eV, wherein the filler particles (18) are designed to increase the electrical conductivity of the encapsulation material (12) to a range of 10 when the electric field strength increases to a value of more than 5 V / µm -16 S / m up to 10 -2 to increase S / m, and the filler particles have maximum dimensions in a range of approximately 30 µm to approximately 100 µm.

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