Semiconductor device with a Germanium region arranged in a semiconductor substrate

Abstract

SPAD device with: a silicon substrate (102) with a recess (104) in a top side (102u) of the silicon substrate (102); a p-region (106) which is located in the silicon substrate (102) under a bottom of the recess (104); an n-avalanche region (108) located in the silicon substrate (102) below the p-region (106) and meeting the p-region (106) at a pn junction (110); a germanium region (112) which is arranged in the recess (104) above the pn junction (110); and an intrinsically conductive silicon region (118) located between an upper part of the p-region (106) and a lower part of the germanium region (112), wherein the intrinsically conductive silicon region (118) is configured to act as an electron channel extending over the entire distance between the pn junction (110) and the germanium region (112), wherein the germanium region has the following: an upper germanium region with a first p-doping concentration; and a lower germanium region with a second p-doping concentration, wherein the second p-doping concentration is lower than the first p-doping concentration, and the SPAD device further features the following: a sidewall germanium region that extends continuously along an outer sidewall of the germanium region and traverses the upper germanium region and the lower germanium region.

Description

background

[0001] A single-photon avalanche diode (SPAD) is a solid-state photodetector in the same family as photodiodes and avalanche photodiodes (APDs). Like photodiodes and APDs, a SPAD is arranged around a pn junction of a semiconductor that can be irradiated with ionizing radiation, such as gamma, X-ray, beta, and / or alpha particles, along with a broad portion of the electromagnetic spectrum from ultraviolet (UV) wavelengths through visible wavelengths to infrared (IR) wavelengths. During operation, a carrier generated by photon absorption is accelerated by an electric field within the device to a kinetic energy sufficient to overcome the ionization energy of the solid material, knocking electrons out of atoms within the material. A large avalanche of current carriers grows exponentially and can be triggered by a single carrier initiated by just one photon.A SPAD is capable of detecting individual photons, providing short-term trigger pulses that can be counted. It can also be used to determine the arrival time of the incoming photon based on the high velocity that builds up in the avalanche.

[0002] US 2021 / 0375959A1 discloses a photovoltaic cell comprising a germanium-containing well embedded in a single-crystal silicon substrate and extending to a proximal horizontal surface of the single-crystal silicon substrate, wherein the germanium-containing well contains germanium in an atomic percentage of more than 50%. A silicon-containing cover structure is located on an upper surface of the germanium-containing well and contains silicon in an atomic percentage of more than 42%. The silicon-containing cover structure prevents oxidation of the germanium-containing well. A photovoltaic compound can be formed within or across the well by implanting dopants of a first conductivity type and dopants of a second conductivity type.

[0003] US 2021 / 0091239A1 discloses a photosensor device, wherein the photosensor device comprises a substrate with a silicon layer on a front side, a photosensitive element projecting into and at least partially surrounded by the silicon layer, and a composite layer arranged between the photosensitive element and the silicon layer and surrounding the photosensitive element, wherein the composite layer comprises a first material and a second material different from the first material.

[0004] WO 2021 / 215066A1 discloses an optical detector comprising: a pixel area in which pixels with a photoelectric conversion unit are arranged multiple times in a matrix, each photoelectric conversion unit comprising: a first semiconductor unit divided by partitions; a second semiconductor unit located closer to a first surface between the first surface and a second surface positioned on opposite sides of the first semiconductor unit, the second semiconductor unit containing germanium; a light absorption unit provided on the second semiconductor unit, the light absorption unit absorbing light incident on the second semiconductor unit and generating a charge carrier;and a multiplier unit provided on the first semiconductor unit, wherein the multiplier unit performs an avalanche multiplication of the charge carrier generated by the light absorption unit.

[0005] Further state of the art is known from DISMUKES, JP; EKSTROM, L.; PAFF, RJ: Lattice parameter and density in germanium-silicon alloys. In: The journal of physical chemistry, Vol. 68, 1964, No. 10, pp. 3021-3027. - ISSN 0022-3654.

[0006] The invention is defined in the claims. Brief description of the drawings

[0007] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Rather, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 shows a sectional view of some embodiments of an integrated chip with a SPAD device having a germanium area embedded in a silicon substrate. Fig. Figure 2 shows a sectional view of some embodiments of an integrated chip with a SPAD device having a germanium area embedded in a silicon substrate. Fig. Figure 3A shows a sectional view of some embodiments of an integrated chip with a SPAD device having a germanium area embedded in a silicon substrate. Fig. Figure 3B shows a band gap diagram of some embodiments of a SPAD device, which Fig. 3A corresponds to this. The Fig. 4 and Fig. Figure 5 shows sectional views of some embodiments of an integrated chip with a SPAD device, each having a germanium area embedded in a silicon substrate. The Fig. Figures 6 to 14 show a manufacturing process according to some embodiments. The Fig. Figures 15 to 21 show a further manufacturing process according to other embodiments. The Fig. Figures 22 to 29 show a further manufacturing process according to other embodiments. Fig. Figure 30 shows a flowchart of a manufacturing process according to some embodiments. Detailed description

[0008] The disclosure below provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the fabrication of a first element over or on top of a second element in the description below may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present disclosure.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0009] Fig. Figure 1 shows a single-photon avalanche detector device (SPAD device) 100 according to some embodiments. The SPAD device 100 has a silicon substrate 102 with a recess 104 in a top surface 102u of the silicon substrate 102. A p-region 106 is arranged in the silicon substrate 102 below a lower part of the recess 104. An n-avalanche region 108 is arranged in the silicon substrate 102 below the p-region 106, which intersects the p-region 106 at a pn junction 110 corresponding to a photodiode in the silicon substrate 102. A germanium region 112 is arranged in the recess 104. A top surface of the germanium region 112 can be located at a depth d below the top surface 102u of the silicon substrate 102 (see 112ub), can be at the same level as the top surface 102u of the substrate (see 112ul), or can be located at a height h above the top surface 102u of the substrate (see 112uu).In some embodiments, an intrinsically conductive silicon region 118 can be arranged between an upper part of the p-region 106 and a lower part of the germanium region 112. The intrinsically conductive silicon region 118 is configured to act as an electron channel between the pn junction 110 and the germanium region 112. A biasing circuit 150 is configured to apply a bias voltage to the pn junction 110 in order to apply a voltage greater than an avalanche breakdown voltage to the SPAD device 100. The biasing circuit 150 is also configured to cool the SPAD device 100 after an avalanche has occurred. The biasing circuit 150 can be implemented using transistors and / or other active or passive devices arranged on or in the silicon substrate 102 or in another substrate.

[0010] In some cases, the germanium region 112 meets the silicon substrate 102 at a Ge-Si interface 117. The Ge-Si interface 117 is defined where outer sidewalls and a bottom surface of the germanium region 112 meet inner sidewalls or a recessed top surface of the silicon substrate 102. The Ge-Si interface 117 consists of a Ge-Si alloy with a lattice constant of 0.566 nm to 0.543 nm. In some cases, the Ge-Si alloy can have a thickness of 0.1 nm (1 Å) to 20 nm and a U-shaped cross-section.

[0011] A lateral n-connection region 114 extends laterally from the outer edges of the pn junction 110 and beyond the outer sidewalls of the germanium region 112. A vertical n-connection region 116 extends upwards from the outer edges of the lateral n-connection region 114 to the top surface 102u of the silicon substrate 102. Under certain circumstances, the lateral n-connection region 114 and / or the vertical n-connection region 116 can be described as a "guard ring" because, when viewed from above, the vertical n-connection region 116 laterally surrounds the germanium region 112. In some embodiments, the n-avalanche region 108, the lateral n-connection region 114 and the vertical n-connection region 116 collectively form a U-shaped cross-sectional profile which, when viewed in cross-section, essentially encloses the p-region 106 and the germanium region 112.

[0012] During operation, the bias circuit 150 biases the pn junction 110 such that it is above an avalanche breakdown voltage. Under this bias condition, when an incident photon 152 (e.g., from a laser pulse) is absorbed in an absorption region 113 corresponding to the germanium region 112, an electron-hole pair is generated, and the electrons drift through the intrinsically conductive silicon region 118 and into a gain region 115 containing the pn junction 110. The electrons are then accelerated in the gain region 115, acquiring sufficient kinetic energy to be impact ionized, thus generating a second electron-hole pair. The second electrons and holes of this second electron-hole pair are in turn accelerated and impact ionized, generating further electron-hole pairs in the gain region 115.Further impact ionization of electrons and holes quickly generates a large avalanche current, which can be self-sustaining if the device is biased above the avalanche breakdown voltage. Under these conditions, this results in a detectable electronic signal that can be time-controlled with respect to the initial incident photon 152 (e.g., from the beginning of the laser pulse). After detection, the biasing circuit 150 temporarily biases the SPAD device 100 below the avalanche breakdown voltage to quench the avalanche, and the SPAD device 100 can then return to its rest state, ready to detect further incident photons.

[0013] It should be noted that the presence of the germanium region 112, located in the recess 104 in the top surface 102u of the silicon substrate 102, can reduce the dark current rate (DCR) in some respects compared to other approaches. Furthermore, the germanium region 112 also enables good absorption (detection) of short-wave infrared signals (SWIR signals), which do not occur in purely silicon-based SPADs. Thus, the SPAD device 100 is a separate absorption and multiplication (SAM) device with germanium (Ge) in silicon (Si). In this device, creating the germanium region 112 in the recess 104 in the silicon substrate 102, rather than simply as a plateau on the top surface of the substrate, offers several advantages.

[0014] Fig. Figure 2 shows further embodiments of a SPAD device 100 according to some embodiments. Here too, the SPAD device 100 has a silicon substrate 102 with a recess 104 in a top surface 102u of the silicon substrate 102. A p-region 106 is arranged in the silicon substrate 102 below a lower part of the recess 104. An n-avalanche region 108 is arranged below the p-region 106 and meets the p-region 106 at a pn junction 110. A germanium region 112 is arranged in the recess 104.

[0015] A lateral n-connection region 114 extends laterally from the outer edges of the pn junction 110 and beyond the outer sidewalls of the germanium region 112. A vertical n-connection region 116 extends upwards from the outer edges of the lateral n-connection region 114 to the top surface 102u of the silicon substrate 102. Under certain circumstances, the lateral n-connection region 114 and / or the vertical n-connection region 116 can be described as a "guard ring" because, when viewed from above, the vertical n-connection region 116 laterally surrounds the germanium region 112. In some embodiments, the n-avalanche region 108, the lateral n-connection region 114 and the vertical n-connection region 116 collectively form a U-shaped cross-sectional profile which, when viewed in cross-section, essentially encloses the p-region 106 and the germanium region 112.

[0016] In some embodiments, the SPAD device 100 further comprises a p-surface region 120 that occupies the recess 104 and laterally surrounds the intrinsically conductive silicon region 118. The p-surface region 120 contains silicon, such as monocrystalline silicon. The p-surface region 120 has a base part 120b with a central opening corresponding to the intrinsically conductive silicon region 118, and a sidewall part 120s that extends upward along the outer sidewalls of the germanium region 112 (and / or along the inner sidewalls of the recess 104 in the silicon substrate 102).

[0017] In some embodiments, the germanium region 112 further comprises a solid region corresponding to the absorption region 113, wherein both the solid region and the absorption region 113 are intrinsically conductive (undoped) germanium. A sidewall germanium region 126 extends continuously along an outer sidewall of the germanium region 112. The sidewall germanium region 126 is also p-type conductive. The p-surface region 120 and the sidewall germanium region 126 contribute to reducing leakage loss and can thereby attenuate the dark current caused by mechanical stresses, dislocations, and the like that occur in the Ge-Si interface.

[0018] A cap 128, such as a p-silicon cap, is arranged above a top surface of the germanium region 112 to limit or prevent oxidation of this top surface. In the illustrated example, the cap 128 has a top surface that is flush with or at the same level as the top surface 102u of the silicon substrate 102, but in other cases, the top surface of the cap 128 could be recessed below the top surface of the silicon substrate or could be located above it. Furthermore, in the illustrated embodiment, the cap 128 has a bottom surface that directly contacts the top surfaces of the solid germanium region 112 and the sidewall germanium region 126 and is flush with or at the same level as them.In other embodiments, however, the sidewall germanium area 126 is arranged in an outer edge of the recess 104, and it extends upwards along an outer sidewall of the cap 128 to be at the same level as the top 102u of the silicon substrate 102.

[0019] A dielectric structure 132, which can be made, for example, of silicon dioxide or a dielectric low-k material, extends over the top surface 102u of the substrate. Conductive contacts 134, such as metal contacts, extend through the dielectric structure 132, and metal conductors or conductive pads 136 are fabricated over the conductive contacts 134. The metal conductors or conductive pads 136 can be functionally connected to a bias circuit (e.g., the bias circuit 150 of Fig. 1) be connected, which may include semiconductor devices fabricated on the silicon substrate 102 or another semiconductor substrate. For example, if the semiconductor devices are fabricated on the silicon substrate 102, they may include transistors with fins and / or a gate electrode located on the top surface 102u of the substrate, or alternatively, they may include transistors with fins and / or a gate electrode located on a bottom surface 102l of the substrate, in which case a silicon via may extend through the substrate to provide a functional connection.

[0020] Now let's move on to... Fig. 3A. In some embodiments, the germanium region 112 has an upper germanium region 122 with a first p-doping concentration, an intermediate germanium region 124 with a second p-doping concentration, and a lower germanium region 130 with a third p-doping concentration or intrinsically conductive (undoped) germanium. The second p-doping concentration is lower than the first p-doping concentration, and the third p-doping concentration, when at non-zero doping levels, is lower than the second p-doping concentration.In some cases, the first, second and / or third doping concentrations are essentially flat or constant over their respective depths in the upper germanium region 122, the intermediate germanium region 124 and the lower germanium region 130, while in other cases these doping concentrations show distinct “nodes” or breaks at the depicted upper and lower margins of the respective regions, which are shown in . Fig. 3A. In other cases, the variations in doping concentrations are slower and / or more continuous over the entire depth of the germanium region 112. In some embodiments, the sidewall germanium regions 126 extend continuously along an outer sidewall of the germanium region 112 and traverse the upper germanium region 122, the intermediate germanium region 124, and the lower germanium region 130. The use of these doping regions, which are shown in Fig. As shown in Figure 3A, this can help provide a lensing function for the SPAD device to improve jitter behavior, allowing carriers to drift more efficiently to the pn junction 110.

[0021] Fig. Figure 3B shows an exemplary band diagram illustrating some embodiments of the SPAD device of Fig. 3A corresponds to the band diagram. The band diagram exhibits a conduction band 350 and a valence band 352, with the left part of the band diagram corresponding to an n-type material (e.g., the n-avalanche region 108) and the right part of the band diagram corresponding to a p-type material (e.g., p+ germanium). The Fermi level of the device is represented by a line 354. As shown, at the interface between the absorption region 113 and the gain region 115, there are interfacial states and / or deep adhesion sites near the silicon / germanium heterojunction, and these adhesion sites cause a discontinuity in the valence band and the conduction band. In particular, the valence band has an S-curve in the gain region 115, then shows a steep (e.g.,The conduction band exhibits an S-curve at the interface between the absorption region 113 and the gain region 115, followed by a dip in the absorption region 113 before regaining its maximum valence band energy. The conduction band also has an S-curve in the gain region 115, but here the upper part of the S-curve corresponds to a peak or vertex, followed by a dip in the absorption region 113 before the conduction band regains its maximum conduction band energy.

[0022] The Fig. 4 and Fig. Figure 5 shows some embodiments in which a first and a second SPAD are arranged side by side in a silicon substrate. In the Fig. 4 and Fig. 5 have a first SPAD device 100a and a second SPAD device 100b, each with structural elements as described above with reference to Fig. 2 have been described, wherein structural elements designated a and b have the same or a similar structure and function as described with reference to Fig. 2 have been described (e.g., 102a and 102b in the Fig. 4 to 5 correspond to 102 in Fig. 2, Fig. 106a and Fig. 106b in the Fig. 4 and Fig. 5 corresponds to 106 in Fig. 2, and so on). Thus, encompasses the Fig. 4 and Fig. 5. A first vertical n-connection region 116a laterally surrounds a germanium region 112a of the first SPAD device 100a, and a second vertical n-connection region 116b laterally surrounds a germanium region 112a of the first SPAD device 100a. A portion of the silicon substrate 102 separates the first vertical n-connection region 116a from the second vertical n-connection region 116b. In the embodiment of Fig. 4. This part of the silicon substrate 102 can be self-conducting monocrystalline silicon. In Fig. Figure 5 separates an insulating structure 502, which is made of a dielectric material or has p-type silicon, the first vertical n-connection region 116a from the second vertical n-connection region 116b. It is understood that any number of SPAD devices can be arranged in a silicon substrate, and these SPAD devices can be arranged, for example, in a matrix having a number of rows and columns. In the Fig. 4 and Fig. Although an example has been presented in section 5, in which the first SPAD device 100a and the second SPAD device 100b of the SPAD device of Fig. 2 correspond, but in other embodiments the first SPAD device 100a and the second SPAD device 100b could correspond to the SPAD device of Fig. 1 or Fig. 3A and / or other illustrated embodiments and / or combinations thereof.

[0023] The Fig. Figures 6 to 14 show a manufacturing process according to some embodiments. Fig. Figures 6 to 14 are indeed described for a procedure, but it should be understood that the structures revealed in these figures are not limited to this procedure, but can be used as structures independently and separately from the procedure.

[0024] In Fig. In embodiment 6, a semiconductor base substrate 600 is obtained, and a sacrificial oxide 602 is deposited on one top surface of the semiconductor base substrate 600. In some embodiments, the semiconductor substrate 600 is a monocrystalline silicon wafer, but in other embodiments, the semiconductor substrate can take other forms. For example, the semiconductor substrate 600 can be, among others, a semiconductor-on-insulator substrate, a sapphire substrate, or a III-V substrate. The sacrificial oxide 602 can be, among others, silicon dioxide or another silicon oxide, such as silicon nitride. The sacrificial oxide 602 can be produced by thermal oxidation, rapid thermal annealing, plasma-assisted evaporation, chemical vapor deposition, spin deposition, or other processes. In some embodiments, the sacrificial oxide 602 has a thickness of 3 nm to 30 nm or of 7.5 nm to 12 nm (30 Å to 300 Å or of 75 Å to 120 Å), or its thickness is about 9 nm (90 Å).

[0025] In Fig. 7. A p-protective implantation, such as with boron, aluminum, or indium, is performed to create a buried p-region 138 in the semiconductor substrate. Then, an n-implantation, such as with phosphorus, arsenic, or antimony, is performed with a first photoresist mask in the correct position to create an n-avalanche region 108 and a lateral n-connection region 114.

[0026] In Fig. 8. The sacrificial oxide 602 is removed, and in some cases, an epitaxial monocrystalline silicon region 900 is epitaxially generated over a top surface of the semiconductor base substrate 600, resulting in a monocrystalline silicon substrate. In some embodiments, the removal of the sacrificial oxide 602 and the epitaxial generation of the epitaxial monocrystalline silicon region 900 are performed in situ. The in-situ processing can help ensure an oxide deficiency on the semiconductor base substrate 600, thereby promoting high-quality crystal growth with few or no defects. Then, another sacrificial oxide layer 902 is produced over the epitaxial monocrystalline silicon region 900.In some cases, the sacrificial oxide layer 902 is produced using an ISSG process (ISSG: in-situ vapor generation), but it can also be produced by thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), and the like. In some embodiments, the sacrificial oxide layer 902 has a thickness of 3 nm to 30 nm or 7.5 nm to 12 nm (30 Å to 300 Å or 75 Å to 120 Å), or its thickness is approximately 9 nm (90 Å).

[0027] In Fig. 8. A second photoresist mask 1002 is then produced over the sacrificial oxide layer 902, and subsequently an n-implantation, such as with phosphorus, arsenic, or antimony, is performed with a second photoresist mask in the correct position to create a vertical n-compound region 116. Fig. Although Figure 8 shows that the outer edges of the vertical n-connection area 116 are aligned with the outer edges of the lateral n-connection area 114, in other embodiments there may be some offset between these outer edges, so that the edges of the lateral n-connection area 114 may be shifted to the left or right with respect to the outer edges of the vertical n-connection area 116.

[0028] In Fig. 9. An undoped silicate glass (USG) region is produced, having a thickness of, for example, 20 nm to 120 nm (200 Å to 1200 Å). Then, a third photoresist mask (not shown) is fabricated, and with the third photoresist mask in the correct position, etching is performed to create a recess 104 in a top surface of the silicon substrate 102. In some cases, the recess 104 can have a depth d of about 1 µm. Then, another oxide layer 1102, for example, with a thickness of 50 nm to 100 nm (500 Å to 1000 Å), can be fabricated, for example, by ISSG, such that it extends over the top surface of the semiconductor substrate to cover a bottom surface and side walls of the recess 104.

[0029] In Fig. In step 10, a fourth photoresist mask 1202 is fabricated, and a p-region 106 is created. The p-region 106 can be created with a depth d and a distance below the recessed surface, such that an intrinsically conductive silicon region remains between the p-region and the recessed surface.

[0030] In Fig. In embodiment 11, a p-surface region 120 is created in the semiconductor substrate, leaving an intrinsically conductive silicon region 118 above the p-surface region 106. Additionally, a germanium region 112 is created, for example, by epitaxial growth. The germanium region 112 can be created such that it has a top surface recessed beneath a top surface of the silicon substrate 102. In other embodiments, however, the germanium region 112 can be created such that it has a top surface at the same level as, or even higher than, a top surface of the silicon substrate 102. In some cases, the germanium region 112 forms a thin alloy with the silicon substrate during growth, so that the germanium region 112 meets the silicon substrate 102 at a Ge-Si interface. This Ge-Si interface is defined where outer sidewalls and a bottom surface of the germanium region 112 meet inner sidewalls ora recessed top surface of the silicon substrate 102.

[0031] In Fig. In this process, a cap 128 is fabricated over the germanium region 112. The fabrication of the cap 128 can be carried out using an epitaxial growth process and can be performed in situ (e.g., in the same facility as that used to produce the germanium region 112 and in a controlled atmosphere, such as vacuum or nitrogen) to limit the oxidation of the germanium region 112. In some cases, the cap 128 is epitaxially grown monocrystalline p-silicon, and it may have a top surface that is elevated above the top surface of the substrate, but the top surface of the cap 128 may also be at the same level as the top surface of the substrate or even lower. In this case, an oxide 1502 can be fabricated over the cap 128, for example, by rapid thermal annealing, as a system-associated oxide.

[0032] In Fig. 13. A further ion implantation process is performed to generate p-sidewall germanium regions 126. In some cases, another photomask is prepared prior to this ion implantation, and then the ion implantation is performed with the photomask in the correct position to generate the p-sidewall germanium regions 126.

[0033] In Fig. In step 14, a dielectric structure 132 is fabricated on the top surface of the silicon substrate 102. Contact openings are created through the dielectric structure 132, and conductive contacts 134, such as metal contacts, are fabricated. Metal conductors or conductive pads 136 are fabricated over the conductive contacts 134. The metal conductors or conductive pads 136 can then be functionally connected to a bias circuit, which may include semiconductor devices fabricated on the silicon substrate 102 or another semiconductor substrate.For example, if the semiconductor devices are fabricated on the silicon substrate 102, they may have transistors with fins and / or a gate electrode located on the top side of the substrate, or alternatively, they may have transistors with fins and / or a gate electrode located on the bottom side of the substrate, in which case a silicon via may extend through the substrate to provide a functional connection.

[0034] The Fig. Figures 15 to 21 show a further manufacturing process according to other embodiments. In contrast to the Fig. Figures 6 to 14, which show the manufacture of a single SPAD device, demonstrate the Fig. 15 to 21, a first and a second SPAD device, which are manufactured directly adjacent to each other. Fig. Figures 15 to 21 are indeed described for a procedure, but it should be understood that the structures revealed in these figures are not limited to this procedure, but can be used as structures independently and separately from the procedure.

[0035] In Fig. 15, which in some respects the Fig. Corresponding to 6 to 8, a semiconductor base substrate 600 is obtained, and a buried p-region 138 is created in the semiconductor substrate by means of p-protection implantation. Furthermore, for example, a lateral n-connection region 114 is created by fabricating a photomask and performing ion implantation. An epitaxial monocrystalline silicon region 900 is created above a top surface of the semiconductor base substrate 600, and a vertical n-connection region 116 is created. In this example, a first and a second vertical n-connection region 116a and 116b are laterally separated from each other by an isolation region of the semiconductor substrate.

[0036] In Fig. 16, which in some respects Fig. 9 corresponds to a USG region with a thickness of, for example, 20 nm to 120 nm (200 Å to 1200 Å). A third photoresist mask is then fabricated, and with this mask in the correct position, etching is performed to create recesses 104 in a top surface of the semiconductor substrate. In some cases, the recesses 104 can have a depth of approximately 1 µm. A further oxide layer can then be fabricated, for example, by ISSG, to cover a bottom surface and side walls of the recesses 104.

[0037] In Fig. 17, which in some respects Fig. In accordance with 11, p-regions 106a, 106b, p-sidewall parts 120a and p-base parts 120b are produced in the semiconductor substrate. The p-regions 106a, 106b can be produced with a depth d below the recessed surface, leaving intrinsically conductive silicon regions 118a, 118b between the p-regions and the underside of the recess.

[0038] In Fig. 18, which in some respects also Fig. In embodiment 11, germanium regions 112a, 112b are produced, for example, by epitaxial growth. The germanium regions 112a, 112b can be produced such that they are recessed beneath a top surface of the semiconductor substrate. In other embodiments, however, the germanium regions 112a, 112b can be produced such that they have a top surface that is level with or even higher than a top surface of the semiconductor substrate. In some cases, the germanium regions 112a, 112b form a thin alloy with the silicon substrate when the germanium regions 112a, 112b are grown, so that they meet the silicon substrate 102 in a Ge-Si interface. This Ge-Si interface is defined where outer sidewalls and a bottom surface of the germanium region meet inner sidewalls and a recessed top surface of the silicon substrate, respectively.

[0039] In Fig. 19, which in some respects Fig. As per equation 12, silicon caps 128a, 128b are fabricated over the germanium regions 112a and 112b, respectively. The fabrication of the silicon caps 128a, 128b can be carried out using an epitaxial growth process and can be performed in situ (e.g., in the same facility as for the production of the germanium regions and in a controlled atmosphere, such as vacuum or nitrogen) to limit the oxidation of the germanium regions. In some cases, the epitaxially grown silicon caps 128a, 128b are p-type. In such cases, an oxide can be formed over the silicon caps 128a, 128b, for example, by rapid thermal annealing, as a system-specific oxide.

[0040] In Fig. 20, which in some respects Fig. If the result corresponds to 13, a further ion implantation process is performed to generate p-sidewall germanium regions 126a, 126b. In some cases, another photomask is prepared prior to this ion implantation, and then the ion implantation is performed with the photomask in the correct position.

[0041] In Fig. 21, which in some respects Fig. As per 14, a dielectric is produced on the top surface of the substrate. Contact openings are created through the dielectric, and conductive contacts 134, such as metal contacts, are produced. Metal conductors or conductive pads 136 are then produced over the conductive contacts 134. The metal conductors or conductive pads 136 can then be functionally connected to a bias circuit and a quenching circuit, which may include semiconductor devices fabricated on the semiconductor substrate or another semiconductor substrate.If the semiconductor devices are fabricated on the semiconductor substrate, for example, they can have transistors with fins and / or a gate electrode located on the top side of the substrate, or alternatively, they can have transistors with fins and / or a gate electrode located on the bottom side of the substrate, in which case a silicon via can extend through the substrate to provide a functional connection. Therefore, in . Fig. 21 outer sidewalls of the vertical n-connection regions 116a, 116b (e.g., guard rings) are spaced apart from each other by an insulating region corresponding to a part of the semiconductor substrate and can, in the case of Fig. 21 monocrystalline silicon.

[0042] The Fig. Figures 22 to 29 show a further manufacturing process according to other embodiments. Fig. Figures 22 to 29 are indeed described for a procedure, but it should be understood that the structures revealed in these figures are not limited to this procedure, but can be used as structures independently and separately from the procedure.

[0043] The Fig. 22 to 28 essentially correspond to the preceding ones. Fig. 15 to 21 and show adjacent SPAD devices. In Fig. 29 (which consist of Fig. 28) however, an insulating structure 502 is fabricated from the underside of the semiconductor substrate to isolate the adjacent SPAD devices from each other. In some cases, this insulating structure 502 can be fabricated as follows: fabricating a photomask on the underside of the semiconductor substrate; performing an etch to create a trench in the underside of the semiconductor substrate; and subsequently filling the trench with a dielectric material. In other cases, the insulating structure 502 can be fabricated by implanting ions (e.g., p-dopeds) into the underside of the substrate.

[0044] Fig.Figure 30 shows a flowchart of a method 3300 according to some embodiments. Although the method 3300 is presented and described here as a series of steps or events, it should be understood that the sequence of these steps or events shown should not be interpreted in a restrictive sense. For example, some steps may occur in different sequences and / or concurrently with other steps or events than those shown and / or described here. Furthermore, it may not be necessary to implement one or more aspects or embodiments of the description presented here. In addition, one or more of the steps shown here may be performed in one or more separate steps and / or phases.

[0045] In step 3302, a semiconductor substrate is obtained.

[0046] In step 3304, an ion implantation is performed to create a lateral interconnection area under a top surface of the semiconductor substrate.

[0047] In step 3306, an ion implantation is performed to create a vertical connection area. The vertical connection area and the lateral connection area contact each other to form a protective ring.

[0048] In step 3308, a recess is created in the top surface of the semiconductor substrate, the recess being enclosed laterally by the guard ring and defined by a recessed top surface and inner side walls of the semiconductor substrate.

[0049] In step 3310, a germanium area is created in the recess.

[0050] Thus, some embodiments refer to a SPAD device. The SPAD device has a silicon substrate with a recess in one of its top surfaces. A p-region is arranged in the silicon substrate beneath one of the recess's bottom surfaces. An n-avalanche region is located beneath the p-region in the silicon substrate, intersecting the p-region at a pn junction. A germanium region is arranged above the pn junction in the recess.

[0051] Further embodiments relate to a method. Ion implantation is performed to create a lateral interconnection area beneath the top surface of the semiconductor substrate. A further ion implantation is performed to create a vertical interconnection area. The vertical interconnection area and the lateral interconnection area contact each other to form a protective ring. A recess is created in the top surface of the semiconductor substrate, the recess being laterally enclosed by the protective ring and defined by a recessed top surface and inner sidewalls of the semiconductor substrate. A germanium region is created within the recess.

Claims

[1] SPAD device with: a silicon substrate (102) with a recess (104) in a top side (102u) of the silicon substrate (102); a p-region (106) which is located in the silicon substrate (102) under a bottom of the recess (104); an n-avalanche region (108) located in the silicon substrate (102) below the p-region (106) and meeting the p-region (106) at a pn junction (110); a germanium region (112) which is arranged in the recess (104) above the pn junction (110); and an intrinsically conductive silicon region (118) located between an upper part of the p-region (106) and a lower part of the germanium region (112), wherein the intrinsically conductive silicon region (118) is configured to act as an electron channel extending over the entire distance between the pn junction (110) and the germanium region (112), wherein the germanium region has the following: an upper germanium region with a first p-doping concentration; and a lower germanium region with a second p-doping concentration, wherein the second p-doping concentration is lower than the first p-doping concentration, and the SPAD device further features the following: a sidewall germanium region that extends continuously along an outer sidewall of the germanium region and traverses the upper germanium region and the lower germanium region. [2] SPAD device according to claim 1, further comprising: a p-surface region (120) which is arranged in the silicon substrate (102) and laterally surrounds the intrinsically conductive silicon region (118) and extends upwards along inner side walls of the recess (104) in the silicon substrate (102) and along outer side walls of the germanium region (112). [3] SPAD device according to claim 1 or 2, wherein the germanium region (112) meets the silicon substrate (102) at a Ge-Si interface (117) consisting of a Ge-Si alloy with a lattice constant of 0.566 nm to 0.543 nm, wherein the Ge-Si interface (117) is defined where outer side walls and a bottom surface of the germanium region (112) meet inner side walls or a recessed top surface (102u) of the silicon substrate (102). [4] SPAD device according to any of the preceding claims, further comprising: a lateral n-connection region (114) extending laterally from outer edges of the n-avalanche region (108) across outer side walls of the germanium region (112); and a vertical n-connection region (116) extending from outer edges of the lateral n-connection region (114) upwards to a top surface (102u) of the silicon substrate (102). [5] SPAD device according to claim 4, wherein the n-avalanche region (108), the lateral n-connection region (114) and the vertical n-connection region (116) collectively form a substantially U-shaped profile that substantially encloses the p-region (106) and the germanium region (112). [6] SPAD device according to one of the preceding claims, further comprising a silicon cap (128a, 128b) arranged in the recess (104) above a top surface (102u) of the germanium area (112). [7] SPAD device according to claim 6, wherein the top surface (102u) of the silicon cap (128a, 128b) is at the same level as a top surface of the silicon substrate (102). [8] SPAD device according to claim 6 or 7, further comprising: a sidewall germanium region (126) that is located in an outer edge of the recess (104) and has a top surface (102u) that meets a bottom surface of the silicon cap (128a, 128b). [9] Procedures, comprehensive: Obtaining a semiconductor substrate (600); Performing an ion implantation to create a lateral interconnection area (114) beneath a top surface (102u) of the semiconductor substrate (600); Performing an ion implantation to create a vertical connection area (116) wherein the vertical connection area (116) and the lateral connection area (114) contact each other to form a protective ring; Generating a recess (104) in the top surface (102u) of the semiconductor substrate (600), which is enclosed laterally by the guard ring and is defined by a recessed top surface (102u) of the semiconductor substrate (600) and inner side walls of the semiconductor substrate (600); Creating a germanium region (112) in the recess (104), and After generating the lateral interconnection area (116), an epitaxial silicon region grows over an upper region of the semiconductor substrate (600), wherein the vertical interconnection area (114) is generated in the epitaxial silicon region; and / or wherein the germanium region (112) has outer side walls that extend laterally beyond the outer edges of the pn junction (110). [10] Method according to claim 9, wherein the lateral connection area (116) is an n-type semiconductor material, and the procedure will further include the following: Prior to the growth of the epitaxial silicon region, a p-region (106) is generated which contacts the n semiconductor material at a pn junction (110). [11] Method according to claim 9 or 10, wherein the p-region (106) is generated under a bottom surface of the recess (104) at a distance from it, such that an intrinsically conductive silicon region separates a bottom surface of the germanium region (112) from a top surface of the p-region (106). [12] Method according to any one of claims 9 to 11, further comprising: Fabricating a silicon cap (128a, 128b) over a top surface (102u) of the germanium region (112), wherein the silicon cap (128a, 128b) directly contacts a top surface (102u) of the germanium region (112) without an oxide separating the germanium region (112) from the silicon cap (128a, 128b), wherein The silicon cap (128a, 128b) is grown in situ in the same facility or chamber as the germanium region (112).

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