Galvanic isolation using an insulation break between redistribution layer electrodes

Abstract

Structure (100), comprising: a galvanic insulation (110) with a horizontal section (111), comprising: a first redistribution layer electrode, RDL electrode (150), in a first insulator layer (146); a second RDL electrode (152) in the first insulator layer (146) laterally spaced from the first RDL electrode (150); and an insulation interruption (160) having a trench (162) defined in the first insulator layer (146) between the first RDL electrode (150) and the second RDL electrode (152) and at least one second insulator layer (166, 168) in the trench, wherein the insulation interruption (160) completely surrounds the first RDL electrode (150), wherein the first insulator layer (146) and the at least one second insulator layer (166, 168) are arranged between the first RDL electrode (150) and the second RDL electrode (152).

Description

background

[0001] The present invention relates to integrated circuits and, in particular, to a structure having galvanic isolation comprising an isolation interruption between electrodes of the redistribution layer, and to a corresponding method.

[0002] Galvanic isolation is isolation that prevents a first circuit from exchanging direct current (DC) and unwanted alternating current (AC) with a second circuit, but allows the two circuits to communicate through other mechanisms such as optics, inductance, capacitance, or other means. The two circuits typically have different electrical voltages, such as a high voltage and a low voltage. Galvanic isolation is created by forming a capacitor with parallel plates using electrodes in different metallization layers of the integrated circuit, such as different metallization layers in the back-end-of-line (BEOL) interconnect layers. The dielectrics of the BEOL layers separate the electrodes, forming the capacitor.For higher-voltage applications, the thickness of the BEOL dielectric layers or the number of BEOL dielectric layers is increased to achieve a higher breakdown voltage. As devices operate at increasingly higher voltages, e.g., up to the kV range, the available space for increasing the dielectric thickness or increasing the number of dielectric layers to create reliable and strong galvanic isolation is limited.

[0003] A semiconductor component is known from the document US 2021 / 0 074 675 A1. This semiconductor component comprises a first wafer, a first wiring layer provided in the first wafer, a first insulating layer provided on one side of the first wiring layer along a first direction, a first electrode provided in the first insulating layer and comprising a first surface connected to the first wiring layer, a second surface spaced from the first surface along the first direction, a third surface spaced further from the first surface along the first direction than the second surface, a first side surface extending from the first surface to the second surface, and a fourth surface extending from the second surface to the third surface, a second wafer, a second wiring layer,provided in the second wafer, a second insulating layer provided on a side of the second wiring layer along the first direction facing the side of the first wiring layer, a second electrode provided in the second insulating layer and comprising a fifth surface connected to the second wiring layer, a sixth surface spaced from the fifth surface along the first direction, a seventh surface spaced further from the fifth surface along the first direction than the sixth surface, the seventh surface being connected to the third surface, a second side surface extending from the fifth surface to the sixth surface, and an eighth surface extending from the sixth surface to the seventh surface, and a first layer,which is provided between the fourth surface and a portion of the first insulating layer surrounding the fourth surface and is spaced from the third surface in the first direction.

[0004] The document DE 10 2019 116 588 A1 shows a device for an integrated circuit having a bulk substrate exhibiting semiconductor-on-insulator behavior. The device for an integrated circuit comprises the following: a channel region defined in the bulk substrate, wherein the channel region has a first portion disposed over a second portion, and further wherein: the first portion is disposed between epitaxial source-drain features disposed in the bulk substrate, the second portion is defined by a first isolation feature disposed in the bulk substrate, the epitaxial source-drain features being disposed on the first isolation feature, and a thickness of the channel region is approximately equal to a sum of a thickness of the first isolation feature and a thickness of the epitaxial source-drain features;a second isolation feature disposed in the bulk substrate, the second isolation feature defining an active area including the first portion of the channel region disposed between the epitaxial source-drain features; and wherein a resistance of a portion of the bulk substrate underlying the first isolation feature and the channel region is greater than a resistance of the bulk substrate. Summary

[0005] One aspect of the invention is directed to a structure comprising: a galvanic isolation layer with a horizontal section, comprising: a first redistribution layer (RDL) electrode in a first insulator layer; a second RDL electrode in the first insulator layer, laterally spaced from the first RDL electrode; and an isolation interruption comprising a trench defined in the first insulator layer between the first RDL electrode and the second RDL electrode, and at least one second insulator layer in the trench, wherein the first insulator layer and the at least one second insulator layer are arranged between the first RDL electrode and the second RDL electrode. The isolation interruption completely surrounds the first RDL electrode.

[0006] Another aspect of the invention includes a structure comprising: a high voltage region on a substrate; a low voltage region on the substrate operating at a lower voltage than the high voltage region; galvanic isolation isolating the high voltage region from the low voltage region, the galvanic isolation comprising a horizontal section comprising: a first redistribution layer (RDL) electrode in a first insulator layer over one of the high voltage and low voltage regions; a second RDL electrode in the first insulator layer laterally separated from the first RDL electrode and operatively coupled to the other of the high voltage and low voltage regions;and an insulation interruption comprising a trench defined in the first insulator layer between the first RDL electrode and the second RDL electrode, and at least one second insulator layer in the trench, wherein the first insulator layer and the at least one second insulator layer are arranged between the first RDL electrode and the second RDL electrode;

[0007] One aspect of the invention relates to a method comprising: forming a trench in a first insulator layer between a first redistribution layer (RDL) electrode and a second RDL electrode in the first insulator layer, wherein the first RDL electrode and the second RDL electrode are laterally spaced apart; and filling the trench with at least one second insulator layer, wherein the first insulator layer and the at least one second insulator layer are arranged between the first RDL electrode and the second RDL electrode, wherein the first RDL electrode lies in a first voltage region and the second RDL electrode lies in a second, different voltage region.

[0008] The foregoing and other features of the invention will become apparent from the following detailed description of embodiments of the invention. Short description of the drawings

[0009] The embodiments of the present invention are described in detail with reference to the following figures, wherein like designations denote like elements and wherein: Fig. 1 shows a cross-sectional view of a structure with galvanic isolation according to embodiments of the invention. Fig. 2 shows a plan view of a structure with galvanic isolation according to embodiments of the invention. Fig. 3 shows a cross-sectional view of a structure with galvanic isolation according to other embodiments of the invention. Fig. 4 shows a cross-sectional view of a first structure for forming galvanic isolation with forming a trench according to embodiments of the invention. Fig. 5 is a cross-sectional view of forming an insulator layer in the trench of Fig. 4, according to embodiments of the invention. Fig. 6 a cross-sectional view of forming another insulator layer in the trench of Fig. 4 according to embodiments of the invention.

[0010] The drawings of the invention are not necessarily to scale and are intended to illustrate only typical aspects of the invention and are therefore not to be considered limiting the scope of the invention. In the drawings, like reference numerals refer to like elements. Detailed description

[0011] In the following description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention, and other embodiments may be utilized and changes may be made without departing from the scope of the present invention. The following description, therefore, is for illustrative purposes only.

[0012] When an element such as a layer, region, or substrate is described as being "on" or "over" another element, it may be directly on top of the other element, or there may be intervening elements. On the other hand, when an element is described as being "directly on" or "directly over" another element, there may not necessarily be intervening elements. When an element is described as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. On the other hand, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0013] Reference in the specification to "one embodiment" or "an embodiment" of the present invention, as well as other variations thereof, means that a particular feature, structure, characteristic, etc. described in connection with the embodiment is present in at least one embodiment of the present invention. Therefore, the phrases "in an embodiment" or "in an embodiment," as well as any other variations appearing at various points in the specification, do not necessarily all refer to the same embodiment. The use of " / ," "and / or," and "at least one of," such as in the cases "A / B," "A and / or B," and "at least one of A and B," is intended to encompass only the selection of the first listed option (A), only the selection of the second listed option (B), or the selection of both options (A and B).Another example: In the cases of "A, B and / or C" and "at least one of options A, B and C", this wording is intended to cover only the first listed option (A), or only the selection of the second listed option (B), or only the selection of the third listed option (C), or the selection of the first and second listed options (A and B), or the selection of the first and third listed options (A and C), or the selection of the second and third listed options (B and C), or the selection of all three options (A and B and C). This can be extended to any number of listed options, as will be readily apparent to a person skilled in the art.

[0014] Embodiments of the invention include a galvanic isolation structure comprising a horizontal section with a first redistribution layer (RDL) electrode in a first insulator layer and a second RDL electrode in the first insulator layer at a lateral distance from the first RDL electrode. The first insulator layer may comprise a polyimide over late back-end-of-line interconnect layers in an integrated circuit. An isolation interruption comprises a trench defined in the first insulator layer between the first RDL electrode and the second RDL electrode, and at least one second insulator layer in the trench. The first insulator layer and the second insulator layer(s) are located between the first RDL electrode and the second RDL electrode. The isolation may, for example, separate voltage domains with different voltage levels. A corresponding method is also described.The galvanic isolation may also include a vertical section using the first RDL electrode and a third electrode in a metal layer and separated from the first RDL electrode by a plurality of dielectric interlayers.

[0015] Galvanic isolation provides stronger galvanic isolation (e.g., at the kV level) by increasing capacitive coupling using the isolation break and RDL electrodes in a horizontal section in the late BEOL interconnect layers. Galvanic isolation provides stronger protection than with multiple or thicker BEOL interconnect layers. The horizontal (lateral) section of isolation also prevents the formation of lateral spikes of the high-voltage contact on the bond pad. The first insulator layer, which can be a polyimide packaging layer, can be made thinner than typically used layers or thicker than required to achieve higher galvanic isolation. The manufacturing process is compatible with CMOS (complementary metal-oxide semiconductor) processing but is more cost-effective than increasing the thickness or number of BEOL interconnect layers.

[0016] Fig. 1 shows a cross-sectional view and Fig. 2 shows a plan view of a structure 100 according to embodiments of the invention. The structure 100 comprises a galvanic insulation 110 (hereinafter "insulation 110") with a horizontal section 111. As shown in Fig. 1, the insulation 110 is located at least partially in a galvanic isolation region 112 adjacent to a logic region 114 in an integrated circuit structure 116. The logic region 114 may include any now known or later developed functional elements of an integrated circuit (not shown) formed on a substrate 118, such as, without limitation, transistors (below the M1 layer), resistors, capacitors, etc. A galvanic isolation region 112 may represent a first voltage region 120, and the logic region 114 may represent a second voltage region 122. The first voltage region 120 and the second voltage region 122 have different operating voltages. For example, the first voltage region 120 may represent a relatively high voltage region on the substrate 118, and the second voltage region 122 may represent a relatively low voltage region on the substrate 118.In any case, the second voltage region 122 is operated at a lower voltage than the first voltage region 120.

[0017] Any now known or later developed back-end-of-line (BEOL) interconnect layers 130 may be provided in the logic region 114 and the galvanic isolation region 112. It should be noted that the BEOL interconnect layers 130 may include any known or later developed interlayer dielectric (ILD) layers 132 with conductive wires 134 or vias 136 for electrically connecting parts, e.g., in the logic region 114. The ILD layers 132 may include, without limitation, silicon dioxide, silicon nitride, carbon-doped silicon dioxide materials, fluorinated silicate (FSG) glass, organic polymeric thermosetting materials, silicon oxycarbide, SiCOH dielectrics, spin-on glasses, silsesquioxanes, and any silicon-containing low-k dielectrics. Wires 134 and vias 136 may include any suitable conductor, e.g., silicon dioxide. tungsten, cobalt, copper, aluminum, etc., and any suitable lining, e.g. tantalum nitride, tantalum, etc.Although a specific number of BEOL interconnect layers 130 is illustrated, any number may be used, and they may have any thickness to accommodate the structures provided therein. BEOL interconnect layers 130 scale electrical connections, e.g., wires 134 and vias 136, until the structures, such as input / output pads 138, are large enough to connect to an external structure of the IC structure 116. The BEOL interconnect layers 130 may also include the outermost BEOL interconnect layers 133, which may be referred to as late BEOL (far BEOL, FBEOL) layers.

[0018] The structure 100 includes a redistribution layer (RDL) 140 over an outermost ILD layer 142 with I / O pads 138 (only one of the latter is shown for clarity). RDL 140 and ILD layer 142 may be part of the FBEOL layers 133, as they are the outermost interconnect layers in the IC structure 116. RDL 140 is an additional metal layer on an IC chip that makes the I / O pads 138 of the IC structure 116 available at other locations on the chip, allowing the I / O pads 138 to be more easily accessible when needed. An RDL 140 distributes the contact points around the IC structure 116 so that solder balls 144 can be applied and the thermal load can be distributed. RDL 140 includes a first insulator layer 146 with metal wires 148 to relocate the contact points to locations other than I / O pads 138. First insulator layer 146 may include any dielectric known now or later developed suitable for an RDL 140.In one embodiment, the first insulator layer 146 comprises a polyimide. The first insulator layer 146 may therefore have a dielectric strength of, for example, approximately 300 Vrms / µm (root mean square voltage per micrometer).

[0019] The structure 100, which utilizes selected metal wires 148 in the RDL 140, includes a first RDL electrode 150 in the first insulator layer 146 and a second RDL electrode 152 in the first insulator layer 146, spaced laterally from the first RDL electrode 150. The first RDL electrode 150 and the second RDL electrode 152 are part of the RDL 140, which may include additional metal wires 148 (not shown). The term "electrode," as used herein, may include any conductor capable of forming an electrical plate for a capacitor. The first RDL electrode 150 and the second RDL electrode 152 are located at the same level in the first insulator layer 146. Therefore, the first RDL electrode 150 and the second RDL electrode 152 may be arranged horizontally or laterally at a distance S that may be specified by the user.As usual, other portions of the metal wires 148 in the RDL 140 may be located at different levels for connection purposes, e.g., to the I / O pads 138 or other structures. The RDL electrodes 150, 152 may have any lateral arrangement. In the example shown, the second RDL electrode 152 may be electrically coupled to the second voltage region 122, e.g., in the logic area 114, by a plurality of (BEOL) interconnect layers 130. As previously mentioned, the first voltage region 120 and the second voltage region 122 may have different operating voltages. For example, the first voltage region 120 may be a relatively high voltage region and the second voltage region 122 may be a relatively low voltage region.

[0020] The structure 100 also includes an insulation break 160. The insulation break 160 electrically isolates the first RDL electrode 150 and the second RDL electrode 152. As shown in Fig. 1, the insulation interruption 160 comprises a trench 162 defined in the first insulator layer 146 between the first RDL electrode 150 and the second RDL electrode 152. At least one second insulator layer 166, 168 is located in the trench 162. Thus, the first insulator layer 146 and at least one second insulator layer 166, 168 are located between the first RDL electrode 150 and the second RDL electrode 152. Each second insulator layer 166, 168 has a higher dielectric constant than the first insulator layer 146. In one embodiment, the second insulator layer(s) may comprise at least one nitride layer 166 and at least one oxide layer 168. In the example shown, at least one nitride layer 166 lines a sidewall 160s of the trench 162, and at least one oxide layer 168 fills a remaining portion of the trench 162. However, other arrangements of nitride and oxide are also possible.In this way, the insulation break 160 as shown in . Fig. 2, a nitride-oxide-nitride arrangement between the first RDL electrode 150 and the second RDL electrode 152 increases the capacitive coupling generated by the insulation 110 compared to vertical galvanic isolations with BEOL interconnect layers 130. The nitride layer(s) 166 may comprise, among other materials, silicon nitride, and the oxide layer(s) 168 may comprise, among other materials, silicon oxide. As shown in Fig. 2, the trench 162 and the insulation interruption 160 surround the first RDL electrode 150.

[0021] The insulation break 160 provides additional dielectric strength and thus increased capacitive coupling of the insulation 110. The use of nitride layer(s) 166 and oxide layer(s) 168 allows for further increasing and / or adjusting the dielectric strength of the insulation 110. For example, silicon nitride has a dielectric strength of approximately 1100 Vrms / µm, and silicon oxide (high-temperature version) has a dielectric strength of approximately 500 Vrms / µm—compared to approximately 300 Vrms / µm for polyimide. The type of materials, their thicknesses, and the width of the trench 162 can be individually adjusted to achieve the desired dielectric strength for the insulation break 160 and the desired capacitive coupling of the insulation 110. Other options for the second insulator layer(s) 166, 168 may include, but are not limited to, hydrogenated silicon oxycarbide (SiCOH) (~750 Vrms / µm) or porous SiCOH (750+ Vrms / µm).The type of silicon oxide can also vary and include, for example, tetraethylorthosilicate, Si(OC2H5)4 (TEOS) silicon oxide (~900 Vrms / µm) or low-temperature silicon oxide (~500 Vrms / µm).

[0022] According to the presentation in Fig. 1, the structure 100 and the insulation 110 may also include a vertical section 172. The vertical section 172 may include a third electrode 170 below the first RDL electrode 150 and in a metal layer (M1, M2, etc.) of the first voltage region 120. While the third electrode 170 is shown in the first metal layer M1, it may be located in any metal layer of the BEOL interconnect layers 130. The third electrode 170 is vertically separated from the first RDL electrode 140 by a plurality of ILD layers 132 of the BEOL interconnect layers 130 and forms a vertical section 172 of the galvanic isolation 110. Any number of ILD layers 132 may be used.

[0023] Fig. 3 shows a cross-sectional view of the structure 100 according to an alternative embodiment. The structure 100 in Fig. 3 is essentially similar to that of Fig. 1, except that the first insulator layer 146 comprises at least one nitride layer 180 and at least one oxide layer 182, i.e., it is formed horizontally over the regions 112, 114. The nitride layer(s) 180 and the oxide layer(s) 182 replace the polyimide. The insulation interruption 160 still extends into the trench 162 of the nitride layer(s) 180 and the oxide layer(s) 182. The use of the nitride layer(s) 180 and the oxide layer(s) 182 allows for a further increase and / or adjustment of the dielectric strength of the insulation 110.

[0024] With reference to the Fig. 4-6 are cross-sectional views of a method according to embodiments of the invention. Fig. 4 shows an initial structure 200. The initial structure 200 includes the logic area 114 with any devices (not shown) and BEOL interconnect layers 130 thereon. At this stage, I / O pads 138 and metal wires 148 have been formed in the first insulator layer 146. The metal wires 148 include, among other structures not shown, the first RDL electrode 150 and the second RDL electrode 152 in the first insulator layer 146. The first RDL electrode 150 and the second RDL electrode 152 are laterally spaced from each other, e.g., by the distance S ( Fig. 1). The aforementioned structures can be manufactured using all currently known or later developed processes, e.g., conventional CMOS processes. In contrast to conventional processes, Fig. 4 also illustrates forming a trench 162 in the first insulator layer 146 between the first RDL electrode 150 and the second RDL electrode 152 in the first insulator layer 146. The trench 162 may be formed using a patterned mask 202 and a suitable etching process for the first insulator layer 146, e.g., a reactive ion etching process. The trench 162 does not expose the BEOL interconnect layers 130, but extends far enough beneath the RDL metal electrodes 150, 152 so that the insulation 160 eventually formed therein provides the desired dielectric strength and electrical isolation. The mask 202 may be removed using any suitable ashing process.

[0025] Fig. 5-6 show filling the trench 162 with at least one second insulator layer 166, 168. Fig. 5 shows the formation of at least one nitride layer 166. Each of the second insulating layers 166, 168 has a higher dielectric constant than the first insulating layer 146. In one embodiment, the first insulating layer 146 may comprise a polyimide, and the second insulating layer(s) may comprise at least one nitride layer 166 and at least one oxide layer 168. Although the trench 162 is shown unfilled, a single second insulating layer, e.g., of nitride or oxide, may fill the entire trench 162, such that the isolation discontinuity 160 comprises only a single insulating layer. In the example shown, the nitride layer(s) 166 just cover the sidewall 160s of the trench 162. Fig. 6 shows forming at least one oxide layer 168 over the nitride layer(s) 166, which fills / fills a remaining portion of the trench 162 ( Fig. 5). The filling step(s) may comprise any suitable deposition technique for the formed material. Any suitable planarization may then be performed to remove excess material, e.g., chemical mechanical polishing (CMP).

[0026] The first insulator layer 146 and each second insulator layer 166, 168 are located between the first RDL electrode 150 and the second RDL electrode 152, thereby creating a capacitor and a horizontal section 111 of the galvanic isolation 110. The first RDL electrode 150 is arranged in the first voltage region 120, and the second RDL electrode 122 is arranged in a second, different voltage region 122. As shown in Fig. 1, after the galvanic insulation 110 has been formed, any conventional packaging processes can be performed, such as the formation of a solder stop 144, wire bonding, etc.

[0027] The galvanic isolation 110 provides stronger galvanic isolation (e.g., at the kV level) by increasing capacitive coupling using the isolation break 160 and the RDL electrodes 150, 152 in a horizontal portion thereof in the FBEOL interconnect layers 133. The isolation 110 provides stronger protection than would be possible with multiple or thicker BEOL interconnect layers 132. The horizontal (lateral) portion 111 of the isolation 110 also prevents lateral overvoltage of the high-voltage contact on the I / O pad 138. The first insulator layer 146, which may be a polyimide packaging layer, may be thinner than usual or thicker than required to achieve higher galvanic isolation. The Fig. The manufacturing process shown in Figures 4-6 is compatible with CMOS processing, but is more cost-effective than increasing the thickness or number of BEOL interconnect layers 132.

[0028] The processes described above are used in the manufacture of integrated circuits. The resulting integrated circuit chip packages can be integrated with other chip packaging, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) a final product. The final product can be any product incorporating integrated circuit chips, ranging from toys and other simple applications to advanced computer products with a display, keyboard or other input device, and a central processor.

[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an,” and “the” include the plural forms, unless the context clearly indicates otherwise. The terms “comprises” and / or “comprising,” as used in this description, may specify the presence of certain features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. “Optional” or “may” means that the subsequently described event or circumstance may or may not occur, and that the description includes instances where the event occurs and instances where it does not occur.

[0030] An approximate formulation, as used in the description and claims, may be used to modify any quantitative representation that may permissibly vary without changing the basic function to which it relates. Accordingly, a value modified by one or more terms such as "approximately," "about," and "substantially" is not limited to the precisely stated value. In at least some cases, the approximate formulation may correspond to the accuracy of an instrument for measuring the value. Here and throughout the description and claims, range limits may be combined and / or interchanged; such ranges are identified and include all subranges contained therein unless the context or language indicates otherwise.The term "approximate" when applied to a specific value within a range refers to both values ​​and, unless otherwise determined by the accuracy of the measuring instrument, may mean + / -10% of the stated value(s).

Claims

[1] Structure (100), comprising: a galvanic insulation (110) with a horizontal section (111) comprising: a first redistribution layer electrode, RDL electrode (150), in a first insulating layer (146); a second RDL electrode (152) in the first insulating layer (146), which is laterally spaced from the first RDL electrode (150); and an insulation break (160) with a trench (162) defined in the first insulator layer (146) between the first RDL electrode (150) and the second RDL electrode (152) and at least one second insulator layer (166, 168) in the trench, wherein the insulation break (160) completely surrounds the first RDL electrode (150), wherein the first insulating layer (146) and the at least one second insulating layer (166, 168) are arranged between the first RDL electrode (150) and the second RDL electrode (152). [2] Structure (100) according to claim 1, wherein every second insulating layer (166, 168) has a higher dielectric constant than the first insulating layer (146). [3] Structure (100) according to claim 1, wherein the at least one second insulator layer (166, 168) comprises at least one nitride layer and at least one oxide layer. [4] Structure (100) according to claim 3, wherein the at least one nitride layer coats a side wall (160s) of the trench (162) and the at least one oxide layer fills a remaining section of the trench (162). [5] Structure (100) according to claim 1, wherein the first insulating layer (146) comprises a polyimide. [6] Structure (100) according to claim 1, wherein the galvanic insulation (110) comprises a vertical section (172) with a third electrode (170) below the first RDL electrode (150) and in a metal layer of a first voltage region (120), wherein the third electrode (170) is vertically separated from the first RDL electrode (150) by a plurality of dielectric intermediate layers (132). [7] Structure (100) according to claim 6, wherein the second RDL electrode (152) is electrically coupled to a second voltage region (122) by a plurality of interconnection layers (130), wherein the first voltage region (120) and the second voltage region (122) have different operating voltages. [8] Structure (100) according to claim 1, wherein the first insulator layer (146) comprises at least one nitride layer and at least one oxide layer. [9] Structure (100) according to claim 1, wherein the first RDL electrode (150) and the second RDL electrode (152) are located at the same level in the first insulating layer (146). [10] Structure (100), comprising: a high-voltage area (120) on a substrate (118); a low-voltage area (122) on the substrate (118) which is operated at a lower voltage than the high-voltage area (120); and a galvanic insulation (110) that isolates the high-voltage area (120) from the low-voltage area (122), wherein the galvanic insulation (110) comprises a horizontal section (111), comprising: a first redistribution layer electrode, RDL electrode (150), in a first insulating layer (146) over one of the high voltage and low voltage regions (120, 122); a second RDL electrode (152) in the first insulating layer (146), which is laterally separated from the first RDL electrode (150) and is functionally coupled to the other by the high-voltage and low-voltage regions (120, 122); and an insulation break (160) with a trench (162) defined in the first insulator layer (146) between the first RDL electrode (150) and the second RDL electrode (152), and at least one second insulator layer (166, 168) in the trench (162), wherein the first insulating layer (146) and the at least one second insulating layer (166, 168) are arranged between the first RDL electrode (150) and the second RDL electrode (152). [11] Structure (100) according to claim 10, wherein every second insulating layer (166, 168) has a higher dielectric constant than the first insulating layer (146). [12] Structure (100) according to claim 10, wherein the first insulating layer (146) comprises a polyimide and the at least one second insulating layer (166, 168) comprises at least one nitride layer and at least one oxide layer. [13] Structure (100) according to claim 10, wherein the insulation break (160) surrounds the first RDL electrode (150). [14] Structure (100) according to claim 10, wherein the galvanic insulation (110) comprises a vertical section (172) comprising a third electrode (170) below the first RDL electrode (150) and in a metal layer separated from the high-voltage and low-voltage regions (120, 122), wherein the third electrode (170) is vertically separated from the first RDL electrode (150) by a plurality of dielectric connecting layers (130). [15] Structure (100) according to claim 10, wherein the first insulator layer (146) comprises at least one nitride layer and at least one oxide layer. [16] Structure (100) according to claim 10, wherein the first RDL electrode (150) and the second RDL electrode (152) are arranged at the same level in the first insulating layer (146). [17] Procedures, including: a trench (162) formed in a first insulator layer (146) between a first redistribution layer electrode, RDL electrode (150), and a second RDL electrode (152) in the first insulator layer (146), wherein the first RDL electrode (150) and the second RDL electrode (152) are laterally spaced apart; and a filling of the trench (162) with at least one second insulator layer (166, 168), wherein the first insulating layer (146) and the at least one second insulating layer (166, 168) are arranged between the first RDL electrode (150) and the second RDL electrode (152), wherein the first RDL electrode (150) is arranged in a first voltage range (120) and the second RDL electrode (152) is arranged in a second, different voltage range (122). [18] Method according to claim 17, wherein the at least one second insulating layer (166, 168) has a higher dielectric constant than the first insulating layer (146). [19] Method according to claim 17, wherein the first insulating layer (146) comprises a polyimide and the at least one second insulating layer (166, 168) comprises at least one nitride layer and at least one oxide layer.

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