Stacked chip layer of an integrated circuit with carrier chip layer including capacitors and thermal vias

Abstract

Electronic device (10), comprising: a carrier chip layer (14), comprising: a substrate (32) comprising a first thermally conductive material; at least one thermal via (36) within the substrate (32), wherein the at least one thermal via (36) comprises a second thermally conductive material that is more thermally conductive than the first thermally conductive material; and at least one capacitor (38) within the substrate (32); and an integrated circuit (IC) chip location (12), wherein: the IC chip position (12) has a reverse side (20B); the back side (20B) of the IC chip layer (12) is stacked on the carrier chip layer (14); the IC chip layer (12) further comprises an IC plating (18) on the back (20B) thereof; and the IC plating (18) comprises an IC plating body (50) and at least one IC capacitor terminal area which is electrically isolated from the IC plating body (50) by at least one IC capacitor opening (54).

Description

Area of ​​Disclosure

[0001] The present invention relates to the packaging of integrated circuits (ICs). In particular, the present invention relates to an IC chip layer stacked with a carrier chip layer, including capacitors and thermal vias. background

[0002] Mobile devices, such as mobile phones, increasingly require smaller integrated circuits (ICs), including high-frequency (HF) circuits. The performance of HF circuits in general, and monolithic microwave integrated circuits (MMICs) in particular, is sensitive to the operating temperature of IC components. Further miniaturization of IC packages and module sizes is becoming a challenge, especially with regard to heat transfer from IC components.

[0003] The publication DE 11 2009 000 425 T5 describes micromodules with integrated thin-film inductors and methods for manufacturing them.

[0004] The invention is defined in the independent claim. Embodiments of the invention are described in the dependent claims. Brief description

[0005] Embodiments of the disclosure relate to a chip layer of an integrated circuit (IC) stacked with a carrier chip layer, including capacitors and thermal vias. The carrier chip layer comprises a substrate material to accommodate and electrically insulate one or more capacitors on a rear side of the IC chip layer. The carrier chip layer further comprises a thermal material having the same or higher thermal conductivity than the substrate material for thermal propagation and enhanced heat dissipation. In particular, the carrier chip layer electrically couples capacitors in a stacked configuration to the IC chip layer while also dissipating and dissipating heat from the IC chip layer. Such a configuration reduces the overall footprint of the electronic device, resulting in reduced packaging and module sizes for integrated circuits (ICs).In other words, instead of placing the capacitors next to the IC chip layer, the capacitors are stacked on top of the IC chip layer, thus reducing the overall surface area of ​​the package.

[0006] One embodiment of the disclosure relates to an electronic device comprising a carrier chip layer, which in turn comprises a substrate comprising a first thermally conductive material. The carrier chip layer further comprises at least one thermal via within the substrate. The multiple thermal vias comprise a second thermally conductive material that is equal to or better thermally conductive than the first thermally conductive material. The carrier chip layer further comprises at least one capacitor within the substrate. The electronic device further comprises a chip layer of an integrated circuit (IC) stacked on the carrier chip layer.

[0007] Experts will recognize the scope of the present disclosure and additional aspects thereof after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawing figures. Brief description of the drawing figures

[0008] The accompanying illustrations, which are included in and form part of this description, illustrate several aspects of the revelation and, together with the description, serve to explain the principles of the revelation. Fig. Figure 1A is a perspective exploded view from above of an electronic device with a chip layer of an integrated circuit (IC) stacked on a carrier chip layer. Fig. Figure 1B is a perspective exploded view from below of the electronic device of Fig. 1A. Fig. Figure 1C illustrates a perspective exploded view of the electronic device of Fig. 1A, where the IC plating has exploded from the IC chip layer and the carrier plating has exploded from the carrier chip layer. Fig. 2A is a view of the ground plane plating of the IC chip layer. Fig. 1A-1C. Fig. 2B is a view of the carrier plating of the carrier chip location of the Fig. 1A-1C. Fig. 3 is a rear view of the carrier chip position of the Fig. 1A-1C, which represents thermal ranges. Fig. Figure 4 is a side cross-sectional view of an embodiment of the electronic device of Fig. 1A-3. Detailed description

[0009] The embodiments set forth below provide the necessary information to enable a person skilled in the art to put them into practice and illustrate the best way to do so. By reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the disclosure and recognize applications of these concepts that are not specifically addressed herein. It is understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0010] It is understood that, although the terms first, second, etc., may be used here to describe different elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element could be called a second element, and similarly, a second element could be called a first element, without deviating from the scope of the present revelation. The term "and / or," as used here, includes any and all combinations of one or more of the associated listed elements.

[0011] It is also understood that when an element is described as "connected" or "coupled" to another element, it may be directly connected or coupled to that other element, or there may be intervening elements. Conversely, when an element is described as "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0012] It is understood that, although the terms “upper”, “lower”, “below”, “middle”, “middle”, “above”, and the like may be used here to describe various elements, these elements should not be restricted by these conditions. These terms are used only to distinguish one element from another. For example, a first element might be called the “upper” element, and similarly, a second element might be called the “upper” element, depending on the relative orientations of these elements, without departing from the scope of the present disclosure.

[0013] The terminology used herein serves only to describe certain embodiments and is not intended to limit the disclosure. As used herein, the singular forms "a," "an," and "the" are to include the plural forms unless the context clearly indicates otherwise. It is further understood that the terms "comprises," "comprising," "contains," and / or "including," when used herein, specify the presence of specified features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0014] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meanings as generally understood by a person of average competence in the field to which this disclosure belongs. It is further understood that terms used herein should be interpreted as having meanings consistent with their meanings in the context of this description and the relevant prior art, and not in an idealized or overly formal sense, unless expressly defined herein.

[0015] Embodiments of the disclosure relate to a chip layer of an integrated circuit (IC) stacked with a carrier chip layer, including capacitors and thermal vias. The carrier chip layer comprises a substrate material to accommodate and electrically insulate one or more capacitors on a rear side of the IC chip layer. The carrier chip layer further comprises a thermal material that is as thermally conductive as or better than the substrate material for thermal propagation and enhanced heat dissipation. In particular, the carrier chip layer electrically couples capacitors in a stacked configuration to the IC chip layer while also dissipating and dissipating heat from the IC chip layer. Such a configuration reduces the overall area of ​​the electronic device, resulting in reduced packaging and module sizes for integrated circuits (ICs).In other words, instead of placing the capacitors next to the IC chip layer, the capacitors are stacked on top of the IC chip layer, thus reducing the overall surface area of ​​the package.

[0016] The Fig. Figures 1A-1C illustrate an electronic device 10 comprising an integrated circuit (IC) layer 12 and a carrier layer 14. Specifically, the electronic device 10 (which may also be referred to herein as an IC pack, IC circuit pack, stacked arrangement, etc.) includes an integrated circuit (IC) layer 12 stacked on a carrier layer 14. The IC layer 12 contains active components, while the carrier layer 14 contains capacitors and / or thermal materials. Accordingly, the carrier layer 14 electrically couples capacitors to the IC layer 12 in a stacked configuration, while also distributing and dissipating heat from the IC layer 12.The electronic device 10 disclosed herein provides efficient heat transfer, robust high-frequency (HF) power and millimeter-wave (mmW) frequency operation, all in a cost-effective miniature package with a low profile and small footprint (e.g. surface mountable (SM)).

[0017] The IC chip layer 12 includes an IC substrate 16 and / or an IC plating 18. The IC chip layer 12 further comprises an active side 20A (which can also be referred to as the top, upper side, top surface, etc.) and a corresponding back side 20B (which can also be referred to as the bottom, lower side, bottom surface, etc.). The active side 20A contains active components (e.g., transistors, diodes, RF transmission lines, etc.). In particular, the active side 20A includes input terminals 22A (e.g., RF input terminals), output terminals 22B (e.g., RF output terminals), transmission line 24, amplifier 25, capacitor terminals 26, and / or ground terminal 28. The IC chip layer 12 includes IC vias 30 (which can also be called conductive vias, hot vias, through-hole vias (TCVs), through-substrate vias (TSVs), etc.).(designated as IC vias) extend from the active side 20A through the IC substrate 16 to a back side 20B of the IC chip layer 12. The IC vias 30 include signal vias 30 for routing communication signals between the active side 20A and the back side 20B. The IC vias 30 further include capacitor vias 30(2), 30(3) for connecting the active side 20A to the back side 20B. The RF output 22B can be connected to external hardware via via 30(1). The IC vias 30 can have a variety of shapes, sizes, patterns, and other configurations. In certain embodiments, the IC chip layer has solder or copper pillar bumps (e.g., such as those used for flip-chip mounting to a higher-level substrate in the assembly). Numerous ground vias are connected to the IC plating 18.

[0018] The IC plating 18 is located on the back side 20B of the IC chip layer 12. The IC plating 18 facilitates an isolated electrical coupling between the IC chip layer 12 and the carrier chip layer 14. In particular, the IC plating 18 facilitates an electrical coupling between the IC vias 30 of the IC chip layer 12 and the carrier chip layer 14.

[0019] The carrier layer 14 is positioned on or near the back side 20B of the IC layer 12. The carrier layer 14 includes a substrate 32 and a carrier plating 33 (which may be similar to, the same as, or equivalent to the IC plating 18). The carrier layer 14 provides a primary thermal path for the active components of the IC layer 12. The carrier layer 14 comprises an active side 34A (which may also be referred to as the top, upper side, top surface, etc.) and a back side 34B opposite it (which may also be referred to as the bottom, lower side, bottom surface, etc.). The carrier layer 14 provides highly efficient heat distribution and heat transfer for components (e.g., active components such as diodes and transistors and / or passive components such as RF transmission lines, tuning networks, connecting inductors, capacitors, inductors, etc.).) on the active side 20A of the IC chip layer 12 through the back side 20B of the IC chip layer 12, through the active side 34A of the carrier chip layer 14 to the back side 34B of the carrier chip layer 14.

[0020] The substrate 32 of the carrier chip layer 14 contains a first thermally conductive material (which may also be referred to herein as the substrate material). In certain embodiments, the first thermally conductive material comprises silicon, silicon carbide (SiC), diamond, aluminum nitride (AlN), glass, etc.

[0021] The carrier chip layer 14 further includes at least one carrier via 36 (which may also be referred to as conductive vias, hot vias, TCVs, TSVs, etc.) within the substrate 32, extending from the active side 34A through the substrate 32 to the back side 34B of the carrier chip layer 14. The carrier vias 36 include thermal vias 36 for conducting heat between the active side 34A and the back side 34B. In certain embodiments, the carrier vias 36 also include capacitor vias to form the positive terminal of the capacitor 38. In certain embodiments, the carrier plating 33 serves as the ground.

[0022] The thermal vias 36 contain a second thermally conductive material that is more thermally conductive than the first thermally conductive material. For example, in certain embodiments, the second thermally conductive material contains copper. The substrate 32 electrically insulates the thermal vias 36 from each other. The thermal vias 36 can have a variety of shapes, sizes, patterns, and other configurations.

[0023] In certain embodiments, the carrier plating 33 of the carrier chip layer 14 is located on the active side 34A of the substrate 32. The carrier plating 33 facilitates an isolated electrical coupling between the IC chip layer 12 and the carrier chip layer 14. In particular, the carrier plating 33 facilitates the electrical coupling between the IC vias 30 of the IC chip layer 12 and the carrier vias 36 of the carrier chip layer 14.

[0024] The carrier chip layer 14 further includes at least one capacitor 38 (e.g., high-density capacitor, high-k dielectric, ferroelectric dielectric, deep-trench capacitor, etc.) within the substrate 32. A deep-trench capacitor is a three-dimensional vertical capacitor and can be formed by etching a deep trench into a silicon substrate. In certain embodiments, the capacitors 38 are used for RF bypass, RF decoupling, tuning (e.g., fixed or tunable varactors), energy storage, and / or thermal vias. Each of the capacitors 38 is electrically coupled to the active side 20A of the IC chip layer 12 via the IC vias 30 of the IC chip layer 12. In particular, each of the capacitors 38 is electrically coupled to active components on the active side 20A of the IC chip layer 12 by the carrier plating 33, the IC plating 18 and the IC vias 30.

[0025] Fig. Figure 2A is a view of the IC plating 18 of the IC chip layer 12. In certain embodiments, the IC plating 18 contains at least one layer of gold or tin. In certain embodiments, the IC plating 18 includes an IC plating body 50 and at least one IC capacitor connection pad 52 (which may also be referred to as an IC capacitor I / O pad, IC signal pad, interconnect, etc.) that is electrically isolated from the IC plating body 50 by at least one IC capacitor opening 54. The IC capacitor connection pads 52 are configured to align with capacitors 38 within the carrier chip layer 14. The IC plating 18 is generally known as a ground plane with islands of connection pads 52, wherein the IC plating body and the connection pads 52 form the positive and negative terminals, respectively, of a capacitor 38.

[0026] Fig. Figure 2B is a view of the carrier plating 33 of the carrier chip layer 14. In certain embodiments, the carrier plating 33 contains at least one gold or tin alloy. In certain embodiments, the carrier plating 33 includes a carrier plating body 55 and at least one carrier capacitor termination pad 56 (which may also be referred to as a carrier capacitor I / O pad, carrier signal pad, interconnect, etc.) that is electrically isolated from the carrier plating body 55 by a carrier capacitor opening 58. The carrier capacitor termination pads 56 are configured to align with capacitors 38 within the carrier chip layer 14.

[0027] With reference to the Fig. 2A-2B, the pattern and orientation of the IC plating 18 are the same or at least similar to the carrier plating 33. In particular, the IC capacitor connection pads 52 and / or IC capacitor openings 54 are aligned with the carrier capacitor connection pads 56 and / or the carrier capacitor openings 58. In this way, the at least one IC capacitor connection pad 52 is aligned and electrically coupled with the at least one carrier capacitor connection pad 56.

[0028] Fig. Figure 3 is a rear view of the carrier chip layer 14, illustrating non-thermal areas 60 and thermal areas 62. At least some of the non-thermal areas 60 correspond to positions of capacitors 38 within the carrier chip layer 14. The thermal areas 62 include one or more thermal vias 36. In certain embodiments, these thermal vias 36 correspond to positions of amplifiers (or other heat-generating active components) of the IC chip layer 12.

[0029] Configurations of the thermal areas 62 can depend on the thermal requirements, manufacturing costs, etc., of the electronic device. For example, filling an entire thermal area 62 with thermal material can increase thermal conductivity but also increase costs. Conversely, structuring the thermal area 62 with thermal material can meet thermal conductivity requirements at a reduced cost. Accordingly, in other embodiments, the thermal vias 36 are large, continuous blocks of material (rather than isolated vias). In certain embodiments, the multiple thermal vias 36 are patterned in a two-dimensional array. In certain embodiments, the thermal vias 36 are all the same size.In other embodiments, the thermal vias 36 differ from one another in size, shape and / or configuration, etc. In certain embodiments, the thermal areas 62 are evenly distributed over the substrate 32. In other embodiments, the thermal areas 62 are assigned to specific regions.

[0030] With reference to the Fig. In certain embodiments, IC chip layer 12 is bonded to the carrier chip 14 (e.g., wafer-to-wafer bonding, chip-to-wafer bonding, etc.). In certain embodiments, IC chip layer 12 is bonded to the carrier chip layer 14 using metal-to-metal bonding, solder (e.g., AuSn), conductive adhesives, sintered materials, DB1l bonding techniques, and / or hybrid bonding techniques, etc. Accordingly, the IC plating 18 of IC chip layer 12 contacts (e.g., directly contacts) the carrier plating 33 of the carrier chip layer 14. In particular, the IC capacitor connection pads 52 are aligned with and contact the carrier capacitor connection pads 56. Similarly, the IC capacitor openings 54 are aligned with the carrier capacitor openings 58. Accordingly, the contacts between the connection surfaces 52, 56 are electrically insulated from the bodies 50, 55 of the IC plating 18 and the carrier plating 33.

[0031] As noted above, the carrier chip layer 14 includes capacitors 38 (e.g., deep-trench capacitors) with thermal vias 36 extending between the active side 34A and the back side 34B of the carrier chip layer 14. The thermal vias 36 are adjacent to the capacitors 38. Consequently, the carrier chip layer 14 acts as a heat spreader, drawing heat away from the IC chip layer 12 and conducting the heat away from the IC chip layer 12 through the carrier chip layer 14.

[0032] Stacking the IC chip layer 12 onto the carrier chip layer 14 results in a reduced footprint. In particular, stacking the capacitors of the carrier chip layer 14 with the IC chip layer 12 reduces the space requirement while simultaneously providing heat dissipation.

[0033] Fig. Figure 4 is a side cross-sectional view of an embodiment of the electronic device of Fig.1-3. In certain embodiments, the IC chip layer 12 contains a monolithic microwave integrated circuit (MMIC). In certain embodiments, the MMIC is fabricated on a III-V substrate. It is noted that placing the capacitors 38 close to the IC chip layer 12 reduces the inductance between the capacitors 38 and the IC chip layer 12. In certain embodiments, the capacitances of the capacitors can be approximately or greater than 1 µF / mm. 2 In certain embodiments, the carrier chip layer 14 is connected to the back side 20B of the IC chip layer 12 by means of backside hot via intermediate connections.

[0034] As noted above, in certain embodiments, the IC chip layer 12 contains a plurality of amplifiers 25 (e.g., broadband amplifiers). The plurality of thermal vias 36 are aligned with the amplifiers 25 (e.g., each of the amplifiers 25) of the IC chip layer 12. In certain embodiments, a first section of the plurality of thermal vias 36 is aligned with each amplifier 25 of the IC chip layer 12, and a second section of the plurality of thermal vias 36 is not aligned with any amplifier 25 of the IC chip layer 12. In other embodiments, the thermal vias 36 are aligned only with the amplifiers 25 of the IC chip layer 12. In other words, in certain embodiments, thermal vias 36 are used only for selected active components of the IC chip layer 12 that generate large amounts of heat.

[0035] In certain embodiments, the circuit package includes the IC chip layer 12 and the carrier chip layer 14, surrounded by an overmolded layer 70. An interconnect layer attaches the IC chip layer 12 to a printed circuit board 76 (PCB) or other component that carries the IC package 10 and / or electrically connects the IC chip layer 12 to other components in an RF device (e.g., a mobile device or base station). In this respect, the IC package 10 can form an RF module in which the substrate 32 is packaged using any suitable IC package type. For example, IC packaging can include fan-out wafer-level packaging (FOWLP), fan-out panel-level packaging (FOPLP), fan-in wafer-level packaging (FIWLP), fan-in panel-level packaging (FIPLP), or wafer-level chip-scale packaging (WLCSP), enabling high-density packaging for ICs, including monolithic microwave integrated circuits (MMICs).FOWLP and FOPLP are packing technologies that enable the use of semiconductor-like thin-film processes (e.g., high-resolution lithographic structuring, physical vapor deposition (PVD) metallization, and chemical vapor deposition (CVD) dielectrics) to distribute dense input / output (I / O) connections on the MMIC substrate (e.g., fan-out). In some examples, the IC packing 10 can include multiple substrates and / or other circuit components to form a multi-chip module (MCM), multi-chip package (MCP), or system-in-pack (SiP). In such examples, a common RDL can provide connections between the packing substrates 75 and / or other circuit components. This packing substrate includes vias 76B and intermediate connections 76A, 76C to facilitate the implementation of this component on a PCB 78.

[0036] For example, in one embodiment of the FOWLP process, a known good chip layer (KGD) (e.g., IC chip layer 12 and several additional IC chip layers) and sometimes other passive components are precisely placed on a temporary support, often referred to as a reconstructed wafer, and overmolded with epoxy to form the overmolded layer 70. The KGD can be formed from one or more IC wafers that are diced to form IC chip layer 12 and a variety of additional IC chip layers, and then overmolded to form an overmolded IC array. A portion of the overmolded layer 70 can be removed to expose a top and / or bottom surface of IC chip layer 12, so that the overmolded layer 70 partially surrounds IC chip layer 12 (e.g., only sides of IC chip layer 12, or sides and either the top or bottom surface of IC chip layer 12).

[0037] In certain embodiments, these IC vias 30 through the IC chip layer 12 can facilitate an orientation of the IC chip layer 12 with the chip layer side facing upwards in the IC package 10, so that the active side 20A is oriented away from a redistribution layer (RDL) and / or a next-higher array (NHA) to which the IC package 10 is attached. When combined with other technologies, such as copper pillar (CuP) bumping, the IC package 10 can further facilitate three-dimensional (3D) arrangements using chip-stack and pack-on-pack (POP) processes.

[0038] In certain embodiments, the IC vias 30 of IC chip layer 12 and / or the carrier vias 36 of carrier chip layer 14 pass through a metallization (e.g., copper). The IC vias 30 of IC chip layer 12 and the carrier vias 36 of carrier chip layer 14 provide a thermal conduction path from the active side 20A of IC chip layer 12 through IC chip layer 12 and through carrier chip layer 14. In certain embodiments, the heat transfer extends through the back side 34B to a heat exchanger (e.g., a heat sink or a cooling plate).

[0039] In certain embodiments, an overmolding 70 covers the IC chip layer 12 and / or the carrier chip layer 14. In certain embodiments, the overmolding 70 includes conductive vias for further heat dissipation. A path with high thermal conductivity can also be created through the top surface of the IC package 10 if heat spreaders are formed directly over the hot spots on the IC chip layer 12. For example, conductive pillars 72 or other thermally conductive structures are formed over and near heat sources on the IC chip layer 12 (e.g., transistors or other active elements in the active layer).

[0040] Currently practiced semiconductor processes could be used to form the conductive pillars 72, similar to the formation of copper protrusions for flip-chip mounted semiconductor chips. The conductive pillars 72 can be used to conduct heat from the top of the IC chip layer 12 to the molded side of the IC package 10 if the conductive pillars 72 are suitably exposed from the overmolded layer 70. In this respect, the conductive pillars 72 can be formed before or after the deposition of the overmolded layer 70. If formed beforehand, the overmolded layer 70 can be partially removed to expose the conductive pillars 72.

[0041] In certain embodiments, a heat exchanger 74A, 74B can be attached to the conductive columns 72 of the overmolding 70 and / or the back surface 34B of the carrier chip layer 14. The heat exchanger can be attached to the conductive columns 72, the overmolded layer 70, and / or the carrier chip layer 14 by a suitable technique, such as soldering or brazing to the conductive columns 72 or by an adhesive (e.g., a thermally conductive adhesive). In this way, the conductive columns 72 further facilitate heat conduction to a heat exchanger 74A. The heat exchanger 74A, 74B can be a heat sink or a cooling plate and can exchange heat by liquid, air, conduction, convection, etc., as required.

[0042] In certain embodiments, the conductive columns 72 can provide an electrical connection to features of the IC chip layer 12. For example, a circuit layer can provide a connection between features of the IC chip layer 12, an RF antenna connected to the IC chip layer 12, a connection to external circuits, and so on.

[0043] Experts will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the following claims.

Claims

[1] Electronic device (10) comprising: a carrier chip layer (14), comprising: a substrate (32) comprising a first thermally conductive material; at least one thermal via (36) within the substrate (32), wherein the at least one thermal via (36) comprises a second thermally conductive material that is more thermally conductive than the first thermally conductive material; and at least one capacitor (38) within the substrate (32); and an integrated circuit (IC) chip location (12), wherein: the IC chip position (12) has a reverse side (20B); the back side (20B) of the IC chip layer (12) is stacked on the carrier chip layer (14); the IC chip layer (12) further comprises an IC plating (18) on the back (20B) thereof; and the IC plating (18) comprises an IC plating body (50) and at least one IC capacitor terminal area which is electrically isolated from the IC plating body (50) by at least one IC capacitor opening (54). [2] Electronic device (10) according to claim 1, wherein the IC chip layer (12) comprises a monolithic integrated microwave circuit (MMIC). [3] Electronic device (10) according to claim 1, wherein the IC chip layer (12) is connected to the carrier chip layer (14). [4] Electronic device (10) according to claim 1, wherein the IC chip layer (12) comprises conductive vias extending from a top to a bottom of the IC chip layer. [5] Electronic device (10) according to claim 1, wherein the first thermally conductive material comprises silicon. [6] Electronic device (10) according to claim 1, wherein the second thermally conductive material comprises copper. [7] Electronic device (10) according to claim 1, wherein the at least one thermal via (36) comprises several thermal vias (36). [8] Electronic device (10) according to claim 7, wherein the plurality of thermal vias (36) are structured in a two-dimensional array. [9] Electronic device (10) according to claim 7, wherein the IC chip location (12) comprises a plurality of amplifiers (25); wherein the plurality of thermal vias (36) is aligned with each of the plurality of amplifiers (25) of the IC chip layer (12). [10] Electronic device (10) according to claim 7, wherein a first section of the plurality of thermal vias (36) is aligned with each amplifier (25) of the IC chip layer (12) and a second section of the plurality of thermal vias (36) is not aligned with any amplifier (25) of the IC chip layer (12). [11] Electronic device (10) according to claim 1, wherein the at least one capacitor (38) comprises a plurality of capacitors (38). [12] Electronic device (10) according to claim 1, wherein the at least one capacitor (38) comprises a deep-trench capacitor. [13] Electronic device (10) according to claim 1, wherein the at least one capacitor (38) comprises a plurality of deep-trench capacitors. [14] Electronic device (10) according to claim 1, wherein the IC plating (18) comprises at least one of gold or tin. [15] Electronic device (10) according to claim 1, wherein the carrier chip layer (14) comprises a carrier plating (33) on an active side of the substrate (32); wherein the carrier plating (33) comprises a carrier plating body (56) and at least one carrier capacitor connection surface (56) which is electrically insulated from the carrier plating body (56) by a carrier capacitor opening (58). [16] Electronic device (10) according to claim 15, wherein the carrier plating (33) comprises gold or tin. [17] Electronic device (10) according to claim 1, wherein the carrier chip layer (14) comprises a conductive carrier plating (33) on an active side of the substrate (32); wherein the carrier plating (33) comprises a carrier plating body (56) and at least one carrier capacitor connection surface (56) which is electrically insulated from the carrier plating body (56) by at least one carrier capacitor opening (58); wherein the at least one IC capacitor connection area (52) is aligned with the at least one carrier capacitor connection area (56) and electrically coupled. [18] Electronic device (10) according to claim 17, wherein the at least one IC capacitor terminal area (52) comprises a plurality of IC capacitor terminal areas (52); and wherein the at least one carrier capacitor terminal area (56) comprises a plurality of IC capacitor terminal areas. [19] Electronic device (10) according to claim 17, wherein the at least one IC capacitor terminal area and the at least one carrier capacitor terminal area define a positive terminal of at least one capacitor (38) and the IC plating body (50) and the carrier plating body (56) define a negative terminal of the at least one capacitor (38).

Images