METAL GATES STRUCTURE AND METHOD FOR ITS MANUFACTURING

Abstract

Method (100) for manufacturing a semiconductor device (200), comprising: Creating a gate trench (250) over a semiconductor substrate (202); Deposition of a dielectric gate layer (252) and an exit working layer (254) in the gate groove (250); Separation of a capping layer (256) over the exit working layer (254); Passivating a surface part of the capping layer (256) to produce a passivation layer (258); Removal of the passivation layer (258); Deposition of a fill layer (262) in the gate trench (250); Recess of the filler layer (262) and the capping layer (256); and Forming a metallic contact layer (272) over the capping layer (256) in the gate trench (250).

Description

background

[0001] The IC (integrated semiconductor circuit) industry has experienced exponential growth. Technological advances in IC materials and designs have produced generations of ICs, each generation featuring smaller and more complex circuits than the previous one. Throughout IC evolution, feature density (i.e., the number of interconnected devices per unit area of ​​the chip) has generally increased, while feature size (i.e., the smallest component or trace that can be produced using a manufacturing process) has decreased. This miniaturization process generally offers advantages by increasing production efficiency and reducing associated costs. However, this miniaturization has also increased the complexity of machining and manufacturing ICs.

[0002] One advancement realized with shrinking technology nodes is the replacement of a polysilicon gate with a metal gate in some IC designs to improve device performance at smaller feature sizes. A method for fabricating a metal gate is called a substitute-gate process or "gate-last process," in which the metal gate is fabricated last, allowing for fewer subsequent processes. A gate-last process may include a metal gate gap-filling process and a metal gate back-etching process. In the metal gate gap-filling process, various metal layers, such as exit work metal layers and metallic filler layers, are sequentially deposited in a gate trench created at a location reserved by a dummy gate.In the metal-gate back-etch process, the various layers fabricated in the gate groove are back-etched to save space for the gate metal cap. However, there are challenges in implementing these IC fabrication processes, particularly with miniaturized IC structural elements in modern process nodes. One problem is that voids, often referred to as seams due to their generally high aspect ratio, can become trapped in the gate groove during the metal-gate gap-filling process. These voids can lead to penetration defects during the metal-gate back-etch process and result in poor gate metal cap growth. While current methods are satisfactory in many respects, further improvements in metal-gate fabrication are still needed as transistor dimensions continue to shrink and advance into the sub-10 nm technology range.

[0003] Transistor devices with metal gates and associated manufacturing processes are known, for example, from US 2018 / 0 175 201 A1 and US 2017 / 0 125 536 A1. Brief description of the drawings

[0004] The present invention is best understood with reference to the detailed description below in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various elements are not drawn to scale and serve only for illustrative purposes. Rather, for the sake of clarity, the dimensions of the various elements may be arbitrarily enlarged or reduced. Fig. Figure 1 shows a perspective view of a multigate transistor according to some embodiments. Fig. Figure 2 shows a flowchart of an exemplary method for manufacturing a multigate transistor device according to some embodiments. The Fig. Figures 3 to 20 show sectional views of an exemplary multigate transistor device according to some embodiments, which were developed using the method of Fig. 2 is produced during various stages of production. The Fig. 21, Fig. 22 and Fig. Figure 23 shows sectional views of another exemplary multigate transistor device according to some embodiments. Fig. Figure 24 shows a sectional view of yet another exemplary multigate transistor device according to some embodiments. Detailed description

[0005] The present invention provides methods for manufacturing a semiconductor device with the features of claim 1 and 11, as well as a semiconductor device with the features of claim 18. Exemplary embodiments are specified in the dependent claims.

[0006] The disclosure below provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element over or on top of a second element in the description below may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present disclosure.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe a relationship between the various designs and / or configurations discussed.

[0007] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of one element or structural element to one or more other elements or structural elements depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90° or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.Furthermore, when a number or range of numbers is described using terms like "approximately," "about," or similar, the term should include numbers that lie within ±10% of the specified number, unless otherwise stated. For example, the phrase "approximately 5 nm" covers a dimensional range from 4.5 nm to 5.5 nm.

[0008] In some embodiments of the present disclosure, an improved metal gate fabrication process is provided, which can be used in one of several device types. For example, gate stacks suitable for use in the following devices can be fabricated using embodiments of the present disclosure: in planar metal-oxide-semiconductor field-effect transistors (MOSFETs), (planar or vertical) multigate transistors, such as FinFET devices, gate-all-around transistor devices (GAA transistor devices), vertical transistor devices, as well as in strained semiconductor devices, silicon-on-insulator devices (SOI devices), partially depleted SOI devices, fully depleted SOI devices, or the like. Furthermore, embodiments described herein can be used in the fabrication of p- and / or n-type devices.

[0009] As transistor dimensions continue to shrink, penetrating into the sub-10 nm technology node range and below, a gate trench reserved by a dummy gate over a fin-like structure—comprising a fin for a FinFET device or a stack of channel layers for a GAA device—can have a high aspect ratio and / or a constriction profile. Throughout this description, the terms "fin-like structure" and "fin" are used interchangeably for simplicity.

[0010] The fins can be structured using a suitable process. For example, the fins can be structured using one or more photolithography processes, such as dual or multiple structuring processes. Dual or multiple structuring processes combine photolithography and self-aligning processes, enabling the creation of structures with pitches smaller than those achievable with a single direct photolithography process. For instance, in one embodiment, a sacrificial layer is produced over a substrate and then structured using a photolithography process. Spacers are produced along the structured sacrificial layer using a self-aligning process. Subsequently, the sacrificial layer is removed, and the remaining spacers can then be used to structure the fins.

[0011] When different metal layers are deposited sequentially in the gate trench, seams (or voids) can easily become trapped in the gate trench due to the high aspect ratio and / or constriction profile. During the metal gate back-etching process, etchants can seep into the seams, causing uneven etching of the metal layers and resulting in penetration defects and poor growth of the gate metal cap. In some embodiments, after the deposition of a capping layer over an exit work metal (WFM) layer, a gradient passivation process (e.g., a gradient oxidation process) is performed to passivate a surface portion of the capping layer. Due to the gradient passivation process, the passivated surface portion has a greater thickness near the gate trench opening and a smaller thickness near the bottom of the gate trench.The passivated surface portion is then removed in a selective etching process. Removing this passivated surface transforms the previous constriction profile of the gate groove into a U-shaped (V-shaped) profile with an enlarged opening. This enlarged opening facilitates the subsequent deposition of a gap-filling layer to fill the gate groove without (or with fewer) embedded seams. The proposed metal gate fabrication process improves the uniformity and integrity of the gate metal layers, resulting in better transistor performance.

[0012] Fig. Figure 1 shows an example of a multigate transistor, such as a FinFET 10, in a perspective view. The FinFET 10 has a substrate 50 and a fin 64 that extends beyond the substrate 50. Insulation regions 62 are created on opposite sides of the fin 64, with the fin 64 extending beyond these insulation regions 62. A gate dielectric 66 is arranged along side walls and over a top surface of the fin 64, and a gate 68 is arranged over the gate dielectric 66. Source / drain regions 80 are arranged in the fin 64 and on opposite sides of the gate dielectric 66 and the gate 68. "Source / drain regions" can refer to a source or a drain individually or collectively, depending on the context. Fig. Figure 1 also shows reference cross-sections that will be used in later figures. A cross-section B-B runs along a longitudinal axis of the gate 68 of the FinFET 10. A cross-section A-A is perpendicular to the cross-section B-B and runs along a longitudinal axis of the fin 64 and, for example, in a direction of current flow between the source / drain regions 80. For clarity, later figures refer to these reference cross-sections.

[0013] Fig. Figure 2 shows a flowchart of a method 100 for fabricating a non-planar transistor device according to one or more embodiments of the present disclosure. For example, at least some of the operations of method 100 can be used to fabricate a FinFET device, a GAA transistor device, a vertical transistor device, or the like. It should be noted that method 100 is merely an example and is not intended to limit the present disclosure. It is therefore understood that further operations before, during, and after method 100 may be performed. Fig. 2 can be provided for and some other operations may only be briefly described here. In some embodiments, operations of method 100 may be associated with sectional views of an exemplary semiconductor device 200 (or device 200) at various manufacturing stages, which are shown in the Fig. Figures 3 to 24 are shown and will be described in more detail later.

[0014] The Fig. Figures 3 to 24 each show a sectional view of a part of the device 200 at different stages of the process 100. Fig. 2. In the illustrated embodiments, the device 200 is the one described in Fig. The device 200 is similar to the FinFET device 10 shown in Figure 1, in which a channel region of a transistor is provided by a fin that protrudes continuously from a substrate. In various other embodiments, the device 200 can be a transistor with a channel region provided by a plurality of nanolayers or nanowires stacked vertically on top of each other over a substrate, such as a GAA transistor. Fig. Figures 3 to 6 show sectional views of the device 200 along cross-section B - B. Fig. Figures 7 to 24 show sectional views of the device 200 along cross-section A - A.

[0015] According to an operation 102 of Fig. 2 is Fig. Figure 3 shows a sectional view of the device 200 at one of the various fabrication stages, which includes a semiconductor substrate 202. The substrate 202 can be a semiconductor substrate, such as a solid semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The substrate 202 can be a wafer, such as a silicon wafer. In general, an SOI substrate comprises a layer of semiconductor material fabricated on an insulating layer. The insulating layer can be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is fabricated on a substrate, usually a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, can also be used.In some embodiments, the semiconductor material of substrate 202 may comprise: silicon; germanium; a compound semiconductor, such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.

[0016] According to operation 104 of Fig. 2 is Fig. Figure 4 shows a sectional view of the device 200 at one of the various manufacturing stages, which has a (semiconductor) fin 204. In the illustrated embodiment of Fig. Although only one fin is shown in Figure 4 (and in the following figures), it is understood that the device 200 can have any number of fins without deviating from the scope of protection of this disclosure. In some embodiments, the fin 204 is produced by structuring the substrate 202, for example, using photolithography and etching processes. For example, a mask layer, such as a pad oxide layer 206 and an overlying pad nitride layer 208, is produced over the substrate 202. The pad oxide layer 206 can be a thin layer containing silicon oxide, which is produced, for example, by a thermal oxidation process. The pad oxide layer 206 can act as an adhesive layer between the substrate 202 and the overlying pad nitride layer 208. In some embodiments, the pad nitride layer 208 consists of silicon nitride, silicon oxide nitride, silicon carbonitride, or the like, or a combination thereof.The pad nitride layer 208 can be produced, for example, by low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0017] The mask layer can be patterned using photolithography. Generally, photolithography uses a photoresist material (not shown) that is deposited, irradiated (exposed), and developed to remove some of the photoresist. The remaining photoresist protects the underlying material, such as the mask layer in this example, from subsequent processing steps, such as etching. In this example, the photoresist is used to pattern the pad oxide layer 206 and the pad nitride layer 208 to create a patterned mask 210, as shown in Fig. 4 is shown.

[0018] The structured mask 210 is then used to structure exposed parts of the substrate 202 to create trenches (or openings) 212, thereby defining a fin 204 between adjacent trenches 212, as shown in Fig. Figure 4 shows that when several fins 204 are produced, such a groove can be arranged between adjacent fins 204. In some embodiments, the fin 204 is produced by etching grooves in the substrate 202, for example, by reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. The etching process can be anisotropic. In some embodiments, the grooves 212 can be strips (viewed from above) that are parallel to each other and arranged close together. In some embodiments, the grooves 212 can be continuous and enclose the fin 204.

[0019] The fin 204 can be structured using a suitable process. For example, the fin 204 can be structured using one or more photolithography processes, such as dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithography and self-aligning processes, enabling the creation of structures with, for example, pitches smaller than those achievable with a single direct photolithography process. For example, in one embodiment, a sacrificial layer is produced over a substrate and then structured using a photolithography process. Spacers are produced along the structured sacrificial layer using a self-aligning process. Subsequently, the sacrificial layer is removed, and the remaining spacers, or mandrels, can then be used to structure the fin.

[0020] According to one operation, 106 of Fig. 2 is Fig. Figure 5 shows a sectional view of the device 200 at one of the various manufacturing stages, which has insulation areas 214. The insulation areas 214, which are made of an insulating material, can electrically insulate adjacent fins from one another. The insulating material can be an oxide, such as silicon dioxide, a nitride, or the like, or a combination thereof, and can be deposited by high-density plasma deposition (HDP-CVD), flowable fluid deposition (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing to convert to another material, such as an oxide), or the like, or a combination thereof. Other insulating materials and / or other manufacturing processes can also be used. In the embodiment shown, the insulating material is silicon dioxide, which is deposited by an FCVD process. After the insulating material has been deposited, a tempering process can be carried out.Excess insulating material can be removed by a planarization process, such as chemical-mechanical polishing (CMP), and coplanar top surfaces of the insulation areas 214 and a top surface of the fin 204 can be produced (not shown; the insulation areas 214 are recessed, as in ). Fig. 5 is shown). The structured mask 210 ( Fig. 4) can also be removed using the planarization process.

[0021] In some embodiments, the insulation regions 214 have a coating, e.g., an oxide coating (not shown), at the interface between the insulation region 214 and the substrate 202 (fin 204). In some embodiments, the oxide coating is produced to reduce crystal defects at the interface between the substrate 202 and the insulation region 214. Likewise, the oxide coating can be used to reduce crystal defects at the interface between the fin 204 and the insulation region 214. The oxide coating (e.g., silicon dioxide) can be a thermal oxide produced by thermal oxidation of a surface layer of the substrate 202, but other suitable methods for producing the oxide coating can also be used.

[0022] The insulation areas 214 are then recessed to create STI areas 214 (STI: shallow trench insulation). The insulation areas 214 are recessed such that the upper portions of the fin 204 protrude between adjacent STI areas 214. The top surfaces of the STI areas 214 can have a flat surface (as shown), a convex surface, a concave surface (such as "dishing"), or a combination thereof. The top surfaces of the STI areas 214 can be produced flat, convex, and / or concave by suitable etching. The insulation areas 214 can be recessed using a suitable etching process, such as one that is selective for the material of the insulation areas 214. For example, dry etching or wet etching using dilute hydrofluoric acid (dHF acid) can be performed to recess the insulation areas 214.

[0023] The Fig. Figures 3 to 5 show an embodiment for producing one or more fins (such as fin 204), but the fins can also be produced by various other methods. For example, an upper part of the substrate 202 can be replaced by a suitable material, such as an epitaxial material, which is suitable for a desired doping type (e.g., n- or p-type) of semiconductor devices to be produced. Subsequently, the substrate 202 is patterned with the epitaxial material to produce the fin 204, which incorporates the epitaxial material.

[0024] As another example, a dielectric layer can be produced over the top surface of a substrate; trenches can be etched through the dielectric layer; homoepitaxial structures can be grown epitaxially in the trenches; and the dielectric layer can be recessed so that the homoepitaxial structures protrude from the dielectric layer and form one or more fins.

[0025] In yet another example, a dielectric layer can be produced over the top surface of a substrate; trenches can be etched through the dielectric layer; heteroepitaxial structures can be grown epitaxially in the trenches using a material different from the substrate; and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer and form one or more fins.

[0026] In embodiments where one or more epitaxial materials or structures (e.g., the heteroepitaxial structures or the homoepitaxial structures) are grown, the one or more grown materials or structures can be doped in situ during growth, thus eliminating the need for prior and subsequent implantations. However, in-situ and implantation doping can also be used together. Furthermore, it can be advantageous to epitaxially grow a material in an NMOS region that is different from a material in a PMOS region. In various embodiments, the fin can be silicon germanium (Si₂O₆). x Ge 1-x, where x can be 0 to 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. Materials that can be used to fabricate the III-V compound semiconductor include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

[0027] According to one operation, 108 of Fig. 2 is Fig. Figure 6 shows a sectional view of the device 200 at one of the various manufacturing stages, which has a dummy gate structure 220. In some embodiments, the dummy gate structure 220 has a dummy gate dielectric 202 and a dummy gate electrode 224. A mask 226 can be produced over the dummy gate structure 220. To produce the dummy gate structure 220, a dielectric layer is produced on the fin 204. The dielectric layer can, for example, comprise silicon oxide, silicon nitride, multilayers thereof, or the like, and it can be deposited or thermally grown.

[0028] A gate electrode layer is deposited over the dielectric layer, and a mask layer is deposited over the gate electrode layer. The gate electrode layer can be deposited over the dielectric layer and then planarized, for example, using a CMP. The mask layer can then be deposited over the gate electrode layer. The gate electrode layer can be made of polysilicon, for example, but other materials can also be used. The mask layer can be made of silicon nitride or a similar material, for example.

[0029] After the layers (e.g., the dielectric layer, the gate electrode layer, and the mask layer) have been fabricated, the mask layer can be structured using suitable photolithography and etching techniques to produce the mask 226. The structure of the mask 226 can then be transferred to the gate electrode layer and the dielectric layer using a suitable etching technique to produce the dummy gate electrode 224 and the underlying dummy gate dielectric 222, respectively. The dummy gate electrode 224 and the dummy gate dielectric 222 cover a central portion (e.g., a channel region) of the fin 204. The dummy gate electrode 224 can also have a longitudinal orientation (e.g., the B-B direction of the fin). Fig. 1) have which are essentially perpendicular to a longitudinal direction (e.g. the direction A - A of Fig. 1) the Finn is 204.

[0030] In the example of Fig. Figure 6 shows that the dummy gated dielectric 222 is produced above the fin 204 (e.g., above a top surface and side walls of the fin 204) and above the STI areas 214. In other embodiments, the dummy gated dielectric 222 can be produced, for example, by thermal oxidation of a material of the fin 204, and it can therefore be produced above the fin 204 but not above the STI areas 214. It is understood that these and further modifications are also within the scope of protection of the present disclosure.

[0031] The Fig. Figures 7 to 24 show sectional views of a further machining of the device 200 along the cross-section A - A (along a longitudinal axis of the fin 204).

[0032] According to one operation, 110 of Fig. 2 is Fig. Figure 7 shows a sectional view of the device 200 at one of the various fabrication stages, which has several lightly doped drain regions (LDD regions) 230 that are created in the fin 204. The LDD regions 230 can be created by a plasma doping process. The plasma doping process can include the fabrication and structuring of masks, such as a photoresist, to cover the areas of the device 200 that are to be protected from the plasma doping process. In the plasma doping process, n- or p-doping agents can be implanted into the fin 204 to create the LDD regions 230. For example, p-doping agents such as boron can be implanted into the fin 204 to create LDD regions 230 for a p-type device. As another example, n-doping agents such as phosphorus can be implanted into the fin 204 to create LDD regions 230 for an n-device.In some embodiments, the LDD areas 230 border one of the channel areas of the device 200 (e.g., the central part of the fin 204, which is covered by one of the dummy gate structures 220). Parts of the LDD areas 230 may extend under the dummy gate structure 220 and into the channel area of ​​the device 200. Fig. Figure 7 shows a non-limiting example of the LDD regions 230. Other configurations, shapes, and manufacturing processes for the LDD regions 230 are also possible and are intended to be entirely within the scope of protection of this disclosure. For example, the LDD regions 230 can be generated after the fabrication of gate spacers 232. In some embodiments, the LDD regions 230 are omitted.

[0033] Let's stay with Fig. 7. After the LDD areas 230 have been created, in some embodiments first gate spacers 234 are produced around the dummy gate structures 220 (e.g., along and in contact with side walls of the dummy gate structures 220), and second gate spacers 236 are produced around the first gate spacers 234 (e.g., along and in contact with side walls of the first gate spacers 234). The first gate spacers 234 can, for example, be produced on opposite side walls of the dummy gate structure 220. The second gate spacers 236 can be produced on the first gate spacers 234. It is understood that any number of gate spacers can be produced around the dummy gate structures 220 without deviating from the scope of protection of this disclosure. The first gate spacer 234 and the second gate spacer 236 are collectively referred to as gate spacer 232.The shapes and manufacturing processes for the gate spacers 232, which are in . Fig. Figure 7 (and the following figures) are merely non-limiting examples, and other forms and manufacturing processes are also possible. These and further variations are intended to be entirely within the scope of protection of the present disclosure.

[0034] The first gate spacer 234 can be a low-k spacer made of a suitable dielectric material such as silicon oxide, silicon oxide carbonitride, or the like. The second gate spacer 236 can be made of a nitride such as silicon nitride, silicon oxide nitride, silicon carbonitride, or the like, or a combination thereof. A suitable deposition process such as thermal oxidation, CVD, or the like can be used to fabricate the first gate spacer 234 and the second gate spacer 236. In various embodiments, the first gate spacer 234 and the second gate spacer 236 can be made of different materials to allow for etch selectivity during subsequent processing.

[0035] According to operation 112 of Fig. 2 is Fig. Figure 8 shows a sectional view of the device 200 at one of the various manufacturing stages, which has several source / drain regions 238. The source / drain regions 238 are created in recesses of the fin 204 adjacent to the dummy gate structures 220. For example, the source / drain regions 238 and the dummy gate structures 220 are arranged alternately. In other words, a source / drain region 238 is arranged between adjacent dummy gate structures 220, and / or only one side of the source / drain region 238 is located next to a dummy gate structure 220. In some embodiments, the recesses are created, for example, by an anisotropic etching process using the dummy gate structures 220 as an etching mask, but another suitable etching process can also be used.

[0036] The source / drain regions 238 are generated by epitaxial growth of a semiconductor material in the recess using suitable methods such as metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid-phase epitaxy (LPE), vapor-phase epitaxy (VPE), selective epitaxial growth (SEG) or the like or a combination thereof.

[0037] As in Fig. As shown in Figure 8, the epitaxial source / drain regions 238 can have surfaces that are raised relative to the respective surfaces of the fins 204 (e.g., projecting beyond the non-recessed portions of the fin 204), and they can have chamfers. In some embodiments, the source / drain regions 238 of adjacent fins can merge to form a continuous epitaxial source / drain region (not shown). In some embodiments, the source / drain regions 238 of adjacent fins may not merge and may remain separate source / drain regions 238 (not shown). In some embodiments, if the resulting device is an n-transistor, the source / drain regions 238 may comprise silicon carbide (SiC), silicon phosphorus (SiP), phosphorus-doped silicon carbon (SiCP), or the like.In some embodiments, if the resulting device is a p-transistor, the source / drain regions may contain 238 SiGe and a p-doping material such as boron or indium.

[0038] The epitaxial source / drain regions 238 can be implanted with dopants to create the source / drain regions 238, and subsequently a tempering process can be performed. The implantation process can include the fabrication and structuring of masks, such as a photoresist, to cover the areas of the device 200 that are to be protected during the implantation process. The source / drain regions 238 can have a doping concentration of approximately 1 × 10 19 cm -3 up to about 1 × 10 21 cm -3P-type dopants, such as boron or indium, can be implanted into the source / drain region 238 of a p-type transistor. N-type dopants, such as phosphorus or arsenic, can be implanted into the source / drain region 238 of an n-type transistor. In some embodiments, the epitaxial source / drain regions 238 can be doped in situ during growth.

[0039] According to one operation, 114 of Fig. 2 is Fig. Figure 9 shows a sectional view of the device 200 at one of the various manufacturing stages, which includes an intermediate layer dielectric (ILD) 240. In some embodiments, a contact etch stop layer (CESL) 242 is applied over the ILD 240 prior to its fabrication. Fig. The structure shown in Figure 9 is produced. The CESL 242 can function as an etch stop layer in a subsequent etching process, and it can comprise a suitable material such as silicon oxide, silicon nitride, silicon oxide nitride, combinations thereof or the like, and be produced using a suitable manufacturing process such as CVD, PVD, combinations thereof or the like.

[0040] The ILD 240 is then fabricated over the CESL 242 and the dummy gate structure 220. In some embodiments, the ILD 240 consists of a dielectric material such as silicon dioxide, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), or the like, and can be deposited using a suitable method such as CVD, PECVD, or FCVD. After the ILD 240 has been deposited, a dielectric layer 246 is fabricated over it. The dielectric layer 246 can function as a protective layer to prevent or reduce the loss of the ILD 240 in subsequent etching processes. The dielectric layer 246 can be fabricated from a suitable material such as silicon nitride, silicon carbonitride, or the like using a suitable method such as CVD, PECVD, or FCVD.After the dielectric layer 246 has been fabricated, a planarization process, such as a CMP process, can be performed to achieve a flat top surface for the dielectric layer 246. The CMP process can also remove the mask 226 and parts of the CESL 242 located above the dummy gate electrode 224. After the planarization process, in some embodiments, the top surface of the dielectric layer 246 is flush with the top surface of the dummy gate electrode 224.

[0041] Subsequently, an exemplary gate-load process (occasionally referred to as a replacement-gate process) is carried out to replace the dummy-gate electrode 224 and dummy-gate dielectric 222 of the dummy-gate structure 220 with a metal gate (which may also be referred to as a replacement gate or an active gate).

[0042] According to one operation, 116 of Fig. 2 is Fig. 10 a sectional view of the device 200 at one of the various manufacturing stages, in which the dummy gate structure 220 ( Fig. 9) is removed to create a gate trench 250. During the removal of the dummy gate structure 220, the first gate spacer 234 and the second gate spacer 236 can also be partially etched, so that an upper part of the gate trench 250 is widened horizontally by removing relatively upper portions of the first gate spacer 234 and the second gate spacer 236. The resulting gate trench 250 comprises an upper trench 250U and a lower trench 250L, the upper trench 250U being horizontally wider than the lower trench 250L. Details of the creation of the gate trench 250 will be discussed later.

[0043] In some embodiments, one or more etching steps are performed to remove the dummy gate structure 220, specifically to remove the dummy gate electrode 224 and the dummy gate dielectric 222 directly beneath the dummy gate electrode 224, creating trenches 250 (which can also be referred to as recesses) between the respective first gate spacers 234. The gate trench 250 exposes the channel area of ​​the fin 204. During dummy gate removal, the dummy gate dielectric 222 can be used as an etch stop layer when the dummy gate electrode 224 is etched. After removal of the dummy gate electrode 224, the dummy gate dielectric 222 can also be removed.

[0044] Then, an anisotropic etching process, such as a dry etching process, is performed to remove upper portions of the first gate spacer 234. In some embodiments, the anisotropic etching process is performed using an etchant that is selective with respect to the material of the first gate spacer 234 (e.g., has a higher etch rate for it), so that the first gate spacer 234 is recessed (e.g., upper portions are removed). The recessed first gate spacer 234 exposes the upper sidewalls of the second gate spacer 236. Due to the limited etch selectivity of the etchant, the second gate spacer 236 may also experience etch loss, resulting in the exposed upper sidewalls being recessed laterally. The lateral recess of the exposed upper side walls of the second gate spacer 236, for example, may not be uniform due to charging effects. As in Fig. As shown in Figure 10, a portion of the exposed upper side walls of the second gate spacer 236, located in the middle of the gate trench 250, is laterally more deeply recessed than other parts.

[0045] As in Fig. As shown in Figure 10, after the removal of the upper parts of the first gate spacers 234, the gate trench 250 has an upper trench 250U and a lower trench 250L. The lower trench 250L is located between the remaining lower parts of the first gate spacer 234. The upper trench 250U is located above the lower trench 250L and is defined (e.g., bounded) by the exposed upper side walls of the second gate spacer 236. The gate trench 250 has a wider upper trench 250U and a narrow lower trench 250L, resembling the letter "Y", and therefore the gate trench 250 may occasionally be referred to as a Y-shaped gate trench.

[0046] In some embodiments, the upper trench 250U has a width W1 (i.e., a distance between respective opposing upper side walls of the second gate spacer 236) at its uppermost part of about 18 nm to about 23 nm, a width W2 at its largest opening (W2 > W1) of about 20 nm to about 25 nm, and a depth H1 (i.e., a distance between a top surface of the second gate spacer 236 and the uppermost part of the first gate spacer 234) of about 30 nm to about 80 nm. The lower trench 250L has a width W3 (i.e., a distance between respective opposing side walls of the remaining lower parts of the first gate spacer 234) of about 5 nm to about 10 nm (W2 > W1 > W3) and a depth H2 (i.e., a distance between a bottom surface of the gate trench 250 and the uppermost part of the first gate spacer 234) of about 30 nm to about 80 nm. Gate spacer 234) from about 60 nm to about 100 nm.As will be explained later, in some embodiments a metal gate is produced in the lower trench 250L. For example, a gate electrode material is used to fill the upper trench 250U and the lower trench 250L, which is then recessed to hold the gate electrode of the metal gate in the lower trench 250L. Therefore, the size of the lower trench 250L can determine the size of the metal gate and the size of the gate electrode. However, the constriction profile of the upper trench 250U can cause seams to be trapped in the gate trench, leading to uneven etching during the recessing of the metal gate and thus to penetration defects.

[0047] According to one operation, 118 of Fig. 2 is Fig. Figure 11 shows a sectional view of the device 200 at one of the various manufacturing stages, which has a dielectric gate layer 252. In some embodiments, the dielectric gate layer 252 is conformally deposited in the gate groove 250, such as on the tops and side walls of the fin 204, on the tops and side walls of the gate spacers 232, and on a top surface of the dielectric layer 246. In some embodiments, the dielectric gate layer 252 comprises silicon oxide, silicon nitride, or multilayers thereof. In exemplary embodiments, the dielectric gate layer 252 comprises a high-k dielectric material, and in these embodiments, the dielectric gate layer 252 may have a k-value greater than about 7.0, and it may comprise a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof.Molecular beam epitaxy (MBD), atomic layer deposition (ALD), PECVD, and similar processes can be used as manufacturing methods for the dielectric gate layer 252. The thickness of the dielectric gate layer 252 can range, for example, from approximately 0.8 nm to approximately 2.0 nm.

[0048] According to one operation, 120 of Fig. 2 is Fig. Figure 12 shows a sectional view of the device 200 at one of the various manufacturing stages, which has an exit work layer 254. The exit work layer 254 is produced (e.g., conformally) over the dielectric gate layer 252. In some embodiments, the exit work layer 254 may comprise a p-exit work layer, an n-exit work layer, multiple layers thereof, or combinations thereof. Here, an exit work layer may also be referred to as an exit work metal. Exemplary p-exit work metals that may be used in the gate structures for p-devices are TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-exit work materials, or combinations thereof.Exemplary n-exit work metals that can be used in the gate structures for n-devices are Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-exit work materials, or combinations thereof. An exit work value is associated with the material composition of the exit work layer, and therefore the exit work layer material is selected such that its exit work value can be adjusted to achieve a target threshold voltage Vt in the device being manufactured. The one or more exit work layers can be deposited by CVD, physical vapor deposition (PVD), and / or another suitable method. For example, the thickness of a p-exit work layer can be approximately 0.8 nm to approximately 1.5 nm, and the thickness of an n-exit work layer can be approximately 1.5 nm to approximately 3.0 nm.

[0049] According to one operation, 122 of Fig. 2 is Fig. Figure 13 shows a sectional view of the device 200 at one of the various manufacturing stages, which has a capping layer 256. The capping layer 256 is produced (e.g., conformally) over the exit working layer 254. The capping layer 256 protects the underlying exit working layer 254 from oxidation. The capping layer 256 can be made of a suitable material such as Ta, TaN, Ti, TiN, or TiSiN. In some embodiments, the capping layer 256 is made of TiN. The capping layer 256 can be deposited using a suitable deposition method such as ALD, MBD, CVD, or the like. The thickness of the capping layer 256 can be, for example, about 2 nm to about 5 nm. In some embodiments, the thickness of the capping layer 256 is greater than the thickness of the exit working layer 254 or the thickness of the dielectric gate layer 252.Furthermore, in some embodiments the thickness of the capping layer 256 is greater than the sum of the thicknesses of the exit working layer 254 and the dielectric gate layer 252, as in the example of . Fig. Figure 13 shows that, depending on the width W3 of the lower trench 250L and the thickness of the layers previously produced in the gate trench 250, the capping layer 256 can fill the remaining parts of the lower trench 250L. Depending on the widths W1 and W2 of the upper trench 250U and the layers previously produced in the gate trench 250, the space remaining in the gate trench 250 can have a teardrop shape with a narrow opening at the top and a wider opening in the middle, as in the example shown in Figure 13. Fig. Figure 13 shows that if one or more additional layers are deposited in the gate trench 250, the opening width W1 will soon decrease, and seams will be trapped underneath, which can lead to defects during manufacturing, as explained above.

[0050] According to one operation, 124 of Fig. 2 is Fig. Figure 14 shows a sectional view of the device 200 at one of the various manufacturing stages, which has a passivation layer 258 that has been converted from an upper part of the capping layer 256. In some embodiments, the capping layer 256 is a metal or a metal nitride (e.g., Ta, TaN, Ti, TiN, or TiSiN), and the passivation layer 258 is an oxide layer produced by oxidizing the capping layer 256 with a suitable oxidation process, including, but not limited to, air oxidation (i.e., by contact with air), an oxygen plasma process (a plasma treatment with O2 and / or O3 as oxidizing species), or thermal wet or dry oxidation. In some embodiments, the capping layer 256 is a metal (e.g. Ta or Ti), and the passivation layer 258 is a nitride layer produced by nitriding using an NH3 or (N2 + H2) plasma.In an exemplary process, the capping layer 256 is a TiN layer deposited in a deposition chamber and subsequently treated with an oxygen plasma in a warm environment at a temperature of 25 °C to 600 °C. Continuing with the example of the oxidation process, the passivation environment is controlled such that the oxidant species (O2 and / or O3) have a higher concentration on the top of the device 200, decreasing in a gradient with distance from the top of the device to the bottom of the gate trench 250. As a result, a thicker surface portion of the capping layer 256 is oxidized closer to the top of the device 200. The thickness of the oxidized capping layer 256 (the thickness of the passivation layer 258) decreases in a gradient downwards into the gate trench 250. Accordingly, the oxidation process is also referred to as a gradient oxidation process.Similarly, in a nitration process, the thickness of the nitrated capping layer 256 decreases downwards in a gradient into the gate trench 250. This passivation process is also collectively referred to as a gradient passivation process. In one example, the portions of the capping layer 256 that are deposited outside the gate trench 250 are completely transformed into the passivation layer 258, as shown in [reference]. Fig. 14 is shown.

[0051] According to one operation, 126 of Fig. 2 is Fig. Figure 15 shows a sectional view of the device 200 at one of the various manufacturing stages after removal of the passivation layer 258. In some embodiments, the passivation layer 258 is removed in an etching process, such as a metal halide etching (MHE) process. An MHE process is a dry etching process that uses a metal halide etchant (e.g., a chlorine- or fluorine-based etchant). The MHE process can efficiently remove an overhang at the upper corners of an opening due to a higher reactant molecule density and a large contact area with reactant molecules at the upper corners. The MHE process can be performed in situ (e.g., in the same chamber as the deposition process in Operation 122 and the passivation process in Operation 124).In some embodiments, the chlorine- or fluorine-based metal precursor for the MHE process can be tungsten fluoride (WF6), tungsten chloride (WCl5), molybdenum pentachloride (MoCl5), titanium chloride (TiCl). x ), titanium fluoride (TiF x The etchant(s) can be tantalum chloride (TaCl5) or a combination thereof. Other suitable precursors may also be used. The MHE process can be carried out at temperatures ranging from approximately 200 °C to approximately 1000 °C. The one or more etchants used in the MHE process can be applied at a throughput of approximately 100 Ncm³. 3 / min up to 12,000 Ncm 3The MHE process is introduced into the reaction chamber in pulses at a rate of / min. The process pressure for the MHE process can range from approximately 1 Torr to approximately 20 Torr. The MHE process can be carried out for a duration of approximately 10 s to approximately 300 s. After the gradient passivation process in Operation 124 and the etching process in Operation 126, the opening W1 of the upper trench 250U is widened. The widened upper trench 250U can have a U-shape with substantially vertical sidewalls (W1 ≈ W2), as shown in Fig. Figure 15 is shown. In another example, the widened upper trench 250U can have a V-shape with conical side walls (W1 > W2).

[0052] A thin film 260 containing the residual metal element can be produced on the former interface between the remaining capping layer 256 and the removed passivation layer 258. The thickness of the thin film 260 can be, for example, about 0.2 nm to about 1.0 nm. The residual metal element originates from the metal elements used in the metal halide etchant. For example, a thin film containing tungsten can be produced to cover the capping layer 256. In another example, a thin film containing molybdenum can be produced to cover the capping layer 256. In some embodiments, due to the complete passivation and removal of the capping layer 256 outside the gate trench 250, the thin film 260 can be in contact with the exit working layer 254 outside the gate trench 250, as shown in Fig. Figure 15 shows that the metal residue in the thin film 260 can diffuse further into the capping layer 256 at a decreasing gradient. The concentration of the metal residue drops to zero before reaching the interface between the capping layer 256 and the exit working layer 254. The thickness of the metal-containing thin film 260 can be approximately 0.1 nm to approximately 0.5 nm.

[0053] According to one operation, 128 of Fig. 2 is Fig. Figure 16 shows a sectional view of the device 200 at one of the various manufacturing stages, which includes a gap-filling layer 262 (also referred to as a trench-filling layer or filler layer 262). The gap-filling layer 262 is produced over the capping layer 256 (and the metal-containing thin film 260, if present). The gap-filling layer 262 is produced on the top surface of the device 200 and fills any remaining portion of the upper trench 250U. The gap-filling layer 262 can be produced from a suitable material such as titanium nitride, silicon nitride, tungsten, cobalt, or a combination thereof, using a suitable deposition method such as CVD, PVD, ALD, or the like. The widened upper trench 250U facilitates the deposition of the gap-filling layer 262, so that the filled upper trench 250U is essentially seam-free (or has fewer seams).In one example, the capping layer 256 and the gap-filling layer 262 have different material compositions, such as TiN in the capping layer 256 and SiN in the gap-filling layer 262. In another example, the capping layer 256 and the gap-filling layer 262 have a similar material composition, such as TiN in both layers, but a different nitrogen concentration (e.g., the nitrogen concentration is higher in the gap-filling layer 262). In yet another example, the capping layer 256 and the gap-filling layer 262 have the same material composition, but they are deposited using different methods (e.g., ALD for the capping layer 256 and CVD for the gap-filling layer 262), resulting in different particle sizes (e.g., a smaller particle size in the capping layer 256).Then, a planarization process, such as a CMP process, is performed to remove the excess portion of the gap-filling layer 262 (as well as the horizontal portions of the metal-containing thin film 260, the exit work layer 254, and the dielectric gate layer 252) to expose the top surface of the dielectric layer 246 and the gate spacers 232. The resulting structure after the planarization process is shown in . Fig. 17 shown.

[0054] According to one operation, 130 of Fig. 2 is Fig. Figure 18 shows a sectional view of the device 200 at one of the various manufacturing stages after a metal gate etching process. In some embodiments, material layers (layers 252, 254, 256, 260, and 262) in the upper trench 250U are removed by the metal gate etching process, so that the side walls of the second gate spacers 236 are again exposed. As shown in Fig. As shown in Figure 18, the remaining portions of the dielectric gate layer 252, the exit working layer 254, and the capping layer 256 are recessed beneath an uppermost portion of the first gate spacers 234. The dielectric gate layer 252, the exit working layer 254, and the capping layer 256 in the lower trench 250L can have a concave upper surface, such that an uppermost portion of the dielectric gate layer 252 is located above an uppermost portion of the exit working layer 254, which in turn is located above an uppermost portion of the capping layer 256. In some embodiments, the portions of the various layers remaining in the lower trench 250L, such as the dielectric gate layer 252, the exit working layer 254, and the capping layer 256, can at least partially form a metal gate 270.Since the metal-containing thin film 260 and the gap-filling layer 262 are produced in the upper trench 250U, the metal gate 270 can be free of the metal-containing thin film 260 and the gap-filling layer 262 after the metal gate etching process. In some embodiments, the metal gate etching process is a selective wet etching process that does not substantially attack the gate spacers 232. In some embodiments, the wet etching process is carried out using a chemical containing an acid and an oxidizing agent. The chemical used can be, for example, a mixture of hydrochloric acid (HCl) and hydrogen peroxide (H₂O₂), with HCl acting as the acid and H₂O₂ acting as the oxidizing agent. In some embodiments, the mixing ratio (e.g., a volume ratio) between HCl and H₂O₂ for the wet etching process is approximately 1:1 to 1:20.The wet etching process can be carried out at a temperature of approximately 40 °C to approximately 70 °C for a duration of approximately 1 min to approximately 5 min.

[0055] According to operation 132 of Fig. 2 is Fig. Figure 19 shows a sectional view of the device 200 at one of the various manufacturing stages, in which a metallic contact layer (also referred to as a gate metal cap) 272 is produced. The metallic contact layer 272 is produced over the recessed layers. In some embodiments, the metallic contact layer 272 contains W, Ta, Sn, Nb, Ru, Co, or Mo. In some embodiments, the metallic contact layer 272 is produced by an ALD process using metal halide gases (chloride gases) (e.g., TaCl₅, SnCl₄, NbCl₅, or MoCl₄). In some embodiments, the metallic contact layer 272 contains a fluorine-free metal, for example, fluorine-free metal W, produced with WCl₅ as the source gas.In some embodiments, the ALD process is a selective deposition process combined with an etching process, such that the metallic contact layer 272 grows selectively from metallic sublayers, such as the capping layer 256 and the exit work layer 254, and no metal layer is grown from the dielectric gate layer 252. This selective growth creates a lateral gap between the metallic contact layer 272 and the first gate spacers 234, preventing metallic elements from diffusing into the first gate spacers 234. In some embodiments, the thickness of the metallic contact layer 272 is approximately 1 nm to approximately 10 nm. In some embodiments, a top surface of the metallic contact layer 272 is located beneath the uppermost part of the first gate spacers 234.In some embodiments, the metallic contact layer 272 is thick enough that its upper surface is located above the uppermost part of the first gate spacers 234. In some embodiments, the deposition of the metallic contact layer 272 includes a cleaning operation between two or more deposition processes. In some embodiments, the cleaning operation includes hot water cleaning (e.g., at 80 °C or higher) and / or oxygen treatment.

[0056] According to operation 134 of Fig. 2 is Fig. Figure 20 shows a sectional view of the device 200 for which further manufacturing processes are carried out. For example, a gate cap insulating layer 280 is produced over the metallic contact layer 272. In some embodiments, the gate cap insulating layer 280 contains silicon nitride, SiON, SiOCN, a dielectric low-k material, or another suitable material deposited by a suitable manufacturing process such as PVD, CVD, or the like. Furthermore, a gate contact (also referred to as a contact pin) 282 is produced in the gate cap insulating layer 280 (e.g., such that it extends through it) to electrically connect it to the metallic contact layer 272. In the preceding example, where the gate cap insulating layer 280 is deposited prior to the production of the gate contact 282, for example,A contact opening is created in the gate cap insulating layer 280 by photolithography and etching to expose the metallic contact layer 272. After the contact opening has been created, a barrier layer, a seed layer, and a filler metal (not shown) are successively produced in the contact opening to create the gate contact 282.

[0057] Let's stay with Fig. 20, in which source / drain contacts 284 are produced in the ILD 240 for electrical connection to the source / drain regions 238. In some embodiments, the dielectric layer 246 and the ILD 240 are etched through by an etching process to create contact openings that expose the source / drain regions 238. A silicide element (not shown) is produced above the source / drain regions 238 in a silicide manufacturing process. The silicide element may contain titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel-platinum silicide (NiPtSi), nickel-platinum germanium silicide (NiPtGeSi), nickel-germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), a combination thereof, or other suitable compounds.The source / drain contacts 284 are then produced by depositing a conductive material in the contact openings and are placed on the silicide element. The conductive material can be a suitable material such as W, Co, Ru, Cu, Ta, Ti, Al, Mo, another suitable conductive material, or a combination thereof, and it can be deposited by a suitable process such as CVD, PVD, ALD, plating, other suitable processes, or combinations thereof. Alternatively, the silicide production can be omitted, and the source / drain contacts 284 contact the source / drain areas 238 directly.

[0058] The Fig. Figures 21 to 23 show an alternative embodiment of the device 200. According to operation 130 of Fig. 2 is Fig. Figure 21 shows an alternative sectional view of the device 200 at one of the various manufacturing stages after performing a metal gate etching process. In some embodiments, material layers (layers 252, 254, 256, 260, and 262) in the upper trench 250U are partially removed by the metal gate etching process, leaving lower portions of the upper trench 250U still filled. The portions of various layers remaining in the lower trench 250L, such as the dielectric gate layer 252, the exit work layer 254, the capping layer 256, the metal-containing thin film 260, and the gap-filling layer 262, can at least partially form a metal gate 270. The metal gate 270 can have a concave top surface.Nevertheless, the concave top surface and corresponding uppermost parts of the dielectric gate layer 252, the exit work layer 254, the capping layer 256, the metal-containing thin film 260, and the gap-filling layer 262 are all located above the uppermost part of the first gate spacers 234. The metal-containing thin film 260 may contain a metal element that differs from those used in the fabrication of the capping layer 256 and the gap-filling layer 262. This metal-containing thin film can serve as a detectable tracer to identify whether a gradient passivation process was used during the metal gate fabrication.

[0059] According to operation 132 of Fig. 2 is Fig. Figure 22 shows an alternative sectional view of the device 200 at one of the various manufacturing stages in which a metallic contact layer 272 is produced. The metallic contact layer 272 is produced over the recessed layers. In some embodiments, the metallic contact layer 272 contains W, Ta, Sn, Nb, Ru, Co, or Mo. In some embodiments, the metallic contact layer 272 is produced by an ALD process using metal halide gases (chloride gases) (e.g., TaCl₅, SnCl₄, NbCl₅, or MoCl₄). In some embodiments, the metallic contact layer 272 contains a fluorine-free metal, for example, fluorine-free metal W, produced with WCl₅ as the source gas.In some embodiments, the ALD process is a selective deposition process combined with an etching process, such that the metallic contact layer 272 grows selectively from metallic sublayers, such as the capping layer 256 and the exit work layer 254, and no metal layer is grown from the dielectric gate layer 252. This selective growth creates a lateral gap between the metallic contact layer 272 and the first gate spacers 234, preventing metallic elements from diffusing into the first gate spacers 234. In some embodiments, the thickness of the metallic contact layer 272 is approximately 1 nm to approximately 10 nm. In some embodiments, a bottom surface of the metallic contact layer 272 is located above the top portion of the first gate spacers 234.

[0060] According to operation 134 of Fig. 2 is Fig. Figure 23 shows an alternative sectional view of the device 200, for which further manufacturing processes are carried out. In operation 134 of method 100, the gate cap insulating layer 280, the gate contact 282 and the source / drain contacts 284 can be manufactured similarly to those described above.

[0061] In Fig. Figure 24 shows a sectional view of parts of a device 200'. The device 200' is essentially the one described in Figure 24. Fig. Device 200 shown in Figure 20 is similar, but it has an additional metal gate 270'. As shown, the metal gate 270' is essentially the same as the metal gate 270 of Figure 20. Fig.20, which extends over a distance defining a channel length L1 of a corresponding transistor. However, the metal gate 270' extends over a distance defining a channel length L2 that is significantly larger than L1. A transistor with a relatively short channel length (e.g., a transistor with the metal gate 270) may occasionally be referred to as a short-channel transistor, and a transistor with a relatively long channel length (e.g., a transistor with the metal gate 270') may occasionally be referred to as a long-channel transistor. In the long-channel transistor example, the metal gate 270' may again have the metal-containing thin film 260 and the gap-filling layer 262, which are also deposited in the lower trench 250L. This is due to the relatively long channel length, so that the capping layer 256 does not completely fill the lower trench 250L, but rather fills it in a U-shape.The metal-containing thin film 260 and the gap-filling layer 262 are thereby produced in the remaining portions of the lower trench 250L, which are enclosed by the capping layer 256. Each of the layers 252, 254, 256, 260, and 262 can be located beneath the uppermost portion of the first gate spacer 234. Furthermore, the metal gate 270' can have another metallic contact layer 272. Each of the metallic contact layers 272 is electrically connected to one end of a combination of the U-shaped layers 252, 254, 256, and 260. This allows one or more gate contacts 282 to be formed for connecting the metallic contact layer 272.

[0062] One or more embodiments of the present disclosure, which are not intended to be limiting, offer numerous advantages for a semiconductor device and its fabrication process. For example, embodiments of the present disclosure provide a gradient passivation and etching process for enlarging a gate groove. The enlarged gate groove facilitates subsequent material layer deposition without trapping seams in the gate groove, thus increasing device performance after a metal gate re-etching process. Furthermore, the proposed metal gate fabrication operations can be readily integrated into existing semiconductor fabrication processes.

[0063] In one exemplary aspect, the present disclosure relates to a method for fabricating a semiconductor device. The method comprises the following: creating a gate trench over a semiconductor substrate; depositing a dielectric gate layer and an exit-work layer in the gate trench; depositing a capping layer over the exit-work layer; passivating a surface portion of the capping layer to create a passivation layer; removing the passivation layer; depositing a filler layer in the gate trench; recessing the filler layer and the capping layer; and fabricating a metallic contact layer over the capping layer in the gate trench. In some embodiments, the passivation of the surface portion of the capping layer includes an oxidation process, and the passivation layer is an oxide. In some embodiments, the oxidation process is an oxygen plasma process.In some embodiments, passivating the surface portion of the capping layer involves a nitriding process, and the passivation layer is a nitride. In some embodiments, passivating the surface portion of the capping layer involves applying a passivation species that has a higher concentration at an opening of the gate trench than at a lower portion of the gate trench. In some embodiments, the passivation layer has a greater thickness near an opening of the gate trench than near a lower portion of the gate trench. In some embodiments, after removal of the passivation layer, an opening of the gate trench is enlarged. In some embodiments, removal of the passivation layer results in a metal-containing thin film on the capping layer.In some embodiments, the metal-containing thin film includes a metal element that is not present in the capping layer and the filler layer. In some embodiments, by omitting the filler layer and the capping layer, the filler layer is completely removed from the gate trench.

[0064] In another exemplary aspect, the present disclosure relates to a method for manufacturing a semiconductor device. The method comprises the following: creating a gate trench in a dielectric material by removing a dummy gate and by removing the upper part of a gate spacer arranged on side walls of the dummy gate; depositing a dielectric gate layer and an exit-work layer in the gate trench; depositing a capping layer in the gate trench; performing a passivation treatment on the capping layer to convert a surface portion of the capping layer into a passivation layer; etching the passivation layer, thereby enlarging an opening of the gate trench; and depositing a trench-filling layer in the gate trench. In some embodiments, the trench-filling layer completely fills the gate trench without enclosing seams in the gate trench.In some embodiments, the passivation layer near the gate trench opening has a greater thickness than near the lower part of the gate trench. In some embodiments, the method further comprises removing the trench filler layer, the capping layer, the exit work layer, and the dielectric gate layer; and producing a metallic contact layer directly above the capping layer and the exit work layer in the gate trench. In some embodiments, the trench filler layer is completely removed from the gate trench by the removal. In some embodiments, prior to the deposition of the dielectric gate layer and the exit work layer, the gate trench comprises a lower trench and an upper trench above the lower trench, the upper trench being wider than the lower trench.In some embodiments, before the deposition of the dielectric gate layer and the exit working layer, the gate trench opening is smaller than a mean part of the upper trench, and after etching the passivation layer, the gate trench opening is larger than the mean part of the upper trench.

[0065] In a further exemplary aspect, the present disclosure relates to a semiconductor device. The semiconductor device comprises: a fin projecting from a substrate; a first and a second source / drain region above the fin; a metal gate above the fin, arranged between the first and the source / drain regions; and a gate spacer arranged on sidewalls of the metal gate. The metal gate comprises: a dielectric gate layer, an exit-work layer above the dielectric gate layer, a capping layer above the exit-work layer, a metal-containing thin film enclosed by the capping layer, and a filler layer enclosed by the metal-containing thin film. In some embodiments, the gate spacer has a lower portion that is wider than an upper portion.In some embodiments, the metal-containing thin film contains a metal element that is not included in the capping layer and the filler layer.

Claims

[1] Method (100) for manufacturing a semiconductor device (200), comprising: Creating a gate trench (250) over a semiconductor substrate (202); Deposition of a dielectric gate layer (252) and an exit working layer (254) in the gate groove (250); Separation of a capping layer (256) over the exit working layer (254); Passivating a surface part of the capping layer (256) to produce a passivation layer (258); Removal of the passivation layer (258); Deposition of a fill layer (262) in the gate trench (250); Recess of the filler layer (262) and the capping layer (256); and Forming a metallic contact layer (272) over the capping layer (256) in the gate trench (250). [2] Method (100) according to claim 1, wherein the passivation of the surface part of the capping layer (256) includes an oxidation process, and the passivation layer (258) is an oxide. [3] Method (100) according to claim 2, wherein the oxidation process is an oxygen plasma process. [4] Method (100) according to any one of the preceding claims, wherein the passivation of the surface part of the capping layer (256) includes a nitriding process, and the passivation layer (258) is a nitride. [5] Method (100) according to any of the preceding claims, wherein the passivation of the surface part of the capping layer (256) comprises the application of a passivation species which has a higher concentration at an opening of the gate trench (250) than at a lower part of the gate trench (250). [6] Method (100) according to one of the preceding claims, wherein the passivation layer (258) has a greater thickness near the opening of the gate trench (250) than near a lower part of the gate trench (250). [7] Method (100) according to one of the preceding claims, wherein after removal of the passivation layer (258) an opening of the gate trench (250) is enlarged. [8] Method (100) according to one of the preceding claims, wherein a metal-containing thin film (260) is formed on the capping layer (256) by removing the passivation layer (258). [9] Method (100) according to claim 8, wherein the metal-containing thin film (260) contains a metal element that is not contained in the capping layer (256) and the filling layer (262). [10] Method (100) according to one of the preceding claims, wherein by omitting the fill layer (262) and the capping layer (256) the fill layer (262) is completely removed from the gate trench (250). [11] Method (100) for manufacturing a semiconductor device (200), comprising: Creating a gate trench (250) in a dielectric material (240) by removing a dummy gate (224) and by removing an upper part of a gate spacer (232, 234, 236) arranged on side walls of the dummy gate (224); Deposition of a dielectric gate layer (252) and an exit working layer (254) in the gate groove (250); Deposition of a capping layer (256) in the gate trench (250); Performing a passivation treatment on the capping layer (256) to convert a surface part of the capping layer (256) into a passivation layer (258); Etching of the passivation layer (258), thereby enlarging an opening of the gate trench (250); and Separation of a trench fill layer (262) in the gate trench (250). [12] Method (100) according to claim 11, wherein the trench fill layer (262) completely fills the gate trench (250) without enclosing any seams in the gate trench (250). [13] Method (100) according to claim 11 or 12, wherein the passivation layer (258) has a greater thickness near the opening of the gate trench (250) than near a lower part of the gate trench (250). [14] Method (100) according to any one of claims 11 to 13, further comprising: Omission of the trench fill layer (262), the capping layer (256), the exit working layer (254) and the dielectric gate layer (252); and Establishing a metallic contact layer (272) directly above the capping layer (256) and the exit working layer (254) in the gate trench (250). [15] Method (100) according to claim 14, wherein by the recessing the trench fill layer (262) is completely removed from the gate trench (250). [16] Method (100) according to any one of claims 11 to 15, wherein prior to the deposition of the dielectric gate layer (252) and the exit working layer (254) the gate trench (250) comprises a lower trench (250L) and an upper trench (250U) above the lower trench (250L), wherein the upper trench (250U) is wider than the lower trench (250L). [17] Method (100) according to claim 16, wherein prior to the deposition of the dielectric gate layer (252) and the exit working layer (254), the opening of the gate trench (250) is smaller than a mean part of the upper trench (250U), and After etching the passivation layer (258), the opening of the gate trench (250) is larger than the middle part of the upper trench (250U). [18] Semiconductor device (10, 200) with: a fin (64, 204) protruding from a substrate (50, 202); a first and a second source / drain area (80, 238) above the fin (64, 204); a metal gate (68, 270) above the fin (64, 204) located between the first and second source / drain area (80, 238), wherein the metal gate (68, 270) has the following features: a dielectric gate layer (66, 252), an exit work layer (254) above the dielectric gate layer (66, 252), a capping layer (256) above the exit working layer (254), a metal-containing thin film (260) enclosed by the capping layer (256), and a filler layer (262) enclosed by the metal-containing thin film (260); and a gate spacer (232, 234, 236) arranged on side walls of the metal gate (68, 270), wherein the metal-containing thin film (260) contains a metal element that is not included in the capping layer (256) and the filler layer (262) during their manufacture. [19] Semiconductor device (10, 200) according to claim 18, wherein the gate spacer (232, 234, 236) has a lower part which is wider than an upper part.

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