Method and apparatus for encoding, method and apparatus for decoding, and computer-readable storage media

Abstract

Various aspects of this disclosure provide a device (100) for encoding a digital data word (102). The device (100) may include a processor (104) configured to group (302) a digital data word (102) having a plurality of bits into at least one data word bit group (DB), wherein the at least one data word bit group (DB) has at least two bits; add (304) to the at least one data word bit group (DB) at least one bit (Zb) of a predefined value at a predefined position within the at least one data word bit group (DB); encode (306) the extended at least one data word bit group (106) with the at least one added bit (Zb) using an encoding method that operates on bit groups, such that a codeword (110) is generated having at least one information bit group (112) and at least one check word bit group (114);Removing (308) the at least one added bit (Zb) from the at least one information bit group (112) so that at least one reduced information bit group (116) is formed; and storing (310) the at least one reduced information bit group (116) and the at least one check word bit group (114).

Description

[0001] The invention relates to a method and a device for encoding, a method and a device for decoding, and computer-readable storage media.

[0002] During channel coding and decoding, redundancy information is typically added to a data word to be transmitted or stored. After the resulting codeword, containing the data word and the additional redundancy information, has been stored or transmitted, channel decoding attempts to identify and, if possible, correct any errors in the data word or the redundancy information that occurred during storage or transmission.

[0003] The use of a so-called Reed-Solomon code for encoding / decoding, for example channel encoding / channel decoding, has proven particularly suitable for detecting burst errors.

[0004] Various coding methods that work on bit groups are described, for example, in SB Wicker, Error control systems for digital communication and storage, Prentice Hall, ISBN 0-13-200809-2, pages 190 to 193, 1995, and in TRN Rao and E. Fujiwara, Error-control coding for computer systems, Prentice Hall, ISBN 0-13-283953-9, pages 246 to 252, 1989.

[0005] Various aspects of this disclosure provide a channel encoding device, a channel decoding device, and computer-readable storage media with which a faulty correction can be quickly detected without the need for additional computation.

[0006] To illustrate, a digital data word to be protected is divided into at least one, for example, several data word bit groups. One or more bits are then "temporarily" added to at least one data word bit group, to a subset of several data word bit groups, or to each data word bit group. The redundancy bit(s) (hereinafter also referred to as additional bits) are added at predefined position(s) and each has a predefined value. The position(s) and the value(s) are known to the decoder (e.g., channel decoder). The data word bit group(s) extended in this way are subjected to a coding procedure (e.g., a channel coding procedure) that works on bit groups, such as a Reed-Solomon code (or a truncated Reed-Solomon code).This results in a codeword consisting of one or more information bit groups (representing the user information and thus the data word) and at least one or more checkword bit groups (representing the redundancy information). To store or transmit the complete information, the previously added bit(s) are first removed from the information bit group(s), thus creating a reduced information bit group(s). This reduced information bit group(s) is then stored together with the checkword bit group(s), which remains unchanged, or additionally transmitted (for example, wirelessly or via a wired connection). For decoding (for example, channel decoding), the reduced information bit group(s) and the associated checkword bit group(s) are read from or received from a memory location.Then, the bit(s) that were "temporarily" added before encoding (e.g., channel encoding) are added again before decoding (e.g., channel decoding) at the same predefined position and with the same predefined value (where the respective position and value are known to the channel decoder) to the reduced information bit group(s). The corresponding (channel) decoding procedure is then executed on the now "expanded" information bit group(s) and the associated check word bit group(s). If error correction is subsequently performed, the additional bit(s) can be used to easily verify whether the error correction itself was correct or incorrect.

[0007] Several aspects of this revelation provide for an increase in the probability of error detection of 2-byte errors for 1-byte error-correcting Reed-Solomon codes, generally for codes that operate on bit groups. For example, two check bytes are used to correct the 1-byte errors. This includes, among other things, the case where the data bytes (hereinafter also referred to as data word bit groups) and the associated check bytes (hereinafter also referred to as check word bit groups) are stored in memory cells of an addressable memory.

[0008] In various aspects of this revelation, one or more original data bytes are augmented by predefined bits (ε) to form a byte with a larger word width. These predefined bits are not written to memory and are not automatically added during read operations. Therefore, the data bytes do not require additional storage space.

[0009] For example, all data bytes can be padded with ε zeros. Similarly, it is possible to pad the data bytes in the i-th byte position with the bits (i mod ε (epsilon)). The checksum bytes are formed from the padded bytes during writing. They have a word width ε larger than the data bytes, so that, for example, ε more memory cells are required for each of the two checksum bytes than without modification. After error correction, an incorrectly corrected error that is not a 1-byte error is detected, for example, if the padding bits of the corrected byte do not match the originally specified padding bits.

[0010] Depending on the required probability for detecting 2-byte errors or multi-byte errors, the number ε of completion bits can be selected. For example, the required probability of 2-byte error detection can be achieved by choosing ε (epsilon) without using a full third check byte.

[0011] It should therefore be noted that the methods according to various aspects of this disclosure allow for the very rapid, local detection of an incorrectly corrected error solely on faulty completion ε bits. Since the word width of the check bytes is increased by ε bits, the Galois field to be used also increases, thus enlarging a syndrome generator and a correction unit of the code. However, this may also mean that only a relatively small portion of the possible bytes of the Reed-Solomon code is used in the enlarged Galois field. Consequently, all faulty byte error positions resulting from a 2-byte error or a multi-byte error, which do not belong to an actually used byte, are identifiable as errors.

[0012] An effect of the methods, according to various aspects of the disclosure, can be seen in the possibility of a gradual increase in the error detection of 2-byte and multi-byte errors, a locally fast detectable fault correction, and the additional increase in the error detection probability through the (temporary) increase of the Galois field used.

[0013] Various aspects of this disclosure provide a device for encoding a digital data word. The device may include a processor configured to: group a digital data word having a plurality of bits into at least one data word bit group, wherein the at least one data word bit group has at least two bits; add at least one bit of a predefined value to the at least one data word bit group at a predefined position within the respective data word bit group; encode the extended at least one data word bit group with the at least one added bit, using an encoding method that operates on bit groups, such that a codeword is produced having at least one information bit group and at least one check word bit group;Removing the at least one added bit from the at least one information bit group, so that at least one reduced information bit group is formed; and storing the at least one reduced information bit group and the at least one check word bit group.

[0014] Various aspects of this disclosure provide a device for decoding a (potentially faulty) digital codeword. The device includes a processor configured to: group the (potentially faulty) digital codeword into at least one reduced information bit group and at least one checkword bit group, wherein the at least one information bit group and the at least one checkword bit group each comprise multiple bits; add at least one bit of a predefined value at a predefined position within the at least one reduced information bit group, such that at least one information bit group is formed;Decoding the at least one information bit group and the at least one check word bit group using a decoding method that operates on bit groups, such that at least one reconstructed data word bit group and at least one reconstructed check word bit group, as well as a syndrome, are generated; performing at least one bit group error correction in the at least one reconstructed data word bit group and / or in the at least one reconstructed check word bit group using the syndrome; and verifying the error correction using the at least one additional bit in the at least one reconstructed data word bit group.

[0015] Various aspects of this disclosure provide a device for error correction in at least one digital byteword (also referred to as a digital dataword).The device may include a processor configured to: group the digital byte word into at least one data byte and at least one check byte, wherein the at least one data byte and the at least one check byte have multiple bits; supplement the at least one data byte with at least one predefined additional bit for the byte position, so that at least one supplemented data byte is formed, wherein, in the error-free case, the at least one supplemented data byte forms a codeword of a byte error code; perform an error correction procedure that operates on bit groups, on the at least one supplemented data byte and the at least one check byte; and detect an incorrect error correction if, after performing the error correction, an additional bit of the at least one data byte does not match the at least one predefined additional bit or an invalid byte error position is detected.

[0016] Exemplary embodiments of the invention are shown in the figures and are explained in more detail below.

[0017] They show Fig. 1 a diagram illustrating channel coding according to various aspects of revelation; Fig. 2 a diagram illustrating channel decoding according to different aspects of the revelation; Fig. 3 a flowchart illustrating a channel coding procedure according to various aspects of the revelation; Fig. 4 a flowchart illustrating a procedure for channel decoding according to various aspects of the revelation; and Fig. 5 a flowchart illustrating a procedure for error correction according to various aspects of the revelation.

[0018] The following detailed description refers to the accompanying drawings, which form part thereof and illustrate specific embodiments in which the invention can be implemented. In this context, directional terminology such as "top," "bottom," "front," "back," "anterior," "rear," etc., is used with reference to the orientation of the described figure(s). Since components of embodiments can be positioned in a number of different orientations, the directional terminology serves only for illustration and is in no way limiting. It is understood that other embodiments may be used and structural or logical modifications may be made without deviating from the scope of protection of the present invention.It is understood that the features of the various exemplary embodiments described herein can be combined with one another, unless specifically stated otherwise. The following detailed description is therefore not to be interpreted in a limiting sense, and the scope of protection of the present invention is defined by the appended claims.

[0019] Unless otherwise specified, identical or similar elements, features and structures are designated with the same reference numbers in the drawings.

[0020] Within the scope of this description, the terms "connected," "attached," and "coupled" are used to describe both direct and indirect connections, direct or indirect links, and direct or indirect couplings. In the figures, identical or similar elements are labeled with identical reference symbols where appropriate.

[0021] The terms "processor" and "controller" as used here can be understood as any type of technological unit (e.g., hardware, software, and / or a combination of both) that enables the processing of data. The data can be processed according to one or more specific functions performed by the processor or controller. Furthermore, a processor or controller, as used here, can be understood as any type of circuit, e.g., any type of analog or digital circuit. A processor or controller can therefore be an analog circuit, a digital circuit, a mixed-signal circuit, software, firmware, a logic circuit, a processor, a microprocessor, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a field-programmable gate array (FPGA), an integrated circuit, an application-specific integrated circuit (ASIC), etc.or any combination thereof. Any other type of implementation of the respective functions described in more detail below may also be understood as a processor, controller, or logic circuit. It is understood that two (or more) of the processors, controllers, or logic circuits described herein may be realized as a single unit with equivalent functionality or the like, and conversely, a single processor, controller, or logic circuit described herein may be realized as two (or more) separate units with equivalent functionality or the like.

[0022] The term "memory" here refers to a computer-readable medium (e.g., a non-transient computer-readable medium) in which data or information can be stored for retrieval. When "memory" is mentioned here, it can refer to volatile or non-volatile memory, including random-access memory (RAM), read-only memory (ROM), flash memory, solid-state memory, magnetic tape, hard disk drive, optical drive, 3D XPoint™, or any combination thereof. The term "memory" also includes registers, shift registers, processor registers, data buffers, and others. The term "software" refers to all types of executable instructions, including firmware.

[0023] Unless explicitly stated otherwise, the term "transmission" includes both direct (point-to-point) and indirect transmission (via one or more intermediate points). Similarly, the term "receive" includes both direct and indirect reception. Furthermore, the terms "send," "receive," "communicate," and similar terms encompass both physical transmission (e.g., the transmission of radio signals) and logical transmission (e.g., the transmission of digital data over a software-level logical connection). For example, a processor or control unit may transmit or receive data over a software-level connection with another processor or control unit in the form of radio signals, with the physical transmission and reception being carried out by radio layer components, such as...High-frequency transceivers and antennas are used, and the logical transmission and reception over the connection are handled at the software level by the processors or controllers. The term "communicate" encompasses both sending and receiving, i.e., unidirectional or bidirectional communication in one or both directions, i.e., incoming and outgoing. The term "compute" encompasses both "direct" computations using a mathematical expression / formula / relationship and "indirect" computations using lookup or hash tables and other array indexing or search operations.

[0024] Fig.Figure 1 shows a device 100 for channel-coding a digital data word 102. The digital data word 102 can contain any number of data bits (for example, thousands, millions, billions, or even more). The digital data word 102 can contain any type of data, such as image content, video content, audio content, text content, or other types of information. The digital data word 102 can contain, for example, raw data or source-coded data. In general, the digital data word 102 can contain any type of data that is to be protected by channel coding.

[0025] Various aspects of this disclosure employ a channel encoding and decoding method that operates on bit groups. Although, as an example, such a channel encoding and decoding method is based on a so-called Reed-Solomon code, it should be emphasized that the various aspects are not limited to such a code; any method that operates on bit groups, where each bit group comprises multiple bits, can be used, for example, a truncated Reed-Solomon code. Explanation of some basic terms

[0026] First, some basic terms related to a Reed-Solomon Code will be explained.

[0027] A Galois field GF(2) m ) is a finite field with 2 mThe following operations are explained for the elements: addition, subtraction, multiplication, and division. Division by an element as the dividend and zero as the divisor is undefined. The elements of the finite field can be represented in various ways; generally, the exponential representation, the polynomial representation, the vector representation, and the matrix representation are common.

[0028] Table 1 lists the elements in the representations mentioned above for the Galois field GF(2). 3 ) listed. To simplify the representation, a Galois field GF(2) is used. 3 ) explained in more detail, although the aspects of revelation are not limited to this and generally a GF(2 m ), with m being an integer greater than or equal to 2, can be provided (in the further concrete implementation examples a GF(2 ) 4 ) (also m = 4) is used).

[0029] Possible representations of elements of the finite field GF (2 3 ) Table 1 Exponential representation Polynomial representation Vector representation Matrix representation 0 0 (000) 0 1 1 (100) T 0 α x (010) T 1 α 2 x 2 (001) T 2 α 3 1+x (110) T 3 α 4 x+x 2 (011) T 4 α 5 1+x+x 2 (111) T 5 α 6 1+x 2 (101) T 6

[0030] The T listed in Table 1 i consisted of m consecutive elements from GF(2 m ) together, generally speaking: Ti=(αiαi=1…αi+m−1).

[0031] For GF(2 3 ) is T0=(100010001),T1=(001101010),T2=(010011101),T3=(101111011),T4=(011110111),T5=(111100110)andT6=(110001100).

[0032] Elements in one representation can be freely transformed into another. Each representation has advantages and disadvantages with regard to operations. In exponential and matrix representations, for example, multiplication and division are easily calculated by adding or subtracting the exponents. In binary, addition and subtraction yield the same result; these operations are easily calculated in vector and polynomial representations.

[0033] The example from Table 1 is assumed. If one wants to α 3 + a 4 To calculate this without using a LUT (lookup table), it is only possible by entering the polynomial representation 1+ x +x + x. 2 = 1 + x 2 switches to the vector representation (110) + (011) = (101) in order to then switch back to the exponential representation.

[0034] In general, in the exponential representation, every element except the element "0" is represented as a power of a generating element α. i The polynomial representation corresponds to the remainders of the division of the powers of a variable X,X. 0 ,X 1 ,X 2 , X 3 ...when dividing these powers by the chosen modular polynomial. The vector representation of an element corresponds to the coefficients of the element in its polynomial representation, and the matrix representation of an element α given in exponential form i is T i = (α i α i+1 ...α i+m-1 ), where the Alpha i, i+1, ... are used in their vector representation as m-component column vectors.

[0035] In the present description, Reed-Solomon codes are used over a Galois field GF(2). m) considered. These are byte error correcting codes and, for an odd number of check bytes, also byte error detecting codes. A byte comprises m bits, where m is a natural number greater than 0. A Galois field GF(2 m ) shows 2 m Elements. When correcting a byte error, both the faulty byte position and the byte error value by which the faulty byte must be corrected must be determined.

[0036] It should be emphasized that, within the context of this description, a byte does not necessarily contain 8 bits, but refers to the size of the Galois field m.

[0037] The elements of a Galois field, except for the element "0", can be generated by the powers of a generating element α. These elements can be expressed in the form α 0 ,α 1 , α 2 , ...,α 2m-2 be represented. An unabridged Reed-Solomon code consists of 2 m - 1 byte to m bits.

[0038] If t bytes need to be corrected, then 2t check bytes with m bits are required. A 1-byte error-correcting Reed-Solomon code accordingly has 2 check bytes, a 2-byte error-correcting Reed-Solomon code has 4 check bytes. If a code that corrects 1 byte and detects 2 bytes also requires 3 check bytes, then a code that corrects 2 bytes and detects 3 bytes requires 5 check bytes.

[0039] This description introduces 1-byte error-correcting Reed-Solomon codes and 1-byte error-correcting and 2-byte error-detecting Reed-Solomon codes, as well as a generalization of the H-matrix for t-byte error-correcting Reed-Solomon codes.

[0040] The H-matrix of a Reed-Solomon code can also be described in various ways. For a 1-byte error-correcting Reed-Solomon code, the H-matrix can be... H=(α0α0α0…α0α0α1α2…αn−1)=(H1H2) are used. Here, α 0 , α 1 , α 2 ,...α n-1 (n = 2 m -1) Elements of the Galois field GF(2 m ) in its exponential representation. Similarly, the H-matrix H=(α0α1α2…αn−1α0α2α4…α2⋅(n−1))=(H1H2) are used, with the columns (αiα2i) in equation (4) by multiplying the original columns (α0αi) from equation (3) with α i emerge.

[0041] In binary representation, the H-matrices yield (equation (3)) and (equation (4)) H=(T0T0T0…T0T0T1T2…Tn−1) and H=(T0T1T2…Tn−1T0T2T4…T2⋅(n−1)).

[0042] All exponents i of α i and T i are modulo n = 2 m - 1 to be interpreted. This involves T0,T1,…,Tn−1 the elements of the Galois field in their matrix representation.

[0043] The following explains how the syndrome components are calculated using the H-matrix.

[0044] Is V=(v0,v1,…vn−1) a stored vector consisting of n components v0,v1,...,v n-1 of the Galois field GF(2 m ) so the corresponding read-out vector R=(r0,r1,…,rn−1) a around the error vector E=(e0,e1,…,en−1) distorted vector. The relationship R = V - E holds component-wise for r i = v i - e i with i from 0 to n - 1, in an unshortened code. Since this consideration involves binary values, addition and subtraction are equivalent. The error syndrome of R is represented by the H-matrix according to equation (3) as s=H⋅RT=(α0α0…α0α0α1…αn−1)⋅RT =(α0r0+α0r1+⋯α0rn−1α0r0+α1r1+⋯αn−1rn−1)=(s1s2) determined. r0,r1,r2,...,r n-1 , are elements of the GF(2 m ).

[0045] Is the element r for j = 0,...,n- 1?i Described as a binary vector, it corresponds to an element α. ji the exponential representation and R allows the representation R = (α j0 , α j1 , α j2 , ..., α jn-1 ) and the error syndrome with its syndrome components s1 and s2 can be calculated directly.

[0046] In the binary representation of the components r0, r1,...,r n-1 can the binary form s=H⋅RT=(T0T0…T0T0T1…Tn−1)(r0r1⋮rn−1)=(s1s2) with s1=T0r0+T0r1+⋯+T0rn−1=r0+r1+⋯rn−1s2=T0r0+T1r1+⋯Tn−1rn−1 can be used. T 0 = I m the m-dimensional identity matrix.

[0047] If R = V is a codeword, then H⋅VT=(S1S2)=(0→0→)

[0048] This refers to 0→ the m-dimensional 0-vector.

[0049] If there is a 1-byte error in the j-th byte position α jwith a byte error value a, then the error vector E=(e0,e1,...,en−1)=(0,...,0︸j,a,0,...,0︸n−j−1).

[0050] Both e0,...,e n-1 as well as 0→ and α are m-dimensional binary vectors. Subtraction is in the Galois field GF(2). m ) is equal to the + operation, which is performed on the elements in their vector representation or their matrix representation as a component-wise XOR operation. Therefore, V = (v o ,v1, ...,v n-1 ) and R = (r0,r1,...,r n-1 ) only in the j-th byte position, such that the following holds r0=v0−e0,r1=v1−e1,...,rn−1=vn−1−en−1 r0=v0,r1=v1,...,rj−1=vj−1,rj=vj−a,rj+1=vj+1,...,rn−1=vn−1 and the following applies to the error syndrome (also referred to as syndrome) s1=a,s2=αja where s1, s2 and α are expressed in exponential notation and s1=a,s2=Well where s1, s2, and a are described as m-digit binary vectors. In the case of a 1-byte error with the byte error vector α, which does not need to be calculated separately, the byte position α can be j through αj=s2s1 to be determined.

[0051] For a 1-byte error-correcting Reed-Solomon code with the H-matrix (equation 4), the error syndrome of R is described by s=H⋅RT=(α0α1⋯αn−1α0α2⋯α2⋅(n−1))⋅RT =(α0r0+α1r1+⋯+αn−1rn−1α0r0+α2r1+⋯+α2⋅(n−1)rn−1)=(s1s2) determined. The components r i of R as elements of the Galois field GF(2 m The numbers ) are interpreted here in their exponential representation. The syndrome components are represented as binary vectors using the H-matrix (Equation 6). s=H⋅RT=(T0T1…Tn−1T0T2…T2⋅(n−1))(r0r1⋮rn−1)=(s1s2) with s1=T0r0+T1r1+⋯+Tn−1rn−1s2=T0r0+T2r1+⋯+T2⋅(n−1)rn−1 calculated.

[0052] Is there a 1-byte error in the j-th byte position α?j If a byte error value a is present, then the following applies to the error syndrome with s1, s2 and a in exponential notation. s1=αja,s2=α2ja

[0053] If s1, s2 and a are m-ary binary vectors, then the following holds: s1=Well, s2=Well, yes

[0054] In the case of a 1-byte error with byte error position α j , which are αj=s2s1 The byte error value a can be determined by a=s1αj=s12s2 to be determined.

[0055] The G-matrix can be generated from the H-matrix and is used for encoding (also called coding, for example, channel coding). For this purpose, the H-matrix is ​​transformed into the systematic form H = (IP) using, for example, the Gauss-Jordan algorithm. Then the G-matrix is ​​G = (P). T I), where the elements T iThey must also be transposed into P; in this case, the components of the G and H matrices are the matrices T. 0 ,T 1 ,T 2 ,.... If the Gauss-Jordan algorithm is applied bitwise to the binary H-matrix, then this step is not necessary.

[0056] For a code with ρ check bytes and n̂ ≤ 2 m - 1 used elements from the Galois field GF(2 m ) results in the systematic H-matrix H=IρPρ×n^−ρ, where I ρ a ρ × ρ identity matrix with 0 and T 0 from GF(2 m ) as the unit element and P ρ×n̂-ρ a ρ × n̂ - ρ-matrix is ​​with elements in matrix representation from GF(2 m ). For the G-matrix, P is used. T an n̂ - ρ × n̂ - p identity matrix is ​​appended and then yields G=Pn^−ρ×ρTIn^−ρ.

[0057] For the same code, the H-matrix represented by binary vectors has the dimensions H=IρmPρm×(n^−ρ)m, where I ρm a ρm × ρm identity matrix with 0 and 1 is and P ρm×(n̂-p)m a ρm × (n̂ - ρ)m matrix is ​​with α i from GF(2 m ) in vector representation, where the m × m submatrices are represented as T i to be interpreted. The G-matrix can also be represented with binary vectors and has the form G=P(n^−ρ)m×ρmTI(n^−ρ)m. Example of a 1-byte correcting Reed-Solomon code

[0058] The example of a 1-byte correcting Reed-Solomon code consists of calculating a codeword from an arbitrary data word using the G-matrix and then validating that it is a codeword using the H-matrix.

[0059] In the second step, this codeword is added to an error vector to simulate a 1-byte error. This codeword is then multiplied by the H-matrix to determine the byte error position and value using the syndrome components.

[0060] The example with H-matrix and G-matrix from elements of the Galois field GF(2) 3 ) is shown in exponential notation.

[0061] The H-matrix will be used again. H=(α0α1α2α3α4α5α6α0α2α4α6α1α3α5) used with the G-matrix calculated from it G=(α3α4α00000α0α00α0000α3α500α000α1α5000α00α1α40000α0).

[0062] For an arbitrarily chosen but fixed data word W = (α 6 0 α 5 α 4 α 1 ) the codeword V is replaced by V=W⋅G calculated. The i-th component v is calculated. i V is determined by the sum of the component-wise multiplication of W with the i-th column of G (equation (45)), so that in this example v0=α6⋅α3+0⋅α0+α5⋅α3+α4⋅α1+α1⋅α1=α6v1=α6⋅α4+0⋅α0+α5⋅α5+ α4⋅α5+α1⋅α4=α3v2=α6⋅α0+0⋅0+α5⋅0+α4⋅0+α1⋅0=α6v3=α6⋅0+0⋅ α0+α5⋅0+α4⋅0+α1⋅0=0v4=α6⋅0+0⋅0+α5⋅α0+α4⋅0+α1⋅0=α5v5=α6 ⋅0+0⋅0+α5⋅0+α4⋅α0+α1⋅0=α4v6=α6⋅0+0⋅0+α5⋅0+α4⋅0+α1⋅α0=α1 the codeword V = (α 6 α 3 α 6 0 α 5 α 4 α 1 ) result.

[0063] Multiplying a codeword V by the H-matrix H yields the syndrome s = H·V T = 0. Here, the first syndrome component results from the sum of the component-wise multiplication of the first row of the H-matrix (equation (32)) by the transposed codeword vector. The second syndrome component results analogously from the sum of the component-wise multiplication of the second row of the H-matrix by the transposed codeword vector. The syndrome then consists of s1=α6⋅α0+α6⋅α1+α6⋅α2+0⋅α3+α5⋅α4+α4⋅α5+α1⋅α6=0 s2=α6⋅α0+α3⋅α2+α6⋅α4+0⋅α6+α5⋅α1+α4⋅α3+α1⋅α5=0 to s=(00) together, and therefore V is indeed a code word.

[0064] A 1-byte error occurs, described by the error vector E at the byte error position α. 3 with the byte error value α 0 The byte error vector E = (0 0 0 α) is on 0 0 0 0). This results in the erroneous word vector. R=(α6+0α3+0α6+00+α0α5+0α4+0α1+0)=(α6α3α6α0α5α4α1).

[0065] If s = H·R T The syndrome components are formed s1=α6⋅α0+α3⋅α1+α6⋅α2+α0⋅α3+α5⋅α4+α4⋅α5+α1⋅α6=α3 s2=α6⋅α0+α3⋅α2+α6⋅α4+α0⋅α6+α5⋅α1+α4⋅α3+α1⋅α5=α6 calculated. The byte error position is determined using the equation calculated and the byte error value using the equation a=s1αi=α3α3=α0, This allows the 1-byte error at byte position α to be corrected. 3 with the byte error value α 0 be corrected properly.

[0066] Now referring again to Fig. The digital data word 102 has a plurality of bits. The digital data word 102 is processed, for example, by one or more processors 104. The one or more processors 104 are configured to implement the channel-coding procedure for the digital data word 102 described below, the procedure itself also shown in a flowchart 300 in Fig. 3 is shown.

[0067] The digital data word 102, which has a multitude of bits, is grouped in 302 into at least one data word bit group. The at least one data word bit group DB has at least two bits, but it can also have more bits, for example, generally m bits with m greater than or equal to 2. In other words, various aspects of this revelation can be described as an encoding using a coding procedure that operates on bit groups over a Galois field GF(2). m) are considered.

[0068] Subsequently, in step 304, at least one bit Zb (hereinafter also referred to as additional bit Zb) of a predefined value is added to at least one data word bit group DB at a predefined position within the respective data word bit group DB. If several data word bit groups DB are contained in the digital data word 102, then the at least one additional bit Zb can be added to only one data word bit group DB, alternatively, at least one additional bit Zb can be added to each of several data word bit groups DB, or at least one additional bit Zb can be added to each data word bit group DB. The additional bit(s) Zb of a respective data word bit group DB has a fixed position or a fixed value (fixed in this context means that a decoder knows both the position and the value of the additional bit(s) and that these remain unchanged).The fixed value of a given additional bit Zb can also be determined by its position within a given data word bit group DB or the digital data word 102. Generally, one, several, or all data word bit groups DB can have ε additional bits added (however, it is also possible to add a different number of additional bits Zb to different data word bit groups DB). Thus, one or more extended data word bit groups 106 (by, for example, ε additional bits) are formed. The additional bits Zb can, for example, all have the same value (e.g., all the value "0" or all the value "1") or they can have different values. The additional bits Zb can, for example, be added to the end of each data word bit group DB.

[0069] Subsequently, in 306, for example by means of an encoder 108, for example a channel encoder 108, the extended at least one data word bit group 106 with the at least one added bit can be encoded, for example channel-encoded (or several extended data word bit groups 106). The encoder 108 is configured to perform an encoding procedure that works on bit groups and is based, for example, on a Reed-Solomon code. The result of the encoding is a codeword 110 having at least one information bit group 112 (or several information bit groups 112) and at least one check word bit group 114 (or several check word bit groups 114).

[0070] In 308, at least one added extra bit Zb can be removed from at least one information bit group 112 (for example, several extra bits Zb from one or more information bit groups 112), so that at least one reduced information bit group 116 is formed (or several reduced information bit groups 116 are formed). The at least one check word bit group 114 (or the several check word bit groups 114) remains unchanged. It should be noted that if ε extra bits are added to all data word bit groups DB, the check word bit groups formed by encoder 108 will have (m + ε) bits. If all ε extra bits are also removed from one or more information bit groups 112, the one or more reduced information bit groups 116 will have m bits.

[0071] In 310, the one or more reduced information bit groups 116 and the one or more check word bit groups 114 are stored in a memory 118 as a reduced codeword 120. The memory 118 can be any type of memory 118, for example, non-volatile memory such as a register array. The memory 118 can be configured as a resistive random-access memory (RRAM). The additional bits temporarily added to the data word bit group(s) DB do not need to be stored; only the check word bit group(s) 114 have ε additional bits. In this way, as will be explained in more detail later, the Galois field is temporarily extended for decoding without the need to store the ε additional bits.

[0072] Even when optionally transmitting the reduced codeword 120 over a channel, these additional ε bits for the data word bit groups DB do not need to be transmitted. It is only necessary to store the additional ε bits in each checkword bit group 114 and transmit them if necessary.

[0073] Fig. Figure 2 shows a device 200 for channel decoding a digital codeword 202, for example, the reduced codeword 120. The reduced codeword 120 is stored in the memory 118. The reduced codeword 120 is processed, for example, by one or more processors 202. The one or more processors 202 are configured to implement the channel decoding method for the reduced codeword 120 described below, the method also shown in a flowchart 400 in Figure 2. Fig. 4 is shown.

[0074] In 402, the digital reduced codeword 120 read from memory 118 can be grouped into at least one reduced information bit group 204 (or several reduced information bit groups 204) and at least one checkword bit group 114, 206 (or several checkword bit groups 114, 206). The at least one reduced information bit group 204 and the at least one checkword bit group 114, 206 each contain several bits.

[0075] In 404, the processor or processors 202 can add additional bits with the same value to the at least one information bit group 204 (or the multiple information bit groups 204) at the same position as was temporarily done with the data word bit group(s) DB during encoding (in 304). Generally, in 404, at least one bit of a predefined value is added at a predefined position within the at least one reduced information bit group 204, so that at least one information bit group 208 is formed (or multiple information bit groups 208 are formed). The one or more read check word bit groups 114, 206 remain unchanged.The processor 202 knows the position and value of each of the (for example, ε) additional bits temporarily added during encoding, for example, due to a list previously communicated to the processor 102 and the processor 202, which contains the position(s) and respective value(s) of the additional bits, or due to a message from the processor 102 to the processor 202.

[0076] Subsequently, in 406, the at least one information bit group 208 (or the multiple information bit groups 208) and the at least one check word bit group 206 (or the multiple check word bit groups 206) are decoded using a decoding procedure that works on bit groups, so that at least one reconstructed data word bit group 212 and at least one reconstructed check word bit group (not shown) as well as a syndrome are generated.

[0077] In 408, at least one bit group error correction (also called byte error correction) 210 is performed in the at least one reconstructed data word bit group 212 and / or in the at least one reconstructed check word bit group using the syndrome.

[0078] The error correction can be verified in 410 using the at least one additional bit in the at least one reconstructed data word bit group 212.

[0079] If an invalid position of a byte error is detected, for example a byte position that was removed when the code was shortened (an “invalid position” refers to an invalid byte error position, i.e., if a byte error position is shown in the bytes that were shortened (of the larger Galois field)), then the processor 202 determines that an error has occurred as part of the byte error correction 210 (block 216).

[0080] If a changed value of an additional bit is detected at a predefined position (block 218), then the processor 202 determines that an error has occurred as part of the byte error correction 210 (block 220).

[0081] If no error is detected (block 222), then the reconstructed data word bit groups 224 (without the added reconstructed extra bits) are used as correctly reconstructed one or more data word bit groups corresponding to the one or more data word bit groups DB.

[0082] Fig. Figure 5 shows a flowchart 500, which describes a procedure for error correction in at least one digital byteword (for example, also implemented by the processor 202).

[0083] The method may include, in 502, grouping the digital byteword into at least one data byte and at least one check byte, wherein the at least one data byte and the at least one check byte each have several bits, wherein the at least one digital byteword in the error-free case forms a codeword of a byte error code.

[0084] In 504, the procedure refers to supplementing the at least one data byte with at least one additional bit predefined for the byte position, so that at least one supplemented data byte is formed.

[0085] In 506, the procedure refers to carrying out an error correction procedure that operates on bit groups, on which at least one added data byte and at least one check byte are used.

[0086] In 508, the procedure indicates a finding of an incorrect error correction if, after performing the error correction, an additional bit of the at least one data byte does not match the at least one predefined additional bit or an invalid byte error position is found.

[0087] The following section explains further technical details of various aspects of this revelation.

[0088] In several aspects, a method is provided to improve error detection in Reed-Solomon codes, generally any code operating on bit groups of multiple bits. This involves extending one or more data bytes (in other words, one or more data word bit groups) by adding ε bits, where these ε bits have a fixed value or a value calculable from the byte position. The bits are determined independently of the original byte value. If ε = 1 bits with the fixed value "0" are added, they do not need to be stored together with the data bytes due to the separability of the code. The ε bits at the check bytes are stored because they are generated depending on the data bytes. After an incorrect correction, the added bits can be used to determine whether an error occurred. After reading the data, the fixed value is appended to the data bytes and the error is corrected.If the additional bits have changed their value due to the correction, then the error that occurred was certainly corrected incorrectly. Thus, with ε = 1, half of the incorrectly corrected errors can be detected and generalized. 1−12ε The incorrectly corrected errors are detected. The number of added bits should be stored for each check byte.

[0089] The following section explains in more detail the application of the described procedure for 1-byte error-correcting Reed-Solomon codes.

[0090] A 1-byte error-correcting Reed-Solomon code is given by the H-matrix in equation (39) H=(α0α1 α2…αn−1α0α2 α4…(α2)n−1)=(H1H2) given. α 0 ,α 1 , α 2 , ...,α n-1 with n = 2 m - 1 are again elements in exponential representation of the Galois field GF(2 m ). The H-matrix has the equivalent representation in equation (40), H=(T0T1 T2…Tn−1T0T2 T4…(T2)n−1)=(H1H2), which elements are used in matrix representation.

[0091] For this code, the ε additional bits can be, for example, provided by the function f(u1u2…um)=u1u2…um00…0︸ε, These additional bits are generated. Since these extra bits are not stored with the data bytes, they only need to be appended to the data bytes before encoding and then again before decoding. It follows that, after successful correction, the byte error values ​​at the positions of these added bits must always be "0".

[0092] If these additional bits after correction (of a 2-byte error) differ from the additional bits before correction, an error is detected. Each augmented vector can be modified by an element α. ij of the higher Galois field. This allows for the following: H1⋅(αi1αi2 ⋮αin)=s1 the first syndrome component is identified and through H2⋅(αi1αi2 ⋮αin)=s2 The second syndrome component will be determined.

[0093] As an example of the presented extension to a 1-byte error-correcting Reed-Solomon code, a code with the H-matrix in equation (39) is used. The code is extended with the presented extension, and an additional check byte is added. The two versions are then compared. The H-matrix shown in equation (44) contains elements of the Galois field GF(2). 4 ) in exponential notation and is unshortened. HA=(α0α1α2α3α4α5α6α7α8α9α10α11α12α13α14α0α2α4α6α8α10α12α14α1α3α5α7α9α11α13)

[0094] As mentioned, the code can now be extended by adding a check byte. The resulting code, for example, has the H-matrix in equation (45). The H-matrix H B also uses elements of the Galois field GF(2) 4) in exponential notation. HB=(α0α1α2α3α4α5α6α7α8α9α10α11α12α13α14α0α2α4α6α8α10α12α14α1α3α5α7α9α11α13α0α3α6α9α12α0α3α6α9α12α0α3α6α9α12)

[0095] Secondly, the code can be extended using the presented method. First, the number of additional bits to be stored is determined. In this example, a total of two additional bits, i.e., half of a complete byte, are to be added. This means that each check byte is extended by ε = 1 bit if the starting point is a code with the H-matrix (see equation (39)).

[0096] A 0 is appended to the right of the data bytes, which is not stored. The code therefore uses a truncated H-matrix with elements of the Galois field GF(2). 5 ) in exponential representation. These elements from GF(2 5 ) are divided by α̂ i of the elements α i from GF(2 4) differed. The extended code uses the H-matrix in equation (84). HC=(α^0α^1α^2α^3α^4α^5α^6α^7α^8α^9α^10α^11α^12α^13α^14α^0α^2α^4α^6α^8α^10α^12α^14α^16α^18α^20α^22α^24α^26α^28)

[0097] To illustrate the functionality of the presented extension using an example, the G-matrix is ​​first generated from the H-matrix. For this, the H-matrix is ​​transformed using the Gauss-Jordan algorithm into a form where the first matrix is ​​an identity matrix, such that H = (IP). Using the submatrix P, the G-matrix can then be generated in systematic form G = (P T I) be determined.

[0098] The G-matrix in equation (47) was obtained by this transformation of the H-matrix in equation (39). When using elements of the Galois field in matrix form, these must be used in their transposed form in the G-matrix. GA=(α3α5α0000000000000α8α120α000000000000α0α000α00000000000α3α 10000α0000000000α13α140000α000000000α2α1100000α00000000α14α5000 000α0000000α8α110000000α000000α14α1000000000α00000α13α300000000 0α0000α6α30000000000α000α6α1400000000000α00α2α12000000000000α0)

[0099] For the 1-byte error-correcting and 2-byte error-detecting Reed-Solomon code with the H-matrix (equation (45)), the G-matrix is ​​shown in equation (48). Due to the nature of the Reed-Solomon code, the 1-byte error-correcting and 2-byte error-detecting Reed-Solomon code loses one data byte that can be stored compared to the 1-byte error-correcting Reed-Solomon code, because of the additional checksum byte. Thus, one data byte is exchanged for one checksum byte. This is also evident in the G-matrix, since the matrix P T has three columns and the identity matrix is ​​one smaller. GB=(α6α13α11α0000000000000α2α5α50α00000000000α11α6α200α0000000000α8α12α0000α000000000α6α3α00000α00000000α6α0α500000α0000000α11α2α4000000α00000α10α9α80000000α0000α14α7α1400000000α0000α5α5α6000000000α000α12α8α1000000000α00α7α5α90000000000α0)

[0100] Die aus der H-Matrix (Gleichung (45)) erstellte G-Matrix in Gleichung (49) verwendet ebenfalls Elemente aus dem Galois-Feld GF(2 5 ) . GC=(α^3α^19α^00000000000000α^22α^130α^000000000000α^16α^2600α^000000000000α^29α^19000α^0000000000α^22α^140000α^000000000α^17α^1000000α^00000000α^13α^90 00000a^0000000a^12a^60000000a^000000a^9a^26000000000a^00000a^29a^110000000000a^0000a^14a^160000000000a^000a^19a^800000000000a^00a^11a^800000000000a^0)

[0101] All three codes can correct 1-byte errors. The first code cannot detect 2-byte errors, and the second code can detect all 2-byte errors. The third code, with the proposed extension, can detect a subset of 2-byte errors with fewer check bits than the second code, thus offering a more precise fit to the specification.

[0102] The following section considers a 2-byte error and illustrates its effects on the three codes. The 2-byte error is represented by the tuples (α 5 ,α 11 ) and (α 11 ,α 3 ) described. A byte error occurs at position α. 5 with the byte error value α 11 and simultaneously a byte error occurs at position α 11 with the byte error value α 3 on. In vector representation of the Galois field GF(2) 4 ) are the byte error values α11=(0111) and α3=(0001). Correction using the unmodified 1-byte error correcting code

[0103] The data word is represented by elements of the Galois field GF(2). 4 ) described in exponential notation. For example, the data word WA=(α5α12α14α6α6α2α1α6α5α7α0α0α3) used. By WA⋅GA=VA will be the code word VA=(α7α4α5α12α14α6α6α2α1α6α5α7α0α0α3) generated by the error (α 5 , α 11 )( α 11 , α 3 ) the codeword V A into the faulty word RA=(α7α4α5α12α14α1α6α2α1α6α5α4α0α0α3) changed. A change in the byte value means vA5+α11=rA5,aA11+α3=rA11 or α6+α11=α1, α7+α3=α4 or (0011)+(0111)=(0100),(1101)+(0001)=(1100).

[0104] The error syndrome s is described by the equation s=HA⋅RAT determined. The syndrome calculated with the equation has the syndrome components s1 = α 7 and s2 = α 7 The byte position α is derived from the syndrome components. i = α 0 and the byte error value α = α 7 determined. Since there is no way to distinguish the 2-byte error from a 1-byte error, this 2-byte error is treated as a 1-byte error at position α. 0 with the value α 7 incorrectly corrected. Correction using the unmodified 1-byte error correcting and 2-byte error detecting code

[0105] The same 2-byte error (α) will occur again. 5 ,α 11 )(α 11 ,α 3 ) considered, this time in connection with the Reed-Solomon code, which corrects 1-byte errors and detects 2-byte errors. Here, the codeword can hold one less data byte, therefore a byte is omitted from the end of the data word. From the data word WB=(α5α12α14α6α6α2α1α6α5α7α0α0) The codeword is obtained by multiplication with the G-matrix. VB=(α5α5α5α5α12α14α6α6α2α1α6α5α7α0α0) generated. Due to the 2-byte error, the codeword changes to the erroneous word. RB=(α5α5α5α5α12α10α6α6α2α1α6α11α7α0α0).

[0106] The syndrome components determined using the H-matrix are s1 = α 7 , s2 = α 7 and s3 = α 1 .

[0107] For a 1-byte error, the following equation applies: 0=s1⋅s3+s22, A 2-byte error cannot satisfy this equation; therefore, the following holds true: 0≠s1⋅s3+s22. This allows 1-byte errors and 2-byte errors to be distinguished.

[0108] In this case, the equation yields α7⋅α1+α14=α6 0≠α6 This allows the 2-byte error to be successfully detected. Such calculations are relatively slow compared to checking a single bit.

[0109] For a given number of data bytes, an additional check byte of 4 bits is used here. In the general case of GF(2) m ) m bits are no longer usable as data bytes, but are stored as check bytes. Correction using the modified 1-byte error correcting code

[0110] The error under consideration must be described differently for the proposed codes and procedures.

[0111] In the Galois field GF(2 4 ) the 2-byte error that occurred at byte position α was corrected. 5 with the byte error value α 11 = 0111 and in byte position α 11 with the byte error value α 3 = 0001 is falsified.

[0112] Each byte value read from the memory cells has a bit with the value "0" appended to it. Similarly, a bit with the value "0" is appended to each byte error value, so that the byte error value 0111 becomes the byte error value 01110 = α̂ after the bit with the value "0" is appended. 12 in the Galois field GF(2 5 ) corresponds to. Similarly, the byte error value 0001 after appending a bit with the value "0" corresponds to the value 00010 = α̂ 3 in the Galois field GF(2 5 ).

[0113] The byte error value is displayed. α11=(0111)to(01110)=α^12 and α3=(0001)to(00010)=α^3.

[0114] If we attach GF(2) to each element of the Galois field 4 ) in vector representation a “0” so these vectors can be considered elements of the Galois field GF(2 5 ) can be interpreted in vector form. For a set A with all elements α i from the Galois field GF(2 4) und eine Menge  mit den Elementen α̂ j from GF(2 5 ) die in Vektordarstellung an letzter Stelle eine „0“ haben kann die Abbildung F:A→ mit F(α0)=α^0,F(α1)=α^1,F(α2)=α^2,F(α3)=α^3,F(α4)=α^18,F(α5)=α^19,F(α6)=α^20,F(α7)=α^27,F(α8)=α^5,F(α9)=α^6,F(α10)=α^11,F(α11)=α^12,F(α12)=α^23,F(α13)=α^8,F(α14)=α^29 be determined.

[0115] Der 2-Byte-Fehler kann mit Elementen des Galois-Feldes GF(2 5 ) in Exponentendarstellung durch die Tupel (α̂ 5 ,a 12 )(a 11 ,a 3 ) beschreibung werden. Das Datenwort W A kann durch Gleitung (67) in das verwendbare Datenwort Wc=(α^19α^23α^29α^20α^20α^2α^1α^20α^19α^27α^0α^0α^3) transformiert werden. Durch Multiplication von W C with the G-Matrix G C aus Gleichung (49) entsteht das Codewort Vc=(α^0α^9α^19α^23α^29α^20α^20α^2α^1α^20α^19α^27α^0α^0α^3).

[0116] The first two check bytes are stored completely, and the fifth position of the data bytes is always "0" and therefore does not need to be stored. If the codeword V is used... C due to the 2-byte error (α̂ 5 ,α̂ 12 )(α̂ 11 ,α̂ 3 The incorrect word has been changed by Rc=(α^0α^9α^19α^23α^29α^1α^20α^2α^1α^20α^19α^18α^0α^0α^3). describable. The multiplication of the H-matrix H C from equation (45) with RCT This results in the error syndrome with the syndrome components s1 = α̂ 12 and s2 = α̂ 20 If this is now treated like a regular 1-byte error, the error position is determined as follows: α^i=s2s1=α^20α^12=α^8 and the byte error value to a=s1α^i=α^12α^8=α^4.

[0117] The incorrectly determined byte error value α^4=(00001) Its 5th bit position has the value "1".

[0118] However, since all error-free byte values ​​in the 5th byte position are equal to "0", it is recognized that a miscorrection has occurred and that there was no 1-byte error.

[0119] The error is detected solely because the 5th bit position of the byte error value equals "1". Therefore, no additional calculations are required. Simulation of 2-byte errors

[0120] This section presents the results of the simulation of all possible 2-byte errors for a 1-byte error-correcting Reed-Solomon code with the proposed modification and compares them with simulations of all 2-byte errors of unmodified 1-byte error-correcting Reed-Solomon codes.

[0121] For this purpose, all possible 2-byte errors are corrected for an unmodified m-bit byte 1-byte error-correcting Reed-Solomon code and for the modified m'-bit byte (m' = m + ε) 1-byte error-correcting Reed-Solomon code. (n2)n=2m−1 or (n'2)(n'=2m'−1) with all possible byte error values ​​n 2 or n '2 simulated. During the simulation, if an error occurs at a data byte position, the elements of the n' elements from GF(2) are replaced. m' ) excluded those that would produce an error in the additional bits.

[0122] The simulations used a method in which zeros are appended to the data bytes ε. After correction, it was classified whether the error was detected by the modification, by shortening the code, or by the syndromes alone. The percentage indicates the probability of detecting a 2-byte error when the probability of the error distribution follows a uniform distribution.

[0123] The results are summarized in Table 2. The column "m" describes the m used in GF(2) for the unmodified original code. m). “m'” specifies the Galois field GF(2) used by the modification. m' ) and can be calculated from "m" and the next column ε. "n= 2 m -1" and "n'=2 m'-1 represents the maximum number of non-zero elements in the Galois arrays, where "n" corresponds to the code length. The "shortened" column lists the errors detectable by shortening the code. "ε false" is the number of errors where the ε bits no longer match the added zeros after correction, and "ε correct" is the number of errors that could not be detected by either shortening or modifying the code. For a 2-byte error, s1 = s2 = 0 cannot occur, but s1 = 0 or s2 = 0 can. These cases are represented as "s1 null" and "s2 null". "Total" is the total number of possible 2-byte errors, and "%" is the probability of detecting a 2-byte error with a uniform distribution of errors.

[0124] The first row of Table 2 describes the case where m = 3 is the Galois field GF(2 3The code uses a 1-byte error-correcting Reed-Solomon code. No additional bits are used, therefore ε equals 0. Since the code is unshortened, no errors are shown in the "shortened" column. Similarly, the unmodified code cannot detect errors using the additional bits, which are listed in "ε incorrect". The number of errors not detected by either shortening or modification is 735, as can be seen in the "ε correct" column.

[0125] If a 1-byte error occurs, then s1 cannot be zero, s2 cannot be zero, and s1 and s2 cannot both be zero simultaneously. With a 2-byte error, either s1 can be zero or s2 can be zero, but both components of the error cannot be zero at the same time. The validity of this statement, as well as how it distinguishes a 2-byte error from a 1-byte error, will be demonstrated later.

[0126] This code contains a total of (72)⋅72=1029 Two-byte errors are possible, and 28.5% of them can be detected. This two-byte error detection probability is comprised of 147 cases where s1 equals zero and 147 cases where s2 equals zero.

[0127] The second line summarizes the results of a modified and thus shortened 1-byte error-correcting Reed-Solomon code. The code uses seven of the 15 possible non-zero elements of the Galois field GF(2). 4 This allows 944 two-byte errors to be detected through the shortening and an additional 246 errors through the modification. Setting s1 to zero and s2 to zero each detects 115 errors. 345 two-byte errors out of a total of 1765 possible errors go undetected, meaning that with just one additional bit (two extra bits that need to be stored), over 80% of the two-byte errors are already detected.

[0128] In the third row of the table, the code uses a Galois field GF(2). 5 The original code was extended by two additional bits. In the simulation, this modified code detects 2802 errors due to the shortening and 361 errors due to the modification. 228 errors go undetected. Therefore, 93.7% of the 3621 errors are detected.

[0129] To illustrate another simulation, let's consider the line with m = 5 and ε = 2. Of the 634,641 two-byte errors, 478,816 are detected by shortening the code. The remaining 102,242 two-byte errors, which are not detected by shortening, are detected by modifying the code. An additional 4,991 two-byte errors are detected by setting s1 to zero, and 4,879 two-byte errors are detected by setting s2 to zero. Therefore, with a uniform distribution, two additional bits per check byte detect a total of 93% of the two-byte errors. Differentiation between 1-byte and 2-byte errors by the syndrome components

[0130] It is shown that for a 1-byte error in a 1-byte error-correcting Reed-Solomon code, the syndrome components s1 and s2 cannot be "0". Let be an arbitrary 1-byte error at byte position α. i If the byte error value a occurred, then the syndrome components are... s1=αia and s2=α2ia to calculate. α i and α 2i The elements of a Galois field are non-zero, and 'a' is an m-bit byte that can be interpreted as an element of the Galois field. If s1 = 0 and s2 = 0, then 'a' equals 0, which is a contradiction. If s1 = 0 and s2 = 0, then 'a' also equals 0, which is a contradiction. Similarly, if s1 = 0 and s2 = 0, then 'a' also equals 0, which is also a contradiction.

[0131] The fact that the byte error value is zero contradicts the assumption that a 1-byte error has occurred; therefore, s1 ≠ 0 and s2 ≠ 0 in the case of a 1-byte error.

[0132] It is shown that for any 2-byte error in a 1-byte error-correcting Reed-Solomon code, the syndrome components s1 and s2 cannot be "0" simultaneously.

[0133] The 2-byte error occurs at byte position α i with the byte error value a and at byte position a j with the byte error value b. Assume there is a 2-byte error where s1 and s2 are equal to "0", then the syndrome components can be described with s1=αia+αjb=0 and s2=α2ia+α2jb=0 describe. There are again α i , α 2i , α j and α 2j Elements other than “0” of a Galois field and a and b are m-bit bytes that can be interpreted as elements of the Galois field.

[0134] Equation (75) for s1 is solved for α i rearranged and results αi=αjba.

[0135] If the second equation (76) is solved for α i Rearranged, this results in αi=α2jbαia.

[0136] The two rearranged equations are set equal to each other, resulting in the equation αjba=α2jbαia the αi+jb=α2jb This can be rearranged. That means that i + j = 2j, so i = j, and therefore both errors are in the same position.

[0137] The assumption that s1 = s2 = 0 in the case of a 2-byte error leads to a contradiction. It has been shown that in the case of a 2-byte error, both syndrome components cannot be zero simultaneously.

[0138] For a 2-byte error, one of the syndrome components can result in "0", either equation (75) or equation (76) can hold.

[0139] The cases from the simulation for equation (75) are shown in Table 2 in the 9th column (s1 null).

[0140] If equation (76) applies to a 2-byte error, then these cases are located in the 10th column (s2 null) of Table 2.

[0141] Since equation (75) or equation (76) can apply to a 2-byte error, but this cannot occur with a 1-byte error, it is possible to distinguish 2-byte errors from 1-byte errors based on the syndrome components.

[0142] One effect of various methods according to aspects of this revelation is that a faulty correction can be detected very quickly using the additional bits, and no additional calculation is necessary.

[0143] The following explains various aspects of the revelation: Example 1 is a method for encoding a digital data word.The method may include: grouping a digital data word having a plurality of bits into at least one data word bit group, wherein the at least one data word bit group has at least two bits; adding at least one bit of a predefined value to the at least one data word bit group at a predefined position within the at least one data word bit group; encoding the extended at least one data word bit group with the at least one added bit, using an encoding method that operates on bit groups, such that a codeword is generated having at least one information bit group and at least one check word bit group; removing the at least one added bit from the at least one information bit group, so that at least one reduced information bit group is formed; and storing the at least one reduced information bit group and the at least one check word bit group. In Example 2, the subject of Example 1 may optionally feature that the digital data word is grouped into multiple data word bit groups, each data word bit group having at least two bits; and that at least one bit of a predefined value is added to each data word bit group at a predefined position within the respective data word bit group. In Example 3, the subject of either Example 1 or 2 may optionally include channel coding using a channel coding method that operates on groups of bits. In Example 4, the item may optionally exhibit any of Examples 1 to 3, such that the coding method is a Reed-Solomon code coding method or an abbreviated Reed-Solomon code coding method. In Example 5, the object of any of Examples 1 to 4 may optionally have the at least one bit with the predefined value added to the end of the at least one data word bit group. In Example 6, the item can optionally exhibit any of Examples 1 to 5 such that the predefined value of all added bits is the same. In Example 7, the item can optionally exhibit that the predefined value of at least some of the added bits is zero, as in any of Examples 1 to 6. In Example 8, the subject matter can optionally include any of Examples 1 to 7, and the method further includes storing the at least one reduced information bit group and the at least one check word bit group in a memory, for example, in a resistive random access memory (RRAM). Example 9 is a method for decoding a digital codeword. The method may include: grouping the digital codeword into at least one reduced information bit group and at least one checkword bit group, wherein the at least one reduced information bit group and the at least one checkword bit group each contain multiple bits; adding at least one bit of a predefined value at a predefined position within the at least one reduced information bit group, such that at least one information bit group is formed; decoding the at least one information bit group and the at least one checkword bit group using a decoding method that operates on bit groups, such that at least one reconstructed dataword bit group and at least one reconstructed checkword bit group, as well as a syndrome, are generated;Performing at least one bit group error correction in the at least one reconstructed data word bit group and / or in the at least one reconstructed check word bit group using the syndrome; and verifying the error correction using the at least one additional bit in the at least one reconstructed data word bit group. In Example 10, the subject of Example 9 may optionally include that the digital codeword is grouped into several reduced information bit groups and at least one checkword bit group, each reduced information bit group having at least two bits; that the several extended information bit groups and the at least one checkword bit group are decoded using the decoding procedure, generating several reconstructed dataword bit groups and at least one reconstructed checkword bit group, as well as a syndrome; that at least one bit group error correction is performed in at least one dataword bit group of the several reconstructed dataword bit groups and / or in the at least one reconstructed checkword bit group using the syndrome; and that the error correction is verified using the at least one additional bit in the at least one reconstructed dataword bit group. In Example 11, the subject of any of Examples 9 or 10 may optionally include the decoding of the at least one information bit group and the at least one check word bit group, channel decoding of the at least one information bit group and the at least one check word bit group using a channel decoding procedure that operates on bit groups, such that at least one reconstructed data word bit group and at least one reconstructed check word bit group and a syndrome are produced. In Example 12, the item may optionally include any of Examples 9 to 11, such that the decoding method is a Reed-Solomon code decoding method or an abbreviated Reed-Solomon code decoding method. In Example 13, the object can optionally have any of Examples 9 to 12 such that the at least one bit with the predefined value is added to the end of the at least one reduced information bit group. In Example 14, the item can optionally exhibit any of Examples 9 to 13 such that the predefined value of all added bits is the same. In Example 15, the item can optionally exhibit any of Examples 9 to 14 that the predefined value of at least some of the added bits is zero. In Example 16, the object of any of Examples 9 to 15 may optionally include the detection of an error if, during error correction checks, at least one bit with the predefined value at the respective predefined position of a reconstructed data word bit group does not have the corresponding predefined value. In Example 17, the object of any of Examples 9 to 16 may optionally exhibit that an error is detected if, during the error correction check, at least one bit with the predefined value is not in the predefined position of a reconstructed data word bit group. In Example 18, the subject matter of any of Examples 9 to 17 may optionally include the method further comprising a reading of the at least one reduced information bit group and the at least one check word bit group from a memory, for example, from a resistive random access memory (RRAM). Example 19 is a method for error correction in at least one digital byteword. The method may include: grouping the digital byteword into at least one data byte and at least one check byte, wherein the at least one data byte and the at least one check byte have multiple bits; supplementing the at least one data byte with at least one predefined additional bit for the byte position, so that at least one supplemented data byte is formed, wherein, in the error-free case, the at least one supplemented data byte forms a codeword of a byte error code; performing an error correction procedure that operates on bit groups, on the at least one supplemented data byte and the at least one check byte; and detecting an incorrect error correction if, after performing the error correction, an additional bit of the at least one data byte does not match the at least one predefined additional bit or an invalid byte error position is detected. In Example 20, the subject of Example 19 may optionally exhibit that an uncorrected error is displayed if an incorrect error correction has been detected. In Example 21, the object of any of Examples 19 or 20 may optionally have that the at least one digital byte word is read from a memory, wherein the at least one predefined additional bit is not stored in the memory. In Example 22, the item can optionally exhibit any of Examples 19 to 21 that the byte error code is a Reed-Solomon code or a truncated Reed-Solomon code. Example 23 is a device for encoding a digital data word. The device may include a processor configured to: group a digital data word having a plurality of bits into at least one data word bit group, wherein the at least one data word bit group has at least two bits; add at least one bit of a predefined value to the at least one data word bit group at a predefined position within the at least one data word bit group; encode the extended at least one data word bit group with the at least one added bit, using an encoding procedure that operates on bit groups, such that a codeword is produced having at least one information bit group and at least one check word bit group; remove the at least one added bit from the at least one information bit group, such that at least one reduced information bit group is formed;and storing the at least one reduced information bit group and the at least one check word bit group. In Example 24, the subject of Example 23 may optionally include that the processor is further configured to group the digital data word into multiple data word bit groups, each data word bit group having at least two bits; and that at least one bit of a predefined value is added to each data word bit group at a predefined position within the respective data word bit group. In Example 25, the subject of any of Examples 23 or 24 may optionally include that the processor is further configured to perform channel coding using a channel coding method that operates on groups of bits. In Example 26, the item may optionally include any of Examples 23 to 25, such that the coding method is a Reed-Solomon code coding method or an abbreviated Reed-Solomon code coding method. In Example 27, the subject of any of Examples 23 to 26 may optionally include that the processor is further configured to add the at least one bit with the predefined value to the end of the at least one data word bit group. In Example 28, the object can optionally include any of Examples 23 to 27, such that the processor is further configured so that the predefined value of all added bits is equal. In Example 29, the object of any of Examples 23 to 28 may optionally include that the processor is further configured such that the predefined value of at least some of the added bits is zero. In Example 30, the subject matter of any of Examples 23 to 29 may optionally include that the device further comprises a memory, for example a resistive random access memory (RRAM), in which the reduced information bit groups and the checkword bit groups are stored in one. Example 31 is a device for decoding a digital codeword. The device may include a processor configured to: group the digital codeword into at least one reduced information bit group and at least one checkword bit group, wherein the at least one reduced information bit group and the at least one checkword bit group each contain multiple bits; add at least one bit of a predefined value at a predefined position within the at least one reduced information bit group, such that at least one information bit group is formed; decode the at least one information bit group and the at least one checkword bit group using a decoding procedure that operates on bit groups, such that at least one reconstructed dataword bit group and at least one reconstructed checkword bit group, as well as a syndrome, are produced;Performing at least one bit group error correction in the at least one reconstructed data word bit group and / or in the at least one reconstructed check word bit group using the syndrome; and verifying the error correction using the at least one additional bit in the at least one reconstructed data word bit group. In Example 32, the subject of Example 31 may optionally include that the processor is further configured to group the digital codeword into several reduced information bit groups and at least one checkword bit group, each reduced information bit group having at least two bits; that the several information bit groups and the at least one checkword bit group are decoded using the decoding procedure, such that several reconstructed dataword bit groups and at least one reconstructed checkword bit group, as well as a syndrome, are generated; that at least one bit group error correction is performed in at least one dataword bit group of the several reconstructed dataword bit groups and / or in the at least one reconstructed checkword bit group using the syndrome;and that the error correction is verified using at least one additional bit in the at least one reconstructed data word bit group. In Example 33, the subject of any of Examples 31 or 32 may optionally include that the processor is further configured to perform channel decoding of the at least one information bit group and the at least one check word bit group using a channel decoding procedure that operates on bit groups, such that at least one reconstructed data word bit group and at least one reconstructed check word bit group and a syndrome are produced. In Example 34, the subject of any of Examples 31 to 33 may optionally include a Reed-Solomon code decoding method or an abbreviated Reed-Solomon code decoding method. In Example 35, the object of any of Examples 31 to 34 may optionally include that the processor is further configured to add at least one bit with the predefined value to the end of each reduced information bit group. In Example 36, the object of any of Examples 31 to 35 may optionally include that the processor is further configured such that the predefined value of all added bits is equal. In Example 37, the object of any of Examples 31 to 36 may optionally include that the processor is further configured such that the predefined value of at least some of the added bits is zero. In Example 38, the subject of any of Examples 31 to 37 may optionally include that the processor is further configured to detect an error if, during the error correction check, the at least one bit with the predefined value at the respective predefined position of a reconstructed data word bit group does not have the corresponding predefined value. In Example 39, the subject of any of Examples 31 to 38 may optionally include that the processor is further configured to detect an error if, during error correction verification, the at least one bit with the predefined value is not in the predefined position at the respective predefined position of a reconstructed data word bit group. In Example 40, the subject matter of any of Examples 31 to 39 may optionally include that the device further comprises a memory, for example a resistive random access memory (RRAM), in which the reduced information bit groups and the checkword bit groups are stored. Example 41 is a device for error correction in at least one digital byteword.The device may include a processor configured to: group the digital byte word into at least one data byte and at least one check byte, wherein the at least one data byte and the at least one check byte have multiple bits; supplement the at least one data byte with at least one predefined additional bit for the byte position, so that at least one supplemented data byte is formed, wherein, in the error-free case, the at least one supplemented data byte forms a codeword of a byte error code; perform an error correction procedure that operates on bit groups, on the at least one supplemented data byte and the at least one check byte; and detect an incorrect error correction if, after performing the error correction, an additional bit of the at least one data byte does not match the at least one predefined additional bit or an invalid byte error position is detected. In Example 42, the subject of Example 41 may optionally include the processor being further configured to indicate an uncorrected error if an incorrect error correction has been detected. In Example 43, the subject of any of Examples 41 or 42 may optionally include that the processor is further configured to read the at least one digital byteword from a memory, wherein the at least one predefined additional bit is not stored in the memory. In Example 44, the item may optionally exhibit any of Examples 41 to 43 that the byte error code is a Reed-Solomon code or a truncated Reed-Solomon code. Example 45 is a vehicle with a device according to one of Examples 23 to 44. In Example 46, the subject of Example 45 may optionally include a memory, for example a resistive direct access memory for storing the reduced information bit groups and / or the checkword bit groups. Example 47 is a chip card with a device according to one of Examples 23 to 44. In Example 48, the subject of Example 47 may optionally include a memory, for example a resistive direct access memory for storing the reduced information bit groups and / or the checkword bit groups. Example 49 is a computer-readable storage medium containing instructions which, when executed by a processor, implement a procedure for encoding a digital data word.The method may include: grouping a digital data word having a plurality of bits into at least one data word bit group, wherein the at least one data word bit group has at least two bits; adding at least one bit of a predefined value to the at least one data word bit group at a predefined position within the at least one data word bit group; encoding the extended at least one data word bit group with the at least one added bit, using an encoding method that operates on bit groups, such that a codeword is generated having at least one information bit group and at least one check word bit group; removing the at least one added bit from the at least one information bit group, so that at least one reduced information bit group is formed; and storing the at least one reduced information bit group and the at least one check word bit group. In Example 50, the subject of Example 49 may optionally feature that the digital data word is grouped into multiple data word bit groups, each data word bit group having at least two bits; and that at least one bit of a predefined value is added to each data word bit group at a predefined position within the respective data word bit group. In Example 51, the subject of any of Examples 49 or 50 may optionally include channel coding using a channel coding method that operates on groups of bits. In Example 52, the subject matter of any of Examples 49 to 51 may optionally include the coding method being a Reed-Solomon code coding method or an abbreviated Reed-Solomon code coding method. In Example 53, the object of any of Examples 49 to 52 may optionally have the at least one bit with the predefined value added to the end of the at least one data word bit group. In Example 54, the item can optionally exhibit any of Examples 49 to 53 such that the predefined value of all added bits is the same. In Example 55, the item can optionally exhibit any of Examples 49 to 54 that the predefined value of at least some of the added bits is zero. In Example 56, the subject of any of Examples 49 to 55 may optionally include the reduced information bit groups and the checkword bit groups being stored in a memory, for example, in a resistive random access memory (RRAM). Example 57 is a computer-readable storage medium containing instructions which, when executed by a processor, implement a method for decoding a digital codeword. The method may include: grouping the digital codeword into at least one reduced information bit group and at least one checkword bit group, wherein the at least one reduced information bit group and the at least one checkword bit group each contain multiple bits; adding at least one bit of a predefined value at a predefined position within the at least one reduced information bit group, such that at least one information bit group is formed;Decoding the at least one information bit group and the at least one check word bit group using a decoding method that operates on bit groups, such that at least one reconstructed data word bit group and at least one reconstructed check word bit group, as well as a syndrome, are generated; performing at least one bit group error correction in the at least one reconstructed data word bit group and / or in the at least one reconstructed check word bit group using the syndrome; and verifying the error correction using the at least one additional bit in the at least one reconstructed data word bit group. In Example 58, the subject of Example 57 may optionally include that the digital codeword is grouped into several reduced information bit groups and at least one checkword bit group, each reduced information bit group having at least two bits; that the several information bit groups and the at least one checkword bit group are decoded using the decoding procedure, such that several reconstructed dataword bit groups and at least one reconstructed checkword bit group, as well as a syndrome, are produced; that at least one bit group error correction is performed in at least one dataword bit group of the several reconstructed dataword bit groups and / or in the at least one reconstructed checkword bit group using the syndrome; and that the error correction is verified using the at least one additional bit in the at least one reconstructed dataword bit group. In Example 59, the subject of any of Examples 57 or 58 may optionally include the decoding of the at least one extended information bit group and the at least one check word bit group, a channel decoding of the at least one extended information bit group and the at least one check word bit group using a channel decoding procedure that operates on bit groups, such that at least one reconstructed data word bit group and at least one reconstructed check word bit group and a syndrome are produced. In Example 60, the subject of any of Examples 57 to 59 may optionally include a Reed-Solomon code decoding method or an abbreviated Reed-Solomon code decoding method. In Example 61, the object of any of Examples 57 to 60 may optionally have the at least one bit with the predefined value added to the end of the at least one reduced information bit group. In Example 62, the item can optionally exhibit any of Examples 57 to 61 such that the predefined value of all added bits is the same. In Example 63, the item of any of Examples 57 to 62 may optionally have the predefined value of at least some of the added bits zero. In Example 64, the subject of any of Examples 57 to 63 may optionally include the detection of an error if, during error correction checks, at least one bit with the predefined value at the respective predefined position of a reconstructed data word bit group does not have the corresponding predefined value. In Example 65, the subject of any of Examples 57 to 64 may optionally include the detection of an error if, during the error correction check, at least one bit with the predefined value is not in the predefined position of a reconstructed data word bit group. In Example 66, the object of any of Examples 57 to 65 may optionally include the reduced information bit groups and check word bit groups being read from a memory, for example, a resistive random access memory (RRAM). Example 67 is a computer-readable storage medium containing instructions which, when executed by a processor, implement an error correction procedure in at least one digital byteword.The method may include: grouping the digital byteword into at least one data byte and at least one check byte, wherein the at least one data byte and the at least one check byte have multiple bits; supplementing the at least one data byte with at least one predefined additional bit for the byte position, so that at least one supplemented data byte is formed, wherein, in the error-free case, the at least one supplemented data byte forms a codeword of a byte error code; performing an error correction procedure that operates on bit groups, on the at least one supplemented data byte and the at least one check byte; and determining an incorrect error correction if, after performing the error correction, an additional bit of the at least one data byte does not match the at least one predefined additional bit or an invalid byte error position is determined. In Example 68, the subject of Example 67 may optionally exhibit that an uncorrected error is displayed if an incorrect error correction has been detected. In Example 69, the object of any of Examples 67 or 68 may optionally have that the at least one digital byte word is read from a memory, wherein the at least one predefined additional bit is not stored in the memory. In Example 70, the item may optionally exhibit any of Examples 67 to 69 that the byte error code is a Reed-Solomon code or a truncated Reed-Solomon code. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited non-patent literature

[0000] SB Wicker, Error control systems for digital communication and storage, Prentice Hall, ISBN 0-13-200809-2, pages 190 to 193, 1995

[0004] TRN Rao and E. Fujiwara, Error-control coding for computer systems, Prentice Hall, ISBN 0-13-283953-9, pages 246 to 252, 1989

[0004]

Claims

[1] A method (300) for encoding a digital data word, the method (300) comprising: • grouping (302) a digital data word (102) having a plurality of bits into at least one data word bit group (DB), wherein the at least one data word bit group (DB) has at least two bits; • adding (304) to the at least one data word bit group (DB) at least one bit (Zb) of a predefined value at a predefined position within the at least one data word bit group (DB); • encoding (306) the extended at least one data word bit group (106) with the at least one added bit, using an encoding method that operates on bit groups, so that a code word (110) is generated comprising at least one information bit group (112) and at least one check word bit group (114); • removing (308) the at least one added bit (Zb) from the at least one information bit group (112) so that at least one reduced information bit group (116) is formed; and • Storing (310) the at least one reduced information bit group (116) and the at least one check word bit group (114). [2] A method (400) for decoding a digital codeword (120), the method (400) comprising: • Grouping (402) the digital codeword (120) into at least one reduced information bit group (204) and at least one check word bit group (206), wherein the at least one reduced information bit group (204) and the at least one check word bit group (206) each have a plurality of bits; • adding (404) at least one bit (Zb) of a predefined value at a predefined position within the at least one reduced information bit group (204) so that at least one information bit group (208) is formed; • decoding (406) the at least one information bit group (208) and the at least one check word bit group (206) using a decoding method that operates on bit groups, so that at least one reconstructed data word bit group (212) and at least one reconstructed check word bit group and a syndrome are generated; • performing (408) at least one bit group error correction (210) in the at least one reconstructed data word bit group (212) and / or in the at least one reconstructed check word bit group using the syndrome; and • Checking (410) the error correction (210) using the at least one additional bit (Zb) in the at least one reconstructed data word bit group (212). [3] A method (500) for correcting errors in at least one digital byte word, the method comprising: • Grouping (502) the digital byte word into at least one data byte and at least one check byte, wherein the at least one data byte and the at least one check byte have a plurality of bits, wherein the at least one digital byte word forms a code word of a byte error code in the error-free case; • Supplementing (504) the at least one data byte with at least one additional bit predefined for the byte position, so that at least one supplemented data byte is formed; • performing (506) an error correction method operating on bit groups on the at least one supplemented data byte and the at least one check byte; and • Determining (508) an erroneous error correction if, after performing the error correction, an additional bit of the at least one data byte does not match the at least one predefined additional bit or an invalid byte error position is determined. [4] Device (100) for encoding a digital data word (102), the device comprising a processor (104) which is arranged to: • Grouping a digital data word (102) having a plurality of bits into at least one data word bit group (DB), wherein the at least one data word bit group (DB) has at least two bits; • Adding to the at least one data word bit group (DB) at least one bit (Zb) of a predefined value at a predefined position within the at least one data word bit group (DB); • encoding the extended at least one data word bit group with the at least one added bit, using a coding method that operates on bit groups, so that a code word (110) is generated comprising at least one information bit group (112) and at least one check word bit group (114); • removing the at least one added bit (Zb) from the at least one information bit group (112) so that at least one reduced information bit group (116) is formed; and • Storing the at least one reduced information bit group (116) and the at least one check word bit group (114). [5] Device (100) according to claim 4, wherein the processor (104) is further configured to • the digital data word (102) is grouped into a plurality of data word bit groups (DB), each data word bit group (DB) having at least two bits; • at least one bit of a predefined value is added to each data word bit group (DB) at a predefined position within the respective data word bit group (DB). [6] The apparatus (100) of claim 4 or 5, wherein the processor (104) is further configured such that the coding comprises channel coding using a channel coding method operating on bit groups. [7] The device (100) according to any one of claims 4 to 6, wherein the coding method comprises a Reed-Solomon code coding method or a truncated Reed-Solomon code coding method. [8] Device (100) according to one of claims 4 to 7, wherein the processor (104) is further configured to add the at least one bit (Zb) with the predefined value to the end of the at least one data word bit group (DB). [9] Device (100) according to one of claims 4 to 8, wherein the processor (104) is further arranged such that the predefined value of all added bits (Zb) is the same. [10] The device (100) according to any one of claims 4 to 9, wherein the processor (104) is further configured such that the predefined value of at least some of the added bits (Zb) is zero. [11] Device (100) according to one of claims 4 to 10, further comprising: a memory (118), in particular a resistive random access memory (RRAM), in which the at least one reduced information bit group (116) and the check word bit groups are stored in one (114). [12] Device (200) for decoding a digital code word (120), the device (200) comprising a processor (202) which is arranged to: • Grouping the digital codeword (120) into at least one reduced information bit group (204) and at least one checkword bit group (206), wherein the at least one reduced information bit group (204) and the at least one checkword bit group (206) each have a plurality of bits; • adding at least one bit (Zb) of a predefined value at a predefined position within the at least one reduced information bit group (204) so that at least one information bit group (208) is formed; • Decoding the at least one information bit group (208) and the at least one check word bit group (206) using a decoding method that operates on bit groups, so that at least one reconstructed data word bit group (212) and at least one reconstructed check word bit group and a syndrome are generated; • performing at least one bit group error correction in the at least one reconstructed data word bit group (212) and / or in the at least one reconstructed check word bit group using the syndrome; and • Checking the error correction using the at least one additional bit in the at least one reconstructed data word bit group (212). [13] The device (200) according to claim 12, wherein the processor (202) is further configured to • the digital codeword (120) is grouped into a plurality of reduced information bit groups (204) and at least one checkword bit group (206), each reduced information bit group (204) having at least two bits; • the plurality of information bit groups (208) and the at least one check word bit group (206) are decoded using the decoding method so that a plurality of reconstructed data word bit groups (212) and at least one reconstructed check word bit group (206) and a syndrome are generated; • at least one bit group error correction (210) is performed in at least one reconstructed data word bit group (212) of the plurality of reconstructed data word bit groups (212) and / or in the at least one reconstructed check word bit group using the syndrome; and • the error correction is checked using the at least one additional bit in the at least one reconstructed data word bit group (212). [14] The apparatus (200) of claim 12 or 13, wherein the processor (202) is further configured such that decoding the at least one information bit group (208) and the at least one check word bit group (206) comprises channel decoding the at least one information bit group (208) and the at least one check word bit group (206) using a channel decoding method that operates on bit groups, such that at least one reconstructed data word bit group (212) and at least one reconstructed check word bit group and a syndrome are generated. [15] The apparatus (200) according to any one of claims 12 to 14, wherein the decoding method comprises a Reed-Solomon code decoding method or a truncated Reed-Solomon code decoding method. [16] Device (200) according to one of claims 12 to 15, wherein the processor (202) is further configured to add the at least one bit (Zb) having the predefined value to the end of the at least one reduced information bit group (204). [17] Device (200) according to one of claims 12 to 16, wherein the processor (202) is further arranged such that the predefined value of all added bits (Zb) is the same. [18] The device (200) according to any one of claims 12 to 17, wherein the processor (202) is further configured such that the predefined value of at least some of the added bits (Zb) is zero. [19] Device (200) according to one of claims 12 to 18, wherein the processor (202) is further configured to detect an error if, when checking the error correction, the at least one bit with the predefined value at the respective predefined position of a reconstructed data word bit group (212) does not have the corresponding predefined value. [20] Device (200) according to one of claims 12 to 19, wherein the processor (202) is further configured to detect an error if, when checking the error correction, the at least one bit with the predefined value at the respective predefined position of a reconstructed data word bit group (212) is not at the predefined position. [21] Device (200) according to one of claims 12 to 20, further comprising: a memory (118), in particular a resistive random access memory (RRAM), in which the reduced information bit groups (204) and the check word bit groups (206) are stored. [22] Device for correcting errors in at least one digital byte word, the device comprising a processor which is arranged to: • Grouping the digital byte word into at least one data byte and at least one check byte, wherein the at least one data byte and the at least one check byte have a plurality of bits; • Supplementing the at least one data byte with at least one additional bit predefined for the byte position, so that at least one supplemented data byte is formed, wherein the at least one supplemented data byte forms a code word of a byte error code in the error-free case; and • Performing an error correction procedure that operates on bit groups, on the at least one supplemented data byte and the at least one check byte; • Determining an incorrect error correction if, after performing the error correction, an additional bit of the at least one data byte does not match the at least one predefined additional bit or an invalid byte error position is determined. [23] The apparatus of claim 22, wherein the processor is further configured to indicate an uncorrected error when an erroneous error correction has been detected. [24] The apparatus of claim 22 or 23, wherein the processor is further configured to read the at least one digital byte word from a memory, wherein the at least one predefined additional bit is not stored in the memory. [25] Apparatus according to any one of claims 22 to 24, wherein the byte error code is a Reed-Solomon code or a truncated Reed-Solomon code. [26] Vehicle or chip card with a device according to one of claims 4 to 25. [27] A computer-readable storage medium having stored therein instructions that, when executed by a processor (104), implement a method (300) for encoding a digital data word (102), the method (300) comprising: • grouping (302) a digital data word (102) having a plurality of bits into at least one data word bit group (DB), wherein the at least one data word bit group (DB) has at least two bits; • adding (304) to the at least one data word bit group (DB) at least one bit (Zb) of a predefined value at a predefined position within the at least one data word bit group (DB); • encoding (306) the extended at least one data word bit group (106) with the at least one added bit, using an encoding method that operates on bit groups, so that a code word (110) is generated comprising at least one information bit group (112) and at least one check word bit group (114); • removing (308) the at least one added bit (Zb) from the at least one information bit group (112) so that at least one reduced information bit group (116) is formed; and • Storing (310) the at least one reduced information bit group (116) and the at least one check word bit group (114). [28] A computer-readable storage medium having stored therein instructions that, when executed by a processor (202), implement a method (400) for decoding a digital codeword (120), the method comprising: • Grouping (402) the digital codeword (120) into at least one reduced information bit group (204) and at least one check word bit group (206), wherein the at least one reduced information bit group (204) and the at least one check word bit group (206) each have a plurality of bits; • adding (404) at least one bit (Zb) of a predefined value at a predefined position within the at least one reduced information bit group (204) so that at least one information bit group (208) is formed; • decoding (406) the at least one information bit group (208) and the at least one check word bit group (206) using a decoding method that operates on bit groups, so that at least one reconstructed data word bit group (212) and at least one reconstructed check word bit group and a syndrome are generated; • performing (408) at least one bit group error correction in the at least one reconstructed data word bit group (212) and / or in the at least one reconstructed check word bit group using the syndrome; and • Checking (410) the error correction using the at least one additional bit (Zb) in the at least one reconstructed data word bit group (212). [29] A computer-readable storage medium having stored therein instructions which, when executed by a processor, implement a method (500) for correcting errors in at least one digital byte word, the method (500) comprising: • Grouping (502) the digital byte word into at least one data byte and at least one check byte, wherein the at least one data byte and the at least one check byte have a plurality of bits, wherein the at least one digital byte word forms a code word of a byte error code in the error-free case; • Supplementing (504) the at least one data byte with at least one additional bit predefined for the byte position, so that at least one supplemented data byte is formed; and • performing (506) an error correction method operating on bit groups on the at least one supplemented data byte and the at least one check byte; • Determining (508) an erroneous error correction if, after performing the error correction, an additional bit of the at least one data byte does not match the at least one predefined additional bit or an invalid byte error position is determined.

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