Power supply binning and temperature compensation for an I / O interface

DE102023116267A1Pending Publication Date: 2024-12-24INTEL CORP
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Patent Information

Application Number
DE102023116267
Authority / Receiving Office
DE · DE
Patent Type
Applications
Current Assignee / Owner
Filing Date
2023-06-21
Publication Date
2024-12-24

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Abstract

The present disclosure relates to a circuit (400) comprising: a delay-locked loop circuit (402) comprising a charge pump (406) configured to generate a bias voltage and a voltage-controlled delay line (408) controlled by the bias voltage, the voltage-controlled delay line comprising at least one transistor; a threshold voltage generator (410) for generating a signal representing a threshold voltage of the transistor; and a monitoring circuit (412) configured to: receive the signal representing the threshold voltage; supply, in sequence, a plurality of supply voltages to the delay-locked loop circuit (402); receive, for each supply voltage, a respective bias voltage generated by the charge pump (406); and determine, for each supply voltage, the corresponding behavior of the bias voltage with respect to the threshold voltage.and selecting one of the many supply voltages as the operating supply voltage, if the respective behavior of the bias voltage meets a predetermined criterion.
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Claims

[1] A circuit (400) comprising: a delay-locked loop circuit (402), the delay-locked loop circuit (402) comprising: a phase detector (404) configured to generate an output signal representing a phase difference between a reference signal and a feedback signal; a charge pump (406) configured to generate a bias voltage based on the output signal of the phase detector (404); and a voltage-controlled delay line (408) configured to impose a delay on the reference signal as a function of the bias voltage and to generate the feedback signal in response to the bias voltage, wherein the voltage-controlled delay line (408) comprises at least one delay cell for imposing a delay on the reference signal, wherein the at least one delay cell comprises at least one transistor; a threshold voltage generator (410) configured to generate a signal representing a threshold voltage of the at least one transistor; and a monitoring circuit (412) arranged to: Receiving the signal from the threshold voltage generator (412) representing the threshold voltage of the at least one transistor; supplying, in sequence, a plurality of supply voltages to the delay locked loop circuit (402); Receiving, for each supply voltage of the plurality of supply voltages, a respective bias voltage generated by the charge pump (406); Determining, for each supply voltage of the plurality of supply voltages, a corresponding behavior of the bias voltage generated by the charge pump (406) with respect to the threshold voltage of the at least one transistor; and Selecting one of the plurality of supply voltages as the operating supply voltage of the delay-locked loop circuit (402) if the respective behavior of the bias voltage satisfies a predetermined criterion with respect to the threshold voltage. [2] Circuit (400) according to claim 1, wherein the monitoring circuit (412) is arranged to: Determining, for each supply voltage of the plurality of supply voltages, a respective overdrive voltage corresponding to a difference between the corresponding bias voltage generated by the charge pump (406) and the threshold voltage of the at least one transistor of the at least one delay cell; Comparing the overdrive voltages associated with different supply voltages; and Selecting one of the plurality of supply voltages as the operating supply voltage of the delay-locked loop circuit (402) based on the result of the comparison. [3] Circuit (400) according to claim 1 or 2, wherein the monitoring circuit (412) is arranged to: Determining a first difference between a first overdrive voltage associated with a first supply voltage and a second overdrive voltage associated with a second supply voltage, wherein the first supply voltage and the second supply voltage are successive supply voltages with respect to the voltage value within the plurality of supply voltages; Determining a second difference between the second overdrive voltage associated with the second supply voltage and a third overdrive voltage associated with a third supply voltage, wherein the second supply voltage and the third supply voltage are successive supply voltages with respect to the voltage value within the plurality of supply voltages; and Selecting the first overdrive voltage as the operating supply voltage of the delay-locked loop circuit (402) if the first difference is less than a predetermined threshold and the second difference is greater than the predetermined threshold. [4] The circuit (400) of claim 3, wherein the predetermined threshold for the difference between the overdrive voltages is a relative change in the value of the overdrive voltages associated with different supply voltages. [5] Circuit (400) according to one of claims 1 to 4, wherein the monitoring circuit (412) is further configured to: Causing or instructing storage of supply voltage information representing the selected operating supply voltage to control a voltage supply to the charge pump (406) during operation of the circuit (400). [6] The circuit (400) of any one of claims 1 to 5, wherein the sequence of supply voltages is ordered starting with the supply voltage having the largest voltage value among the plurality of supply voltages to the supply voltage having the lowest voltage value among the plurality of supply voltages. [7] Circuit (400) according to one of claims 1 to 6, wherein the monitoring circuit (412) comprises an analog-to-digital converter (430) configured to: Generating, for each supply voltage of the plurality of supply voltages, a digital signal (432) representing the bias voltage generated by the charge pump (406) and the threshold voltage of the at least one transistor of the at least one delay cell; wherein the monitoring circuit (412) is arranged to: Comparing the digital signals associated with different supply voltages; and Selecting one of the plurality of supply voltages as the operating supply voltage of the delay-locked loop circuit (402) based on the result of the comparison. [8] A circuit (700) comprising: a temperature-sensitive circuit arrangement (702); at least one circuit (704) configured to output a voltage signal, wherein the at least one circuit (704) is configured such that a change in an operating temperature of the at least one circuit (704) causes a change in a voltage value of the voltage signal; and a processing circuit (706) arranged to: Receiving the voltage signal from the at least one circuit (704); Determining a temperature at which the at least one circuit (704) operates based on the voltage value of the voltage signal; and Establishing a temperature-based correction for operation of the temperature-sensitive circuitry (702) based on the determined temperature. [9] Input / output interface (102) comprising a circuit (400, 700) according to one of claims 1 to 8. [10] A method (610) for selecting an operating supply voltage of a delay-locked loop circuit, the method comprising: Receiving (612) a signal representing a threshold voltage of at least one transistor of a delay cell of a voltage-controlled delay line of the delay-locked loop circuit; supplying (614), in sequence, a plurality of supply voltages to the delay-locked loop circuit to operate a charge pump of the delay-locked loop circuit; Receiving (616) a respective bias voltage generated by the charge pump for each supply voltage of the plurality of supply voltages; Determining (618), for each supply voltage of the plurality of supply voltages, a corresponding behavior of the bias voltage generated by the charge pump with respect to the threshold voltage of the at least one transistor; and Selecting (620) one of the plurality of supply voltages as the operating supply voltage of the delay-locked loop circuit if the respective behavior of the bias voltage satisfies a predetermined criterion with respect to the threshold voltage.

Citation Information

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