Method for executing a function call, system and computer program product

Abstract

The invention relates to a method (100) for executing a function call, comprising: - Receiving (110) a function call comprising at least one function, - Providing (120) an instruction package, wherein the instruction package contains a list of main chip functions executable by a main chip (210), - Determine (130) whether at least one function of the function call is contained in the instruction package and / or can be composed from the main chip functions, and - Executing (140) the function call. Furthermore, the invention relates to a system (200) and a computer program product.

Description

[0001] The invention relates to a method for executing a function call, a system and a computer program product.

[0002] In modern computer systems, tasks are often performed by specialized computing units, also called processors or chips. For example, special chips may be dedicated to computing tasks such as graphics, simulation, artificial intelligence, or processing position sensor data. However, the results of these calculations are usually executed by a central processing unit, which then queries and further processes the results.

[0003] In modern computer systems, this parallel processing is becoming increasingly important to increase performance and efficiency. While the integration of main processors and accelerator processors offers many advantages, challenges also arise when these components are required to work together. In particular, the coordination and synchronization of the various processors regularly proves challenging.

[0004] A major problem arises from the different architectures and characteristics of main processors and accelerator processors. Main processors are generally designed for general-purpose computing and offer high flexibility for a wide range of tasks. Accelerator processors, on the other hand, are specialized units optimized for specific compute-intensive tasks.

[0005] The collaboration between these two types of processors requires seamless integration and efficient communication. Different memory access patterns, processing speeds, and instruction sets can lead to inefficiencies and impact overall system performance.

[0006] In addition, programming and operational issues can also arise. Developing applications that leverage the benefits of parallel processing often requires specialized knowledge and resources. Programming and optimizing software for a heterogeneous processor architecture can be complex and time-consuming. Furthermore, appropriate communication mechanisms must be implemented to efficiently exchange data between the different processors.

[0007] Furthermore, delays and latencies can also occur in communication between the main and accelerator processors. These delays can prevent the expected performance benefits of the accelerator processors from being fully utilized, thus impacting overall system performance.

[0008] It is therefore an object of the present invention to at least partially overcome at least one of the disadvantages described above. In particular, the object of the invention is to provide a method for executing a function call, a system, and a computer program product in which the execution of a function is accelerated, programming is simplified, and costs are reduced.

[0009] The above object is achieved by a method having the features of independent patent claim 1, by a system having the features of independent patent claim 6, and by a computer program product having the features of independent patent claim 10. Further features and details of the invention emerge from the subclaims, the description, and the drawings. Features and details described in connection with the method according to the invention naturally also apply in connection with the system according to the invention and / or in connection with the computer program product according to the invention, and vice versa, so that with regard to the disclosure of the individual aspects of the invention, reference is always made to each other.

[0010] According to the invention, a method for executing a function call is provided, comprising: - Receiving a function call comprising at least one function, in particular by the main chip, - Providing an instruction package, wherein the instruction package contains a list of main chip functions executable by a main chip, in particular by the main chip, - determining whether the at least one function of the function call is contained in the instruction package and / or can be composed of the main chip functions, in particular by the main chip, and - Executing the function call, especially by the main chip.

[0011] In other words, a method for executing a function call may be provided, which includes receiving an instruction to call a function and providing an instruction set architecture (ISA), wherein the instruction set architecture specifies which instructions are executable by a main processor. Furthermore, the method includes detecting whether the instruction is part of the instruction set architecture and / or whether the instruction can be composed of one or more instructions of the instruction set architecture, and starting the instruction.

[0012] The method steps can be performed at least partially simultaneously and / or sequentially, whereby the sequence of the method steps is not limited by the specified order, so that individual steps can be performed in different orders. Furthermore, individual or all steps can be performed repeatedly.

[0013] The method can be implemented as a computer-implemented method.

[0014] In the context of the invention, a function call can be understood as a method that allows a program to call a function and / or a subroutine. A function can comprise a named subsequence of instructions that performs a specific task and, in particular, accepts parameters and / or returns a value.

[0015] Receiving a function call can be understood as an instruction to the main chip to execute a specific function. Depending on the architecture of the main chip, different methods can be provided for how a function call can be implemented. The function call can be executed at least as a call instruction, processing a stack, linking in a link register, or jumping in a jump table.

[0016] Within the scope of the invention, an instruction packet can be understood as an Instruction Set Architecture (ISA). The instruction packet can be designed to define an interface between the hardware and the software. The instruction packet can comprise an abstract description of a main chip, which defines at least the instructions, registers, addressing modes, or memory organization supported by this main chip.

[0017] The instruction package can be ISA documentation, which is provided in particular by a major chip manufacturer and / or a body that defines the ISA. Furthermore, the instruction package can include the functions contained in the ISA documentation and be formatted in such a way that the main chip can determine whether a function is part of the instruction package. In a simple case, this can be done, for example, by searching for a string.

[0018] The instruction package can in particular be implemented as an instruction set architecture for an x86, an ARM, a Reduced Instruction Set Computer (RISC), a Microprocessor without Interlocked Pipeline Stages (MIPS), a Graphics Processing Unit (GPU), a Digital Signal Processor (DSP) or a machine learning application-specific integrated circuit (ML ASIC).

[0019] Providing an instruction packet may include storing the instruction packet in a memory accessible to the main chip and / or a memory of the main chip.

[0020] Determining whether the at least one function of the function call is contained in the instruction packet and / or can be composed of the main chip functions can be understood as an analysis executable by the main chip, in which the function is searched for in the instruction packet and / or one or more functions corresponding to the function are searched for in the instruction packet. Provision can be made for the determination to include dividing the function into subfunctions and / or combining and / or dividing functions of the instruction packet. A simple example would be dividing a multiplication function into several addition functions. Provision can therefore be made for an instruction packet function to be provided that corresponds to the function in the instruction packet and / or is composed of at least two functions that are contained in the instruction packet and, when combined, correspond to the function.

[0021] Executing the function call can be understood as initiating the steps required to execute the function, particularly on the main chip. The function call can be configured to call the functions contained in the instruction packet and / or that can be composed of the main chip functions. In other words, the previously determined functions are called. In other words, the instruction packet function is called.

[0022] The exact design of the function call depends heavily on the architecture of the main chip. The execution of the function call may also include passing parameters, jumping to the function, executing the function, reading the function's return value, and continuing the program.

[0023] It may also be provided that one or more functions intended for an accelerator chip are at least partially replaced by functions of the main chip. This simplification leads to the elimination of cost-intensive accelerator chips, especially ML accelerators, or the use of fewer or more cost-effective versions.

[0024] It can also be provided that functions that are part of an instruction package for an accelerator chip are added to the instruction package. This has the advantage that even instructions that were not originally executable by the main chip can be executed directly by the main chip, thus eliminating the need for accelerator chips entirely or partially.

[0025] Overall, the method according to the invention offers the advantage that the execution of a function is accelerated, programming is simplified and costs are reduced. Receiving a function call represents the reason for calling a function. By providing an instruction package, the functions stored there can be accessed. By determining whether the at least one function of the function call is contained in the instruction package and / or can be composed of the main chip functions, the function is analyzed using the instruction package, thus achieving the advantage of being able to determine whether the function actually requires a special, wide accelerator chip or can also be executed directly on the main chip. Executing the function call offers the advantage that the function can be executed if necessary.is executed directly on the main chip, thus avoiding delays caused by communication with one or more accelerator chips. In particular, the use of accelerator chips can be avoided altogether, thereby reducing costs. For programmers, use of the main chip is simplified, as no or fewer instructions need to be provided for communication between the chips. In other words, it avoids the main chip being choked by calls to accelerator chips, and prevents programmers from having to switch to other tools and programming models. The method according to the invention integrates the function calls into the ISA, so that programmers can use the additional functions with the same programming model.

[0026] Within the scope of the invention, it may be advantageous to further provide for the execution of a function call on an accelerator chip, wherein the function call comprises at least one special function, wherein the special function is not contained in the instruction packet and / or can be composed of the main chip functions. This achieves the advantage that even in the inherently unfavorable case that the function call is not completely contained in the instruction packet and / or can be composed of multiple functions of the instruction packet, the function still remains executable.

[0027] Within the scope of the invention, it is conceivable for the function call to be executed on the accelerator chip in parallel with and / or after the function call on the main chip. This provides the advantage that parallel execution enables an acceleration of program executions overall, particularly if the main chip executes additional functions or instructs other accelerator chips to execute functions while the function call is being executed by the accelerator chip. Executing the function call on the accelerator chip after the function call on the main chip provides the advantage that the accelerator chip does not delay the main chip, for example, by querying or sending a result.

[0028] Within the scope of the invention, it can be provided that the main chip communicates with the accelerator chip via an interprocessor communication protocol, wherein, in particular, the interprocessor communication protocol is integrated into the main chip. This achieves the advantage that the main chip can communicate efficiently with the accelerator chip. In particular, the integration of the interprocessor communication protocol into the main chip simplifies programmability and the actual calling of functions via the interprocessor communication protocol.

[0029] It is also conceivable for the function call to include at least one function intended for execution on an accelerator chip. This provides the advantage that a function originally intended for an accelerator chip can be found in the instruction packet of the main chip and / or can be composed of one or more functions accordingly, thus enabling execution by the main chip as well.

[0030] The above object is further achieved by a system according to the invention for carrying out a method for executing a function call, in particular according to one of the preceding claims, comprising a main chip which is designed to - to receive a function call comprising at least one function, - provide an instruction packet, the instruction packet containing a list of main chip functions executable by the main chip, - to determine whether the at least one function of the function call is contained in the instruction package and / or can be composed of the main chip functions, and - execute the function call.

[0031] Thus, a system according to the invention brings with it the same advantages as have been described in detail with reference to a method according to the invention.

[0032] It is also conceivable to provide an accelerator chip designed to execute a special function contained in the function call, whereby the special function is not contained in the instruction packet and / or can be composed of the main chip functions. The accelerator chip thus provides the advantage that the overall functionality of the system is still maintained for the non-resolvable functions.

[0033] Within the scope of the invention, it is optionally possible for the main chip and / or the accelerator chip to be embodied at least as a CPU, GPU, DSP, or ASIC, in particular a machine learning ASIC. A CPU offers the advantage of being designed for a wide variety of tasks and supporting a wide variety of applications. CPUs generally have high single-thread performance and can thus provide high-performance execution of a single thread or task. They offer good performance for sequential, not highly parallelizable tasks. GPUs offer the advantage of being designed and optimized for the simultaneous processing of many tasks. They have a high number of cores capable of processing large amounts of data in parallel. This makes them ideally suited for computationally intensive, parallelizable tasks such as graphics processing, simulations, and cryptocurrency mining.In addition, GPUs typically have high memory bandwidth, which is advantageous for tasks with high data throughput, such as training neural networks. A DSP is optimized for signal processing and offers high computing power and efficiency for tasks such as audio editing, image processing, speech recognition, and communication systems. This allows signals to be processed in real time and results to be provided quickly. ASICs offer particularly high performance and efficiency because they are specifically developed and optimized for a particular application. They can use specific hardware structures and functions tailored to the application and therefore generally consume less power than other, non-specialized chips. They can also be manufactured particularly cost-effectively in large quantities.Machine Learning ASICs are specifically designed to accelerate machine learning algorithms and therefore offer the advantage that machine learning-specific functions, especially matrix operations, can be performed particularly quickly and energy-efficiently.

[0034] Furthermore, within the scope of the invention, it can be provided that the CPU is implemented at least as an x86, Arm, RISC-V, or MIPS processor. x86, and in particular Intel processors, offer the advantage of broad support and compatibility. The large selection of software and developer tools developed specifically for x86 processors simplifies use for programmers. Furthermore, x86 processors generally offer high single-thread performance. An Arm CPU is characterized by its energy efficiency. Due to the good performance / consumption ratio, ARM CPUs can also be used in battery-powered systems, particularly in mobile devices, embedded systems, and IoT devices. RISCs, in particular RISC-V chips, have a comparatively simple instruction set architecture, which reduces implementation effort and increases execution speed.RISC CPUs also have low power consumption and operate more efficiently than more complex processors like x86. MIPS also offers a simple and efficient instruction set architecture that enables fast instruction decoding.

[0035] The above object is further achieved by a computer program product according to the invention, comprising instructions which, when the program is executed by a computer, in particular by a system according to the invention, cause the computer to carry out a method according to the invention.

[0036] Thus, a computer program product according to the invention brings with it the same advantages as have been described in detail with reference to a method according to the invention and / or a system according to the invention.

[0037] Further advantages, features, and details of the invention will become apparent from the following description, which describes several embodiments of the invention in detail with reference to the drawings. The features mentioned in the claims and in the description may be essential to the invention individually or in any combination. The invention is illustrated in the following figures: Fig. 1: a schematic overview of a method according to the invention, and Fig. 2: a schematic overview of a system according to the invention.

[0038] In the following figures, identical reference numerals are used for the same technical features, even in different embodiments.

[0039] Fig. 1 shows a method 100 according to the invention for executing a function call, comprising: - Receiving 110 a function call comprising at least one function, - Providing 120 an instruction packet, wherein the instruction packet contains a list of main chip functions executable by a main chip 210, - Determining 130 whether the at least one function of the function call is contained in the instruction package and / or can be composed of the main chip functions, and - Execute 140 the function call.

[0040] Overall, the method 100 according to the invention offers the advantage that the execution of a function is accelerated, programming is simplified, and costs are reduced. Receiving 110 a function call represents the reason for calling a function. By providing 120 an instruction packet, the functions stored there can be accessed. By determining 130 whether the at least one function of the function call is contained in the instruction packet and / or can be composed of the main chip functions, the function is analyzed using the instruction packet, thus achieving the advantage of being able to determine whether the function actually requires a special, wide accelerator chip 220 or can also be executed directly on the main chip 210. Executing the function call offers the advantage that the function can, if necessary,is executed directly on the main chip 210, thus avoiding delays caused by communication with one or more accelerator chips 220. In particular, the use of accelerator chips 220 may be avoided entirely, thereby reducing costs. For programmers, the use of the main chip 210 is simplified because no or fewer commands need to be provided for communication between the chips. In other words, it avoids the main chip 210 being choked by calls to accelerator chips 220, and it prevents programmers from having to switch to other tools and programming models. The method 100 according to the invention integrates the function calls into the ISA, so that programmers can use the additional functions with the same programming model.

[0041] Furthermore, execution 150 of a function call on an accelerator chip 220 may be provided, wherein the function call comprises at least one special function, wherein the special function is not contained in the instruction package and / or can be composed of the main chip functions. This provides the advantage that even in the inherently unfavorable case that the function call is not completely contained in the instruction package and / or can be composed of multiple functions of the instruction package, the function still remains executable.

[0042] Fig. 2 shows a system 200 according to the invention for executing a method 100 for executing a function call, in particular a method 100 according to the invention, comprising a main chip 210 which is designed to - to receive a function call comprising at least one function 110, - provide 120 an instruction packet, the instruction packet containing a list of main chip functions executable by the main chip 210, - to determine 130 whether the at least one function of the function call is contained in the instruction package and / or can be composed of the main chip functions, and - execute the function call 140.

[0043] Thus, a system according to the invention brings with it the same advantages as have been described in detail with reference to a method according to the invention.

[0044] The above explanation of the embodiments describes the present invention exclusively by way of examples. Of course, individual features of the embodiments can be freely combined with one another, provided they are technically feasible, without departing from the scope of the present invention. List of reference symbols 100 procedures 110 Received 120 Provision 130 Determine 140 Executing a function call on a main chip 150 Executing a function call on an accelerator chip 200 systems 210 main chip 220 accelerator chip

Claims

[1] A method (100) for executing a function call, comprising: - receiving (110) a function call comprising at least one function, - providing (120) an instruction packet, the instruction packet containing a list of main chip functions executable by a main chip (210), - determining (130) whether the at least one function of the function call is contained in the instruction package and / or can be composed of the main chip functions, and - Execute (140) the function call. [2] Method (100) according to claim 1, characterized by that further an execution (150) of a function call on an accelerator chip (220) is provided, wherein the function call comprises at least one special function, wherein the special function is not contained in the instruction package and / or can be composed of the main chip functions. [3] Method (100) according to claim 2, characterized bythat the execution (150) of the function call on the accelerator chip (220) takes place in parallel and / or after the execution (140) of the function call on the main chip (210). [4] Method (100) according to one of the preceding claims, characterized by that the main chip (210) communicates with the accelerator chip (220) via an interprocessor communication protocol, wherein in particular the interprocessor communication protocol is integrated in the main chip (210). [5] Method (100) according to one of the preceding claims, characterized by that the function call comprises at least one function which is intended for execution on an accelerator chip (220). [6] System (200) for executing a method (100) for executing a function call, in particular according to one of the preceding claims, comprising a main chip (210) which is designed to - to receive a function call comprising at least one function (110), - to provide (120) an instruction packet, the instruction packet containing a list of main chip functions executable by the main chip, - to determine (130) whether the at least one function of the function call is contained in the instruction package and / or can be composed of the main chip functions, and - execute the function call (140). [7] System (200) according to claim 6, characterized by that an accelerator chip (220) is further provided which is designed to execute a special function contained in the function call, wherein the special function is not contained in the instruction package and / or can be composed of the main chip functions. [8] System (200) according to claim 6 or 7, characterized bythat the main chip (210) and / or the accelerator chip (220) is designed at least as a CPU, GPU, DSP or ASIC, in particular a machine learning ASIC. [9] System (200) according to claim 8, characterized by that the CPU is at least x86, Arm, RISC-V or MIPS. [10] Computer program product, comprising instructions which, when the program is executed by a computer, in particular by a system (200) according to one of claims 6-9, cause the computer to carry out a method (100) according to one of claims 1-5.

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