METHOD FOR PREPARING A SUBSTATE

Abstract

Method for producing a substrate (10) for a semiconductor module, wherein the method comprises: Forms of a first electrically conductive layer (111) on a first side of a dielectric insulating layer (11); Structuring the first electrically conductive layer (111) by creating one or more continuous incisions in the first electrically conductive layer (111) extending from an upper surface of the first electrically conductive layer (111) to the dielectric insulating layer (11) in order to completely separate different sections of the first electrically conductive layer (111) from each other; and Forming a passivation layer (40), wherein the passivation layer (40) covers the entire surface of the structured first electrically conductive layer (111), wherein the passivation layer (40) comprises organic molecules with at least one functional group, and wherein the forming of the passivation layer (40) comprises treating the first electrically conductive layer (111) by means of a hydrofluoroether (HFE) purification process.

Description

[0001] The present invention relates to a substrate and a method for producing a substrate, in particular a method for producing a substrate for a power semiconductor module.

[0002] Document US 2011 / 0011531A1 discloses a method for removing oxidation from certain metallic contact surfaces using a combination of commercially available equipment and specialized chemicals. This method is a very fast, dry process that requires neither a vacuum nor a safety chamber or toxic gases / chemicals and does not damage sensitive electronic circuits or components. Furthermore, the process creates a passivation layer on the surface of the metallic contact, which prevents further oxidation and allows for a fast and complete bond, even many hours after surface treatment, without the need to remove the passivation layer. The process utilizes a plasma applicator for ambient environments containing hydrogen, nitrogen, and inert gases.

[0003] Document DE 11 2022 002 914 T5 discloses a method for manufacturing a flexible printed circuit board using a photoresist, comprising: arranging a photomask such that a translucent part is opposite a first zone in order to expose the photoresist;and arranging a second photomask with a second translucent part such that the second translucent part is opposite a second zone to expose the photoresist, each translucent part having a linear shape with tapered first and second tips, each having a corner region and curved sides, and satisfying the following inequality Δx <A<Δx+D-2×Δy×cosθ2×sinθ in der Δx ein Ausmaß der Abweichung des zweiten Ausrichtzielpunktes von der ersten Position in der ersten longitudinalen Richtung ist, Δy ein Ausmaß der Abweichung des zweiten Ausrichtzielpunktes von der ersten Position in der ersten Breitenrichtung ist, und θ ein Ausmaß der Abweichung des zweiten Ausrichtzielpunktes von der ersten Position in einer Drehrichtung um eine erste Normale ist, wobei die erste Normale eine Normale ist, die durch die erste Position hindurch geht und senkrecht auf der ersten Fotomaske steht.;

[0004] Document US 2019 / 0 338 414 A1 discloses a process for forming a passivation layer on a substrate, comprising providing a substrate in a processing chamber. The substrate has a metallic surface consisting of copper, tin, or silver, or an alloyed surface consisting of one or more of the materials copper, tin, or silver. The process further comprises depositing at least one organic layer onto the metallic surface by vapor deposition, wherein the organic layer is formed from an organic precursor. The organic precursor comprises a first functional group comprising at least one of the following elements: oxygen, nitrogen, phosphorus, sulfur, selenium, tellurium, or silicon, and a second functional group selected from hydroxyl (-OH) or carboxyl (-COOH). The first functional group is adsorbed onto the metal surface.The process further comprises the application of at least one inorganic layer to the organic layer by vapor deposition, wherein the second functional group serves as the attachment site for the inorganic layer.

[0005] Power semiconductor modules typically have one or more substrates, which may be arranged on a base plate or a heat sink. A semiconductor array with a multitude of controllable semiconductor devices (e.g., IGBTs) is arranged on at least one of the substrates. A substrate generally has an electrically insulating substrate layer (e.g., a ceramic layer), a first electrically conductive layer (e.g., a first metal layer) arranged on one side of the substrate layer, and a second electrically conductive layer (e.g., a second metal layer) arranged on the opposite side of the substrate layer. The controllable semiconductor devices are, for example, arranged on the first electrically conductive layer. The second electrically conductive layer is usually connected to the base plate or heat sink.connected to the heat sink, meaning that it is located between the base plate / heat sink and the electrically insulating substrate layer.

[0006] At least the first electrically conductive layer is usually a structured layer. This means that the layer has several spaced-apart sections, separated by continuous incisions in the first electrically conductive layer. To create the different sections, an initially continuous electrically conductive layer can be structured accordingly, for example, by etching. The continuous electrically conductive layer may already be contaminated before structuring. Furthermore, contaminants can also be introduced during the structuring process, which may unintentionally remain on the first electrically conductive layer after the structuring process. While any contaminants can be reliably removed completely in special cleaning steps, which usually follow the structuring, these steps are not always possible.If components are subsequently soldered onto the contaminated first electrically conductive layer, even the smallest individual impurities can lead to unwanted damage.

[0007] Therefore, there is a need for a substrate and a method for producing a substrate that is as little susceptible to damage as possible despite possible impurities.

[0008] A method for producing a substrate for a semiconductor module comprises: forming a first electrically conductive layer on a first side of a dielectric insulating layer, structuring the first electrically conductive layer by creating one or more continuous incisions in the first electrically conductive layer extending from an upper surface of the first electrically conductive layer to the dielectric insulating layer in order to completely separate different sections of the first electrically conductive layer from one another, and forming a passivation layer, wherein the passivation layer covers the entire surface of the structured first electrically conductive layer, and wherein the passivation layer comprises organic molecules with at least one functional group.The formation of the passivation layer involves treating the first electrically conductive layer using a hydrofluoroether (HFE) cleaning process.

[0009] A substrate for a semiconductor module comprises a dielectric insulating layer, a first electrically conductive layer arranged on a first side of the dielectric insulating layer, and a passivation layer, wherein the first electrically conductive layer is a structured layer with one or more incisions between different completely separated sections of the first electrically conductive layer, the passivation layer covers the entire surface of the structured first electrically conductive layer, and the passivation layer comprises organic molecules with at least one functional group.

[0010] The invention is explained in more detail below with reference to examples and the figures. The same reference numerals denote the same elements. The representation in the figures is not necessarily to scale.

[0011] Fig. Figure 1 shows an example of a cross-section through a substrate with semiconductor bodies arranged on it;

[0012] Fig. 2 , encompassing the Fig. Figures 2A to 2D show a conventional method for producing a substrate;

[0013] Fig. 3, encompassing the Fig. 3A and Fig. Figure 3B schematically shows the steps of a procedure for producing a substrate according to an example;

[0014] The following detailed description illustrates, using concrete examples, how the invention can be implemented. It is understood that the features of the various examples described herein can be combined with one another, unless otherwise stated. Where certain elements are designated as "first element," "second element," etc., the terms "first," "second," etc., serve only to distinguish between different elements. This designation does not imply any order or enumeration. This means, for example, that a "second element" can be present even if no "first element" is present.

[0015] Referring to Fig. Figure 1 shows a substrate 10. The substrate 10 has a dielectric insulating layer 11, a structured first electrically conductive layer 111, and a (structured) second electrically conductive layer 112. The first electrically conductive layer 111 is arranged on a first side of the dielectric insulating layer 11, and the second electrically conductive layer 112 is arranged on a second side of the dielectric insulating layer 11 opposite the first side. The dielectric insulating layer 11 is thus arranged between the first electrically conductive layer 111 and the second electrically conductive layer 112. The second electrically conductive layer 112 is optional. It is also possible to arrange only the first electrically conductive layer 111 on the dielectric insulating layer 11 and to omit the second electrically conductive layer 112 entirely.

[0016] Each of the first electrically conductive layer 111 and the second electrically conductive layer 112 can consist of or comprise one of the following materials: copper; a copper alloy; aluminum; an aluminum alloy; any other metal or metal alloy that remains in a solid state during operation of the power semiconductor module. The substrate 10 can be a ceramic substrate, that is, a substrate in which the dielectric insulating layer 11 consists of ceramic. The dielectric insulating layer 11 can thus, for example, be a thin ceramic layer. The ceramic of the dielectric insulating layer 11 can, for example, consist of or comprise one of the following materials: aluminum oxide; aluminum nitride; zirconium oxide; silicon nitride; boron nitride; or any other ceramic.For example, the dielectric insulating layer 11 can be made of or comprise one of the following materials: Al₂O₃, AlN, or Si₃N₄. The substrate 10 can be, for example, a so-called Direct Copper Bonding (DCB) substrate, a Direct Aluminum Bonding (DAB) substrate, an Insulated Metal Substrate (IMS), or an Active Metal Brazing (AMB) substrate. The substrate 10 can also be, for example, a conventional printed circuit board (PCB) with a non-ceramic dielectric insulating layer 11. A non-ceramic dielectric insulating layer 11 can, for example, be made of or comprise a cured resin.

[0017] Further referring to Fig. 1. One or more semiconductor bodies 20 can be arranged on the substrate 10. Each of the semiconductor bodies 20 on the substrate 10 can comprise a diode, an IGBT (insulated-gate bipolar transistor), a MOSFET (metal-oxide-semiconductor field-effect transistor), a JFET (junction field-effect transistor), a HEMT (high electron mobility transistor), or any other suitable controllable or non-controllable semiconductor device. The one or more semiconductor bodies 20 can form a semiconductor array on the substrate 10 (e.g., one or more half-bridges). Fig. 1 shows only two semiconductor bodies 20 as examples.

[0018] The Fig. The first electrically conductive layer 111 shown in Figure 1 is a structured layer. In this context, "structured layer" means that the first electrically conductive layer 111 is not a continuous layer, but rather has discontinuities between different sections of the layer. Different semiconductor bodies 20 can be arranged on the same section or on different sections of the first electrically conductive layer 111. The different sections of the first electrically conductive layer 111 may either have no electrical connection to each other or may be electrically connected to each other, for example, by means of bond wires or other connecting elements. Each of the semiconductor bodies 20 can be electrically and mechanically connected to the substrate 10 by means of an electrically conductive bonding layer 22. Fig. Figure 1 shows an example of a substrate 10 with semiconductor bodies 20 and interconnection layers 22 arranged on it. Such an electrically conductive interconnection layer 22 can, for example, be a solder layer. The second electrically conductive layer 112 (if present) can be either a continuous or also a structured layer.

[0019] To connect the semiconductor bodies 20 to the substrate 10, the semiconductor bodies 20 are arranged on the surface (top surface) of the substrate 10, with the bonding layer 22 located between the substrate 10 and the semiconductor body 20. The top surface of the substrate 10 is a surface of the first electrically conductive layer 111, which faces away from the dielectric insulating layer 11. One or more semiconductor bodies 20 can alternatively or additionally be connected to the substrate 10, for example, by means of bond wires 24. The substrate 10 with the at least one semiconductor body 20 arranged on it can, for example, be part of a power semiconductor module and be arranged in a housing (not shown).

[0020] Now, referring to Fig. 2, a process for producing a substrate 10 is schematically illustrated. As in Fig. As shown in Figure 2A, a continuous first electrically conductive layer 111 is typically applied to the dielectric insulating layer 11 (e.g., by suitable deposition processes). This continuous first electrically conductive layer 111 is then structured in a subsequent process step. This is exemplified in Figure 2A. Fig. Figure 2B illustrates this process. When structuring the first electrically conductive layer 111, continuous incisions are created in the first electrically conductive layer 111. These incisions extend from the upper surface of the first electrically conductive layer 111 to the dielectric insulating layer 11, thus completely separating the different sections of the first electrically conductive layer 111 from one another. The incisions can be produced, for example, by means of appropriate etching processes (e.g., wet etching or dry etching). However, after an etching process for structuring the first electrically conductive layer 111, impurities 30, which were already present on the first electrically conductive layer 111 before or during the structuring process, may remain on the first electrically conductive layer 111, as shown in Figure 2B. Fig. Figure 2B illustrates this as an example. For instance, chemicals such as copper chloride (CuCl), sodium hydroxide (NaOH) or sodium carbonate (Na2CO3) are used in the etching of the first electrically conductive layer 111, which can contaminate the surface of the first electrically conductive layer 111 after the etching process.

[0021] To remove such contaminants, a subsequent cleaning process is usually carried out, as in Fig. Figure 2C illustrates this as an example. Such a cleaning process can generally comprise one or more steps in which one or more of a variety of chemicals 34 (e.g., sulfuric acid H₂SO₄ or hydrogen peroxide H₂O₂) are sprayed onto the surface of the first electrically conductive layer 111 and subsequently removed in rinsing steps (not explicitly shown). Finally, a drying step can follow. Such cleaning processes can remove at least a large proportion of the contaminants 30 from the surface of the first electrically conductive layer 111. As shown in Fig. 2C schematically depicted, however, individual contaminants 30 may still remain on the surface even after thorough cleaning processes.

[0022] Now, referring to Fig. In a subsequent step, semiconductor devices 20 are connected to the potentially still contaminated surface of the first electrically conductive layer 111. For example, semiconductor devices 20 can be soldered onto the first electrically conductive layer 111. Solder pastes, preformed solder pellets, or solder preforms can be used for this purpose. When using solder preforms, the soldering process is usually carried out in a formic acid atmosphere. The formic acid 38 can react with impurities 30 remaining on the surface of the first electrically conductive layer 111, or the formic acid 38 can "activate" the impurities 30. Such activation by formic acid 38 is usually not detectable directly during or immediately after the soldering step. Activation is usually only detectable at significantly later times (e.g.,(after at least 12 or at least 24 hours). Activation of impurities 30 by formic acid 38 often leads to clearly visible discolorations on the surface of the first electrically conductive layer 111. Activation of impurities 30 by formic acid 38 can also lead to damage to the substrate 10 and thus to a malfunction of the semiconductor array arranged on the substrate 10.

[0023] For this reason, according to an example, a passivation layer 40 is applied to at least the first electrically conductive layer 111 before elements are applied to the substrate 10. This is exemplified in Fig. 3A is shown. Fig. The step shown in 3A can, for example, be taken after a cleaning step (see below). Fig. 2C) and before applying components to the substrate (see Fig. 2D). That is, the passivation layer 40 is applied to the structured, but still completely unpopulated, first electrically conductive layer 111. Since no components are yet arranged on the first electrically conductive layer 111, the entire first electrically conductive layer 111 is covered by the passivation layer 40. The passivation layer 40 also completely covers any impurities 30 that may still be remaining on the surface of the first electrically conductive layer 111. If semiconductor devices 20 are subsequently soldered on in a formic acid-containing atmosphere (see below), the passivation layer 40 will be completely removed. Fig. 3B), the passivation layer 40 forms a barrier between the formic acid 38 and the impurities 30, so that the impurities 30 cannot be activated by the formic acid.

[0024] The passivation layer 40 can have a thickness in the vertical direction y (perpendicular to the upper surface of the substrate 10) of less than 5 µm or less than 1 µm. For example, the passivation layer 40 can be a so-called monolayer. Monolayers are thin, single layers consisting of atoms, molecules, or cells. The thickness of a monolayer corresponds to the thickness of a single atom, molecule, or cell. The passivation layer 40 can, for example, be a (mono)layer of organic molecules. The organic molecules have functional groups that serve to attach the organic molecules to the surface of the first electrically conductive layer 111. Functional groups are groups of atoms in organic molecules that significantly influence their properties and reactivity.Such a passivation layer 40 made of organic molecules is inherently heat-resistant and is therefore not damaged during a subsequent soldering process. At the same time, such a (thin) passivation layer 40 has no influence on subsequent soldering processes. This means that semiconductor components 20 or any other elements can be soldered onto the substrate 10 just as they would onto substrates without a passivation layer 40. The passivation layer 40 has no influence on the mechanical stability of the resulting connections, nor on their electrical conductivity.

[0025] The passivation layer 40 is produced by treating the substrate 10 with an HFE (hydrofluoroether) cleaning process. Various HFE solutions are known to be used as cleaning solvents. HFE cleaning processes are often multi-stage (e.g., two-stage) processes. For example, in a first step, the entire substrate 10 can be immersed in an initial wash bath. This first wash bath may contain, for example, a cleaning agent for removing flux residues (e.g., so-called "Topclean," with a low HFE content, for example, < 50% or < 25%). In one or more further steps, the substrate 10 can be immersed in further solutions of the HFE cleaning process, which may, for example, have a predominant HFE content (e.g., > 50% or > 70%).During such a multi-stage HFE cleaning process, a thin phosphate-containing layer can be deposited on the first electrically conductive layer 111 (during one or more of the individual cleaning steps), forming the passivation layer 40. However, treatment using an HFE cleaning process to deposit a phosphate passivation layer 40 is only one example. Functional groups of organic molecules suitable for forming a passivation layer 40 can include, for example, one or more of the following: phosphates, thiols, silicones, carbonic acid, esters, and nitrides. Different functional groups can be applied to the surface of the first electrically conductive layer 111 simultaneously in the same step or sequentially in successive steps.

[0026] The passivation layer 40 can be produced, as described above, for example, by immersing the substrate 10 in a suitable solution (immersion coating process). However, this is only one example. The passivation layer 40 can alternatively also be produced, for example, by spraying (spray coating process), by plasma-enhanced deposition (plasma coating process), or by vapor deposition (evaporation process).

[0027] A substrate 10 for a semiconductor module is exemplified in Fig.Figure 3A shows the substrate 10 comprising a dielectric insulating layer 11, a first electrically conductive layer 111 arranged on a first side of the dielectric insulating layer 11, and a passivation layer 40, wherein the first electrically conductive layer 111 is a structured layer with one or more incisions between different completely separated sections of the first electrically conductive layer 111, and the passivation layer 40 covers the entire surface of the structured first electrically conductive layer 111.

Claims

[1] A method for producing a substrate (10) for a semiconductor module, the method comprising: Forming a first electrically conductive layer (111) on a first side of a dielectric insulation layer (11); Structuring the first electrically conductive layer (111) by creating one or more continuous cuts in the first electrically conductive layer (111) which extend from an upper surface of the first electrically conductive layer (111) to the dielectric insulation layer (11) in order to completely separate different sections of the first electrically conductive layer (111) from one another; and Forming a passivation layer (40), wherein the passivation layer (40) covers the entire surface of the structured first electrically conductive layer (111), wherein the passivation layer (40) comprises organic molecules having at least one functional group, and wherein forming the passivation layer (40) comprises treating the first electrically conductive layer (111) by means of a hydrofluoroether (HFE) cleaning process. [2] The method of claim 1, wherein forming the passivation layer (40) comprises: Applying material using a spray coating process, or Applying material by means of a dip coating process, or Applying material using a plasma coating process, or Applying material using a vapor deposition process. [3] The method according to claim 1 or 2, wherein the passivation layer (40) has a thickness of less than 5µm or less than 1µm. [4] The method according to any one of claims 1 to 3, wherein the passivation layer (40) is a monolayer. [5] A method according to any one of the preceding claims, wherein the at least one functional group comprises one or more of phosphates, thiols, silicones, carbonic acid, esters, and nitrides. [6] The method of any preceding claim, wherein structuring the first electrically conductive layer (111) comprises etching the one or more incisions by means of a wet etching process or a dry etching process. [7] Method according to one of the preceding claims, further comprising, after structuring the first electrically conductive layer (111) and before forming the passivation layer (40), at least one cleaning step for removing impurities (30) from the first electrically conductive layer (111). [8] Method according to claim 7, wherein the passivation layer (40) is applied to the electrically conductive layer (111) in such a way that, after the at least one cleaning step, it completely covers impurities (30) still remaining on the surface of the first electrically conductive layer (111). [9] Method according to one of the preceding claims, further comprising, after forming the passivation layer (40), applying one or more semiconductor components (20) to the first electrically conductive layer (111) and the passivation layer (40) by means of a soldering process. [10] The method according to claim 9, wherein the soldering process is carried out using solder preforms and in a formic acid-containing atmosphere.

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