Semiconductor device with superjunction structure

Abstract

A semiconductor device (10) comprises a transistor. The transistor has a plurality of gate grooves (111) formed in a semiconductor substrate (100), the gate grooves (111) structuring the semiconductor substrate (100) into struts (114). Furthermore, the transistor has a gate electrode (110) arranged in at least one of the gate grooves (111). A source region (124), a channel region (122), and part of a current-spreading region (126) are arranged in the struts (114). The semiconductor device (10) also has a superjunction structure (117) arranged at a greater distance from the source region (124) than from the channel region (122). The superjunction structure (117) has a first compensation area (118) of the first conductivity type and a second compensation area (119) of the second conductivity type.The doping concentration of the doped region (120) of the second conductivity type of the channel region (122) decreases in a second horizontal direction crossing the first horizontal direction from a region near the gate electrode (110) to a central region of the bridge (114).

Description

[0001] Examples of the present disclosure relate to semiconductor devices, in particular to semiconductor devices having a transistor including a superjunction structure. BACKGROUND

[0002] Transistors in which a gate electrode is arranged in trenches adjacent to a channel region are widespread. Attempts are being made to further improve the properties of these transistors.

[0003] Further semiconductor devices are known from the document US 2020 / 0 058 760 A1.

[0004] The present disclosure is directed to a semiconductor device having an improved transistor that can be advantageously used, for example, for a silicon carbide substrate. SUMMARY

[0005] According to one example, a semiconductor device comprises a transistor. The transistor comprises a plurality of gate trenches formed in a semiconductor substrate. The gate trenches structure the semiconductor substrate into fins extending in a first horizontal direction. The fins are each arranged between two adjacent gate trenches. Furthermore, the transistor comprises a gate electrode arranged in at least one of the gate trenches. The transistor further comprises a source region of a first conductivity type electrically coupled to a source terminal, a channel region having a doped region of a second conductivity type, a current spreading region of the first conductivity type, and a drain region electrically coupled to a drain terminal. The source region, the channel region, and a part of the current spreading region are arranged in the fins.The gate electrode is insulated from the channel region and the current spreading region, wherein a width of the source region corresponds to a width of the fin. The semiconductor device further comprises a superjunction structure arranged at a greater distance from the source region than from the channel region. The superjunction structure comprises a first compensation region of the first conductivity type, wherein the first compensation region is electrically coupled to the drain terminal. Furthermore, the superjunction structure comprises a second compensation region of the second conductivity type, wherein the second compensation region is electrically coupled to the doped region of the second conductivity type of the channel region. The first and second compensation regions are adjacent to one another.A doping concentration of the doped region of the second conductivity type of the channel region decreases in a second horizontal direction crossing the first horizontal direction from a region near the gate electrode to a central region of the fin.

[0006] According to further examples, a semiconductor device comprises a transistor. The transistor comprises a plurality of gate trenches formed in a SiC substrate. The gate trenches structure the semiconductor substrate into ridges running in a first horizontal direction, wherein the ridges are each arranged between two adjacent gate trenches. The transistor further comprises a gate electrode arranged in at least one of the gate trenches. The transistor further comprises a source region of a first conductivity type electrically coupled to a source terminal, a channel region having a doped region of a second conductivity type, a current spreading region of the first conductivity type, and a drain terminal electrically coupled to a drain terminal. The source region, the channel region, and a part of the current spreading region are arranged in the ridges.The gate electrode is insulated from the channel region and the current spreading region. A width of the source region corresponds to a width of the fin. The semiconductor device further comprises a superjunction structure arranged at a greater distance from the source region than from the channel region. The superjunction structure comprises a first compensation region of the first conductivity type, wherein the first compensation region is electrically coupled to the drain terminal. The superjunction structure further comprises a second compensation region of the second conductivity type. The second compensation region is electrically coupled to the doped region of the second conductivity type of the channel region, wherein the first and second compensation regions are adjacent to one another. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings, together with the description, serve to explain principles of the embodiments. Other embodiments are described in the following detailed description and claims. Fig. 1A shows an example of a vertical cross-sectional view of a portion of a semiconductor device according to examples. Fig. 1B shows a vertical cross-sectional view of a portion of a semiconductor device according to further examples. Fig. 2A shows a horizontal cross-sectional view of a semiconductor device according to examples. Fig. 2B shows vertical sectional views of a portion of a semiconductor device according to examples. Fig. 2C shows vertical cross-sectional views of a portion of the semiconductor device according to further examples. Fig. 3A shows a horizontal cross-sectional view of a semiconductor device according to further examples. Fig. 3B is a vertical cross-sectional view of a portion of the semiconductor device according to examples. Fig. Figure 3C shows an example of a doping concentration in the channel region. Fig. 4A shows a horizontal cross-sectional view of a portion of a semiconductor device according to examples. Fig. Figure 4B shows vertical cross-sectional views of a portion of the semiconductor device at various locations. Fig. 5A shows a horizontal cross-sectional view of a semiconductor device according to further examples. Fig. 5B and Fig. 5C show vertical cross-sectional views of the semiconductor device at different locations. Fig. Figure 5D shows another horizontal cross-sectional view of the semiconductor device. Fig. 5E and Fig. 5F show vertical cross-sectional views of another semiconductor device at various locations. Fig. Figure 5G shows another horizontal cross-sectional view of the semiconductor device. Fig. 6A shows a horizontal cross-sectional view of a semiconductor device according to further examples. Fig. 6B shows a vertical cross-sectional view of the semiconductor device. Fig. Figure 6C shows another horizontal cross-sectional view of the semiconductor device. Fig. 6D and Fig. 6E show vertical cross-sectional views of a semiconductor device according to further examples at various locations. Fig. Figure 6F shows another horizontal cross-sectional view of the semiconductor device. Fig. 7A shows a horizontal cross-sectional view of a semiconductor device according to further examples. Fig. 7B and Fig. 7C show vertical cross-sectional views of the semiconductor device along a second direction at various locations. Fig. 7D and Fig. 7E show vertical cross-sectional views of the semiconductor device along a first direction at various locations. Fig. Figure 7F shows another horizontal cross-sectional view of the semiconductor device. Fig. 8A shows a horizontal cross-sectional view of a portion of a semiconductor device according to further examples. Fig. 8B and Fig. 8C show vertical cross-sectional views of the semiconductor device along a second direction at various locations. Fig. 8D and Fig. 8E show vertical cross-sectional views of the semiconductor device along a first direction at various locations. Fig. 9A to 9H show cross-sectional views of a workpiece when a method of manufacturing a semiconductor device according to examples is performed. Fig. 9I and Fig. 9J show cross-sectional views of a workpiece when a method according to a modification is performed. Fig. 10A to 10H show cross-sectional views of a workpiece when a method of manufacturing a semiconductor device according to examples is performed. Fig. 11A to 11H show cross-sectional views of a workpiece when a method according to further examples is performed. DETAILED DESCRIPTION

[0008] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made. The drawings are not to scale and are for purposes of illustration only. For clarity, like elements are designated by corresponding reference numerals throughout the various drawings unless otherwise noted.

[0009] Ranges specified for physical dimensions include the boundary values. For example, a range for a parameter y from a to b is written as a ≤ y ≤ b. A parameter y with a value of at least c is written as c ≤ y, and a parameter with a value of at most d is written as y ≤ d.

[0010] In the present description, elements of transistor cells of a field-effect transistor are described. In general, the field-effect transistor can have a plurality of transistor cells that are connected or switched in parallel. For example, each individual transistor cell can have a single gate electrode, a single channel region, and other components. The gate electrodes of the individual transistor cells can be connected, e.g., electrically connected, and / or formed from the same materials. For example, the gate electrodes of the individual transistor cells can be connected to a common terminal, e.g., a gate terminal. Other components of the individual transistor cells, e.g., the source regions, can each be connected to a common source terminal. Yet other components of the individual transistor cells, e.g.,The current spreading region or the drift region may be shared among at least some of the transistor cells. This description primarily describes the function and structure of the individual transistor cells. It is readily understood that this description applies equally to the other individual transistor cells. Descriptions describing the general elements of the transistor and the structural implementation by elements of the individual transistor cells, such as "a gate electrode arranged in gate trenches," are intended to mean that individual gate electrodes of respective transistor cells are arranged in respective gate trenches.

[0011] An example of a semiconductor device includes a transistor. The transistor may include a plurality of gate trenches formed in a semiconductor substrate. The gate trenches may structure the semiconductor substrate into ridges extending in a first horizontal direction. The ridges may each be arranged between two adjacent gate trenches. The transistor may further include a gate electrode arranged in at least one of the gate trenches.

[0012] Furthermore, the transistor may have a source region of a first conductivity type that is electrically coupled to a source terminal. The transistor may further have a channel region with a doped region of a second conductivity type and a current spreading region of the first conductivity type. The source region, the channel region, and a portion of the current spreading region are arranged in the fins. The transistor may further have a drain region that is electrically coupled to a drain terminal.

[0013] The gate electrode can be insulated from the channel region and the current spreading region. The source region can be arranged at least in a central region of the fin. The term "central region" can refer to a central region with respect to a second horizontal direction perpendicular to the first horizontal direction. Accordingly, the source region can be arranged in a region of the fin at approximately equal distances from a first side surface and a second side surface of the fin, respectively. According to further embodiments, the arrangement of the source region does not have to be symmetrical with respect to the second horizontal direction. The term "a source region arranged at least in a central region of the fin" is intended to refer to an arrangement according to which doped regions of the second conductivity type can be arranged in a horizontal edge region of the fin, e.g., adjacent to at least one of the side surfaces of the fin.

[0014] The semiconductor device may further comprise a superjunction structure arranged at a greater distance from the source region than from the channel region. The superjunction structure may comprise a first compensation region of the first conductivity type and a second compensation region of the second conductivity type. The first compensation region may be electrically coupled to the drain terminal. The second compensation region may be electrically coupled to the doped region of the second conductivity type of the channel region. The first and second compensation regions may be arranged adjacent to one another.

[0015] A doping concentration of the doped region of the second conductivity type of the channel region may decrease in a second horizontal direction that crosses the first horizontal direction, from a region near the gate electrode to a central region of the fin. For example, the channel region may have a doped region of the first conductivity type in the central region of the fin.

[0016] When a suitable voltage is applied to the gate electrode, a conductive channel is formed in the channel region. As a consequence, a current path with a vertical component is formed between the source region, the channel region, the current spreading region, and the drain region. The current path from the source region to the current spreading region may extend in a depth direction of the silicon carbide substrate. For example, the depth direction may correspond to a vertical direction, e.g., the z-direction. According to further embodiments, the depth direction may be a direction different from the vertical direction. Generally, the depth direction is a direction different from a lateral or horizontal direction. For example, the depth direction may have a component perpendicular to the lateral direction or to a main surface of the silicon carbide substrate.For example, the depth direction may be oblique with respect to the vertical direction.

[0017] The term "fin" as used in this disclosure is intended to mean or refer to a structure, e.g., a mesa, having two sidewalls and a top region between the sidewalls. The sidewalls extend in a depth direction. For example, the sidewalls may be inclined with respect to a vertical direction. According to further interpretations, the term "fin" may also be understood as a configuration of a "fin." Since the channel of the transistor is arranged within the fin, the transistor is also referred to as a "FinFET."

[0018] Transistors described herein may specifically include IGFETs ("Insulated Gate Field Effect Transistors"). IGFETs are voltage-controlled devices that include MOSFETs ("Metal Oxide Semiconductor FETs") and other FETs with gate electrodes based on a doped semiconductor material and / or with gate dielectrics that are not, or not exclusively, based on an oxide. As will be clearly understood, transistors may also refer to IGBTs ("Insulated Gate Bipolar Transistors").

[0019] According to the embodiments, a width of the source region may correspond to a width of the fin. Accordingly, the source region may extend from one side surface of the fin to another side surface of the fin. In other words, it is possible for no further trench or doped region of a different conductivity type to be present within the source region.

[0020] For example, the doped region of the second conductivity type of the channel region can be electrically connected to the source terminal via a body contact region.

[0021] For example, the second compensation region may be electrically coupled to the source terminal. The second compensation region may, for example, be electrically coupled to the doped region of the second conductivity type of the channel region. Accordingly, the second compensation region may be electrically coupled to the source terminal via the channel region.

[0022] The superjunction structure enables a reduced resistance of the drift zone, while the breakdown voltage V brcompared to a drift zone of the first conductivity type without a superjunction structure. A lateral width of the first and second compensation regions may be smaller than an extension of the first and second compensation regions in the depth direction.

[0023] The gate electrode may be isolated from the channel region and the current spreading region. For example, the gate electrode may be isolated from the channel region and the current spreading region by a gate dielectric, such as silicon oxide, silicon nitride, or a combination of these materials. According to further examples, any other dielectric material, such as a high-k dielectric, may be used.

[0024] In summary, the semiconductor device combines a FinFET structure with a superjunction structure. The FinFET structure allows for reduced channel resistance. The superjunction structure also allows for reduced resistance in the drift region. As a result, a power transistor with low turn-on losses can be realized.

[0025] For example, the channel region may have a doped region of the first conductivity type in the central region of the fin. In this case, the first compensation region may be electrically coupled to the doped region of the first conductivity type.

[0026] Furthermore, the second compensation region may be electrically coupled to the source terminal via a body contact region that electrically couples the doped region of the second conductivity type of the channel region to the source terminal.

[0027] For example, the semiconductor device may further comprise a shielding region of the second conductivity type, which is arranged below each gate trench. The shielding region may, for example, be doped with a higher doping concentration than the second compensation region. The second compensation region may be electrically coupled to the shielding region.

[0028] The shielding region can contribute to shielding a gate dielectric against an electrical potential that can be applied to the backside of the silicon carbide body. In a blocking mode of the silicon carbide device, the shielding region can reduce the electric field in the gate dielectric and can thus contribute to increasing the reliability of the device. For example, the shielding region can be doped with a higher doping level than the doped region of the second conductivity type of the channel region. The shielding region can be in contact with the current spreading region. The shielding region can be in contact with a source metallization layer that is electrically coupled to the source terminal.

[0029] According to examples, the superjunction structure may extend in the first horizontal direction.

[0030] According to further examples, the superjunction structure may extend in a second horizontal direction crossing the first horizontal direction.

[0031] According to examples, the source region may be continuously extended along the first horizontal direction in the webs.

[0032] According to further examples, the source region may be segmented into source region segments along the first horizontal direction. Furthermore, the transistor may include body contact areas arranged between adjacent source region segments.

[0033] According to examples, the transistor may further comprise a drift region of the first conductivity type arranged between the superjunction structure and the drain region.

[0034] For example, the gate trenches may extend continuously in the first horizontal direction.

[0035] The semiconductor device may further include contact grooves or depressions extending in the first horizontal direction. The contact depressions may extend through the gate trenches in a depth direction. A metal layer arranged in the contact depressions may be electrically coupled to the source terminal. The metal layer may further be electrically coupled to the second compensation region of the second conductivity type. Furthermore, or alternatively, the contact depressions may be in contact with the shielding regions. In this way, the shielding regions may be electrically coupled to the source terminal. Furthermore, or alternatively, the metal layer in the contact depression may be in contact with the body contact region.For example, the metal layer in the contact recesses may be separated from a region of the first conductivity type to avoid a direct, uncontrollable current path between source and drain regions.

[0036] For example, the contact recesses may extend continuously in the first horizontal direction. According to further examples, the contact recesses may be segmented into contact recess islands. In this case, the gate electrode may be present between adjacent contact recess islands.

[0037] According to further examples, the gate trenches may be segmented into a plurality of trench segments arranged along the first horizontal direction.

[0038] For example, the semiconductor device may further comprise a metal layer electrically coupled to the source terminal. The metal layer may be arranged in contact with the source region between adjacent trench segments. In this way, for example, the source regions and the doped region of the second conductivity type of the channel region may be electrically coupled to the source terminal.

[0039] According to further examples, a semiconductor device may include a transistor. The transistor may include a plurality of gate trenches formed in a SiC substrate. The gate trenches may structure the semiconductor substrate into fins extending in a first horizontal direction. The fins may each be arranged between two adjacent gate trenches. The transistor may further include a gate electrode arranged in at least one of the gate trenches and a source region of a first conductivity type electrically coupled to a source terminal. Furthermore, the transistor may include a channel region with a doped region of a second conductivity type, a current spreading region of the first conductivity type, and a drain region electrically coupled to a drain terminal. The source region, the channel region, and a part of the current spreading region may be arranged in the fins.The gate electrode may be isolated from the channel region and the current spreading region. A width of the source region may correspond to a width of the fin.

[0040] Furthermore, the semiconductor device may comprise a superjunction structure arranged at a greater distance from the source region than from the channel region. The superjunction structure may comprise a first compensation region of the first conductivity type, which is electrically coupled to the drain terminal, and a second compensation region of the second conductivity type. The second compensation region may be electrically coupled to the doped region of the second conductivity type of the channel region. The first and second compensation regions may be arranged adjacent to one another.

[0041] For example, the first compensation region may be electrically coupled to the current spreading region.

[0042] For example, a doping concentration of the doped region of the second conductivity type of the channel region may decrease in a second horizontal direction crossing the first horizontal direction from a region near the gate electrode to a central region of the fin.

[0043] The channel region may, for example, further comprise a doped region of the first conductivity type in the central region of the ridge. The first compensation region may be electrically coupled to the doped region of the first conductivity type in the central region of the ridge.

[0044] As described herein, the semiconductor substrate may be a silicon carbide (SiC) substrate. According to one example, the silicon carbide substrate may have a hexagonal crystal lattice with a c-plane and other principal planes. The other principal planes may include a-planes or m-planes.

[0045] The c-plane is a {0001} lattice plane. The other principal planes can include a-planes ({11-20} family of lattice planes) and m-planes ({1-100} family of lattice planes). The a-planes comprise the six differently oriented lattice planes (11-20), (1-210), (-2110), (-1-120), (-12-10), and (2-1-10). The m-planes comprise the six differently oriented lattice planes (1-100), (10-10), (01-10), (-1100), (-1010), and (0-110).

[0046] The central surface plane of the silicon carbide substrate may be inclined at an off-axis angle to the c-plane. In other words, the c-axis may be inclined at the off-axis angle to the vertical direction. The off-axis angle may be in a range from 2 degrees to 8 degrees, for example, in a range from 3 degrees to 5 degrees. In particular, the off-axis angle may be approximately 4 degrees. For example, the c-axis may be inclined such that a plane spanned by the vertical direction and the c-axis is inclined to the {11-20} plane. According to another example, the c-axis may be inclined such that a plane spanned by the vertical direction and the c-axis is parallel to a {1-100} plane. At the back side of the silicon carbide substrate, a second main surface of the silicon carbide substrate may extend parallel or approximately parallel to the central surface plane at the front side.

[0047] A first main surface on a front side of the silicon carbide substrate can be planar or ribbed. A mean surface plane of the first main surface extends along the horizontal directions. The mean surface plane of a planar first main surface is identical to the planar first main surface. The mean surface plane of a ribbed first main surface is defined by the least-squares planar plane of the ribbed first main surface. The position and orientation of the least-squares planar plane are defined such that the sum of the squares of the deviations of surface points of the ribbed first main surface from the least-squares planar plane is minimum.

[0048] The silicon carbide substrate may extend horizontally along a plane spanned by the horizontal directions. Accordingly, the silicon carbide body may have a surface extension along two horizontal directions and may have a thickness along a vertical direction perpendicular to the horizontal directions. In other words, the vertical direction is parallel to a surface normal to the mean surface plane.

[0049] The gate trenches can structure the first region of the silicon carbide substrate into ridges. For example, at least one of the sidewalls of the gate trenches and the ridges can be parallel to the (1-100) or (-1000) planes.

[0050] The terms "first horizontal direction" and "second horizontal direction" define intersecting horizontal directions. Although some of the figures show the x-direction and the y-direction as examples of the first and second horizontal directions for illustrative purposes, it is understood that the first horizontal direction and the second horizontal direction need not be perpendicular to each other. The term "depth direction" defines a direction with a component perpendicular to the mean surface plane. The term "depth direction" includes the vertical direction and any other direction other than a horizontal direction.

[0051] Fig. 1A shows a vertical cross-sectional view of a semiconductor device 10 according to examples. The semiconductor device 10 includes a transistor. The transistor includes a plurality of gate trenches 111 formed in a semiconductor substrate 100, e.g., a SiC substrate. The gate trenches 111 structure the semiconductor device substrate 100 into ridges 114 extending in a first horizontal direction, e.g., the y-direction. The ridges 114 are each arranged between two adjacent gate trenches 111. The transistor further includes a gate electrode 110 arranged in at least one of the gate trenches 111. The semiconductor device 10 further includes a source region 124 of a first conductivity type, e.g., an n-type, electrically coupled to a source terminal 130. Furthermore, the transistor has a channel region 122 with a doped region of a second conductivity type, e.g.a p-type, a current spreading region 126 of the first conductivity type and a drain region 125 which is electrically coupled to a drain terminal 129.

[0052] The source region 124, the channel region 122, and a portion of the current spreading region 126 are arranged in the fins 114. The gate electrode 110 is insulated from the channel region 122 and the current spreading region 126. The source region 124 is arranged in a central area of ​​the fin 114. A width w of the source region 124 may correspond to a width of the fin 114. The channel region 122 may be electrically coupled to the source terminal 130.

[0053] The semiconductor device further comprises a superjunction structure 117, which is arranged at a greater distance from the source region 124 than from the channel region 122. The superjunction structure 117 comprises a first compensation region 118 of the first conductivity type. The first compensation region 118 is electrically coupled to the drain terminal 129. The superjunction structure further comprises a second compensation region 119 of the second conductivity type. The second compensation region 119 is electrically coupled to the doped region of the second conductivity type of the channel region 122. Furthermore, the second compensation region 119 can be electrically coupled to the source terminal 130 via a body contact region 123. The first and second compensation regions 118, 119 are arranged adjacent to one another. The superjunction structure is arranged at a greater depth within the semiconductor substrate than the source region and the channel region.

[0054] As in Fig. As shown in Figure 1A, the first compensation region 118 and the second compensation region 119 are arranged alternately below a region in which the gate trenches 111 are formed. A sequence of the arrangement of the first and second compensation regions 118, 119 may be continuous.

[0055] Fig. 1B shows a vertical cross-sectional view of a semiconductor device 10 according to further examples. The semiconductor device 10 has similar or identical components as those shown in Fig. 1A. Deviating from the semiconductor device 10 shown in Fig. 1A, extended trench regions 113 are arranged below the gate trenches 111. In more detail, the superjunction structure 117 of the semiconductor device 10 shown in Fig. 1B, a first compensation region 118 of the first conductivity type in a similar manner as described with reference to Fig. 1A. The second compensation region 119 of the second conductivity type is implemented by a doped sidewall region at the extended trench region 113. This specific arrangement of the superjunction structure 117 may be due to a manufacturing process including a tilted ion implantation process. During this process, a portion of the trench is retained after performing the ion implantation process. If the extended trench region 113 is fully embedded in a doped material of the second conductivity type, the gate dielectric 112 may be effectively shielded in some examples. In other examples, the gate dielectric 112 may not be effectively shielded. Furthermore, current spreading losses may be reduced.

[0056] According to the Fig. 1A and Fig. In the examples illustrated in FIG. 1B, the first compensation region 118 may be arranged below the fins 114. Furthermore, the second compensation regions 119 may, for example, be arranged below the gate trenches 111.

[0057] As in Fig. 1A, the semiconductor device may further include a drift region 127 of the first conductivity type disposed between the superjunction structure 117 and the drain region 125. The drift region 127 may be disposed between the drain region 125 and the current spreading region 126.

[0058] According to examples, the channel region 122 may be doped with a constant doping profile. According to further examples, a doping concentration of the second conductivity type may decrease from an edge region of the channel region 122 to its central region in a horizontal direction. According to further embodiments, the channel region 122 may have a doped region of the first conductivity type in its central region. This will be explained in more detail below.

[0059] Fig. 2A shows a horizontal cross-sectional view of a semiconductor device 10 according to further examples. As illustrated, the semiconductor substrate is structured by gate trenches 111 into fins 114. For example, a width of the gate trenches 111, measured in a second horizontal direction, may be much larger than a width of the fins 114, measured in the second horizontal direction. For example, the width of the gate trenches 111 may be larger than 3 * (the width of the fins 114). Furthermore, the source region 124 may be segmented into source region segments 109 along the first horizontal direction. The semiconductor device 10 may further include body contact portions 123 between adjacent source region segments 109 along the first horizontal direction.

[0060] Fig. Figure 2B shows cross-sectional views of the semiconductor device when the superjunction structure 117 is formed in a manner similar to that shown in Fig. 1A. In more detail, the first and second compensation regions 118, 119 alternate continuously along the second direction. The left area of Fig. Figure 2B shows a cross-sectional view taken at a location 1 such that it intersects the source region segment 109. The right area of Fig. 2B is taken at a position 2 such that it intersects the body contact area 123.

[0061] Fig. 2B shows a portion of the gate trench 111. A gate electrode 110 is arranged in the gate trench. The gate electrode may be isolated from the other elements of the transistor by a gate dielectric 112. The first compensation region 118 and the second compensation region 119 extend in a depth direction, e.g., the z-direction or another direction with a component in the z-direction, and are arranged sequentially along the second direction. As shown in the left-hand portion of Fig. As shown in FIG. 2B, the source region 124 is arranged adjacent to a first main surface 101 of the semiconductor substrate 100 and is in direct contact with a source metallization layer 103. The channel region 122 is arranged below the source region 124. A current spreading region 126 is arranged below the channel region 122. The first compensation region 118 may be electrically coupled to the current spreading region 126. The second compensation region 119 is arranged adjacent to the first compensation region. The superjunction structure 117 comprises a first compensation region 118 and a second compensation region 119.

[0062] The right area of Fig. Figure 2B shows a portion of a cross-sectional view at a position 2 intersecting the body contact area 123. Furthermore, Fig. 2B, a shielding region 116 of the second conductivity type arranged adjacent to the channel region 122. The second compensation region 119 may be electrically coupled to the channel region 122 via the shielding region 116.

[0063] The shielding region can contribute to shielding a gate dielectric from an electrical potential that may be applied to the backside of the silicon carbide body. In a blocking mode of the silicon carbide device, the shielding region can reduce the electric field in the gate dielectric and thus contribute to increasing the reliability of the device.

[0064] Fig. 2C shows an implementation or configuration of the semiconductor device 10 when the superjunction structure 117 has a sidewall doping of an extended trench region 113. The left area of Fig. Figure 2C shows a cross-sectional view intersecting the source region 124. The left portion of Fig. 2C is the one in the left area of Fig. 2B. Deviating from the structure shown in Fig. 2B, the second compensation region 119 of the second conductivity type is formed as a sidewall doping of the extended trench region 113.

[0065] The right area of Fig. Figure 2C shows a similar structure to that seen in the right panel of Fig. 2B. Deviating from the Fig. 2B, the second compensation region 119 of the second conductivity type is formed as a sidewall doping of the extended trench region 113. A dielectric layer 115 may be arranged adjacent to the sidewall of the extended trench region 113. In a similar manner as in the right-hand region of Fig. 2B, the second compensation region 119 may be electrically coupled to the channel region 122 via a shielding region 116.

[0066] According to implementations, a doping concentration within the channel region 122 may vary along a second horizontal direction from an edge region of the fin 114 to a central region of the fin 114. For example, the concentration of dopants of the second conductivity type may decrease in a direction toward the central region of the fin. According to further examples, the channel region 122 may include a doped region 121 of the first conductivity type in the central region of the fin.

[0067] Fig. 3A shows a horizontal cross-sectional view of the semiconductor device 10. As illustrated, the semiconductor substrate is structured into ridges 114 by gate trenches 111. Each of the ridges 114 has a doped region 120 of the second conductivity type at the edge region and a doped region 121 of the first conductivity type in the central region. The doped region 121 of the first conductivity type may extend continuously along the first horizontal direction. Furthermore, the doped region 120 of the second conductivity type may extend continuously along the first direction.

[0068] Fig. 3B shows a vertical cross-sectional view of the semiconductor device. As illustrated, the channel region 122 includes a doped region 121 of the first conductivity type in the central region. A source region 124 is arranged above the doped region 121 of the first conductivity type of the channel region 122. The source region 124 is in direct contact with a source metallization layer 103. Furthermore, a body contact region 123 is electrically coupled to the doped region 120 of the second conductivity type of the channel region. The body contact region 123 may be in direct contact with the source metallization layer.

[0069] The superjunction structure 117 has a first compensation region 118 of the first conductivity type and a second compensation region 119 of the second conductivity type. The first compensation region 118 can be electrically connected to the doped region 121 of the first conductivity type. Accordingly, electrical contact can be easily established due to the presence of the doped region 121 of the first conductivity type. Furthermore, the mobility of charge carriers in the channel region can be increased. The high doping at the side surface of the channel region 122 can suppress the formation of an inversion layer near the interface. Instead, an electron accumulation layer can be formed in the doped region 121 of the first conductivity type of the channel region. In this way, bulk accumulation can be achieved.Bulk enhancement can be achieved with larger widths of the mesa or ridge 114 compared to a FinFET with uniform doping of the second conductivity type. The contact elements for contacting the doped regions of the first and second conductivity types can be arranged one after the other, as shown in FIG. Fig. 3A. As shown in Fig. 3B, the second compensation region 119 may be implemented as a doped region of a sidewall adjacent to an extended trench region 113. According to further concepts, the superjunction structure 117 may be formed, for example, in the manner described above with reference to Fig. 1A and Fig. 2B has been implemented.

[0070] Fig. 3C shows a schematic representation of a doping concentration of dopants of the second conductivity type in the channel region 122. As indicated by a curve (a), the doping concentration decreases from an edge region to a central region of the fin 114. The doping concentration of the dopants of the second conductivity type has a positive value. In other words, the channel region 122 has no doped regions of the first conductivity type.

[0071] According to curve (b), the doping concentration in the central region becomes negative. Accordingly, channel region 122 has a doped region 121 of the first conductivity type.

[0072] Fig. 4A shows an example of a semiconductor device in which the source region 124 is segmented into source region segments 109. The source region segments 109 and the body contact areas 123 are arranged alternately along the first direction.

[0073] Fig. 4B shows vertical cross-sectional views of the semiconductor device. As shown in the left panel of Fig. 4B, at a position 1, the source region 124 is arranged in direct contact with a source metallization layer 103. The source metallization layer 103 may be electrically coupled to a source terminal. The right-hand portion of Fig. 4B shows a cross-sectional view with a body contact region 123. The body contact region 123 is in direct contact with the source metallization 103. Other components of the semiconductor device are similar or identical to those shown in Fig. 3B were explained.

[0074] Fig. 5A to 5G show cross-sectional views of examples of a semiconductor device 10, wherein the channel region 122 includes a doped region of the second conductivity type and does not include a doped region of the first conductivity type.

[0075] Fig. 5A is a horizontal cross-sectional view of the semiconductor device 10. As illustrated, gate trenches 111 structure the semiconductor substrate into fins 114. Source regions 124 and body contact areas 123 are alternately arranged along the first direction. Fig. 5A further shows contact recesses 106 extending in the first horizontal direction and arranged in a central region of the gate trenches 111. The conductive material is filled into the contact recesses 106 to form recess contacts 128.

[0076] Fig. Figure 5B shows a cross-sectional view taken between I and I' such that it intersects areas where the source region 124 is in electrical contact with the source metallization layer 103. The Fig. The structure illustrated in FIGS. 5A to 5D refers to a structure in which, in addition, a contact recess 106 is arranged in the central region of the gate trench 111 to contact the shielding region 116. The contact recess 106 extends through the gate electrode 110. Accordingly, the contact recess 106 extends to a greater depth than according to embodiments in which the contact is made via a surface of a fin or a mesa. For example, the contact recess may extend to a greater depth than the gate trench 111. A conductive material in the contact recess 106 forms a recess contact 128. Accordingly, the gate electrode 110 may be interrupted along the second direction. A source region 124 is arranged in an upper region of the fin 114 and is arranged in electrical contact with the source metallization layer 103.Furthermore, a channel region 122 is arranged in the fin below the source region 124. A current spreading region 126 of the first conductivity type is arranged adjacent to the channel region 122. The current spreading region 126 does not extend continuously along the second horizontal direction. Shielding regions 116 of the second conductivity type are arranged between adjacent regions of the current spreading region 126. The shielding regions 116 are electrically coupled to the source metallization 103 via the recess contact 128.

[0077] A superjunction structure 117 is arranged below the current spreading region 126 and the shielding regions 116. The superjunction structure 117 has a first compensation region 118 of the first conductivity type and a second compensation region 119 of the second conductivity type. For example, the first compensation region 118 can be electrically coupled to the current spreading region 126. Furthermore, the second compensation region 119 can be electrically coupled to the shielding region 116. The current spreading regions 126 and the first compensation region 118 can be arranged below the fins. Furthermore, regions of the current spreading regions 126 and regions of the shielding regions 116 are arranged below the gate electrode. The current spreading region 126 and the shielding regions 116 extend in the first direction. The second compensation region 119 may be arranged below the shielding region 116 and below the gate trenches 111.

[0078] Fig. Figure 5C shows a cross-sectional view taken between II and II' so as to intersect the body contact areas 123. The cross-sectional view of Fig. 5C is similar or identical to the cross-sectional view of Fig. 5B. Deviating from the cross-sectional view of Fig. 5B, the body contact region 123 is in contact with the source metallization layer 103.

[0079] Fig. Figure 5D is a horizontal cross-sectional view of the semiconductor device located between III and III', as well as in Fig. 5B and Fig. 5C, is taken to intersect the superjunction structure 117. As shown, the first compensation region 118 and the second compensation region 119 extend in the first horizontal direction. The first compensation region 118 and the second compensation region 119 are arranged alternately along the second horizontal direction.

[0080] According to further examples, the first and second compensation regions 118, 119 may extend in the second horizontal direction.

[0081] Fig. 5E shows a vertical cross-sectional view of a semiconductor device 10, wherein the arrangement of the source region 114, the channel region 112, the current spreading region 126 and the shielding region 116 is similar to that in Fig. 5A to 5C. The cross-sectional view of Fig. 5E is between I and I', as in Fig. 5A, taken so as to intersect the source region 124. As illustrated, the first compensation region 118 may extend in the second horizontal direction. The first compensation region 118 may be electrically coupled to the current spreading region 126.

[0082] Fig. Figure 5F shows a vertical cross-sectional view taken between II and II', as in Fig. 5A, is taken to intersect the body contact area 123. As illustrated, the compensation region 119 may extend in the second horizontal direction. The second compensation region 119 may be electrically connected to the shielding area 116.

[0083] Fig. Figure 5G is a horizontal cross-sectional view of the semiconductor device located between III and III', as also shown in Fig. 5E and Fig. 5F, is taken to intersect the superjunction structure 117. As shown, the first compensation region 118 and the second compensation region 119 extend in the second horizontal direction. The first compensation region 118 and the second compensation region 119 are arranged alternately along the first horizontal direction.

[0084] According to Fig. 5A to 5G, the source region 124 can be contacted via the source metallization 103 from the top side of the semiconductor device. The shielding regions 116 and the second compensation region 119 of the second conductivity type are connected via the recess contact 128. Furthermore, the body contact region 123 provides electrical contact between the source terminal and the channel region 122.

[0085] Fig. 6A shows a horizontal cross-sectional view of a semiconductor device 10 in which the channel region 122 comprises a doped region 120 of the second conductivity type and further a doped region 121 of the first conductivity type arranged in the central region of the fin 114. Similarly, as described with reference to Fig. As explained in Figure 5A, gate trenches 111 structure the semiconductor substrate into fins 114. Furthermore, contact recesses 106 are arranged in a central region of the gate trenches 118. The contact recesses 106 extend in the first horizontal direction. The source region 124 extends continuously along the first direction.

[0086] Fig. 6B is a vertical cross-sectional view taken between I and I'. As can be seen, a doped region 121 of the first conductivity type is arranged in the central region of each of the fins 114. The doped region 120 of the second conductivity type is in contact with the shielding region 116. The first compensation region 118 of the first conductivity type may be electrically coupled to the doped region 121 of the first conductivity type via the current spreading region 126. The gate electrode 110 is arranged adjacent to the channel region 122. The gate electrode 110 is insulated from the channel region 122 by a gate dielectric 112. The gate electrode 110 may be divided into two gate electrodes by the contact recess 106. For example, a source metallization layer 103 may be arranged in the contact recess 106 to realize a recess contact 128.Due to the recess contact 128, the shielding region 116 can be electrically coupled to the source terminal.

[0087] The Fig. 6A and Fig. The semiconductor device illustrated in Figure 6B has a low gate-drain capacitance because the gate is fully embedded in the source metallization layer and the doped regions 120 of the second conductivity type, which are electrically coupled to the source terminal 130.

[0088] As in Fig. As further illustrated in Figure 6B, the doped region 120 of the second conductivity type is contacted from below by the shielding region 116. In this configuration, the shielding region 116 can be arranged in a self-aligned manner when an implantation process is performed into the gate trenches 111.

[0089] Fig. 6C is a horizontal cross-sectional view of the semiconductor device such that it intersects the superjunction structure 117. As illustrated, the first compensation region 118 and the second compensation region 119 extend in the first horizontal direction. The first compensation region 118 and the second compensation region 119 are arranged alternately along the second horizontal direction.

[0090] According to further examples, the first and second compensation regions 118, 118 may extend in the horizontal direction.

[0091] Fig. Figure 6D shows a vertical cross-sectional view of a semiconductor device 10, wherein the arrangement of the source region 114, the channel region 122, the current spreading region 126 and the shielding region 116 is similar to that in Fig. 6A and Fig. 6B. The cross-sectional view of Fig. 6D is taken between I and I', as in Fig. 6A. As illustrated, the first compensation region 118 may extend in the second horizontal direction. The first compensation region 118 may be electrically coupled to the current spreading region 126.

[0092] Fig. Figure 6E shows a vertical cross-sectional view taken between II and II', as also in Fig. 6A. As shown, the second compensation region 119 may extend in the second horizontal direction. The second compensation region 119 may be electrically coupled to the shielding region 116.

[0093] Fig. 6F is a horizontal cross-sectional view of the semiconductor device taken intersecting the superjunction structure 117. As illustrated, the first compensation region 118 and the second compensation region 119 extend in the second horizontal direction. The first compensation region 118 and the second compensation region 119 are arranged alternately along the first horizontal direction.

[0094] Fig. 7A shows a horizontal cross-sectional view of a semiconductor device 10 according to another example. The semiconductor device of Fig. 7A is the Fig. 5A. Deviating from the semiconductor devices illustrated in Fig. 5A, the contact recess 106 and therefore the recess contact 128 are not implemented to extend continuously along the first direction. Instead, the recess contact 128 is implemented as islands or segments. As shown in Fig. 7A, the gate trenches 111 of the semiconductor substrate are structured into ridges 114. The source region 124 is arranged in the ridges 114 and extends continuously in the first direction. As described below with reference to Fig. As explained in Figure 7C, a body contact to the channel region 122 may be implemented or realized via the shielding areas 116. Recess contacts 128 may be arranged as recess contact islands 108 within the gate trenches 111.

[0095] Fig. Figure 7B is a cross-sectional view of the semiconductor device between I and I' in a region where no recess contact pads 108 are present. As in Fig. 7B, the gate trenches 111 structure the semiconductor substrate 100 into fins 114. The source region 124 is arranged in an upper portion of the fins. A channel region 122 of the second conductivity type is arranged adjacent to the source region 124. A current spreading region 126 of the first conductivity type is partially arranged within the fins 114. Optionally, a doped region of the second conductivity type can be arranged below the gate trenches 111. As a result, the gate-drain capacitance C GD can be reduced and the gate-source capacitance C GSincreased. Consequently, the risk of a parasitic turn-on operation may be reduced. The gate electrode 110 is arranged in the gate trenches between adjacent fins 114. The gate electrode is insulated from the channel region 122 by a gate dielectric 112. According to examples, the first compensation region 118 and the second compensation region 119 may extend in the second horizontal direction crossing the first direction. As shown in Fig. 7B, the first compensation region 118 of the first conductivity type can accordingly be arranged below the current spreading region 126.

[0096] Fig. Figure 7C shows a cross-sectional view taken between II and II' at a position intersecting the contact recess 128. The cross-sectional view of Fig. 7C further shows a region in which a shielding region 116 of the second conductivity type is arranged below the gate trenches and below the fins 114. Furthermore, the second compensation region 119 is arranged below the gate trenches. As can be seen from a comparison of the Fig. 7B and Fig. As can be seen from Figure 7C, stripes of the current spreading region 126 and the shielding region 116 may be arranged alternately along the first direction. The stripes of the current spreading region 126 and the shielding region 116 extend in the second horizontal direction. Accordingly, the first compensation region 118 and the second compensation region 119 are arranged as stripes extending in the second direction. The first compensation region 118 and the second compensation region 119 are arranged alternately along the first horizontal direction. The shielding regions 116 are arranged to overlap with the second compensation regions 119. Furthermore, the current spreading regions 126 are arranged to overlap with the first compensation regions 118.

[0097] In the cross-sectional view of Fig. 7C, a recess contact 128 extends to the shielding region 116. Accordingly, the source metallization layer 103 is in contact with the shielding region 116. In this way, the channel region 122 is electrically coupled to the source terminal 130 through the shielding regions 116 and the recess contact 128.

[0098] Fig. 7D shows a cross-sectional view taken between III and III' along a gate trench 111 containing recess contacts 128. As illustrated, the first compensation region 118 and the second compensation region 119 are alternately arranged along the first direction. Furthermore, the current spreading region 126 and the shielding regions 116 are alternately arranged along the first direction. The first compensation region 118 and the current spreading region 126 are arranged in a region below the gate electrode 110. The shielding region 116 and the second compensation region 119 are arranged below the source metallization layer 103.

[0099] Fig. 7E shows a cross-sectional view taken between IV and IV' along the first horizontal direction at a position of the source region 124 or a fin. As illustrated, the channel region 122 is continuously arranged below the source region 124. Shielding regions 116 and current spreading regions 126 are arranged alternately along the first direction.

[0100] Fig. Figure 7F is a horizontal cross-sectional view taken between V and V' as shown in Fig. 7B and Fig. 7C. As shown, the first compensation region 118 and the second compensation region 119 extend in the second horizontal direction. The first compensation region 118 and the second compensation region 119 are arranged alternately along the first horizontal direction.

[0101] Fig. 8A is a horizontal cross-sectional view of a semiconductor device 10 according to further examples. For example, the cross-sectional view of Fig. 8A between V and V', as in Fig. 8B and Fig. 8C. According to embodiments shown in Fig. 8A, the gate trenches 111 are formed as segmented trenches. Accordingly, the gate trenches do not extend continuously along the first horizontal direction. Instead, trench segments 107 are formed. For example, a lateral length of the gate trench segments 107 in the first horizontal direction may be less than a width in the second horizontal direction.

[0102] As in Fig. 8A, fins 114 are arranged between adjacent trench segments 107 along a second horizontal direction. Furthermore, alternating doped regions of the first and second conductivity types are formed between adjacent trench segments 107 along the first direction. A gate metal layer region is formed over the trench segments 107 and extends along the second direction. As described below with reference to Fig. 8B and Fig. As explained in FIG. 8C, a source metallization layer 103 may be disposed over the entire device. The source metallization layer 103 may be in direct contact with the source regions 124 and the body contact areas 123 between adjacent trench segments 107.

[0103] Fig. Figure 8B shows a cross-sectional view of the semiconductor device between I and I'. The cross-sectional view of Fig. 8B is configured to intersect trench segments 107. The cross-sectional view is taken along the second horizontal direction. As illustrated, trench segments 107 structure the semiconductor substrate into fins 114. A source region 124 and a channel region 122 and a portion of a current spreading region 126 are disposed in fins 114. A gate electrode 110 is disposed in trench segments 107. Gate electrode 110 is isolated from channel region 122 by a gate dielectric layer 112. A portion of a conductive material forming gate electrode 110 is disposed between source region 124 and source metallization layer 103. A shield region 116 of the second conductivity type is disposed below trench segments 107. A first compensation region 118 is arranged below the current spreading region 126.A portion of the gate dielectric layer 112 may be disposed between the conductive material forming the gate electrode 110 and the source metallization layer 103.

[0104] Fig. Figure 8C shows a cross-sectional view taken between II and II' along the second horizontal direction at a position where no trench segment is present. In Fig. In the cross-section illustrated in FIG. 8C, source regions 124 are arranged alternately with body contact regions 123 of the second conductivity type. A doped region 105 of the second conductivity type is arranged below the source regions 124. The source regions 124 and the body contact regions 123 are in contact with the source metallization layer 103. The shielding regions 116 are indicated by dashed lines. A second compensation region 119 is arranged below the doped region 105 of the second conductivity type.

[0105] Fig. 8D shows a cross-sectional view taken between III and III' along the first horizontal direction. As illustrated, the trench segment 107 is arranged in a central region. The gate electrode 110 is arranged in the trench segment 107 and is insulated from the adjacent semiconductor material by a gate dielectric 112. A source metallization layer 103 is arranged above the gate electrode 110. The source metallization layer 103 is insulated from the gate electrode 110. A doped region 105 of the second conductivity type is arranged laterally adjacent to the gate electrode 110. A shield region 116 of the second conductivity type is arranged below the gate electrode 110. A superjunction structure 117 with a first compensation region 118 and a second compensation region 119 is arranged below the gate electrode. The first compensation region 118 overlaps horizontally with the gate electrode 110.The second compensation region 119 is arranged laterally adjacent to the gate electrode 110.

[0106] Fig. Figure 8E shows a cross-sectional view taken between IV and IV' as shown in Fig. 8A. The cross-sectional view is taken along a fin 114. As illustrated, a channel region 122 and a portion of a current spreading region 126 are disposed within the fin 114. The source regions 124 extend continuously along the first horizontal direction. The first compensation region 118 is disposed below the current spreading region 126. Furthermore, a doped region 105 of the second conductivity type is disposed adjacent to the fin 114. Furthermore, the second compensation region 119 is disposed laterally adjacent to the first compensation region 118.

[0107] For example, if the Fig. 8A to 8E, the shielding region 116 may be defined over the gate trench 111 using a low-energy implantation process. Furthermore, the doped region of the channel region 122 may be formed within the fin 114. As shown in Fig. 8B, the source region 124 does not contact the source metallization layer 103 at the top of the fins 114. Contact with the source metallization layer 103 may be made at the gable ends of the fins 114, such as in Fig. 8C. The channel region 122 may be electrically coupled to the source metallization layer 103 via the doped region 105 of the second conductivity type and the body contact region 123. The shielding region 116 may be formed via the doped region 105 of the second conductivity type as shown in Fig. 8C illustrates that the semiconductor device may be electrically coupled to the source metallization layer 103. According to further embodiments, different contact schemes may be used.

[0108] Methods for manufacturing the semiconductor device as explained above are described below. Fig. 9A shows an example of a workpiece 15 with an epitaxially grown region 134, e.g., a SiC region. As in Fig. As illustrated in Figure 9B, ion implantation processes 133 may be performed to provide a first doped region 131 of a first conductivity type and a second doped region 132 of a second conductivity type. For example, the ion implantation process 133 may be performed using a doping mask to provide the first and second doped regions 131, 132.

[0109] Referring to Fig. 9C, a further epitaxial growth process may be performed to form another epitaxially grown region 134. Referring to Fig. 9D, a further ion implantation process 133 may then be performed to provide a first doped region 131 and a second doped region 132. The Fig. 9C and Fig. The sequence described in Figure 9D can be repeated until a desired height of the first and second doped regions is reached.

[0110] Fig. 9E shows a further process for epitaxial growth of a semiconductor region 134. Thereafter, a further implantation process 133 is performed to provide a source region 124 of a first conductivity type adjacent to a first main surface of the workpiece 15. Gate trenches 111 are then defined in the main surface of a resulting workpiece, as shown in Fig. 9G. For example, the gate trenches 111 may be etched to a bottom portion of the epitaxially grown region 134 disposed above the first doped region 131 and the second doped region 132. According to further embodiments, the gate trenches 111 may be etched to a depth less than the thickness of the epitaxially grown region 134, such that a portion of the epitaxially grown region 134 is retained below the gate trenches 111.

[0111] After that, as in Fig. 9H, a tilted ion implantation process may be performed to form the second conductivity type doped region 120 and the first conductivity type doped region 121. During the tilted ion implantation process 136, the implantation angle and energy may be appropriately set to form the first doped region 120 and the second doped region 121. Fig. 9H shows an example of a resulting workpiece 15. Thereafter, further processes for defining elements of the semiconductor device can be performed.

[0112] According to an alternative approach, from the Fig. Starting from the structure shown in Figure 9F, a further ion implantation process 133 may be performed to define the channel region 122. Gate trenches 111 may then be etched, resulting in the definition of the fins 114. Fig. 9J shows an example of a resulting workpiece 15. Thereafter, further processes for defining elements of the semiconductor device can be performed.

[0113] According to further examples, an epitaxial process may be performed to form an epitaxially grown region 134, e.g., a SiC body. As in Fig. 10B, various blanket, e.g., unmasked, ion implantation processes 133 may then be performed to define the current spreading region 126, the channel region 122, and the source region 124. In particular, various implantation processes for dopants with different conductivity types may be performed.

[0114] Referring to Fig. 10C, trenches 135 can then be etched in the surface of a resulting workpiece. Fig. 10C shows an example of a resulting workpiece 15. Tilted ion implantation processes 136 may then be performed to provide a doped sidewall region. Fig. 10D shows an example of a workpiece with a doped sidewall region 138 of the second conductivity type.

[0115] Referring to Fig. 10E, a further implantation process 136 may subsequently be performed to define the doped sidewall region 137 of the first conductivity type. According to further examples, the order of the processes may be reversed. Thereafter, a dielectric material 139 may be formed. For example, the dielectric material 139 may comprise a silicon oxide. The dielectric material 139 may be formed to cover sidewalls of the trench 135. Furthermore, a filling with the dielectric material 139 may be formed in an upper trench region.

[0116] Referring to Fig. 10G, a gate trench 111 is etched, defining fins 114. Referring to Fig. 10H, a gate dielectric layer 112 is then formed adjacent to the sidewalls of the gate trench 111. Furthermore, a conductive material is filled to form the gate electrode 110. Subsequently, the workpiece 15 can be further processed to provide additional components of the semiconductor device.

[0117] According to further examples, an epitaxially grown region 134 may first be formed, as in Fig. 11A. After that, as shown in Fig. 11B, an ion implantation process 133 may be performed to form the source region 124 of the first conductivity type. Referring to Fig. 11C, trenches 135 can be formed in the workpiece 15. Thereafter, referring to Fig. 11D, a tilted ion implantation process 136 may be performed. As a result, a first doped sidewall region 138 of the second conductivity type may be formed directly adjacent to the sidewall. Furthermore, referring to Fig. 11E, a doped sidewall region 137 of the first conductivity type can be formed. As in Fig. 11F, a further tilted ion implantation process 136 may then be performed to form doped regions of the second conductivity type 120 of the channel region.

[0118] As in Fig. 11G, a further tilted ion implantation process 136 may then be performed to form the doped region 121 of the first conductivity type in a central region of the ridge 114. As shown in Fig. 11H, a dielectric material 135 is further formed on the sidewall of an extended trench region 113. A dielectric material 135 for forming the gate dielectric layer 112 is further formed in the upper trench region. Furthermore, a conductive material for forming the gate electrode 110 is filled into the trenches. Fig. 11D and Fig. 11E are carried out such that the implanted regions 138, 135 extend down to the bottom of the trench. In the embodiment illustrated with reference to Fig. 11F and Fig. 11G, the angle of inclination is greater than in the processes described in Fig. 11D and Fig. 11E. The tilt angle is adjusted to establish a desired length of the channel region 122.

Claims

[1] A semiconductor device (10) comprising a transistor, the transistor comprising: a plurality of gate trenches (111) formed in a semiconductor substrate (100), the gate trenches (111) structuring the semiconductor substrate (100) into webs (114) extending in a first horizontal direction, the webs (114) each being arranged between two adjacent gate trenches (111); a gate electrode (110) arranged in at least one of the gate trenches (111); a source region (124) of a first conductivity type electrically coupled to a source terminal (130), a channel region (122) having a doped region (120) of a second conductivity type, a current spreading region (126) of the first conductivity type, and a drain region (125) electrically coupled to a drain terminal (129), wherein the source region (124), the channel region (122), and a portion of the current spreading region (126) are disposed in the fins (114), the gate electrode (110) being insulated from the channel region (122) and the current spreading region (126), the source region (124) being disposed at least in a central region of the fin (114); wherein the semiconductor device (10) further comprises a superjunction structure (117) arranged at a greater distance from the source region (124) than the channel region (122), comprising: a first compensation region (118) of the first conductivity type, wherein the first compensation region (118) is electrically coupled to the drain terminal (129); and a second compensation region (119) of the second conductivity type, wherein the first and second compensation regions (118, 119) are adjacent to each other, wherein a doping concentration of the doped region (120) of the second conductivity type of the channel region (122) decreases in a second horizontal direction crossing the first horizontal direction from a region near the gate electrode (110) to a central region of the fin (114). [2] The semiconductor device (10) of claim 1, wherein the channel region (122) further comprises a doped region (121) of the first conductivity type in the central region of the fin (114). [3] The semiconductor device (10) of claim 2, wherein the first compensation region (118) is electrically coupled to the doped region (121) of the first conductivity type in the central region of the fin (114). [4] The semiconductor device (10) according to any one of claims 1 to 3, further comprising a shielding region (116) of the second conductivity type arranged below each of the gate trenches (111), the shielding region (116) having a higher doping concentration than the second compensation region (119), the second compensation region (119) being electrically coupled to the shielding region (116). [5] A semiconductor device (10) according to any one of the preceding claims, wherein the superjunction structure (117) extends in the first horizontal direction. [6] The semiconductor device (10) according to any one of the preceding claims 1 to 4, wherein the superjunction structure (117) extends in a second horizontal direction crossing the first horizontal direction. [7] A semiconductor device (10) according to any one of the preceding claims, wherein the source region (124) extends continuously along the first horizontal direction. [8] The semiconductor device (10) of any one of claims 1 to 6, wherein the source region (124) is segmented into source region segments (109) along the first horizontal direction, the semiconductor device further comprising body contact regions (123) between adjacent source region segments (109), the body contact regions (123) being electrically coupled to the source terminal (130). [9] Semiconductor device (10) according to one of the preceding claims, further comprising a drift region (127) of the first conductivity type arranged between the superjunction structure (117) and the drain region (125). [10] A semiconductor device (10) according to any one of the preceding claims, wherein the gate trenches (111) extend continuously in the first horizontal direction. [11] The semiconductor device (10) of claim 10, further comprising contact recesses (106) extending in the first horizontal direction and extending through the gate trenches (111), wherein a metal layer disposed in the contact recesses (106) is electrically coupled to the source terminal (130) and to the second compensation region (119) of the second conductivity type. [12] The semiconductor device (10) of claim 11, wherein the contact recesses (106) extend continuously in the first horizontal direction. [13] The semiconductor device (10) of claim 11, wherein the contact recesses (106) are segmented into recess contact islands (108). [14] The semiconductor device (10) according to any one of claims 1 to 10, wherein the gate trenches (111) comprise a plurality of trench segments (107) arranged along the first horizontal direction. [15] The semiconductor device (10) of claim 14, further comprising a metal layer electrically coupled to the source terminal (130), the metal layer being arranged in contact with the source region (124) between adjacent trench segments (107) and with the doped region (120) of the second conductivity type of the channel region (121). [16] A semiconductor device (10) comprising a transistor, the transistor comprising: a plurality of gate trenches (111) formed in a SiC substrate (100), the gate trenches (111) structuring the SiC substrate (100) into webs (114) extending in a first horizontal direction, the webs (114) each being arranged between two adjacent gate trenches (111); a gate electrode (110) arranged in at least one of the gate trenches (111); a source region (124) of a first conductivity type electrically coupled to a source terminal (130), a channel region (122) having a doped region (120) of a second conductivity type, a current spreading region (126) of the first conductivity type, and a drain region (125) electrically coupled to a drain terminal (129), wherein the source region (124), the channel region (122), and a portion of the current spreading region (126) are disposed in the fins (114), the gate electrode (110) being insulated from the channel region (122) and the current spreading region (126), a width of the source region (124) corresponding to a width of the fin (114); wherein the semiconductor device (10) further comprises a superjunction structure (117) arranged at a greater distance from the source region (124) than the channel region (122), the superjunction structure (117) comprising: a first compensation region (118) of the first conductivity type, wherein the first compensation region (118) is electrically coupled to the drain terminal (129); and a second compensation region (119) of the second conductivity type, wherein the second compensation region (119) is electrically coupled to the doped region (120) of the second conductivity type of the channel region (122), wherein the first and second compensation regions (118, 119) are adjacent to one another. [17] The semiconductor device (10) of claim 16, wherein the first compensation region (118) is electrically coupled to the current spreading region (126). [18] The semiconductor device (10) according to any one of claims 16 or 17, wherein a doping concentration of the doped region (120) of the second conductivity type of the channel region (122) decreases in a second horizontal direction crossing the first horizontal direction from a region near the gate electrode (110) to a central region of the fin (114). [19] The semiconductor device (10) of claim 18, wherein the channel region (122) further comprises a doped region (121) of the first conductivity type in the central region of the fin (114). [20] The semiconductor device (10) of claim 19, wherein the first compensation region (118) is electrically coupled to the doped region (121) of the first conductivity type in the central region of the ridge (114). [21] The semiconductor device (10) according to any one of claims 16 to 20, further comprising contact recesses (106) extending in the first horizontal direction and extending from a bottom region of the gate trenches (111) in a depth direction, wherein a metal layer disposed in the contact recesses (106) is electrically coupled to the source terminal (130). [22] The semiconductor device (10) according to any one of claims 16 to 20, wherein the gate trenches (111) comprise a plurality of trench segments (107) arranged along the first horizontal direction. [23] The semiconductor device (10) of claim 22, further comprising a metal layer electrically coupled to the source terminal (130), wherein the metal layer is arranged in contact with the source region (124) between adjacent trench segments (107).

Images