Method for manufacturing a stacked chip package, chip package and semiconductor package

Abstract

A process that includes the following steps: Providing one or more upper dies (112) and one or more lower dies (114), wherein a first surface of each of the one or more upper dies (112) is coupled to a first interconnect layer (120), and a first surface of each of the one or more lower dies (114) is coupled to a second interconnect layer (122), wherein the first and second interconnect layers each comprise the following: a layer (116) comprising copper pads and a dielectric layer (118); Performing a coupling of the first and second interconnection layers (120, 122) between the one or more upper dies (112) and the one or more lower dies (114) via a hybrid copper bond; Applying a material (130) to at least partially cover the second bonding layer (122), wherein the one or more upper dies and the material form a continuous surface; Coupling a first surface of a support die (132) with a second surface of at least one of the one or more upper dies (112); and Coupling a second surface of at least one of the one or more lower dies (114) with a plurality of microbumps (134, 302), wherein coupling the first surface of the support die (132) with the second surface of at least one of the one or more upper dies (112) comprises coupling the support die (132) with the second surface of at least one of the one or more upper dies (112) via a bonding film (138), wherein the binding film (138) comprises a filler material and a resin material, the filler material comprises one or more of the following: Silver, aluminum flakes, silver-coated copper spheres, silver-diamond or copper-diamond particles; and wherein the resin material comprises one or more of the following: Polyimide, benzocyclobutane, epoxy, phenolic resin, polyurethane or silicon.

Description

BACKGROUND

[0001] As the performance of semiconductor packages increases and more processors and logic circuits are added, thermal conductivity and structural support between components become increasingly challenging. Improving thermal conductivity and structural support between components within a semiconductor package is essential to enhance package yield and durability. For example, interconnecting dies by stacking them within a package increases interconnect density but presents an unresolved mechanical and thermal challenge. Semiconductor packages can incorporate interconnect components with enhanced package support capabilities. These interconnect components can also be designed to conduct heat dissipation and provide active cooling across the entire package.The ability to support, dissipate heat, and actively cool semiconductor packages enables higher power density, durability, and efficiency. Furthermore, a common process flow using hybrid copper bonding may be required to accommodate multiple configurations of manufactured semiconductor packages and minimize supply chain complexity, while simultaneously meeting product requirements for signal bandwidth, power delivery network (PDN), and heat dissipation.

[0002] US 2020 / 0 381 397 A1 discloses a system formed by package-in-package formation. The system comprises a first device die and a second device die coupled by hybrid bonding. A first isolation region encapsulates the first device die. The first device die, the second device die, or the first isolation region form parts of a first package. A third device die is coupled to the first package by hybrid bonding. The first package, the third device die, and a second isolation region form parts of a second package.

[0003] DE 10 2017 120 875 A1 discloses an RDL-load-process-formed package. A method comprises bonding a first device chip and a second device chip to a substrate and filling a gap between the first and second chips with a gap-filling material. Electrical vias are electrically coupled to the first and second device chips. SUMMARY

[0004] In one aspect, embodiments of the inventive concepts disclosed herein are directed to a method according to claim 1. The method provides one or more upper dies, one or more lower dies, two or more layers of copper pads, and two or more dielectric layers, wherein a first surface of each of the one or more upper dies is coupled to a first interconnect layer, and a first surface of each of the one or more lower dies is coupled to a second interconnect layer. The first and second interconnect layers may comprise one of the two or more layers of copper pads and one of the two or more dielectric layers. The coupling of the first and second interconnect layers between the one or more upper dies and the one or more lower dies includes a filler between the one or more coupled upper dies.One surface of one or more dies is thinned (made thinner) to form a continuous surface. The surface of a support die is coupled to the second surface of at least one of the one or more upper dies. In operation, successive layers of upper dies can be stacked before the surface of the support die is coupled to the second surface of at least one of the one or more upper dies.

[0005] In a further aspect, the embodiments of the inventive concepts disclosed here are directed to a chip package according to claim 3. The chip package can comprise one or more upper dies, one or more lower dies, two or more layers of copper pads, two or more dielectric layers, a first interconnect layer, a second interconnect layer, a material, a support die, and a plurality of microbumps. A first surface of each of the one or more upper dies is coupled to the first interconnect layer, and a first surface of each of the one or more lower dies is coupled to the second interconnect layer. The first and second interconnect layers can each contain one of the two or more layers of copper pads and one of the two or more dielectric layers.The first and second bonding layers between the one or more upper dies and the one or more lower dies are connected via a hybrid copper bond. A material is deposited between the one or more connected upper dies. The surface of the support die is connected to a second surface of the one or more upper dies. The majority of the microbumps are connected to a second surface of at least one of the one or more lower dies.

[0006] In another aspect, the embodiments of the inventive concepts disclosed herein are directed to a semiconductor package according to claim 10. The semiconductor package is manufactured by a method. The method provides for the fabrication of one or more chip packages. The manufactured chip packages are produced by a method. The method provides for one or more upper dies, one or more lower dies, two or more layers of copper pads, and two or more dielectric layers, wherein a first surface of each of the one or more upper dies is coupled to a first interconnect layer, and a first surface of each of the one or more lower dies is coupled to a second interconnect layer. The first and the second interconnect layer can each contain one of the two or more layers of copper pads and one of the two or more dielectric layers.The coupling of the first and second bonding layers between the one or more upper dies and the one or more lower dies involves applying a material to fill one or more gaps between the one or more upper dies. A surface of the one or more dies is thinned to form a continuous surface. The surface of a support die is coupled to the second surface of at least one of the one or more upper dies. In operation, successive layers of upper dies can be stacked before the surface of the support die is coupled to the second surface of at least one of the one or more upper dies.

[0007] The second surface of at least one of the one or more lower dies is coupled to a first plurality of microbumps. The one or more fabricated chip packages are coupled to an interposer. A second surface of the interposer is coupled to a second plurality of microbumps. The second plurality of microbumps is coupled to a first surface of a substrate. A second surface of the substrate is coupled to a third plurality of microbumps.

[0008] This summary serves only as an introduction to the subject matter, which is fully described in the detailed description and the drawings. The summary is not to be considered a description of essential features and is not intended to be used to determine the scope of the claims. Furthermore, both the preceding summary and the following detailed description are merely exemplary and explanatory and are not necessarily limiting to the claimed subject matter. The accompanying drawings, which form part of the description, illustrate exemplary embodiments of the inventive concepts disclosed herein and, together with the general description, serve to explain the principles.

[0009] Some drawings can depict process flows for the manufacture of devices. These process flows, which may be a sequence of steps for manufacturing a device, can contain many structures, numbers, and labels that are common to two or more consecutive steps. In such cases, some labels, numbers, and structures used to depict a particular step may already have been described in the drawings of the preceding steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The detailed description is explained with reference to the accompanying figures. The use of the same reference numbers in different places in the description and in the figures may indicate similar or identical elements. Various embodiments or examples (“Examples”) of the present disclosure are disclosed in the following detailed description and the accompanying drawings. The drawings are not necessarily to scale. In general, the operations of the disclosed methods can be carried out in any order, unless otherwise specified in the claims. The numerous advantages of the embodiments of the inventive concepts disclosed herein can be better understood by those skilled in the art with reference to the accompanying figures. Fig. Figure 1A shows a method for manufacturing a chip package using hybrid copper bonding; Fig. Figure 1B shows a first step in the process for manufacturing a chip package in Fig. 1A; Fig. Figure 1C shows a second step in the process for manufacturing a chip package in Fig. 1A, which represents a coupling process of an upper die with a lower die via hybrid copper bonding; Fig. Figure 1D shows a third step in the process for manufacturing a chip package in Fig. 1A, which represents a thinning of an upper die and a material; Fig. Figure 1E shows a fourth step in the process for manufacturing a chip package in Fig. 1A, which represents a coupling of a support die with an upper die; Fig. Figure 1F shows a fifth step in the process for manufacturing a chip package in Fig. 1A, which represents a thinning of the lower die; Fig. 1G and Fig.1H show alternative embodiments of the method for manufacturing a chip package in Fig. 1A; Fig. 2A shows a front cross-section through a chip package; Fig. 2B to Fig. 2D shows alternative embodiments of the chip package in Fig. 2A; Fig. Figure 3A shows a front cross-section through a semiconductor package; Fig. 3B to Fig. 3D images show alternative embodiments of the semiconductor package in Fig. 3A; Fig. Figure 4 shows a top and side cross-sectional view of a support die with microfluidic channels; and Fig. Figure 5 shows a flowchart of a process for manufacturing a chip package. DETAILED DESCRIPTION

[0011] The following section discusses in detail the object depicted in the attached drawings.

[0012] In general, the inventive concepts disclosed here relate to a manufacturing process for a chip package, a chip package obtained by the manufacturing process, and a semiconductor package obtained by applying the manufacturing process as part of a process flow for manufacturing the semiconductor package. A chip package can refer to a die mounted on a package substrate (for example, another die). A semiconductor package can refer to a chip package mounted on a package substrate (for example, an interposer or another substrate). The semiconductor package can also be referred to as a module.The embodiments of the chip package and the semiconductor package comprise a bonding film and a support die with the inventive concepts disclosed herein, which further enhance the thermal conductivity and structural support of the chip package and the semiconductor package.

[0013] With reference to Fig.Figure 1A describes a process 100 for manufacturing a chip package using a hybrid copper bond according to one or more embodiments of the present disclosure. The process 100 comprises a first step 102, a second step 104, a third step 106, a fourth step 108, and a fifth step 110 for manufacturing the chip package. Each of the steps 102, 104, 106, 108, and 110 is shown in cross-section from the front. The process 100 can be a single process sequence for manufacturing a chip package using the hybrid copper bond. The Fig.The common process flow shown in Figure 1A can enable a manufacturer to simplify the fabrication process of chip packages that can be coupled using hybrid copper bonding. A common process flow can accommodate multiple configurations of manufactured semiconductor packages and minimize supply chain complexity. The common process flow can also meet product requirements for signal bandwidth, power distribution network (PDN), and heat dissipation. Step 110, shown in Method 100, can resemble an embodiment of a chip package, which is discussed in more detail below.

[0014] With reference to Fig.Figure 1B shows a front cross-sectional view of the first step 102 of the method 100 according to one or more embodiments of the present disclosure. The first step 102 may comprise the provision of one or more upper dies 112 (for example, chip, wafer, compute die, memory die, I / O die, or the like), one or more lower dies 114 (for example, chip, wafer, compute die, memory die, I / O die, or the like), two or more layers of copper pads 116 (for example, active copper), and two or more dielectric layers 118. The copper pads 116 may refer to an exposed area that can be used for the electrical and / or mechanical connection between dies. The copper pads 116 may also be referred to as a "landing pad," "surface mount pad," "bonding pad," or the like.The term layer can refer to a layer of the dies that contains both the copper pads 116 and the dielectric. For example, die 112 can contain a layer with the copper pads 116 and the dielectric layer 118. Another example is that die 114 contains a layer with the copper pads 116 and the dielectric layer 118. The copper pads 116 can then transmit electrical signals or current between the dies. A first surface of each of the one or more upper dies 112 is coupled to a first interconnect layer 120, and a first surface of each of the one or more lower dies 114 is coupled to a second interconnect layer 122. The first and second interconnect layers each comprise one or more layers of copper pads 116 and one or more dielectric layers 118.

[0015] In some embodiments, the upper dies 112 or the lower dies 114 of the method can include 100 through-silicon vias (TSVs) 124, which provide power and signal conductivity 128 between the components (for example, between the upper dies 112 and the lower dies 114). The TSVs 124 are a type of via connection (vertical interconnect access) used in microchip fabrication that partially or completely penetrate silicon dies to allow die stacking (for example, stacking the lower dies 112 and the upper dies 114). Coupling through the TSVs 124 does not require a direct connection between the vias and the components. For example, the TSVs 124 can be connected to pads (for example, the copper pads 116) or have multiple vias interconnected by conductor tracks.The TSVs 124 enable the separate construction of multiple layers of transistors 126. The TSVs 124 can establish the conductive signal connection 128 (for example, the power or data connection) between the layers of transistors 126. For example, the TSVs 124 can provide a power and data connection between the upper dies 112 and the lower dies 114. In another example, the TSVs 124 can provide a stack and data connection between a stack of upper dies 112 and / or the lower dies 114.

[0016] Alternatively or additionally, the upper dies 112 or the lower dies 114 of the method 100 can include other interconnection components (for example, deep-trench capacitors or integrated voltage regulators) that help regulate the signal conductance 128 of the chip package fabricated by the method 100. Deep-trench capacitors are semiconductor devices used to add capacitance to various integrated circuits within the chip package. For example, the deep-trench capacitors can store electrostatic energy in an electric field and release this energy, when needed, to the integrated circuit components of the chip package (for example, the transistors 126 of the upper dies 112 and the lower dies 114).Integrated voltage regulators are semiconductor devices that can provide a constant, fixed output voltage to the various integrated circuit components (for example, the transistors 126 of the upper dies 112 and the lower dies 114) of the chip package, regardless of any change in the load or input voltage.

[0017] In some embodiments, the upper dies 112 or the lower dies 114 of method 100 can be an active die or a passive die. Active dies require an energy source to perform their specific function and can include semiconductor devices (for example, diodes, transistors 126, or integrated circuits) that can supply energy to a circuit and are capable of electrically controlling and amplifying the current flow through the components of the chip package. Alternatively, passive dies can include components (for example, resistors, capacitors, inductors, transducers) that can influence the current flow through them. For example, at least one of the upper dies 112 can be a passive die.A passive die may, for example, include deep-trench capacitors that provide additional power consumption or storage within the chip package, and at least one of the lower dies 114 may be an active die that controls the signal conductivity 128 (for example, the amplification of the electrical current flow) of the chip package.

[0018] In some embodiments, the two or more dielectric layers 118 can consist of a stoichiometry of silicon and oxygen molecules. The dielectric layers can comprise silicon dioxide (SiOx), where x is an integer. For example, the two or more dielectric layers 118 can consist of silicon dioxide (which, for example, may be optimized for hybrid copper bonding due to its low coefficient of thermal expansion and high bond energy). In certain embodiments, the dielectric layers 118 can comprise several dielectric sublayers. The dielectric sublayers can contain the silicon dioxide or a similar material.

[0019] With reference to Fig.Figure 1C shows a front cross-sectional view of the second step 104 of the method 100, illustrating a coupling process of one or more upper dies 112 and one or more lower dies 114 by means of a hybrid copper bond according to one or more embodiments of the present disclosure. The second step 104 may include: performing a coupling of the first and second compound layers 120, 122 between the one or more upper dies 112 and the one or more lower dies 114 via a hybrid copper bond. The coupling may be face-to-face. The coupling may also be performed at an elevated temperature (for example, in the range of 25 to 400°C) and / or an elevated pressure (for example, in the range of 50 to 150 MPa).

[0020] A hybrid copper bond can be a bond that combines a dielectric bond with embedded copper metal to form interconnects. These interconnects can be used to couple different components of a chip package (for example, the upper dies 112 with the lower dies 114). The hybrid copper bond increases the interconnect density (connection spacing) compared to microbumps (from 40 micrometers to less than 10 micrometers) for connecting the various components in the chip packages. A connection spacing can refer to the center-to-center distance of one connection (for example, one of the microbumps or one of the copper pads 116) to another. The higher the interconnect density (connection spacing), the smaller the center-to-center distance between the connections.The hybrid copper bond can include planarized dielectric layers (for example, the dielectric layers 118) and embedded copper connection points (for example, the copper pads 116). The dielectric layers 118 and the copper pads 116 can be connected in the same plane at the bond interface to form the first and second connection layers 120 and 122, respectively. Connecting the dielectric layers 118 and the copper pads 116 in the same plane can enable face-to-face coupling between the upper dies 112 and the lower dies 114. Face-to-face coupling can refer to a type of coupling in three-dimensional integrated circuits that connects two or more stacked dies. For example, the upper Dies 112 and / or the lower Dies 114 can use the upper metal (the surface) as the coupling side when coupling the upper Dies 112 with the lower Dies 114.The transistors 126 of the upper die 112 and the lower die 114 can face each other when the upper dies 112 are coupled face-to-face with the lower dies 112. For example, the first and second interconnect layers 120, 122 are coupled simultaneously, so that the dielectric layer 118 of the first interconnect layer 120 is coupled with the dielectric layer 118 of the second interconnect layer 122, creating a structure that essentially acts like a die. The interconnect can be a connection at elevated temperature between two clean oxide surfaces (for example, silicon dioxide). At elevated temperature, the layers of the copper pads 116 expand more than the dielectric layers 118, causing the individual layers of the copper pads 116 to connect to each other (for example, at the copper connection points), creating an automatic pressure connection.

[0021] With reference to Fig.Figure 1D shows a front cross-sectional view of the third step 106, which illustrates thinning (for example, reducing, refining, highlighting) of one or more upper dies 112 and of a material 130 according to one or more embodiments of the present disclosure. The third step 106 may include: applying the material 130. The material 130 may be applied to at least partially cover the compound layer 122 and / or the die 114. Partial covering may refer to placing the material above the surface of the compound layer 122 and / or the die 114 and is not limited to covering the entire surface of the compound layer 122 and / or the die 114. The material 130 may be applied such that it is located at or above a height of the one or more dies 112.If the one or more upper dies 112 comprise at least two upper dies, the material can also fill one or more gaps (spaces) between the at least two upper dies (see for example . Fig.1G). The material 130 can be applied in one or more steps. The material 130 can also comprise multiple materials. A second surface of the one or more upper dies 112 and the material 130 can then be thinned to form a continuous surface. The continuous surface can be bounded by an outer perimeter of the one or more upper dies 112 and the material. The continuous surface can refer to a substantially flat, smooth, level, or planar surface defined by the one or more upper dies 112 and the material 130. The continuous surface can be horizontal or nearly horizontal, without significant curvature or inclination and without significant elevations or depressions. For example, the second surface of the one or more upper dies 112 and the material 130 can be thinned to a suitable height during the third step 106.In some embodiments, the thinning of one or more upper dies 112 and of the material 130 can resemble a chemical-mechanical polishing (CMP) process, in which fillers are introduced to uniformize the metal density and reduce height variations after thinning. In some embodiments, the thinning can be achieved by mechanical grinding. For example, a diamond- and resin-bonded grinding wheel mounted on a high-speed spindle can be used to perform the thinning. In other embodiments, the thinning can be achieved by wet etching. For example, liquid etchants can be used that diffuse onto the surface of the dies to achieve thinning. In other embodiments, the thinning can be achieved by dry chemical etching (DCE).For example, atmospheric plasma etching (ADP) is a type of DCE in which a reactive process gas is used to roughen the surface of the die (for example, to make it thinner).

[0022] In some embodiments, the material 130 can comprise stoichiometries of molecules such as silicon and oxygen molecules, silicon, oxygen, and nitrogen molecules, and / or silicon, carbon, and nitrogen molecules (for example, silicon oxide, oxynitride, or oxycyanide). The material 130 can provide structural support and additional heat transfer capabilities during the process 100 for manufacturing the chip package, based on its molecular composition. The following table compares the mechanical and functional properties of various carbon-based epoxy resin composites that can be used in the material 130 to enhance the structural support and / or heat transfer capabilities of the invention.Furthermore, the epoxy composite materials listed in the table below can also be used in a bonding film, which will be described later in this document. Comparison of the mechanical and functional performance of various carbon-based epoxy composite materials materials Filter type Tensile strength (MPa) Young module (GPa) K1C (Mpa.m 0,5 ) G1C (J.m -2 ) Shear strength (MPa) Electrical conductivity (S / cm) Thermal conductivity (W / mK) Epoxy composites SWCNT (1 wt.%) 10,5-74,1 0,503-3,27 0,58 7 × 10-9 MWCNT (1 wt%) 46,4-50 1,59-2,83 2,8 270 0,25-0,38 TR-GO ~10-9 0,254 R-GO (0.05 wt.%) 53 3,0 0,48 77 1,68 × 10-10 GO (0.5 wt%) 66 3,0 0,75 250 - - GnPs (1 wt%) 18,2-62 2,23-3,0 0,95 298 m-GnPs (1 wt%) 59-63,98 2,8 0,75 245 ~10-9 0,234 m-GnPs (0.489 vol. %) 49,21 3,412 1,258 557 3 × 10-9 Epoxy composite adhesives SWCNT (1 wt.%) 10 ~10-4 MWCNT (1 wt%) 0,068 -15 CNF (0.5 wt%) ~96 9,2 - - CNF (0.25 wt%) GO (1 wt%) 58,98 3,025 - -105 - 9,2 6,36 7,4 × 10-16 0,37 R-GO (1 wt.%) 51,31 2,894 6,174 1,6 × 10-14 0,31 m-GnPs (6 wt%) 53 3,4 8,9 GnPs (1 wt%) -7,5 -0,2 GnPs (0.5% by volume)* 33 2,64 1,68 896 12,34 4 × 10-9 0,24 * 0.5 vol-% GnPs is equivalent to 1 wt% GnPs Qingshi Meng, Sensen Han, Sheril Araby, Yu Zhao, Zhiwen Liu & Shaowei Lu (2019): Mechanically robust, electrically and thermally conductive graphene-based epoxy adhesives, Journal of Adhesion Science and Technology, DOI- 10.1080 / 01694243.2019.1595890

[0023] With reference to Fig.Figure 1E shows a front cross-sectional view of the fourth step 108, which represents a coupling of a support die 132 with the one or more upper dies 112 according to one or more embodiments of the present disclosure. The fourth step 108 may include: coupling a first surface of the support die 132 with the second surface of at least one of the one or more upper dies 112. In some embodiments, the support die 132 may be (temporarily) coupled or connected to the one or more upper dies 112. In some embodiments, the support die 132 may comprise aluminum nitride, silicon, and / or similar silicon-based compositions (for example, graphene on silicon or diamond on silicon). In some embodiments, the support die 132 may consist of silicon. In some embodiments, a back surface of the support die 132 may comprise bare silicon or a back surface metallization.The back side of the support die 132 can improve the thermal efficiency of the support die 132 and / or further enhance the thermal conductivity of the chip package. For example, applying metal layers to the support die 132 can enable the formation of additional conductive paths between the support die 132 and another semiconductor device.

[0024] In some embodiments, such as in Fig. As shown in more detail in Figure 4, the support die 132 can include one or more microfluidic channels 136. The support die 132 can be used more efficiently by utilizing its interior and integrating the microfluidic channels 136. The microfluidic channels 136 can improve heat transfer within the chip package. For example, the microfluidic channels 136 can be filled with a fluidic material (for example, a dielectric fluid, such as fluorocarbon, mineral oil, hydrocarbon, 3M™ Fluorinert™, 3M™ Novec™, or similar). Materials such as these can provide a liquid-cooled heat transfer process within the chip package, while the support die 132 simultaneously provides passive heat transfer through the areas in its interior that do not interact with the microfluidic channels 136.

[0025] The support die 132 is connected to the second surface of the upper dies 112 via a bonding film 138. The bonding film 138 comprises a filler material and a resin material. For example, the filler material can fill the inner body of the bonding film 138, while the resin material can act as an adhesive, covering the outer body of the bonding film 138 and being in direct contact with one or more upper dies 112 and the support die 132 during the fourth step 108 of the process 100. The filler material comprises silver-, aluminum-, and / or copper-containing compositions (for example, silver, aluminum flakes, silver-coated copper spheres, silver-diamond, or copper-diamond particles). The resin material comprises various polymers (for example, polyimide, benzocyclobutane, epoxy, phenolic resin, polyurethane, or silicone).

[0026] The binding film 138 can be an important component of the chip package for several reasons. For example, the binding film 138 can conduct heat throughout the entire manufactured chip package. The resin material can be selected to dissipate heat from the interfaces between the binding film 138 and the one or more upper dies 112, the support die 132, and the filler material. Additionally, the filler material can further improve the thermal conductivity of the binding film 138, depending on the composition chosen for the filter material. Furthermore, the microfluidic channels 136 inside the support die 132 can also conduct heat by acting as a heat sink.

[0027] The use of the bonding film 138 to connect one or more upper dies 112 to the support die 132 can provide additional structural support within the chip package structure. For example, the upper dies 112 and the lower dies 114 can be very thin (e.g., several micrometers). Therefore, the support die 132 can provide additional mechanical robustness and support to the chip package fabricated by method 100.

[0028] With reference to Fig. Figure 1F shows a front cross-sectional view of the fifth step 110, which illustrates thinning of one or more lower dies 114 according to one or more embodiments of the present disclosure. The fifth step 110 may include thinning a second surface of the one or more lower dies 114. The second surface of the one or more lower dies 114 may then be coupled to a plurality of microbumps 134. The thinning may be performed by any of the techniques described herein.

[0029] In some embodiments, the one or more lower dies 114 can include the TSVs 124. For example, in the fifth step 110, the one or more lower dies 114 (for example, containing the TSVs 124) can be thinned until the TSVs 124 are exposed, and the plurality of microbumps 134 (for example, solder microbumps) can then be coupled to the second surface of the one or more lower dies 114 (for example, the microbumps 134 associated with the TSVs 124). In contrast to the hybrid copper bond used to couple the one or more dies 112, 114 within the chip package, the plurality of microbumps 134 can be used to couple the chip package to an external component of a semiconductor package. For example, the majority of microbumps can comprise 134 solder bumps, forming a coupling point between the chip packages and an interposer.The interposer is an electrical interface through which electrical signals can be transmitted to another component (for example, another chip package). For instance, the chip package, which comprises a stack of one or more of the upper dies 112 and one of the lower dies 114 (which includes the TSVs 124), can be connected to the interposer by coupling the microbumps 134 to the interposer, thus establishing the signal conductivity 128 between the chip package and the interposer. Further embodiments in which the chip package is coupled to an interposer via the microbumps 134 are explained in more detail below.

[0030] With reference to Fig. Figure 1G shows an alternative embodiment of the method 100, which displays a front cross-sectional view of an end product 140 produced by the method 100 in accordance with one or more embodiments of the present disclosure. In some embodiments, the end product 140 may be configured with two or more of the one or more upper dies 112 and one or more of the one or more lower dies 114. For example, in some embodiments, the method 100 may be configured such that the end product 140 is produced with two of the one or more upper dies 112 and one of the one or more lower dies 114. For example, during the second step 104, the two upper dies 112 may be coupled face-to-face to the one lower die 114 on the same planarized surface (for example, the first compound layer 120) by hybrid copper bonding.For example, during the second step 104, described previously, the two upper dies 112 can be coupled to the dielectric layer 118 of the first interconnect layer 120, and during the third step 106, the material 130 can be applied to one or more gaps between the two upper dies 112. In some embodiments, the supporting die 132 of the final product 140 can include the microfluidic channels 136 or the bonding film 138 to support the increased power density resulting from the presence of more than one of the upper dies 112 compared to only one (for example, as in ). Fig. 1F). In some embodiments, the final product 140 can be configured with only one of the upper dies 112 and one of the lower dies 114 (for example, as in Fig. 1F to be seen).

[0031] With reference to Fig. Figure 1H shows an alternative but unclaimed embodiment of the method 100, which presents a front cross-sectional view of an end product 140 with additional upper dies 142 (for example, one or more upper dies 112) coupled to the one or more upper dies 112 in a stacked configuration according to one or more embodiments of the present disclosure. In some embodiments, as in Fig. As can be seen in Figure 1H, the method 100 can further be configured to produce a stacked chip package comprising one or more additional upper dies coupled to the one or more upper dies 112 via hybrid copper bonding. For example, the third step 106 (for example, as in Fig. (as shown in 1D) further includes coupling a first surface of one or more additional upper dies 142 with the thinned second surface of one or more upper dies 112 via hybrid copper bonding. For example, after thinning the second surface of one or more upper dies 112, as shown in step 3 106, one of the additional upper dies 142 can be coupled with the thinned second surface of one or more upper dies 112 via step 1 102, step 2 104, and step 3 106. As shown in step 1 102 and step 2 104, for example, face-to-face coupling via hybrid copper bonding can be performed between one or more upper dies 112 and one of the additional upper dies 142.As shown in step 106, material 130 can then be applied, and the second surface of the additional upper die 142 can be thinned. Material 130 can be applied in such a way that it at least partially covers the additional upper die 142. At this point, another upper die 142 (not shown) can be coupled to the thinned second surface of the previous upper die 142 via step 102, step 104, and step 106. Any number of additional upper dies 142 can be coupled to the one or more upper dies 112 (for example, in a stacked configuration).After coupling one or more additional upper dies 142 to one or more upper dies 112, a second surface of an additional upper die 142, which is not in contact with another additional upper die 142, can then be coupled to the first surface of the support die 132 (for example, via the fourth step 108). In a preferred embodiment, the additional upper die 142 with the highest density in the stacked chip package configuration is the additional upper die 142 that is coupled to the support die 132. The second surface of at least one of the one or more lower dies 114 can then be thinned and coupled to a plurality of microbumps 134 (for example, via the fifth step 110).

[0032] The stacked chip package presented here can include any number of additional upper dies 142. Stacking three or more dies (for example, a lower die 114, an upper die 112, and one or more additional upper dies 142) increases the power density of the chip package and may require additional components to support the structure and heat transfer throughout the chip package. For example, a chip package containing any number of upper dies 112, 142 can additionally include the support die 132 with microfluidic channels 136, which is connected to the one or more upper dies 112, 142 via the bonding film 138. The support die 132 with the microfluidic channels can dissipate heat through the stacked chip package with the higher power density while also providing additional mechanical support.Furthermore, each of the one or more lower dies 114 and the one or more upper dies 112, 142 can comprise the TSVs 124. The lower dies 114 and the upper dies 112, 142 with the TSVs 124 can provide the signal conductivity 128 between the multiple layers of transistors 126 within the stacked chip package. Alternatively or additionally, the additional upper dies 142 of the method 100 can comprise other interconnection components (for example, deep-trench capacitors or integrated voltage regulators) that help regulate the signal conductivity 128 of the final product 140 produced by the method 100. The applicant points out that the features and capabilities of the upper dies 112 described herein should be interpreted to also extend to the one or more additional upper dies 142.

[0033] With reference to Fig. Figure 2A shows a front cross-sectional view of a chip package 200 according to one or more embodiments of the present disclosure. The applicant points out that the chip package 200 can be an end product 140 of the method 100 described herein. The embodiments and enabling components associated with the method 100 for producing the end product 140 should be interpreted as extending to the chip package 200. However, it is further pointed out that the chip package 200 is not limited to the architecture of the method 100 or the end product 140.

[0034] In some embodiments, the chip package 200 can comprise one of the one or more upper dies 112 coupled face-to-face to one of the one or more lower dies 114 via hybrid copper bonding (by coupling the first interconnect layer 120 and the second interconnect layer 122, as in Fig. (1C shown). The first and second interconnection layers 120, 122 can each comprise: one of the two or more layers of copper pads 116 and one of the two or more dielectric layers 118. The chip package 200 can further comprise the material 130 used to fill the gaps created by the coupling of the one or more upper dies 112 and the one or more lower dies 114, the support die 132 coupled to the one or more upper dies 112, and the plurality of microbumps 134 coupled to the one or more lower dies 114.

[0035] In some embodiments, the upper dies 112 or the lower dies 114 of the chip package 200 may include the TSVs 124. The TSVs 124 may provide power and signal conductivity 128 between the components (for example, between the lower dies 114, the upper dies 112, and the additional upper dies 112). For example, the chip package 200 may include the TSVs 124 that are exposed from the second surface of one or more lower dies 114 and coupled to the plurality of microbumps 134. Alternatively or additionally, the upper dies 112 or the lower dies 114 may include other interconnection components (for example, deep-trench capacitors or integrated voltage regulators) that contribute to regulating the signal conductivity 128 of the chip package 200. In some embodiments, the upper dies 112 or the lower dies 114 can be an active die or a passive die.For example, at least one of the upper dies 112 can be a passive die that provides additional consumption or storage of energy within the chip package 200, and at least one of the lower dies 114 can be an active die that controls the signal conductivity 128 of the chip package 200.

[0036] With reference to Fig. Figure 2B shows an alternative embodiment of the chip package 200 according to one or more embodiments of the present disclosure. In some embodiments, the support die 132 can comprise one or more microfluidic channels 136. The microfluidic channels 136 can improve heat transfer within the chip package 200. For example, the microfluidic channels 136 can be filled with a fluidic material (for example, a dielectric fluid). The fluidic material can provide a liquid-cooled heat transfer process within the chip package 200, while the support die 132 simultaneously provides passive heat transfer through the regions inside it that do not interact with the microfluidic channels 136.

[0037] The support die 132 is connected to the second surface of the upper die 112 via the bonding film 138. The bonding film 138 comprises the filler material and the resin material. For example, the filler material can fill the inner body of the bonding film 138, while the resin material can act as an adhesive, covering the outer body of the bonding film 138 and coming into direct contact with one or more upper dies 112 and the support die 132.

[0038] With reference to Fig. Figure 2C is an alternative embodiment of the chip package 200 according to one or more embodiments of the present disclosure. In some embodiments, the chip package 200 can comprise two of the one or more upper dies 112 and one of the one or more lower dies 114. For example, the two upper dies 112 can be coupled with the same planarized surface (for example, the first interconnect layer 120) and directly connected to the one lower die 114 via a hybrid copper bond. For example, as in Fig. As shown in Figure 2C, the two upper dies 112 can be coupled to the dielectric layer 118 of the first interconnection layer 120, and the one lower die 114 can be coupled to the second interconnection layer 122, wherein the first and second interconnection layers 120, 122 can be coupled via hybrid copper bonding, and the material 130 can be applied to one or more gaps between the two upper dies 112.

[0039] With reference to Fig. 2D is an alternative embodiment of the chip package 200 according to one or more embodiments of the present disclosure. In some embodiments, the supporting die 132 may comprise the microfluidic channels 136 and / or the binding film 138 to support the increased power density resulting from the inclusion of more than one of the upper dies 112 compared to only one of the upper dies 112, as shown in Fig. 2B is shown, it is present.

[0040] In some embodiments, the chip package 200 can comprise two or more upper dies 112, 142, which are stacked and coupled together via the hybrid copper bonding process, as previously described in Fig. 1G shown and discussed (for example, the final product 140). For example, the chip package 200 can include one or more additional upper dies 142 coupled to the one or more upper dies 112 and connected via the hybrid copper bond through the first step 102, the second step 104, and the third step 106 of the method 100. In some embodiments, the supporting die 132 can include the microfluidic channels 136 and / or the bonding film 138 to support the increased power density resulting from stacking more than one upper die 112, 142 within the chip package 200.

[0041] The embodiments or examples shown do not limit the number of configurations that the chip package 200 can have. For example, the chip package 200 can be configured such that any number of upper dies 112, 142 are stacked within the chip package by means of hybrid copper bonding. Furthermore, in some embodiments, the chip package 200 can be configured such that three or more upper dies 112 and / or lower dies 114 are arranged on the same planarized surface (for example, horizontally aligned on the same compound layer 120, 122) via hybrid copper bonding.

[0042] With reference to Fig. Figure 3A shows a front cross-sectional view of a semiconductor package 300 according to one or more embodiments of the present disclosure. The applicant points out that the chip package 200 can be configured to be a component of the semiconductor package 300, and that the chip package 200 can also be an end product 140 of the method 100 described herein, and that the embodiments and enabling components associated with the method 100 for producing the end product 140 should be designed to extend to the chip package 200 as used in the semiconductor package 300. However, it should be noted that the semiconductor package 300 is not limited to the architecture of the method 100, the end product 140, or the chip package 200 as described herein.

[0043] In some embodiments, the semiconductor package 300 can comprise a first plurality of microbumps 302, one or more of the chip packages 200, an interposer 304, a second plurality of microbumps 306, a substrate 308, a third plurality of microbumps 310, and one or more package fillers 312 (for example, a compute die, a memory die, an I / O die, or the like). For example, a first plurality of microbumps 302 (which can comprise the plurality of microbumps 134 coupled to the one or more chip packages 200) can be coupled to a first surface of the one or more package fillers 312. For example, the one or more chip packages 200 can be coupled with the first plurality of microbumps 302 (for example, the plurality of microbumps 134), and the one or more package fillers 312 can also be coupled with the first plurality of microbumps 302.The first plurality of microbumps 302 can comprise solder bumps that form a coupling point between the one or more package fillers 312 and the interposer 304, as well as a coupling point between the one or more chip packages 200 and the interposer 304. The first plurality of microbumps 302 can be coupled to a first surface of the interposer 304, a second surface of the interposer 304 can be coupled to the second plurality of microbumps 306, a first surface of the substrate 308 can be coupled to the second plurality of microbumps 306, and a second surface of the substrate 308 can be coupled to the third plurality of microbumps 310.

[0044] As discussed previously herein, the interposer 304 is an electrical interface that can be used to conduct electrical signals through it to another component (for example, from the chip packages 200 to the package fillers 312). For example, connecting (via the first plurality of microbumps 302) the one or more chip packages 200 to the interposer 304 can establish the signal conductivity 128 between the one or more chip packages 200, the one or more package fillers 312, and the interposer 304. The substrate 308 is a support material (for example, a metal oxide) with which the elements of the semiconductor package 300 (for example, the chip packages 200, the interposer 304, or the package fillers 312) can be coupled.The substrate 308 can provide the semiconductor package 300 with a mechanical support base and form an electrical interface (for example, via the coupled third plural of microbumps 310), which further enables the semiconductor package 300 to be coupled with various electronic circuits (for example, printed circuit boards).

[0045] In some embodiments, the back side of one or more package fillers 312 can comprise bare silicon or a back-side metallization to improve the thermal efficiency of the one or more package fillers 312 and to further enhance the thermal conductivity of the semiconductor package 300. For example, the application of metal layers to the one or more package fillers 312 can enable the formation of additional conductive paths between the one or more package fillers 312 and another semiconductor device.

[0046] With reference to Fig. Figure 3B is an alternative embodiment of the semiconductor package 300 according to one or more embodiments of the present disclosure. In some embodiments, the semiconductor package 300 may comprise two or more of the chip packages 200, which may be coupled to the interposer 304 via the first plurality of microbumps 302.

[0047] With reference to Fig. 3C is an alternative embodiment of the semiconductor package 300 according to one or more embodiments of the present disclosure. In some embodiments, the one or more chip packages 200 can be configured to include two of the one or more upper dies 112 horizontally aligned and one of the one or more lower dies 114 (as in Fig. 1G, Fig. 2C and Fig. (shown in 2D). In some (not shown) embodiments, the chip package 200 can comprise two or more upper dies 112, 142, which are stacked and coupled to each other via the hybrid copper bond, as previously shown in Fig. 1G shown and discussed (for example, the final product 140). For example, the chip package 200 can include one or more additional upper dies 142 coupled to the one or more upper dies 112 and connected via the hybrid copper bond through the first step 102, the second step 104, and the third step 106 of the process 100. In some embodiments, the supporting die 132 can include the microfluidic channels 136 and / or the bonding film 138 to support the increased power density resulting from the vertical stacking of more than one upper die 112, 142 within the chip package 200.

[0048] With reference to Fig. 3D is an alternative embodiment of the semiconductor package 300 according to one or more embodiments of the present disclosure. In some embodiments, the one or more chip packages 200 can include the microfluidic channels 136 and the binding film 138. The embodiments or examples shown do not limit the number of configurations of the semiconductor package 300.

[0049] With reference to Fig. Figure 4 shows a top cross-sectional view 402 and a side cross-sectional view 404 of the support die 132 with the microfluidic channels 136 according to one or more embodiments of the present disclosure. As previously disclosed herein, the support die 132 shown in the method 100, the chip package 200, and the semiconductor package 300 can contain the one or more microfluidic channels 136. The microfluidic channels 136 can enhance heat transfer within the chip package 200. For example, the microfluidic channels 136 can be filled with a fluidic material (for example, a dielectric fluid) that provides a liquid-cooled heat transfer process within the chip package 200, while the support die 132 simultaneously ensures passive heat transfer through the regions inside it that do not interact with the one or more microfluidic channels 136.In some embodiments, the one or more microfluidic channels 136 can be designed as a single continuous path within the support die 132, which may include a fluid inlet point 406 and a fluid outlet point 408. In some embodiments, the microfluidic channels 136 may have dimensions that extend to the inner walls of the support die 132.

[0050] With reference to Fig. Figure 5 shows a flowchart illustrating the steps of a process 500 for manufacturing a chip package 200 according to one or more embodiments of the present disclosure. The applicant points out that the embodiments and basic technologies previously described herein in connection with manufacturing process 100 should be interpreted, to the extent appropriate for the person skilled in the art, as also extending to process 500.

[0051] In some embodiments, the method 500 comprises a step 502 of providing one or more upper dies, one or more lower dies, two or more layers of copper pads and two or more dielectric layers, wherein a first surface of each of the one or more upper dies is coupled to a first interconnect layer and a first surface of each of the one or more lower dies is coupled to a second interconnect layer, wherein the first and the second interconnect layer each comprise one of the two or more layers of copper pads and one of the two or more dielectric layers.

[0052] In some embodiments, the method 500 comprises a step 504 of performing a face-to-face coupling of the first and second interconnect layers between the one or more upper dies and the one or more lower dies via a hybrid copper bond.

[0053] In some embodiments, method 500 comprises a step 506 of applying a material and thinning a second surface of the one or more upper dies, wherein both the one or more upper dies and the material form a continuous surface. The material can be applied to at least partially cover the one or more lower dies and / or to fill one or more gaps between the coupled upper dies.

[0054] In some embodiments, the method 500 comprises a step 508 of coupling a first surface of a support die with the second surface of at least one of the one or more upper dies.

[0055] In some embodiments, the method 500 comprises a step 510 of thinning a second surface of at least one of the one or more lower dies and coupling the second surface of at least one of the one or more lower dies with a plurality of microbumps.

[0056] It is understood that embodiments of the methods disclosed herein may include one or more of the steps described herein. Furthermore, these steps may be performed in any order, and two or more of the steps may be performed simultaneously. Two or more of the steps disclosed herein may be combined into a single step, and in some embodiments, one or more of the steps may be performed as two or more sub-steps. In addition, other steps or sub-steps may be performed in addition to or as a replacement for one or more of the steps disclosed herein.

Claims

[1] Procedure comprising the following steps: Providing one or more upper dies (112) and one or more lower dies (114), wherein a first surface of each of the one or more upper dies (112) is coupled to a first interconnect layer (120), and a first surface of each of the one or more lower dies (114) is coupled to a second interconnect layer (122), wherein the first and second interconnect layers each comprise: a layer (116) comprising copper pads and a dielectric layer (118); performing a coupling of the first and second interconnect layers (120, 122) between the one or more upper dies (112) and the one or more lower dies (114) via a hybrid copper bond; Applying a material (130) to at least partially cover the second connecting layer (122), wherein the one or more upper dies and the material form a continuous surface; coupling a first surface of a support die (132) to a second surface of at least one of the one or more upper dies (112); and Coupling a second surface of at least one of the one or more lower dies (114) to a plurality of microbumps (134, 302), wherein coupling the first surface of the support die (132) to the second surface of at least one of the one or more upper dies (112) comprises coupling the support die (132) to the second surface of at least one of the one or more upper dies (112) via a bonding film (138), wherein the bonding film (138) comprises a filler material and a resin material, wherein the filler material comprises one or more of the following: Silver, aluminum flakes, silver-coated copper balls, silver-diamond or copper-diamond particles; and wherein the resin material comprises one or more of the following: Polyimide, benzocyclobutane, epoxy, phenolic resin, polyurethane or silicon. [2] The method of claim 1, wherein the support die (132) comprises microfluidic channels (136). [3] Chip package (200) comprising: one or more upper dies (112); one or more lower dies (114); a first interconnect layer (120); a second interconnect layer (122), wherein a first surface of each of the one or more upper dies (112) is coupled to the first interconnect layer (120), wherein a first surface of each of the one or more lower dies (114) is coupled to the second interconnect layer (122), wherein the first and second interconnect layers (120, 122) each comprise: a layer (116) comprising copper pads and a dielectric layer (118), wherein the first and second interconnect layers are coupled between the one or more upper dies (112) and the one or more lower dies (114) via a hybrid copper bond; a material (130), the material being applied to at least partially cover the second bonding layer (122), the one or more upper dies (112) and the material (130) defining a continuous surface; a support die (132), wherein a first surface of the support die (132) is coupled to a second surface of at least one of the one or more upper dies (112); and a plurality of microbumps (134, 302), wherein the plurality of microbumps (134, 302) are coupled to a second surface of at least one of the one or more lower dies (114), wherein the second surface of the one or more upper dies (112) and the first surface of the support die (132) are coupled via a bonding film (138), wherein the bonding film (138) comprises a filler material and a resin material, wherein the filler material comprises one or more of the following: Silver, aluminum flakes, silver-coated copper balls, silver-diamond or copper-diamond particles; and wherein the resin material comprises one or more of the following: polyimide, benzocyclobutane, epoxy, phenolic resin, polyurethane, or silicon. [4] Chip package according to claim 3, wherein the support die (132) comprises one or more of the following: Aluminum nitride, graphene on silicon, diamond on silicon or silicon. [5] Chip package according to one of claims 3 or 4, wherein the dielectric layer (118) comprises silicon oxide. [6] Chip package according to one of claims 3 to 5, wherein at least one of the one or more upper dies (112) and the one or more lower dies (114) further comprises one or more of the following: one or more through-silicon vias; one or more deep trench capacitors; or one or more integrated voltage regulators. [7] Chip package according to one of claims 3 to 6, wherein at least one of the one or more upper dies (112) and the one or more lower dies (114) comprises an active die. [8] Chip package according to one of claims 3 to 7, wherein the support die (132) comprises microfluidic channels (136). [9] Chip package according to one of claims 3 to 8, wherein the material (130) comprises one or more of the following: silicon and oxygen molecules; silicon, oxygen and nitrogen molecules; or Silicon, carbon and nitrogen molecules. [10] Semiconductor package (300) obtained by a method comprising the following steps: Producing one or more chip packages (200) with the steps according to one of claims 1 or 2; coupling the one or more fabricated chip packages (200) via the first plurality of microbumps (134, 302) to a first surface of an interposer (304), wherein a second surface of the interposer (304) is coupled to a second plurality of microbumps (306); and Coupling the second plurality of microbumps (306) to a first surface of a substrate (308), wherein a second surface of the substrate (308) is coupled to a third plurality of microbumps (310). [11] The semiconductor package of claim 10, further comprising: one or more package fillers (312), wherein the one or more package fillers are coupled to the first surface of the interposer (304) via the first plurality of microbumps (134, 302). [12] Semiconductor package according to one of claims 10 to 11, wherein the support die (132) comprises microfluidic channels (136).

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