Array substrate and display panel

Abstract

The present application provides an array substrate and a display panel, comprising: a substrate;and a first transistor arranged on the substrate and comprising: a first active layer located on the substrate and comprising a first channel section, a first doped section and a second doped section, wherein the first doped section and the second doped section are each connected to opposite ends of the first channel section, wherein the first doped section comprises a first doped subsection and a second doped subsection, wherein the second doped subsection is connected between the first channel section and the first doped subsection, wherein the second doped subsection has an ion doping concentration that is lower than the ion doping concentration of the first doped subsection, and wherein the ion doping concentration of the first doped subsection is the same as that of the second doped section;a first gate electrode located on one side of the first active layer and overlapping the first channel section; and a source electrode and a drain electrode, the source electrode being connected to the second doped section and the drain electrode being connected to the first doped subsection of the first doped section.

Description

Technical area

[0001] The present application relates to the field of display technology, in particular to an array substrate and a display panel. State of the art

[0002] Currently, the development of high-mobility transistors to improve the operating performance of display panels is a key research focus in the field of display technology. However, high-mobility transistors suffer from poor stability during operation.

[0003] How to improve the poor stability of high-mobility transistors is therefore a technical problem to be solved. Disclosure of the invention

[0004] The object of the present application is to provide an array substrate and a display panel to solve the problem of poor stability of transistors.

[0005] In a first aspect, the present application provides an array substrate comprising: a substrate; and a first transistor arranged on the substrate and comprising: a first active layer located on the substrate and comprising a first channel portion, a first doped portion, and a second doped portion, the first doped portion and the second doped portion being respectively connected to both opposite ends of the first channel portion, the first doped portion comprising a first doped subportion and a second doped subportion, the second doped subportion being connected between the first channel portion and the first doped subportion, the second doped subportion having an ion doping concentration that is lower than the ion doping concentration of the first doped subportion, and the ion doping concentration of the first doped subportion being the same as that of the second doped portion; a first gate electrode located on one side of the first active layer and overlapping the first channel portion; and a source electrode and a drain electrode, wherein the source electrode is connected to the second doped section and the drain electrode is connected to the first doped subsection of the first doped section.

[0006] In a second aspect, the present application provides a display panel comprising an array substrate according to some of the above-mentioned embodiments.

[0007] Advantageous effects: Since the ion doping concentration of the second doped sub-portion is lower than the ion doping concentration of the first doped sub-portion and the ion doping concentration of the first doped sub-portion is the same as the ion doping concentration of the second doped sub-portion, the resistance of the second doped sub-portion is larger than the resistance of the first doped sub-portion, thereby reducing the voltage drop of the first doped portion connected to the drain electrode and solving the problem of poor stability of the first transistor caused by self-heating. Short description of the characters Fig. 1A to Fig. 1H each shows a schematic structural view of a manufacturing process of an array substrate according to some embodiments of the present application; Fig. 2 shows a schematic structural view of an array substrate according to some further embodiments of the present application; Fig. 3 shows a schematic structural view of an array substrate according to some embodiments of the present application; Fig. 4 shows a schematic sectional view of a display panel according to some embodiments of the present application; and Fig. 5 shows a schematic sectional view of a display panel according to some further embodiments of the present application. List of reference symbols:

[0008] 30. Display panel; 10. Array substrate; 201. Light-emitting element layer; 2011. Light-emitting element; 202. Counter substrate; 203. Liquid crystal layer; 101. Substrate; 102. Buffer layer; 103a. first semiconductor layer; 103b. first active layer; 1031. first channel section; 1032a. first initially doped section; 1032a1. first region; 1032a2. second region; 1032. first doped section; 1032a1. first doped subsection; 1032a2. second doped subsection; 1033a. second initially doped section; 1041. fourth insulating layer; 1042. first insulating layer; 1043. second insulating layer; 1044. third insulating layer; 105. first gate electrode; 106a. second semiconductor layer; 106. second active layer; 1061. second channel section; 1062. third doped section; 1063. fourth doped section; 107. second gate electrode; 10a. first via; 10d. second via; 10b. third via; 10e. fourth via; 10c. fifth via; 10f. sixth via; 1081. Source electrode; 1082. Drain electrode; T1. first transistor; T2. second transistor. Detailed embodiments

[0009] In conjunction with the figures in the embodiment of the present application, the technical solutions in the embodiment of the present application will be explained clearly and completely below. It should be understood that the described embodiments represent a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those skilled in the art from the embodiments of the application without inventive steps are also within the scope of the application.

[0010] Reference is made to Fig. 1A to Fig. 1H, each of which shows a schematic structural view of a manufacturing process of an array substrate according to some embodiments of the present application. In the following, the manufacturing process of the array substrate according to some embodiments of the present application will be described with reference to Fig. 1A to 1H are described in detail.

[0011] With reference to Fig. 1A, a first semiconductor layer 103a is first formed on a substrate 101.

[0012] In some embodiments, as in Fig. 1A, the manufacturing process of the array substrate before forming a first semiconductor layer 103a on a substrate 101 further: forming a buffer layer 102 on the substrate 101.

[0013] By way of example, the substrate 101 comprises, but is not limited to, a glass substrate. The substrate 101 may also be a flexible substrate comprising a polymer layer.

[0014] By way of example, the buffer layer 102 comprises, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a stack of a silicon nitride layer and a silicon oxide layer.

[0015] In some embodiments, forming a first semiconductor layer 103a on a substrate 101 comprises: forming a first semiconductor layer 103a on a surface of the buffer layer 102 facing away from the substrate 101.

[0016] In some embodiments, the first semiconductor layer 103a is a single-layer semiconductor layer. Materials of the first semiconductor layer 103a include amorphous silicon, polysilicon, or metal oxide.

[0017] The polysilicon can be obtained by crystallizing amorphous silicon through laser annealing or by other crystallization processes. The metal oxide comprises at least one of the following elements: indium, zinc, tungsten, tin, gallium, and aluminum. Metal oxide materials include, but are not limited to, indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium gallium oxide (IGO), indium zinc oxide (IZO), aluminum indium zinc oxide (AIZO), aluminum tin zinc oxide (ATZO), and other metal oxides with lower leakage current.

[0018] Then, as in Fig. 1B, a first gate electrode 105, which overlaps the first semiconductor layer 103a, is formed on a side of the first semiconductor layer 103a facing away from the substrate 101.

[0019] In some embodiments, as in Fig. 1B, the manufacturing process of the array substrate before forming a first gate electrode 105 overlapping the first semiconductor layer 103a on a side of the first semiconductor layer 103a facing away from the substrate 101 further comprises: forming a fourth insulating layer 1041 on the first semiconductor layer 103a, wherein the fourth insulating layer 1041 overlaps a part of the first semiconductor layer 103a.

[0020] The fourth insulating layer 1041 is a first gate insulating layer. In some embodiments, the materials of the fourth insulating layer 1041 include, but are not limited to, at least one of silicon oxide, aluminum oxide, and silicon nitride. By way of example, the fourth insulating layer 1041 includes a silicon oxide layer or a stack of an aluminum oxide layer, a silicon nitride layer, and a silicon oxide layer, or a stack of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.

[0021] In some embodiments, forming a first gate electrode 105 overlapping the first semiconductor layer 103a on a side of the first semiconductor layer 103a facing away from the substrate 101 comprises: forming a first gate electrode 105 on a side of the fourth insulating layer 1041 facing away from the substrate 101.

[0022] In some embodiments, the materials of the first gate electrode 105 include, but are not limited to, at least one of molybdenum, aluminum, copper, titanium, indium zinc oxide, and indium tin oxide. By way of example, the first gate electrode 105 includes: a molybdenum layer (Mo); or a stack of a molybdenum layer and an aluminum layer (Mo / Al); or a stack of a molybdenum layer and a copper layer (Mo / Cu); or a stack of a molybdenum-titanium alloy layer and a copper layer (MoTi / Cu); or a molybdenum-titanium alloy layer, a copper layer, and a molybdenum-titanium alloy layer (MoTi / Cu / MoTi) stacked on top of each other; or a titanium layer, an aluminum layer, and a titanium layer (Ti / Al / Ti) stacked on top of each other. or a titanium layer, a copper layer and a titanium layer (Ti / Cu / Ti) stacked on top of each other;or a stack of a molybdenum layer, a copper layer, and an indium zinc oxide (Mo / Cu / IZO) layer stacked one above the other; or a stack of an indium zinc oxide, a copper layer, and an indium zinc oxide (IZO / Cu / IZO) layer stacked one above the other.

[0023] Then, as in Fig. 1C, using the first gate electrode 105 as a mask, the first semiconductor layer 103a is subjected to a first doping, so that the first semiconductor layer 103a subjected to the first doping forms a first initially doped portion 1032a and a second initially doped portion 1033a and a first channel portion 1031, wherein the first initially doped portion 1032a and the second initially doped portion 1033a are respectively connected to both opposite ends of the first channel portion 1031.

[0024] In some embodiments of the present application, after the first doping of the first semiconductor layer 103a using the first gate electrode 105 as a mask, the doped portions of the first semiconductor layer 103a each form the first initially doped portion 1032a and the second initially doped portion 1033a, wherein the undoped portion of the first semiconductor layer 103a forms the first channel portion 1031. The first initially doped portion 1032a and the second initially doped portion 1033a have the same ion doping concentration, while the first initially doped portion 1032a and the second initially doped portion 1033a have a conductivity. The orthographic projection of the first channel portion 1031 on the substrate 101 completely overlaps the orthographic projection of the first gate electrode 105 on the substrate 101.In other words, the orthographic projection of the first channel portion 1031 on the substrate 101 and the orthographic projection of the first gate electrode 105 on the substrate 101 are substantially the same orthographic projection.

[0025] In some embodiments, the length of the first initially doped section 1032a is greater than the length of the second initially doped section 1033a, wherein the length of the first initially doped section 1032a is long enough to allow for subsequent differentiated design for resistors in different regions of the first initially doped section 1032a. At the same time, in a direction perpendicular to the thickness of the substrate 101, the distance between the first gate electrode 105 and an edge of the first initially doped section 1032a facing away from the first channel section 1031 is greater than the distance between the first gate electrode 105 and an edge of the second initially doped section 1033a facing away from the first channel section 1031.

[0026] In some further embodiments, the length of the first initially doped section 1032a may also be less than or equal to the length of the second initially doped section 1033a.

[0027] In some embodiments of the present application, the first initially doped portion 1032a includes a first region 1032a1 and a second region 1032a2, wherein the second region 1032a2 is located between the first region 1032a1 and the first channel portion 1031. Further ion doping is required for the first initially doped portion 1032a of the first region 1032a1. No further ion doping is required for the first initially doped portion 1032a of the second region 1032a2.

[0028] In some embodiments, the first doping is a heavy N-type doping or a heavy P-type doping. The ions used for a heavy N-type doping include, but are not limited to, phosphorus ions. The ions used for a heavy P-type doping include, but are not limited to, boron ions.

[0029] In some embodiments, the doping concentration of the first doping is 1 × 10 14 / cm 2 up to 9 × 10 14 / cm 2 For example, the doping concentration of the first doping is 4 × 10 14 / cm 2 .

[0030] Then, as in Fig. 1E, a second semiconductor layer 106a is formed on a side of the first gate electrode 105 facing away from the substrate 101, wherein the second semiconductor layer 106a overlaps the first channel portion 1031, the second region 1032a2 and a part of the first region 1032a1 of the first initially doped portion 1032a and the second initially doped portion 1033a.

[0031] In some embodiments, as in Fig. 1D, the manufacturing method of the array substrate, before forming a second semiconductor layer 106a on a side of the first gate electrode 105 facing away from the substrate 101, further comprises: forming a first insulating layer 1042 covering the first gate electrode 105, the first initially doped portion 1032a, the second initially doped portion 1033a, and the buffer layer 102, and forming a first via 10a overlapping the second initially doped portion 1033a on the first insulating layer 1042.

[0032] In some embodiments, the materials of the first insulating layer 1042 include, but are not limited to, at least one of silicon oxide, silicon oxynitride, aluminum oxide, and silicon nitride. By way of example, the first insulating layer 1042 includes any one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a stack of a silicon nitride layer and a silicon oxide layer.

[0033] In some embodiments, as in Fig. 1E, forming a second semiconductor layer 106a on a side of the first gate electrode 105 facing away from the substrate 101; forming a second semiconductor layer 106a on a surface of the first insulating layer 1042 facing away from the substrate 101 and in the first via 10a.

[0034] By way of example, the second semiconductor layer 106a is a single-layer semiconductor layer. The materials of the second semiconductor layer 106a include, but are not limited to, amorphous silicon, polysilicon, or metal oxide. The selection of polysilicon and metal oxides is as described above and will not be repeated here.

[0035] In some embodiments, the material of the second semiconductor layer 106a is the same as the material of the first semiconductor layer 103a, but is not limited thereto. By way of example, both the second semiconductor layer 106a and the first semiconductor layer 103a are metal oxide semiconductor layers.

[0036] In some further embodiments, the material of the second semiconductor layer 106a may differ from the material of the first semiconductor layer 103a. For example, the first semiconductor layer 103a is a metal oxide semiconductor layer, while the second semiconductor layer 106a is a polysilicon semiconductor layer.

[0037] Then, as in Fig. 1F and Fig. 1G, a second gate electrode 107 is formed on a side of the second semiconductor layer 106a facing away from the substrate 101, wherein, using the second gate electrode 107 as a mask, the second semiconductor layer 106a, the first initially doped portion 1032a in the first region 1032a1 and the second initially doped portion 1033a are subjected to a second doping, such that the second semiconductor layer 106a forms a second active layer 106 after the doping, and the first initially doped portion 1032a in the first region 1032a1 and the second initially doped portion 1033a each form a first doped sub-portion 10321 and a second doped portion 1033 after the doping.

[0038] In some embodiments of the present application, the array substrate manufacturing method further comprises, prior to forming a second gate electrode 107 on a side of the second semiconductor layer 106a facing away from the substrate 101: forming a second insulating layer 1043 covering the second semiconductor layer 106a and the first insulating layer 1042.

[0039] The second insulating layer 1043 is a second gate insulating layer. In some embodiments, the materials of the second insulating layer 1043 include, but are not limited to, at least one of silicon oxide, aluminum oxide, and silicon nitride. By way of example, the second insulating layer 1043 includes a silicon oxide layer or a stack of an aluminum oxide layer, a silicon nitride layer, and a silicon oxide layer, or a stack of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.

[0040] In some embodiments of the present application, after the second doping of the second semiconductor layer 106a, the first initially doped portion 1032a in the first region 1032a1 and the second initially doped portion 1033a using the second gate electrode 107 as a mask, the doped parts of the second semiconductor layer 106a each form a third doped portion 1062 and a fourth doped portion 1063, wherein the undoped part of the second semiconductor layer 106a forms a second channel portion 1061, wherein the third doped portion 1062 and the fourth doped portion 1063 are each connected to both opposite sides of the second channel portion 1061, wherein the second channel portion 1061, the third doped portion 1062 and the fourth doped portion 1063 form the second active layer 106.

[0041] In addition, in the first region 1032a1, the first initially doped section 1032a forms a first doped subsection 10321 after its second doping, and the second initially doped section 1033a forms a second doped section 1033 after its second doping, while the first initially doped section 1032a in the second region 1032a2 is not subjected to a second doping and does not form a second doped subsection 10322, wherein the first doped subsection 10321 and the second doped subsection 10322 form a first doped section 1032, wherein the first doped section 1032, the second doped section 1033 and the first channel section 1031 form the first active layer 103.

[0042] In some embodiments of the present application, the orthographic projection of the second channel portion 1061 on the substrate 101 completely overlaps the orthographic projection of the second gate electrode 107 on the substrate 101. In other words, the orthographic projection of the second channel portion 1061 on the substrate 101 and the orthographic projection of the second gate electrode 107 on the substrate 101 are substantially the same orthographic projection.

[0043] In some embodiments of the present application, the second channel portion 1061 overlaps the first channel portion 1031 and the second doped subportion 10322, wherein the third doped portion 1062 overlaps the second doped portion 1033 such that the second channel portion 1061 overlaps the first channel portion 1031, and wherein the length of the second channel portion 1061 is greater than the length of the first channel portion 1031, which contributes to the fact that, using the second gate electrode 107 as a mask, the second active layer 106 and the first active layer 103 are formed simultaneously by a self-alignment process in conjunction with the ion doping, thereby further reducing the number of photomasks required to fabricate the array substrate.

[0044] In some embodiments of the present application, the third doped portion 1062 and the fourth doped portion 1063 are formed by one and the same doping process using the second gate electrode 107 as a mask, which is why the third doped portion 1062 and the fourth doped portion 1063 have the same ion doping concentration, and the third doped portion 1062 and the fourth doped portion 1063 have conductivity. Furthermore, the third doped portion 1062 and the second doped portion 1033 are in contact and connected via a first via 10a, thereby reducing the number of wirings connecting the third doped portion 1062 to the second doped portion 1033 and thus further reducing the number of photomasks required to form the wirings.

[0045] In some embodiments of the present application, both the first doped subsection 10321 and the second doped subsection 1033 are formed by the first doping and the second doping, and the second doped subsection 10322 is formed by the first doping. Therefore, the ion doping concentrations of the first doped subsection 10321 and the second doped subsection 1033 are the same, the ion doping concentration of the second doped subsection 10322 is lower than the ion doping concentration of the first doped subsection 10321, and the resistance of the second doped subsection 10322 is greater than the resistance of the first doped subsection 10321, thereby reducing the voltage drop of the first doped subsection 1032 to be connected to the drain electrode.

[0046] In some embodiments of the present application, the ratio of the ion doping concentration of the second doped subsection 10322 to the ion doping concentration of the first doped subsection 10321 is greater than or equal to 0.02 and less than or equal to 0.1, such that while increasing the resistance of the second doped subsection 10322, the resistance of the first doped subsection 10321 is reduced, and while reducing the voltage drop of the first doped section 1032 that must be connected to the drain electrode, the connection impedance between the first doped subsection 10321 and the drain electrode is reduced.

[0047] In some embodiments, both the first doping and the second doping are a strong N-doping; alternatively, both the first doping and the second doping are a strong P-doping.

[0048] In some embodiments, the doping ions used for the first doping and the doping ions used for the first doping are the same, but not limited thereto. It is also possible for the doping ions used for the first doping and the doping ions used for the first doping to be different.

[0049] For example, the second doping is a strong N-doping or a strong P-doping. The ions used for a strong N-doping include, but are not limited to, phosphorus ions. The ions used for a strong P-doping include, but are not limited to, boron ions. The doping concentration of the second doping is 1 × 10 14 / cm 2 up to 9 × 10 14 / cm 2 .

[0050] In some embodiments, the thickness of the second active layer 106 is smaller than the thickness of the first active layer 103, which helps the first active layer 103 to more easily form a crystalline phase during a thermal annealing process.

[0051] In some embodiments, after forming the first active layer 103 and the second active layer 106, the manufacturing method of the array substrate further includes: performing an annealing process for the first active layer 103 to form a crystalline phase; causing the second active layer 106 to include an amorphous phase to improve the performance stability of the first active layer 103; and maintaining the semiconductor properties of the second active layer 106.

[0052] In some embodiments, after the second doping of the second semiconductor layer 106a, the first initially doped portion 1032a in the first region 1032a1, and the second initially doped portion 1033a, the array substrate manufacturing method further comprises: forming a third insulating layer 1044 covering the second gate electrode 107 and the second insulating layer 1043.

[0053] In some embodiments, with reference to Fig. 1G, after forming the third insulating layer 1044 covering the second gate electrode 107 and the second insulating layer 1043, a third via 10b, a fifth via 10c, and a second via 10d are formed, wherein the third via 10b overlaps the first doped sub-portion 10321 and is passed through the third insulating layer 1044, the second insulating layer 1043, and the first insulating layer 1042, wherein the fifth via 10c overlaps the fourth doped portion 1063 and is passed through the third insulating layer 1044 and the second insulating layer 1043, and wherein the second via 10d overlaps the third doped portion 1062 and is passed through the third insulating layer 1044 and the second insulating layer 1043.

[0054] In some embodiments, the third via 10b, the fifth via 10c, and the second via 10d are formed using a photomask in conjunction with an etching process to reduce the number of photomasks required to fabricate the array substrate.

[0055] In some embodiments, with reference to Fig. 1H, a source electrode 1081 and a drain electrode 1082 are formed, wherein the drain electrode 1082 is formed in the third via 10b, in the fifth via 10c and on a surface of the third insulating layer 1044 facing away from the substrate 101, wherein the source electrode 1081 is formed in the second via 10d and on the surface of the third insulating layer 1044 facing away from the substrate 101, such that the drain electrode 1082 is connected to the fourth doped portion 1063 and the first doped subportion 10321 and the source electrode 1081 is connected to the third doped portion 1062 and the second doped portion 1033.

[0056] In some embodiments, the materials of the source electrode 1081 and the drain electrode 1082 include, but are not limited to, at least one of molybdenum, aluminum, copper, titanium, indium zinc oxide, and indium tin oxide. By way of example, the source electrode 1081 and the drain electrode 1082 comprisethe drain electrode 1082: a molybdenum layer (Mo); or a stack of a molybdenum layer and an aluminum layer (Mo / Al); or a stack of a molybdenum layer and a copper layer (Mo / Cu); or a stack of a molybdenum-titanium alloy layer and a copper layer (MoTi / Cu); or a molybdenum-titanium alloy layer, a copper layer, and a molybdenum-titanium alloy layer (MoTi / Cu / MoTi) stacked one on top of the other; or a titanium layer, an aluminum layer, and a titanium layer (Ti / Al / Ti) stacked one on top of the other; or a titanium layer, a copper layer, and a titanium layer (Ti / Cu / Ti) stacked one on top of the other; or a stack of a molybdenum layer, a copper layer, and an indium zinc oxide layer (Mo / Cu / IZO) stacked one on top of the other; or a stack of an indium zinc oxide layer, a copper layer and an indium tin oxide layer (IZO / Cu / ITO) stacked on top of each other.

[0057] In some embodiments of the present application, a transistor is formed by the method described above, wherein the transistor comprises a first transistor T1 and a second transistor T2 connected in parallel to increase the mobility of the transistor. The first transistor T1 is a narrow-channel transistor, which further increases the mobility of the transistor. The first transistor T1 comprises a source electrode 1081, a drain electrode 1082, a first active layer 103, and a first gate electrode 105. The second transistor T2 comprises a second active layer 106, a second gate electrode 107, a source electrode 1081, and a drain electrode 1082.The first transistor T1 and the second transistor T2 are connected via a third doped section 1062. The first transistor T1 and the second transistor T2 share the source electrode 1081 and the drain electrode 1082, further reducing the number of photomasks required to fabricate the array substrate. Furthermore, the foil layers of the first transistor T1 and the second transistor T2 are stacked, thereby achieving high mobility of the transistor while reducing the horizontal space occupied by the transistor, improving the self-heating of the transistor, and increasing the performance stability of the transistor.

[0058] Reference is made to Fig. 1H, which illustrates a schematic cross-sectional view of an array substrate according to some embodiments of the present application. The array substrate 10 includes a substrate 101, a first transistor T1, and a second transistor T2. Both the first transistor T1 and the second transistor T2 are arranged on the substrate 101.

[0059] In some embodiments, the array substrate 10 further comprises a buffer layer 102, wherein the buffer layer 102 is located between the first transistor T1 and the substrate 101.

[0060] The first transistor T1 includes a first active layer 103, a first gate electrode 105, a source electrode 1081, and a drain electrode 1082. The first active layer 103 is located on the substrate 101, and the first gate electrode 105 is located on one side of the first active layer 103.

[0061] In particular, the first gate electrode 105 is located on a side of the first active layer 103 facing away from the substrate 101. That is, the first transistor T1 is a top-gate thin-film transistor, so that it is easier to form a first active layer 103 using the first gate electrode 105 as a mask and by means of ion doping, thereby reducing the number of photomasks required to manufacture the array substrate 10.

[0062] In some further embodiments, the first gate electrode 105 may also be located between the first active layer 103 and the substrate 101. In other words, the first transistor T1 may also be a bottom-gate thin-film transistor.

[0063] In some embodiments, the first active layer 103 comprises a crystalline phase to improve the performance stability of the first transistor T1.

[0064] In some embodiments, the first active layer 103 includes a first channel portion 1031, a first doped portion 1032, and a second doped portion 1033, wherein the first doped portion 1032 and the second doped portion 1033 are each connected to both opposite ends of the first channel portion 1031. The first gate electrode 105 overlaps the first channel portion 1031.The first doped section 1032 comprises a first doped subsection 10321 and a second doped subsection 10322, wherein the second doped subsection 10322 is connected between the first channel section 1031 and the first doped subsection 10321, wherein the second doped subsection 10322 has an ion doping concentration lower than the ion doping concentration of the first doped subsection 10321, and wherein the ion doping concentration of the first doped subsection 10321 is the same as that of the second doped section 1033. The source electrode 1081 is connected to the second doped section 1033, and the drain electrode 1082 is connected to the first doped subsection 10321 of the first doped section 1032.Due to this design, the resistance of the second doped subsection 10322 is greater than the resistance of the first doped subsection 10321, so the voltage drop of the first doped section 1032 connected to the drain electrode 1082 is reduced. Thus, the connection impedance between the first doped subsection 10321 and the drain electrode 1082 is reduced while solving the problem of poor stability caused by heating of the first transistor by hot carriers.

[0065] In some embodiments, along a direction in which the first active layer 103 extends from the first doped section 1032 to the second doped section 1033, the length of the first doped section 1032 is greater than the length of the second doped section 1033, which facilitates, but is not limited to, the use of ion doping to differentially shape the resistance of the first doped section 1032 in different regions. The length of the first doped section 1032 may also be less than or equal to the length of the second doped section 1033.

[0066] In some embodiments, along a direction in which the first active layer 103 extends from the first doped portion 1032 to the second doped portion 1033, the length of the first doped subportion 10321 is greater than that of the second doped subportion 10322. In this way, the total resistance of the first doped portion 1032 is made smaller while the voltage drop of the first doped portion 1032 is reduced to address the problem of poor stability of the first transistor caused by self-heating.

[0067] In some embodiments, the array substrate 10 further includes a fourth insulating layer 1041, wherein the fourth insulating layer 1041 is a first gate insulating layer. The fourth insulating layer 1041 is disposed between the first gate electrode 105 and the first active layer 103.

[0068] In some embodiments, the array substrate 10 further includes a first insulating layer 1042, wherein the first insulating layer 1042 is an interlayer insulating layer. The first insulating layer 1042 covers the first gate electrode 105, the first active layer 103, and the buffer layer 102.

[0069] The second transistor T2 comprises a second active layer 106 and a second gate electrode 107. At least a portion of the second active layer 106 is located on a side of the first gate electrode 105 facing away from the substrate 101. In particular, a portion of the second active layer 106 is located on a surface of the first insulating layer 1042 facing away from the substrate 101.

[0070] The second gate electrode 107 is located on the side of the second active layer 106 facing away from the substrate 101 and overlaps the second channel portion 1061, so that it is easier to form the second active layer 106 by ion doping using the second gate electrode 107 as a mask and to reduce the number of photomasks required to manufacture the array substrate 10.

[0071] The second active layer 106 includes a second channel portion 1061, a third doped portion 1062, and a fourth doped portion 1063, wherein the third doped portion 1062 and the fourth doped portion 1063 are each connected to both opposite ends of the second channel portion 1061.

[0072] The third doped portion 1062 and the second doped portion 1033 are connected via the via 10a, which is passed through the first insulating layer 1042, to realize the connection between the first transistor T1 and the second transistor T2, thereby saving additional wiring required to connect the third doped portion 1062 to the second doped portion 1033 and further reducing the number of DIYI photomasks required to manufacture the array substrate 10.

[0073] The second channel portion 1061 overlaps the first channel portion 1031 and the second doped subportion 10322. In other words, the length of the second channel portion 1061 is greater than the length of the first channel portion 1031. The third doped portion 1062 overlaps the second doped portion 1033, and the fourth doped portion 1063 overlaps the first doped subportion 10321. Due to this design, the first doped subportion 10321 and the second doped portion 1033 are formed using the second gate electrode 107 as a mask, while the formation of the second active layer 106 is facilitated using the second gate electrode 107 as a mask and by the ion doping, so that the number of photomasks required to form the first active layer 103 is further reduced, and thus the number of photomasks required to form the array substrate 10 is reduced.

[0074] In some embodiments, the second active layer 106 comprises an amorphous phase to ensure the switching performance of the second transistor T2.

[0075] In some embodiments, the thickness of the second active layer 106 is smaller than the thickness of the first active layer 103, which helps to more easily form the first active layer 103 containing a crystalline phase during a thermal annealing process.

[0076] In some embodiments, the array substrate 10 further includes a second insulating layer 1043 and a third insulating layer 1044. The second insulating layer 1043 is located between the second active layer 106 and the second gate electrode 107. The third insulating layer 1044 covers the second gate electrode 107 and the second insulating layer 1043.

[0077] In some embodiments, the first transistor T1 and the second transistor T2 are connected in parallel to increase the mobility of the transistor consisting of the first transistor T1 and the second transistor T2.

[0078] The source electrode 1081 and the drain electrode 1082 are located on the side of the second gate electrode 107 facing away from the substrate 101. Both the source electrode 1081 and the drain electrode 1082 are located on the surface of the third insulating layer 1044 facing away from the substrate 101.

[0079] In some embodiments, the drain electrode 1082 is connected to the fourth doped section 1063 via the fifth via 10c, which is passed through the third insulating layer 1044 and the second insulating layer 1043. This cooperates with the connection of the drain electrode 1082 to the first doped subsection 10321 of the first doped section 1032 via a third via 10b, which is passed through the third insulating layer 1044, the second insulating layer 1043, and the first insulating layer 1042, thereby realizing a parallel connection of the first transistor T1 and the second transistor T2.

[0080] In some embodiments, the source electrode 1081 is connected to the third doped portion 1062 via the second via 10d. This cooperates with the connection of the third doped portion 1062 to the second doped portion 1033 via the first via 10a, such that the source electrode 1081 is connected to the second doped portion 1033 through the third doped portion 1062, thereby further reducing the wiring connecting the first transistor T1 to the second transistor T2, reducing the number of photomasks required to fabricate the wiring, and lowering the cost of fabricating the array substrate.

[0081] Reference is made to Fig. 2, which shows a schematic sectional view of an array substrate according to some further embodiments of the present application. Fig. The array substrate shown in Figure 2 is essentially similar to that shown in Fig. 1H, and the similarities will not be repeated. The differences include that the third doped portion 1062 is connected to the second doped portion 1033 through the first via 10a, and the fourth doped portion 1063 is connected to the first doped subportion 10321 via the fourth via 10e, that is, the first transistor T1 and the second transistor T2 are connected in parallel via the third doped portion 1062 and the fourth doped portion 1063 of the second active layer 106 to reduce the wiring required to connect the first transistor T1 and the second transistor T2 in parallel and to further reduce the number of photomasks required to fabricate the array substrate. Here, the fourth via 10e is passed through the first insulating layer 1042.

[0082] Reference is made to Fig. 3, which shows a schematic sectional view of an array substrate according to some embodiments of the present application. Fig. The array substrate shown in Figure 3 is essentially similar to that shown in Fig. 1H, and the similarities will not be repeated. Differences include that the drain electrode 1082 is connected to the fourth doped portion 1063 via the sixth via 10f, and that the fourth doped portion 1063 is connected to the first doped subportion 10321 via the fourth via 10e. Here, the sixth via 10f overlaps the fourth doped portion 1063 and is routed through the third insulating layer 1044 and the second insulating layer 1043, while the fourth via 10e overlaps the first doped subportion 10321 and is routed through the first insulating layer 1042.

[0083] It should be noted that the first transistor T1 and the second transistor T2 can also be connected in series.

[0084] With reference to Fig. 4 and Fig. 5, the present application also provides a display panel 30, wherein the display panel 30 comprises an array substrate 10 according to any of the above embodiments.

[0085] With reference to Fig. 4, the display panel 30 includes an array substrate 10 and a light-emitting element layer 201, wherein the light-emitting element layer 201 includes a light-emitting element 2011, wherein the light-emitting element 2011 is connected to at least one of the first transistor T1 and the second transistor T2. The light-emitting element 2011 includes at least one of, but is not limited to, an organic light-emitting diode, a quantum dot light-emitting diode, a micro-light-emitting diode, and a submillimeter light-emitting diode.

[0086] With reference to Fig. 5, the display panel 30 includes an array substrate 10, a counter substrate 202, and a liquid crystal layer 203, wherein the liquid crystal layer 203 is disposed between the array substrate 10 and the counter substrate 202.

[0087] The illustration of the above embodiments serves only to assist in understanding the technical solutions and core ideas of the present application. Those of ordinary skill in the art should understand that they may modify the technical solutions described in the above embodiments or substitute some of the technical features contained therein with equivalents; however, these modifications or substitutions do not cause the essence of the respective technical solutions to deviate from the scope of the technical solutions of the individual embodiments of the present application.

Claims

[1] Array substrate, characterized by that the array substrate includes: a substrate; and a first transistor arranged on the substrate and comprising: a first active layer located on the substrate and comprising a first channel portion, a first doped portion, and a second doped portion, the first doped portion and the second doped portion being respectively connected to both opposite ends of the first channel portion, the first doped portion comprising a first doped subportion and a second doped subportion, the second doped subportion being connected between the first channel portion and the first doped subportion, the second doped subportion having an ion doping concentration that is lower than the ion doping concentration of the first doped subportion, and the ion doping concentration of the first doped subportion being the same as that of the second doped portion; a first gate electrode located on one side of the first active layer and overlapping the first channel portion; and a source electrode and a drain electrode, wherein the source electrode is connected to the second doped section and the drain electrode is connected to the first doped subsection of the first doped section. [2] Array substrate according to claim 1, characterized by that the first gate electrode is located on a side of the first active layer facing away from the substrate; wherein the array substrate further comprises: a second transistor comprising: a second active layer, wherein at least a portion of the second active layer is located on a side of the first gate electrode facing away from the substrate, wherein the second active layer comprises a second channel portion, a third doped portion, and a fourth doped portion, wherein the third doped portion and the fourth doped portion are each connected to both opposite ends of the second channel portion, wherein the second channel portion overlaps the first channel portion and the second doped subportion, wherein the third doped portion overlaps the second doped portion, and wherein the fourth doped portion overlaps the first doped subportion; and a second gate electrode located on a side of the second active layer facing away from the substrate and overlapping the second channel portion. [3] Array substrate according to claim 2, characterized bythat the first transistor and the second transistor are connected in parallel. [4] Array substrate according to claim 2, characterized by that it further comprises a first insulating layer arranged between the first gate electrode and the second active layer, wherein the third doped section is connected to the second doped section via a first via passing through the first insulating layer. [5] Array substrate according to claim 4, characterized by that it further comprises a second insulating layer arranged between the second active layer and the second gate electrode, and a third insulating layer covering the second gate electrode, wherein the source electrode is located on the third insulating layer, and wherein the source electrode is connected to the third doped section via a second via passed through the second insulating layer and the third insulating layer. [6] Array substrate according to claim 5, characterized by that the drain electrode is located on the third insulating layer, wherein the drain electrode is connected to the first doped subsection via a third via which is passed through the first insulating layer, the second insulating layer and the third insulating layer. [7] Array substrate according to claim 6, characterized by that the fourth doped section is connected to the first doped subsection via a fourth via which is passed through the first insulating layer. [8] Array substrate according to claim 6, characterized by that the array substrate further comprises a fifth via passed through the second insulating layer and the third insulating layer, wherein the drain electrode is connected to the fourth doped section via the fifth via. [9] Array substrate according to claim 2, characterized bythat the thickness of the second active layer is smaller than the thickness of the first active layer. [10] Display panel, characterized by that the display panel comprises an array substrate according to one of claims 1 to 9.

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