Field-effect transistor with an electrode trench structure

Abstract

A field-effect transistor, FET (100), is proposed. The FET (100) comprises a semiconductor substrate (102) having a mesa (104) arranged between an electrode trench structure (106) along a first lateral direction (x). The FET (100) further comprises a trench contact (108) extending from a top surface (1041) of the mesa (104) into the mesa (104). A bottom of the trench contact (108) is located at a first vertical reference level (yref1). The mesa (104) comprises a source region (110) of a first conductivity type, a body structure (112) of a second conductivity type, and a drift region (114) of the first conductivity type. The drift region (114) forms a pn junction (116) with the body structure (112).The pn junction (116) has a minimum vertical distance (dmin) to the upper surface (1041) of the mesa (104) at a second vertical reference level (yref2) and a maximum vertical distance (dmax) to the upper surface (1041) of the mesa (104) at a third vertical reference level (yref3). At a fourth vertical reference level (yref4), a doping concentration (c) of the body structure (112) increases by a factor of 5 to 100 along the first lateral direction (x) from the electrode trench structure (106) to a center of the mesa (104). The fourth vertical reference level (yref4) is located between the second vertical reference level (yref2) and the first vertical reference level (yref1) at a first vertical distance (d1) from the first reference level (yref1).The first vertical distance (d1) is greater by a factor of 1.5 to 10 than a second vertical distance (d2) from the fourth vertical reference level (yref4) to the second vertical reference level (yref2).

Description

TECHNICAL FIELDThe present disclosure relates to a semiconductor device, and more particularly, to a field effect transistor, FET, having an electrode trench structure and a manufacturing method thereof.BACKGROUNDThe technological development of new generations of semiconductor devices, e.g., field effect transistors (FETs), aims to improve electrical device characteristics and reduce costs by shrinking device geometries. Although cost may be reduced by shrinking device geometries, a variety of tradeoffs and challenges must be met as device functionalities per unit area are increased. For example, a trade-off between area specific on-state resistance, R on xA, and reliability requirements affected by avalanche breakdown behavior, for example, requires design optimization. Reference is made by way of example to the disclosure content in the publications US 2014 / 0 264 564 A1, DE 102 50 175 B4 and U.S. Pat. No. 9 847 387 B2.Thus, there is a need for an improved field effect transistor.SUMMARYAn example of the present disclosure relates to a field effect transistor, FET. The FET includes a semiconductor substrate having a mesa disposed between an electrode trench structure along a first lateral direction. The FET further includes a trench contact extending into the mesa from a top surface of the mesa. A bottom of the trench contact is at a first vertical reference level. The mesa includes a source region of a first conductivity type, a body structure of a second conductivity type, and a drift region of the first conductivity type. The drift region forms a pn-junction with the body structure. The pn junction has a minimum vertical distance to the top surface of the mesa at a second vertical reference level and a maximum vertical distance to the top surface of the mesa at a third vertical reference level. At a fourth vertical reference level, a doping concentration of the body structure increases by a factor of 5 to 100 along the first lateral direction from the electrode trench structure to a center of the mesa. The fourth vertical reference level is located between the second vertical reference level and the first vertical reference level at a first vertical distance from the first reference level. The first vertical distance is greater by a factor of 1.5 to 10 than a second vertical distance from the fourth vertical reference level to the second vertical reference level.Another example of the present disclosure relates to a method of manufacturing a field effect transistor, FET. The method includes forming a mesa disposed in a semiconductor substrate between an electrode trench structure along a first lateral direction. The method further includes forming a trench contact extending into the mesa from a top surface of the mesa. A bottom of the trench contact is at a first vertical reference level. The method further comprises forming a source region of a first conductivity type in the mesa. The method further comprises forming a body structure of a second conductivity type in the mesa. The method further includes forming a drift region of the first conductivity type in the mesa. The drift region forms a pn-junction with the body structure. The pn junction has a minimum vertical distance to the top surface of the mesa at a second vertical reference level and a maximum vertical distance to the top surface of the mesa at a third vertical reference level. At a fourth vertical reference level, a doping concentration of the body structure increases by a factor of 5 to 100 along the first lateral direction from the electrode trench structure to a center of the mesa. The fourth vertical reference level is located between the second vertical reference level and the first vertical reference level at a first vertical distance from the first reference level. The first vertical distance is greater by a factor of 1.5 to 10 than a second vertical distance from the fourth vertical reference level to the second vertical reference level.Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGSThe accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate examples of FETs and together with the description serve to explain principles of the examples. Further examples are described in the following detailed description and claims. FIG. 1A is a schematic cross-sectional view for illustrating a configuration example of an FET including a trench contact and a body structure. FIG. 1B is a schematic diagram for illustrating an example doping concentration profile of the body structure along a lateral direction at a fourth vertical reference level. FIG. 2 is a schematic diagram for illustrating an example doping concentration profile of the body structure along a vertical direction in a center of the mesa. FIG. 3 is a schematic cross-sectional view for illustrating a configuration example of an FET including an electrode trench structure having a gate electrode and a field electrode. FIGS. 4A to 4D are schematic cross-sectional views for illustrating process features for manufacturing an FET including a trench contact and a body structure.DETAILED DESCRIPTIONIn the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration specific examples of FETs. It should be understood that other examples may be used and structural or logical changes may be made without departing from the scope of the present disclosure. For example, features illustrated or described for one example may be used in conjunction with other examples to provide yet another example. It is intended that the present disclosure encompass such modifications and variations. The examples are described using a specific language, which should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. Corresponding elements are denoted by the same reference numerals throughout the several drawings, unless otherwise indicated.The terms "have", "contain", "comprise", "have" and the like are open-ended, and the terms indicate the presence of the stated structures, elements or features, but do not exclude the presence of additional elements or features. The articles "a", "an", and "the / s" are intended to include both the plural and the singular, unless the context clearly indicates otherwise.The term "electrically connected" may describe a permanent low-ohmic connection between electrically connected elements, for example a direct contact between the relevant elements or a low-ohmic connection via a metal and / or heavily doped semiconductor material. The term "electrically coupled" may include that one or more intermediate element(s) configured for signal and / or power transmission may / may be connected between the electrically coupled elements, for example elements controllable to temporarily provide a low impedance connection in a first state and a high impedance electrical decoupling in a second state. An ohmic contact is a non-rectifying electrical junction.Ranges indicated for physical dimensions may include the limits. For example, a range for a parameter y reads from a to b as a≤y≤b. The same applies to ranges having a limit value such as "at most" and "at least.".The terms "on" and "over" are not to be interpreted as meaning only "directly on" and "directly over". Rather, when an element is positioned "on" or "over" another element (e.g., a layer "on" or "over" another layer or "on" or "over" a substrate), another component (e.g., another layer) may be positioned between the two elements (e.g., another layer may be positioned between a layer and a substrate when the layer is "on" or "over" the substrate).An example of the present disclosure relates to a field effect transistor, FET. The FET includes a semiconductor substrate having a mesa disposed between an electrode trench structure along a first lateral direction. The FET further includes a trench contact extending into the mesa from a top surface of the mesa. A bottom of the trench contact is at a first vertical reference level. The mesa includes a source region of a first conductivity type, a body structure of a second conductivity type, and a drift region of the first conductivity type. The drift region forms a pn-junction with the body structure. The pn junction has a minimum vertical distance to the top surface of the mesa at a second vertical reference level and a maximum vertical distance to the top surface of the mesa at a third vertical reference level. At a fourth vertical reference level, a doping concentration of the body structure may increase by a factor of 5 to 100 along the first lateral direction from the electrode trench structure to a center of the mesa. The fourth vertical reference level is located between the second vertical reference level and the first vertical reference level at a first vertical distance from the first reference level. The first vertical distance may be greater than a second vertical distance from the fourth vertical reference level to the second vertical reference level by a factor of 1.5 to 10.The first conductivity type may be an n-type and the second conductivity type may be a p-type. In this case, the FET is, for example, an n-channel FET. The first conductivity type may also be a p-type and the second conductivity type may be an n-type. In this case, the FET is, for example, a p-channel FET.For example, the FET may be a lateral FET. In a lateral FET, a load current flow direction is a lateral direction, and the source region and the drain region are spaced apart from each other along the lateral direction. For example, the lateral FET may be a lateral trench FET, such as a lateral trench metal oxide semiconductor field effect transistor, lateral trench MOSFET. The FET may also be a vertical FET. In a vertical FET, a load current flow direction is a vertical direction, and the source region and the drain region are spaced apart from each other along the vertical direction. For example, the source region may be electrically connected to a source electrode over a first surface of the semiconductor substrate and the drain region may be electrically coupled to a drain electrode over a second surface of the semiconductor substrate, the second surface being opposite the first surface.For example, the FET may be part of an integrated circuit or may be a discrete semiconductor device or a semiconductor module. For example, the FET may be monolithically implemented using mixed technology. Such mixed technologies may be used, for example, to form analog circuit blocks in a chip by the bipolar devices included in this technology for providing interfaces to digital systems and to form digital circuit blocks by the complementary metal oxide semiconductor (CMOS) devices included in this technology for providing signal processing and to form low, medium or high voltage or power blocks by field effect transistors included in this technology. Such mixed technologies are known, for example, as bipolar CMOS DMOS, BCD technologies or smart power technologies, SPT, and are used in a variety of application fields in the field of, for example, lighting, engine control, automotive electronics, power management for mobile devices, audio amplifiers, power supply, hard disks, printers. The FET can be part of a BCD or smart power chip in one of the above fields of application, for example.The semiconductor substrate may be based on various semiconductor materials, for example silicon (Si), silicon-on-insulator (SOI), silicon sapphire (SOS), silicon germanium, germanium, gallium arsenide, silicon carbide, gallium nitride or other compound semiconductor materials. The semiconductor substrate may be based on a semiconductor base substrate, for example a semiconductor wafer, and may include one or more epitaxial layers deposited thereon and / or may be rediluted.To realize a desired current carrying capacity, the FET may be designed by a plurality of transistor cells connected in parallel. The transistor cells connected in parallel can be, for example, transistor cells which are designed in the form of a strip or a strip segment. Of course, the transistor cells can also have any other shape, for example circular, elliptical, polygonal, such as hexagonal or octahedral. The transistor cells may be arranged in a transistor cell region of the semiconductor substrate. The transistor cell region may be an active region in which the source region of the FET is electrically connected to a source electrode. In the active region, a load current may enter or exit the semiconductor substrate of the FET, e.g. via contact plugs on the first surface of the semiconductor substrate.The semiconductor substrate may have a first surface, which may be a front surface or an upper surface of the semiconductor substrate. The first surface may be, for example, the surface on which the mesa with the source region is located. The second surface may be, for example, a back surface or a back surface of the semiconductor substrate. In vertical FETs, the second surface may be the surface on which the drain is located. The semiconductor substrate may be attached to a lead frame via the second surface, for example. Bonding pads may be disposed over the first surface of the semiconductor substrate and bonding wires may be bonded to the bonding pads, for example.The source region and the body structure may be electrically connected to a source electrode via the trench contact. The source electrode and the trench contact may be part of a wiring region over the first surface of the semiconductor substrate, for example. The wiring region may comprise one or more than one, e.g. two, three, four or even more wiring levels. Each wiring level may be formed by a single or a stack of conductive layers, e.g. metal layer(s). The wiring planes can be lithographically structured, for example. An interlayer dielectric structure may be disposed between stacked wiring planes. Contact plug(s) or contact line(s) may be formed in openings in the interlayer dielectric structure to electrically connect portions, e.g., metal lines or contact regions, of different wiring levels to each other. The trench contact may provide an electrical contact between an active area in the semiconductor substrate and the first wiring level, wherein the first wiring level is the wiring level closest to the first surface of the semiconductor substrate. The trench contact may comprise one or more conductive materials as well as adhesion and / or diffusion barrier materials / liners. The source electrode may be formed by one or more elements of the wiring region. Similarly, the FET may further include a drain electrode. Also, the drain electrode may be formed by one or more elements of the wiring region over the first surface for lateral FETs. For example, the source electrode and the drain electrode may comprise separate parts of a patterned first wiring level, e.g. a first metal layer. In some examples related to lateral FETs, the drain electrode may also be formed over the second surface of the semiconductor substrate. In this case, a drain region of the FET may be electrically connected to the drain electrode through a via or trench contact extending at least partially through the semiconductor substrate. In some examples related to vertical FETs, the drain electrode may be formed over the second surface of the semiconductor substrate.The drift region may extend from the mesa into a region of the semiconductor substrate below the electrode trench structure, for example. The blocking voltage of the FET may be adjusted, among other things, along a vertical direction perpendicular to the first surface by adjusting parameters of the drift region, e.g. vertical extension and / or doping profile. The drift region may convert into a highly doped drain region or into a buried layer region, for example, along the vertical direction. A doping concentration in the drift region may increase or decrease gradually or in steps with increasing distance to the first surface at least in regions of its vertical extension. According to other examples, the impurity concentration in the drift region may be approximately uniform in the vertical direction.The second vertical reference level may be at or near the electrode trench structure. The third vertical reference level may be in a central region or in the middle of the mesa with respect to the first lateral direction. A difference between the second vertical reference level and the third vertical reference level corresponds to a vertical extension of the pn junction in the mesa.The body structure of the configuration examples described herein refers to a pn junction between the body structure and the drift region having a vertical extension between the second vertical reference level and the third vertical reference level. A lower or lowest point of the pn junction is located in the central region of the mesa. This makes it possible to keep avalanche current, e.g. holes in the case of an n-channel FET, away from the sensitive channel region at the sidewalls of the electrode trench structure. Thereby, avalanche robustness and safe operating range can be improved.For example, the body structure may comprise a superposition of doping concentration profiles of at least a body region, a body contact region and a body gain region. The pn-junction at the third vertical reference level may coincide with an intersection along the vertical direction between a doping concentration profile of the body gain region and a doping concentration profile of the drift region. The body gain region of the body structure may thus be the part of the body structure that determines avalanche breakdown behavior with respect to the location of the hole avalanche current path for n-channel devices. The body region of the body structure may be the part of the body structure that determines the channel behavior, e.g. threshold voltage. The body contact region of the body structure may be the part of the body structure that determines the ohmic contact behavior to the trench contact, for example. By forming the body structure by the superposition of doping concentration profiles of at least the body region, the body contact region and the body gain region, the performance of the FET in terms of threshold voltage, avalanche robustness and ohmic contact behavior may be separately tuned. Moreover, in forming the body gain region (and the body contact region) by ion implantation of dopants through a bottom of the trench, a separate mask process for optimizing avalanche breakdown robustness is not required for the trench contact.For example, a maximum concentration of the doping concentration profile of the body contact region may be greater than a maximum concentration of the doping concentration profile of the body gain region by a factor of 5 to 200 or by a factor of 8 to 150. For example, dopants of the body contact region may be implanted at a higher dose but lower energy than dopants of the body gain region.For example, a maximum concentration of the doping concentration profile of the body gain region may be greater than a maximum concentration of the doping concentration profile of the body region by a factor of 5 to 200 or by a factor of 8 to 150. For example, dopants of the body gain region may be implanted at a higher dose than dopants of the body region.For example, a doping concentration of the body structure at the first vertical reference level at or near the electrode trench structure may be predominantly determined by the doping concentration of the body region. This makes it possible to adjust the channel behavior, e.g. threshold voltage, of the FET by the doping concentration profile of the body region, which predominates in the doping concentration of the body structure in the channel region.For example, a doping concentration of the body structure at the first vertical reference level at or near a bottom of the trench contact may be predominantly (e.g. by more than 50%) determined by the doping concentration of the body contact region.For example, a doping concentration of the body structure at or near the third vertical reference level may be predominantly determined by the doping concentration of the body gain region.For example, an absolute difference between the second vertical reference level and the third vertical reference level may have a value in a range from 30% to 150% or from 50% to 130% of an absolute difference between the first vertical reference level and the second vertical reference level. This may enable, for example, an advantageous breakdown behavior of the FET.For example, the electrode trench structure may include an electrode structure and a dielectric structure. The electrode structure may include a gate electrode and a field electrode. Apart from a single field electrode in the trench, a plurality of field electrodes may also be arranged in the trench, e.g. stacked one above the other along the vertical direction, wherein a part of the dielectric structure is arranged between each pair of field electrodes.The dielectric structure may include, for example, a gate dielectric portion that electrically isolates the gate electrode from a surrounding portion of the semiconductor substrate. For example, the gate dielectric may be an insulating material, such as an oxide, e.g., SiO 2, a nitride, e.g., Si 3 N 4, a high-k dielectric, or a low-k dielectric, or any combination thereof. The dielectric structure may further include a field dielectric that electrically isolates the field electrode(s) from a surrounding portion of the semiconductor substrate. For example, the field dielectric may be an insulating material such as an oxide, e.g., SiO 2, a nitride, e.g., Si 3 N 4, a high-k dielectric, or a low-k dielectric, or any combination thereof. For example, the field dielectric may be formed as or comprise a thermal oxide and / or a deposited and annealed oxide. For example, the field dielectric may have a greater thickness than the gate dielectric. The gate electrode and field electrode(s) may be formed of one or more conductive materials, e.g., metal, metal silicide, metal compound, highly doped semiconductor material, such as highly doped polycrystalline silicon. For example, the gate electrode may be a single layer, e.g. a highly doped polycrystalline layer, or a stack of layers.For example, a portion of the dielectric structure may be disposed between the gate electrode and the field electrode. In the case of an n-channel FET, this may allow to improve the electric field property in order to keep holes generated during an avalanche breakdown event, for example, away from the channel region at the gate electrode.For example, the maximum vertical distance may be greater than a vertical distance from a bottom of the gate electrode to the top surface of the mesa. In the case of an n-channel FET, holes generated during an avalanche breakdown event may be kept away from the channel region / gate electrode / gate dielectric, for example.For example, the maximum vertical distance may be less than a vertical distance from a top surface of the field electrode to the top surface of the mesa.For example, the FET may be a vertical FET having a source electrode over a first surface of the semiconductor substrate. The vertical FET may further include a drain electrode over a second surface of the semiconductor substrate, the second surface opposing the first surface.Details regarding the structure or function or technical utility of features described above with respect to an FET apply equally to the example methods described herein.The specification and drawings merely illustrate the principles of the disclosure. Furthermore, all examples listed herein are expressly intended to be expressly for purposes of illustration only in order to assist the reader in understanding the principles of the disclosure and the concepts contributed by the inventor(s) to further developing the technique.It should be understood that the disclosure of multiple steps, processes, operations, steps, or functions disclosed in the specification or claims may not be construed as being in the specific order unless expressly or implicitly stated otherwise, e.g., by terms such as "thereafter," for example, for technical reasons. Therefore, the disclosure of multiple steps or functions does not limit them to a particular order unless these steps or functions are not interchangeable for technical reasons. Further, in some examples, a single step, function, process, operation, or step may include or be broken into multiple substeps, functions, processes, operations, or steps. Such substeps may be included and form part of the disclosure of this single step unless expressly excluded. Processing a semiconductor substrate wafer to produce the FET may comprise one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more examples described above or below.An example of the present disclosure relates to a method of manufacturing a field effect transistor, FET. The method includes forming a mesa disposed in a semiconductor substrate between an electrode trench structure along a first lateral direction. The method further includes forming a trench contact extending into the mesa from a top surface of the mesa. A bottom of the trench contact is at a first vertical reference level. The method further comprises forming a source region of a first conductivity type in the mesa. The method further comprises forming a body structure of a second conductivity type in the mesa. The method further includes forming a drift region of the first conductivity type in the mesa. The drift region forms a pn-junction with the body structure. The pn junction has a minimum vertical distance to the top surface of the mesa at a second vertical reference level and a maximum vertical distance to the top surface of the mesa at a third vertical reference level. At a fourth vertical reference level, a doping concentration of the body structure may increase by a factor of 5 to 100 along the first lateral direction from the electrode trench structure to a center of the mesa. The fourth vertical reference level is located between the second vertical reference level and the first vertical reference level at a first vertical distance from the first reference level. The first vertical distance may be greater than a second vertical distance from the fourth vertical reference level to the second vertical reference level by a factor of 1.5 to 10.For example, forming the body structure may comprise forming a superposition of doping concentration profiles of at least a body region, a body contact region and a body gain region. The pn-junction at the third vertical reference level may coincide with an intersection along the vertical direction between a doping concentration profile of the body gain region and a doping concentration profile of the drift region. For example, the doping concentration profile of the body gain region may extend from the upper surface deeper into the mesa region than the doping concentration profile of the body region. The doping concentration profile of the body region may extend from the upper surface deeper into the mesa region than the doping concentration profile of the body contact region.For example, the body region may be formed by ion implantation of dopants before forming the trench contact, for example.For example, forming the trench contact may include forming a trench, e.g., by an etching process using an etch mask. Thereafter, forming the body contact region may include introducing dopants into the semiconductor substrate through a bottom of the trench by a first ion implantation process. Forming the body gain region may include introducing dopants into the semiconductor substrate through a bottom of the trench by a second ion implantation process. The second ion implantation process may be performed after or before the first ion implantation process. The electrical activation of the dopants of the body contact region and the dopants of the body gain region may be performed by a common thermal annealing process. In other words, the implanted dopants may be activated with one and the same thermal budget.For example, an ion implantation energy of the first ion implantation process may be smaller than an ion implantation energy of the second ion implantation process. For example, the ion implantation energy of the first ion implantation process may range from 3% to 25% of an ion implantation energy of the second ion implantation process when the same dopant species, e.g., BF 2, is used.The method of any one of the three preceding claims, wherein an ion implantation dose of the first ion implantation process may be greater than an ion implantation dose of the second ion implantation process.The examples and features described above and below may be combined.In the following, further examples of field effect transistors, FETs, are explained in connection with the attached drawings. Functional and structural details described with respect to the above examples apply equally to the example embodiments illustrated in the figures and further described below. In the illustrated examples, the first conductivity is an n-type and the second conductivity type is a p-type for an n-channel FET. However, the first conductivity type may be a p-type and the second conductivity type may be an n-type for a p-channel FET.FIG. 1A schematically and exemplarily shows a cross-sectional view of a portion of a transistor cell of an FET 100.The FET 100 includes a semiconductor substrate 102. For example, the semiconductor substrate 102 may include a base substrate and an n-doped semiconductor layer on the base substrate, e.g., an epitaxial layer formed by a layer deposition process.The semiconductor substrate 102 comprises a mesa 104 arranged between an electrode trench structure 106 along a first lateral direction x. The mesa 104 may be defined by a masked etching process, for example, when forming trenches of the electrode trench structure 106.An electrical contact to the semiconductor substrate 102 is provided by a trench contact 108 extending into the mesa 104 from a top surface 1041 of the mesa 104. At a first vertical reference level yref 1, a bottom of the trench contact 108 is positioned.An n +- doped source region 110 is formed in the mesa 104. The n +- doped source region 110 laterally adjoins the electrode trench structure 106 on one side and further adjoins the trench contact 108 on the other side.A p-doped body structure 112 is formed under the source region 110. The p-doped body structure 112 is based on a superposition of p-type doping concentration profiles, e.g. a superposition of a doping concentration profile defining a body region 1121, a doping concentration profile defining a body contact region 1122, and a doping concentration profile defining a body gain region 1123.An n-doped drift region 114 forms a pn-junction 116 with the body structure 112 in the mesa 104. The pn-junction 116 has a minimum vertical distance dminto the top surface 1041of the mesa 104 at a second vertical reference level yref2. The minimum vertical distance dminof the pn junction 116 is at or near a sidewall of the electrode trench structure 106. The pn-junction 116 further has a maximum vertical distance dmaxto the top surface 1041of the mesa 104 at a third vertical reference level yref3. The maximum vertical distance dmax of the pn junction 116 is at or near a center of the mesa 104 along the first lateral direction x.Referring to FIG. 1A and the schematic diagram of FIG. 1B, an example doping concentration c of the body structure 112 along the first lateral direction x with respect to a fourth vertical reference level yref 4 is illustrated. The first vertical distance d 1 is greater by a factor of 1.5 to 10 than a second vertical distance d 2 from the fourth vertical reference level yref 4 to the second vertical reference level yref 2. At the fourth vertical reference level yref4, the doping concentration c of the body structure 112 increases by a factor of 5 to 100 along the first lateral direction x from the electrode trench structure 106 to a center of the mesa 104. As schematically illustrated in FIG. 1B, the doping concentration c of the body structure 112 at the second vertical reference level yref 2 at or near the electrode trench structure 106 is predominantly determined by a doping concentration c 1 of the body region 1121, and the doping concentration c of the body structure 112 at or near the third vertical reference level yref 3 is predominantly determined by a doping concentration c 3 of the body gain region 1123. Referring to FIG. 1A, an absolute difference between the second vertical reference level yref 2 and the third vertical reference level yref 3 may have a value in a range of 30% to 150% of an absolute difference between the first vertical reference level yref 1 and the second vertical reference level yref 2.Referring to FIG. 1A and the schematic diagram of FIG. 2, an example doping concentration c of the body structure 112 along the vertical direction y with respect to a center of the mesa 102 is illustrated. The pn-junction 116 at the third vertical reference level yref 3 is at or near an intersection along the vertical direction y between a doping concentration profile c 3 of the body gain region 1123 and a doping concentration profile c 4 of the drift region 114. The doping concentration c of the body structure 112 at the first vertical reference level yref 1 at or near a bottom of the trench contact 108 is predominantly determined by the doping concentration c 2 of the body contact region 1122.A maximum concentration cmax 2 of the doping concentration profile c 2 of the body contact region 1122 may be greater than a maximum concentration cmax 3 of the doping concentration profile c 3 of the body gain region 1122 by a factor of 5 to 200.Sub-regions of the body structure 112 are called similar to the doping concentration profile, e.g. "body region" for the "body concentration profile" in those parts of the body structure 112 in which a value of the respective doping concentration profile is greater than a value of each of the other doping concentration profiles of the body structure 112. The dopant concentration profile is determined by the manufacturing process, e.g., ion implantation energy, dose, and dopant species. For example, a sub-region of the body structure 112 may be referred to as body contact region 1122, although dopants of the doping concentration profile c 3 of the body gain region 1123 or dopants of the doping concentration profile c 1 of the body region 1121 are also present in the body contact region 1122. However, in the body contact region 1122, a concentration of dopants of the doping concentration profile c 2 (body contact region) is greater than a concentration of dopants of the doping concentration profile c 1 (body region) or c 3 (body gain region).Referring to FIG. 2, a maximum concentration cmax 2 of the doping concentration profile c 2 of the body contact region 1122 may be greater than a maximum concentration cmax 3 of the doping concentration profile c 3 of the body gain region 1122 by a factor of 5 to 200.FIG. 3 schematically and exemplarily shows a cross-sectional view of a part of a transistor cell of another configuration example of an FET 100.The electrode trench structure 106 of the FET 100 includes an electrode structure 118 and a dielectric structure 120. The electrode structure 118 includes a gate electrode 1181 and a field electrode 1182. A portion of the dielectric structure 120 is disposed between the gate electrode 1181 and the field electrode 1182.The FET 100 further includes a source electrode S over the top surface 1041 of the mesa 104 and over the electrode trench structure 106. The source electrode S is electrically insulated from the gate electrode 1181 by an interlayer dielectric 122 disposed between the gate electrode 1181 and the source electrode S.In the configuration example illustrated in FIG. 3, the maximum vertical distance dmax is greater than a vertical distance dg from a bottom of the gate electrode 1181 to the top surface 1041 of the mesa 104. Moreover, the maximum vertical distance dmax is smaller than a vertical distance df from a top surface of the field electrode 1182 to the top surface 1041 of the mesa 104. In some other configuration examples, the maximum vertical distance dmax may also be equal to or greater than the vertical distance df from a top surface of the field electrode 1182 to the top surface 1041 of the mesa 104.The schematic cross-sectional views of FIGS. 4A through 4D illustrate process features for fabricating FETs 100 as described herein.Referring to FIG. 4A, the body region 1121 of the body structure 112 and a source layer 1101 are formed prior to forming a trench contact, e.g. by ion implantation of dopants.Referring to FIG. 4B, a trench 1081 of the trench contact is formed by an etching process using a mask 124 after forming the body region 1121 and after forming the source layer 1101. The etching process patterns the source layer 1101 into the source regions 110.Referring to FIG. 4C, after forming the trench 1081, dopants are introduced into the semiconductor substrate 102 through a bottom of the trench 1081 by a first ion implantation process I 1 to form the body contact region 1122.Referring to FIG. 4D, further dopants are introduced into the semiconductor substrate 102 through a bottom of the trench 1081 by a second ion implantation process I 2 to form the body gain region 1123. The process illustrated in FIG. 4C may also be performed after the process illustrated in FIG. 4D. An ion implantation energy of the first ion implantation process I 1 may be smaller than an ion implantation energy of the second ion implantation process I 2, e.g., for a common dopant type such as boron. An ion implantation dose of the first ion implantation process may be greater than an ion implantation dose of the second ion implantation process, e.g., for a common dopant type such as boron.The aspects and features mentioned and described together with one or more of the examples and figures described above can also be combined with one or more of the other examples in order to replace a similar feature of the other example or in order to additionally introduce the feature into the other example.

Claims

A field effect transistor, FET (100), comprising: a semiconductor substrate (102) having a mesa (104) arranged between an electrode trench structure (106) along a first lateral direction (x); a trench contact (108) extending into the mesa (104) from an upper surface (1041) of the mesa (104), wherein a bottom of the trench contact (108) is at a first vertical reference level (yref1), and the mesa (104) comprises: a source region (110) of a first conductivity type; a body structure (112) of a second conductivity type; a drift region (114) of the first conductivity type, wherein the drift region (114) forms a pn-junction (116) with the body structure (112), wherein the pn-junction (116) has a minimum vertical distance (dmin) to the top surface (1041) of the mesa (104) at a second vertical reference level (yref2) and a maximum vertical distance (dmax) to the top surface (1041) of the mesa (104) at a third vertical reference level (yref3); and wherein, at a fourth vertical reference level (yref4), a doping concentration (c) of the body structure (112) increases by a factor of 5 to 100 along the first lateral direction (x) from the electrode trench structure (106) to a center of the mesa (104), wherein the fourth vertical reference level (yref4) is located between the second vertical reference level (yref2) and the first vertical reference level (yref1) at a first vertical distance (d1) from the first reference level (yref1), wherein the first vertical distance (d1) is greater by a factor of 1.5 to 10 than a second vertical distance (d2) from the fourth vertical reference level (yref4) to the second vertical reference level (yref2).The FET (100) according to the preceding claim, wherein the body structure (112) comprises a superposition of doping concentration profiles (c1, c2, c3) of at least a body region (1121), a body contact region (1122) and a body gain region (1123), and the pn junction (116) at the third vertical reference level (yref3) coincides with an intersection along the vertical direction (y) between a doping concentration profile (c3) of the body gain region (1123) and a doping concentration profile (c4) of the drift region (114).The FET (100) according to the preceding claim, wherein a maximum concentration (cmax2) of the doping concentration profile (c2) of the body contact region (1122) is greater than a maximum concentration (cmax3) of the doping concentration profile (c3) of the body gain region (1123) by a factor of 5 to 200.The FET (100) according to any of the two preceding claims, wherein a maximum concentration (cmax3) of the doping concentration profile (c3) of the body gain region (1123) is greater than a maximum concentration of the doping concentration profile of the body region by a factor of 5 to 200.The FET (100) according to any of the three preceding claims, wherein a doping concentration (c) of the body structure (112) at the second vertical reference level (yref2) at or near the electrode trench structure (106) is predominantly determined by the doping concentration (c1) of the body region (1121).The FET (100) of any of the four preceding claims, wherein a doping concentration of the body structure (112) at the first vertical reference level (yref1) at or near a bottom of the trench contact (108) is predominantly determined by the doping concentration (c2) of the body contact region (1122).The FET (100) according to any of the five preceding claims, wherein a doping concentration (c) of the body structure (112) at or near the third vertical reference level (yref3) is predominantly determined by the doping concentration (c3) of the body gain region (1123).The FET (100) of any preceding claim, wherein an absolute difference between the second vertical reference level (yref2) and the third vertical reference level (yref3) has a value in a range of 30% to 150% of an absolute difference between the first vertical reference level (yref1) and the second vertical reference level (yref2).The FET (100) of any preceding claim, wherein the electrode trench structure (106) comprises an electrode structure (118) and a dielectric structure (120), wherein the electrode structure (118) comprises a gate electrode (1181) and a field electrode (1182).The FET (100) of the preceding claim, wherein a portion of the dielectric structure (120) is disposed between the gate electrode (1181) and the field electrode (1182).The FET (100) of the preceding claim, wherein the maximum vertical distance (dmax) is greater than a vertical distance from a bottom of the gate electrode (1181) to the top surface (1041) of the mesa (104).The FET (100) of the preceding claim, wherein the maximum vertical distance (dmax) is less than a vertical distance from a top surface of the field electrode (1182) to the top surface (1041) of the mesa (104).The FET (100) of any preceding claim, wherein the FET (100) is a vertical FET having a source electrode (S) over a first surface of the semiconductor substrate (102) and a drain electrode over a second surface of the semiconductor substrate (102), the second surface opposing the first surface.A method of manufacturing a field effect transistor, FET (100), the method comprising: forming a mesa (104) arranged in a semiconductor substrate (102) between an electrode trench structure (106) along a first lateral direction (x); forming a trench contact (108) extending into the mesa (104) from a top surface (1041) of the mesa (104), wherein a bottom of the trench contact (108) is at a first vertical reference level (yref1); and wherein the method further comprises: forming a source region (110) of a first conductivity type in the mesa; forming a body structure (112) of a second conductivity type in the mesa; forming a drift region (114) of the first conductivity type in the mesa, the drift region (114) forming a pn-junction (116) with the body structure (112), the pn-junction (116) having a minimum vertical distance (dmin) to the top surface (1041) of the mesa (104) at a second vertical reference level (yref2) and a maximum vertical distance (dmax) to the top surface (1041) of the mesa (104) at a third vertical reference level (yref3); and wherein, at a fourth vertical reference level (yref4), a doping concentration (c) of the body structure (112) increases by a factor of 5 to 100 along the first lateral direction (x) from the electrode trench structure (106) to a center of the mesa (104), wherein the fourth vertical reference level (yref4) is located between the second vertical reference level (yref2) and the first vertical reference level (yref1) at a first vertical distance (d1) from the first reference level (yref1), wherein the first vertical distance (d1) is greater by a factor of 1.5 to 10 than a second vertical distance (d2) from the fourth vertical reference level (yref4) to the second vertical reference level (yref2).The method according to the preceding claim, wherein forming the body structure (112) comprises forming a superposition of doping concentration profiles (c1, c2, c3) of at least a body region (1121), a body contact region (1122) and a body gain region (1123), and the pn junction (116) at the third vertical reference level (yref3) coincides with an intersection along the vertical direction (y) between a doping concentration profile (c3) of the body gain region (1223) and a doping concentration profile (c4) of the drift region (114).The method of the preceding claim, wherein the body region (1121) is formed before forming the trench contact (108).The method of any of the two preceding claims, wherein forming the trench contact (108) comprises forming a trench; and thereafter forming the body contact region (1122) comprises introducing dopants into the semiconductor substrate (102) through a bottom of the trench by a first ion implantation process; and forming the body gain region (1123) comprises introducing dopants into the semiconductor substrate (102) through a bottom of the trench by a second ion implantation process.The method according to the preceding claim, wherein an ion implantation energy of the first ion implantation process is smaller than an ion implantation energy of the second ion implantation process.The method of any one of the three preceding claims, wherein an ion implantation dose of the first ion implantation process is greater than an ion implantation dose of the second ion implantation process.

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