Circuit arrangement for converting a digital signal into an analog signal

Abstract

Circuit arrangement (100, 200, 300) for converting a digital signal into an analog signal, with: a first digitally controllable generator (V1) to provide a first digital signal; a second digitally controllable generator (D1, V2) to provide a second digital signal; wherein a circuit node (K1, K2) of the circuit arrangement (100, 200, 300) is electrically coupled to an output terminal of the first digitally controllable generator by means of a first coupling impedance (R1); and wherein the circuit node (K1, K2) is coupled to an output terminal of the second digitally controllable generator (D1, V2) by means of a second coupling impedance (R2); wherein the circuit arrangement comprises a plurality of digitally controllable generators (V52, V53, V54, V55) which are each electrically coupled to the circuit node (K1, K2, K3) by means of a respective coupling impedance (R52, R53, R54, R55), wherein the multiple digitally controllable generators (V52, V53, V54, V55) each provide a pulse-width modulated signal, and wherein the respective digitally controllable generators (V52, V53, V54, V55) are configured such that the respective pulse-width modulated signals have a clock shift relative to each other of 360 degrees divided by a number of the multitude of digitally controllable generators; and a filter circuit (C1, C32) coupled to the circuit node (K1, K2) to provide the analog signal; wherein the first digitally controllable generator (V1) and the second digitally controllable generator (D1, V2) are coupled such that there is a fixed phase relationship between the first digital signal and the second digital signal in order to achieve the lowest possible residual ripple of the analog signal with the circuit arrangement (100, 200, 300).

Description

background

[0001] Circuit arrangements that generate an analog signal from a digital signal, or digital-to-analog converters (DACs), can be implemented using different concepts. For example, with a voltage divider or an R / 2R network, or based on a pulse-width modulation signal (PWM-DAC).

[0002] Patent US 4,931,751A, in its abstract, describes a device with multi-bit sampling of digital information for generating a pulse-width modulated signal, wherein the device comprises: a first signal matching detector that responds to a first subset of the multi-bit sampling to generate a first signal that can transition between a first and a second logical state; a second signal matching detector that responds to a second subset of the multi-bit sampling to generate a second signal that can transition between the first and the second logical state;and a voltage summing circuit for generating a first voltage that is essentially proportional to a magnitude of the first signal in the first logic state or in the second logic state, and for generating a second voltage that is essentially proportional to a magnitude of the second signal in the first logic state or in the second logic state, and for generating an output voltage that is essentially proportional to a sum of the first voltage and the second voltage.

[0003] Patent US 6,072,340A describes, in its abstract, a signal-shaping circuit for shaping amplitude-shifted digital pulses of a digital data stream. The digital data stream consists of a multitude of symbols, from which the signal-shaping circuit generates an output signal with sinusoidally shaped transition regions between logic-level transitions of the digital data stream. The signal-shaping circuit includes an input line that receives each of the digital pulses of the digital data stream. A delay circuit receives each of the digital pulses of the digital data stream at the input line and, after a predefined time delay, outputs delayed digital pulses corresponding to each of the digital pulses received at the input line.A linear-response oscillator filter circuit receives each of the digital pulses of the digital data stream supplied by the input line and each of the digital pulses supplied at the output of the delay circuit. The oscillator filter circuit has a period approximately equal to or less than twice the symbol period of the digital data stream, which in turn determines the value of the predefined delay. Specifically, the pre-delay of the delay circuit is approximately half the period.

[0004] German patent application DE 3427852 A1 describes, in its abstract, a digital-to-analog converter suitable, among other things, for use in a television tuning system to convert the bits of a digital word into a corresponding tuning voltage. It comprises a first digital-to-dual-rate converter that responds to a group of the most significant bits of the digital word to generate a first pulse signal with a stepwise variable duty cycle, and a second digital-to-dual-rate converter that responds to a group of the next lowest bits of the digital word to generate a second pulse signal with a stepwise variable duty cycle. The amplitudes of the first and second pulse signals are weighted differently, for example, by means of resistors dimensioned with a normal tolerance (±10%), so that the maximum DC average of the second signal is greater than a single partial step of the DC average of the first signal.The weighted signals are combined and filtered in a low-pass filter to obtain the tuning voltage. Disclosure of the invention

[0005] Digital potentiometers have the disadvantages of insufficient linearity due to unavoidable resistance tolerances, low resolution due to the resulting high number of resistors required for high resolution, and electrical losses resulting from the current through the resistors. However, digital potentiometers do not require low-pass filtering.

[0006] R / 2R networks also have the disadvantage of low linearity and electrical losses, based on the current through the resistors. Low-pass filtering is not necessary here either.

[0007] PWM DACs, i.e., digital-to-analog converters based on a pulse-width modulated signal, can achieve high resolution with very good linearity and have low power loss. However, the rate of change of the output signal is limited by low-pass filtering.

[0008] The disadvantages of the PWM DAC could be mitigated by increasing the cutoff frequency of the low-pass filter while simultaneously increasing the clock frequency f. However, a higher clock frequency of the PWM signal would necessitate a higher operating frequency of the microcontroller, which can lead to increased current consumption and greater electromagnetic interference.

[0009] According to aspects of the invention, a circuit arrangement for converting a digital signal into an analog signal, an integrated circuit comprising the circuit arrangement, and a use of the circuit arrangement according to the features of the independent claims are proposed. Advantageous embodiments are the subject of the dependent claims and the following description.

[0010] According to aspects of the invention, a circuit arrangement for converting a digital signal into an analog signal is proposed. This circuit arrangement comprises a first digitally controllable generator for providing a first digital signal and a second digitally controllable generator for providing a second digital signal.

[0011] A circuit node of the circuit arrangement is electrically coupled to an output terminal of the first digitally controllable generator by means of a first coupling impedance.

[0012] The circuit node is coupled to an output terminal of the second digitally controllable generator via a second coupling impedance. A filter circuit of the circuit arrangement is coupled to the circuit node to provide the analog signal. An output terminal of the circuit arrangement can be an output terminal of the filter circuit. An input terminal can be a digital signal that controls the first digitally controllable generator and / or the second digitally controllable generator.

[0013] Based on the coupling of the two digitally controllable generators, which is determined by the network of the first and second coupling impedances, the two generators can be considered to be connected in series, similar to a star connection in a three-phase power grid. A series-connected circuit of electronic components can differ from both a parallel and a series connection of these electronic components. The coupling impedances of the circuit arrangement can be different and / or have different values. This allows for different weighting of the digital signals from the respective generators.

[0014] Partial voltages in the circuit arrangement with at least two digitally controllable generators can be determined by virtually short-circuiting all but one voltage source and then adding all partial voltages, taking their sign into account.

[0015] A digital signal can be a signal that can have a first value or a second value at different times. Such a digital signal can be, for example, a voltage signal or a current signal. The change between the two values ​​can be controlled by a clock signal, particularly a periodic one, in order to synchronize different digital signals over time.

[0016] A digitally controllable generator for providing a digital signal can be configured to provide a signal based on a control signal, which can be digital in particular, and which, based on the control signal, alternatively provides a first or a second signal value. The signal provided by the generator can be a periodic signal with a clock frequency, and the digitally controllable generator can be configured to modify the periodic signal based on the control signal. In particular, the digitally controllable generator can be configured to provide a pulse-width modulated voltage with digital signal values ​​at a clock frequency, wherein a duty cycle between a first digital signal value, such as a 0 signal, and a second digital signal value, such as a 1 signal, can be set by means of the control signal. That is to say,In other words, the control signal allows the on-time of the periodic digital signal to be selected.

[0017] Such a digitally controllable generator can have a microcontroller with a fixed operating frequency, which can provide a pulse width modulated (PWM) signal based on an integrated counter and an integrated timer.

[0018] The filter circuit can be designed and configured to filter, analogously or digitally, a signal resulting from the two generators, which is based on the network of coupling impedances and is applied to the circuit node, in particular to reduce ripple in the resulting analog signal.

[0019] The respective coupling impedance can, for example, have a resistance; alternatively or additionally, the coupling impedance can have at least a capacitance and / or at least an inductance and / or other active or passive switching elements.

[0020] Advantageously, such a circuit arrangement can be used to provide an analog setpoint for a current regulator in a 4...20 mA two-wire field device with a resolution of 16 bits. For example, to reduce the required operating current of a microcontroller, especially the respective generator, an operating frequency of 6553600 Hz can be selected. A timer of the microcontroller can output a PWM signal with a fundamental frequency or clock frequency of f = 100 Hz at a duty cycle resolution of 16 bits, corresponding to 1 / 65536. The maximum tolerable ripple of the current then yields the minimum possible time constant of the filter circuit, which can be implemented as a low-pass filter. This filter circuit, or...This low-pass filter limits the speed at which a voltage and / or current can respond to a change in measured value, corresponding to a digital input signal. A corresponding second digitally controlled generator can be constructed in the same way.

[0021] Advantageously, this circuit arrangement avoids the use of a fast R2R DAC, which can be integrated into a microcontroller, in order to avoid the resulting higher power consumption and costs.

[0022] Advantageously, the circuit arrangement described here allows for fast digital-to-analog conversion by superimposing or chaining two or more digital and / or PWM signals. For example, in one of the circuit arrangements, a pulse-width modulated digital signal can be chained with a simple, switchable digital signal. If the duty cycle resolution of the pulse-width modulated signal is 15 bits, this circuit arrangement, combined with the digital signal (1 bit), results in a resolution of 16 bits. By reducing the duty cycle resolution, the clock frequency of the pulse-width modulated signal can be increased accordingly while maintaining the same operating frequency of the microcontroller.

[0023] If the coupling impedances are chosen to be equal, only half of the ripple of the pulse-width modulated signal is included in the resulting signal at the circuit node, so that for the same residual ripple of the analog signal, the time constant of the filter circuit can be reduced to a quarter.

[0024] This results in a fourfold change rate of the analog signal of the circuit arrangement.

[0025] According to one aspect, it is proposed that the circuit arrangement is set up to digitally control the first digitally controllable generator and the second digitally controllable generator in such a way that the first digital signal and the second digital signal are chained together at the first node K1, based on the network of first and second coupling impedance, to form a resulting analog signal.

[0026] Advantageously, the circuit arrangement, in particular the chaining of the first digital signal with the second digital signal, or the coupling of the first digitally controllable generator with the second digitally controllable generator by means of the first coupling impedance and the second coupling impedance, results in a resolution of the analog signal which, based on an original resolution of the respective generator, with each further generator, which is electrically coupled to the circuit node with a coupling impedance, increases the resolution of the analog signal by 1 bit.

[0027] Advantageously, in a circuit arrangement with a multitude of such coupled generators, it can be achieved, additionally or alternatively, that with a further coupled generator, the resolution of each individual generator in the multitude is reduced by 1 bit, while the overall resolution of the output signal remains the same, thus allowing the clock frequency of the individual generators to be increased. The cutoff frequency of the output filter can then be increased, so that, with the same output signal ripple, the response time of the circuit arrangement to changes in the input signal can be reduced.

[0028] According to one aspect, it is proposed that the first digitally controllable generator and the second digitally controllable generator are coupled in such a way that there is a fixed phase relationship between the first digital signal and the second digital signal.

[0029] The fixed phase relationship between the first digital signal and the second digital signal can be based on a phase coupling of the first and second generators. This fixed phase relationship can mean that the respective phases of a plurality of periodic signals, which are particularly digital signals, are coupled, and a phase angle may exist between the respective periodic signals.

[0030] According to one aspect, it is proposed that the first digitally controllable generator is configured to generate a first digital signal that is pulse-width modulated at a first clock rate, or that the first digital signal consists of the first pulse-width modulated signal at the first clock rate. The first digitally controllable generator can then be configured to change the first clock rate of the pulse-width modulated digital signal by means of a first control signal.

[0031] According to one aspect, it is proposed that the second digitally controllable generator is configured to generate a second digital signal pulse-width modulated at a second clock rate, or that the second digital signal consists of the second pulse-width modulated signal at the second clock rate. The second digitally controllable generator can be configured to change the second clock rate of the pulse-width modulated digital signal by means of a second control signal. A combination of the first and second control signals can be the digital input signal of the circuit arrangement. The first control signal can be the same as or different from the second control signal.

[0032] The first clock rate of the first generator of the circuit arrangement can be the same or different from the second clock rate of the second generator of the circuit arrangement.

[0033] The ripple of a pulse-width modulated signal, generated using a low-pass filter, reaches its maximum at a duty cycle of 50% and its minima at 0% and 100%, as the latter two represent static signals. Based on the chaining of the digital signals according to the circuit arrangement, the filter time constant can be further reduced, while maintaining the residual ripple of the analog signal, by adding further generators coupled in a chained circuit.

[0034] To potentially reduce the filter time constant and thus the rise time of the analog signal, the number of coupled generators in the circuit arrangement has a quadratic effect. Two generators reduce the filter time constant to a quarter, three generators to a ninth, four generators to a sixteenth, and so on. The respective digital signals of the number n of generators can be phase-shifted relative to each other by 360° / n to achieve the lowest possible ripple.

[0035] According to one aspect, it is proposed that the first clock rate of the first digitally controllable generator is equal to the second clock rate of the second digitally controllable generator, or that the second clock rate of the second digitally controllable generator is an integer multiple of the first clock rate.

[0036] According to one aspect, it is proposed that the circuit arrangement, in particular with a first and a second generator, is set up such that the first digital signal is phase-shifted by 180 degrees relative to the second digital signal.

[0037] Advantageously, the phase shift of 180° between the two digital signals can minimize and / or reduce residual ripple in the analog signal of the circuit arrangement.

[0038] According to one aspect, it is proposed that the circuit arrangement be set up such that the duty cycle of the first digital signal is equal to the duty cycle of the second digital signal.

[0039] According to one aspect, it is proposed that the second generator be configured to provide the second digital signal optionally with a first potential or with a second potential, or wherein the second generator is configured such that the second digital signal optionally consists of the first potential or the second potential.

[0040] The second digitally controlled generator can be configured to generate either the first or the second potential using a control signal. Specifically, the potential of the second generator can remain constant until the circuit is digitally controlled to generate a different analog signal. The first digitally controlled generator can be configured to provide a pulse-width modulated signal.

[0041] In other words, the second digital signal can be a static signal as long as the output signal of the circuit arrangement remains unchanged.

[0042] According to one aspect, it is suggested that the filter circuit includes a capacitor and / or an analog filter circuit and / or a filter impedance and / or a digital filter.

[0043] Advantageously, by appropriately selecting the filter circuit, the residual ripple of the analog signal and / or the rise time of the analog signal can be adjusted in response to a voltage change.

[0044] According to one aspect, it is proposed that the filter circuit be set up and configured so that the filter circuit interacts with the first coupling impedance and / or the second coupling impedance to provide the analog signal.

[0045] Advantageously, the respective coupling impedance can be dimensioned for interaction with the filter circuit in order to achieve a desired filtering effect.

[0046] According to one aspect, it is proposed that the circuit arrangement comprises a plurality of digitally controllable generators, each electrically coupled to the circuit node by means of a respective coupling impedance, wherein the plurality of digitally controllable generators each provide a pulse-width modulated signal, and wherein the respective digitally controllable generators are configured such that the respective pulse-width modulated signals have a respective clock shift of 360 degrees divided by a number of the plurality of digitally controllable generators.

[0047] This means that the digitally controllable generators are configured such that a fixed phase relationship exists between the respective pulse-width modulated signals of the respective digitally controllable generators. In particular, these phase shifts can be a shift in the respective clock frequency of the respective digital signal. Advantageously, as already explained above, the filter time constant can be further reduced by coupling with additional digitally controllable generators. The pulse-width modulated signals can be phase-shifted by 360° / n relative to each other to achieve the lowest possible residual ripple in the analog signal. The number of digitally controllable generators coupled to the circuit node is n.

[0048] According to one aspect, it is proposed that the number of digitally controllable generators is determined based on a predetermined rise time for the analog signal.

[0049] Advantageously, as previously explained, the residual ripple of the analog signal from the circuit arrangement can be influenced by the number of digitally controllable generators coupled to the circuit nodes. The residual ripple of the circuit arrangement can decrease quadratically with the number n of digitally controllable generators coupled to the circuit nodes.

[0050] According to one aspect, it is suggested that each digitally controllable generator has a respective timer circuit of a microcontroller.

[0051] One approach proposes that the respective digitally controlled generator be configured via the microcontroller's timer circuitry to generate the respective pulse-width modulated signal. Advantageously, using a microcontroller reduces the effort required to provide a digitally controlled generator.

[0052] According to one aspect, it is proposed that the respective timer circuits are synchronized based on an internal controller frequency and / or an external controller frequency in order to couple the respective digital signals in phase.

[0053] In other words, the timer circuit can be triggered by both the internal controller frequency and an external clock, particularly to synchronize multiple participants from several microcontrollers.

[0054] An integrated circuit is proposed that incorporates a network controller, particularly for a fieldbus, and one of the circuit arrangements described above for converting a digital signal into an analog signal. Advantageously, the circuit arrangement described above for converting a digital signal into an analog signal can be part of a microcontroller, which also includes a network controller for establishing and / or controlling a fieldbus. In other words, the circuit arrangement can be integrated into a "HART module" for a fieldbus. This HART module can be configured to convert digital signals into analog HART signals and to supply power to a field device, such as a sensor or actuator.

[0055] The use of one of the circuit arrangements described above in a fieldbus system is proposed. Advantageously, one of the circuit arrangements described above can be used in a fieldbus system, for example, to generate analog signals for communication with the fieldbus system.

[0056] It should also be noted that the various embodiments described above and / or below can be combined with each other. Examples of implementation

[0057] Exemplary embodiments of the invention are described with reference to the Fig. Figures 1 to 6 are shown and explained in more detail below. It shows: Fig. 1a a voltage source with a PWM generator; Fig. 1b a first circuit arrangement with two generators; Fig. 2. A first diagram showing the rate of change; Fig. 3 a second circuit arrangement with two generators; Fig. 4 a second diagram showing ripples in signals; Fig. 5 a third circuit arrangement with four generators; and Fig. 6 a third diagram with PWM signals.

[0058] The Fig. Figure 1a schematically sketches, for a comparison explained later, an equivalent circuit diagram of a typical variable voltage source with a PWM generator (PWM-DAC) based on a pulse-width modulated signal from a PWM generator. The first terminal of the PWM generator is coupled to the first terminal of a capacitor C via a resistor R. The second terminal of the PWM generator and the second terminal of the capacitor C are electrically coupled. The resistor R and the capacitor C can be dimensioned and interact such that the pulse-width modulated signal from the PWM generator is filtered to provide a DC voltage across the capacitor C that exhibits a certain residual ripple.

[0059] The Fig. Figure 1b schematically outlines a first circuit arrangement 100 for converting a digital signal into an analog signal. A first output terminal of a first digitally controllable generator V1, for providing a first digital signal, is electrically coupled to a first circuit node K1 via a first coupling impedance R1. A first output terminal of a second digitally controllable generator D1, for providing a second digital signal, is electrically coupled to the first circuit node K1 via a coupling impedance R2. The second output terminal of generator V1 is electrically coupled to the second output terminal of generator D1. Both the first digitally controllable generator V1 and the second digitally controllable generator D1 are configured to generate their respective digital signals depending on a digital control signal.For example, generator V1 can be set up to be digitally controlled by means of a duty cycle for the generated pulse-width modulated digital signal.

[0060] The first digitally controllable generator V1 and the second digitally controllable generator D1 are digitally controlled by the first circuit arrangement 100 such that the first digital signal and the second digital signal are chained together at the first node K1, based on the network of first coupling impedance K1 and second coupling impedance K2, to form a resulting analog signal.

[0061] The first circuit node K1 of the first circuit arrangement 100 is electrically coupled to the first terminal of a filter circuit C1. The second terminal of the filter circuit C1 is electrically coupled to the second output terminal of the first generator V1 and the second output terminal of the second generator D1. The first circuit arrangement 100 can be configured such that the filter circuit C1 interacts with the respective coupling impedances R1 and R2 in such a way that the signals superimposed at the first circuit node K1 are filtered to provide the analog signal at an output of the filter circuit C1, in this example in parallel with the filter circuit C1.

[0062] Fig. Figure 2 outlines in diagram 20 the rise time of an analog output signal when the output voltage changes and the residual ripple is adjusted, which is derived from simulation calculations with the voltage source using a PWM generator according to the Fig. 1a and the first circuit arrangement 100 according to the Fig. 1b, with different dimensions, were generated for a voltage change from 0 V to 0.35 V.

[0063] Curve 210 describes the voltage profile for an output voltage of the voltage source with a PWM generator at the capacitor C according to Fig. 1a with a clock frequency of the generator PWM of 100 Hz with a maximum amplitude of the pulse width modulated voltage of, for example, 1 V and a resolution of a duty cycle of the generator PWM of 16 bits and with a resistor R of 100 kOhm and a capacitance of 1 µF.

[0064] Curve 220 describes the voltage profile for an output of the first circuit arrangement 100 at the filter circuit C1 according to Fig. 1b in a first dimensioning for a voltage change from 0 V to 0.35 V. The first circuit arrangement 100 is according to Fig. 1b in the first configuration features a pulse-width modulated voltage from the first digitally controllable generator V1 with a maximum voltage of 1 V, a clock frequency of 100 Hz, and a duty cycle resolution of 16 bits. It has a first coupling impedance R1 of 200 kΩ, a second coupling impedance R2 of 200 kΩ, and a filter circuit C1 of 0.5 µF. The second generator D1 is configured to be digitally switched between a voltage of 0 V and 1 V. This allows the first circuit arrangement 100, according to the first configuration, to provide an analog signal between zero and 1 V at an output of the filter circuit C1, i.e., in parallel with the capacitor C1.

[0065] Since the first generator V1, based on the voltage divider between R1 and R2, is set up to provide half the maximum voltage of the circuit arrangement at the first node K1 according to the chained first digital signal and second digital signal, and the first coupling impedance R1 is equal to the second coupling impedance R2, the filter circuit C1 can be dimensioned with half the time constant, since the residual ripple caused by the first generator V1 has only half the amplitude.

[0066] Since the second generator D1 is only switched between two voltages, 0 V and 1 V, no ripple is caused by the second generator D1. Compared to the rise curve 210 of the voltage source with a PWM generator according to Fig. 1a, can be connected to the voltage source with a PWM generator according to the first circuit arrangement 100, according to the first dimensioning. Fig. 1a, a twice as fast increase in voltage, i.e., a twice as fast rate of change, can be achieved.

[0067] In a second dimensioning of the first circuit arrangement 100, a PWM generator can be used in relation to the voltage source according to Fig. 1a A fourfold change rate of the digitally generated analog signal is achieved. For this purpose, the pulse-width modulated voltage of the first digital generator V1 is designed with a maximum voltage of 1 V, a clock frequency of 200 Hz, and a reduced duty cycle resolution of 15 bits compared to the first design. It also features a first coupling impedance R1 of 200 kΩ, a second coupling impedance R2 of 200 kΩ, and a filter circuit C1 of 0.25 µF. The second generator D1 is configured to switch between a voltage of 0 V and 1 V and is electrically coupled to the first circuit node K1 via a second coupling impedance R2 of 200 kΩ.In the second dimensioning, the first circuit arrangement 100 results in a total voltage resolution of 16 bits, since the first generator V1 is configured and set up to have a duty cycle resolution of 15 bits, and an additional bit for the voltage resolution of the analog signal results from the second generator D1, which is cascaded with the first generator V1. For a given controller frequency of the first digitally controllable generator, the clock frequency can advantageously be increased accordingly by reducing the duty cycle resolution without increasing the controller frequency. The resulting ripple corresponds to the previous examples of output signals 210 and 220, whereby the time constant of the filter circuit C1 can be reduced accordingly due to the higher clock frequency of the pulse-width modulated signal of the first generator V1.The result of a simulation measurement with a correspondingly higher rate of rise of the analog signal is shown in curve 230. Fig. 2 is shown in diagram 20.

[0068] The Fig. Figure 3 schematically outlines a second circuit arrangement 200 for converting a digital signal into an analog signal, wherein two digitally controllable generators V31, V32 are coupled together, each with a pulse-width modulated digital signal.

[0069] The first output terminal of the first digitally controlled generator V31, for providing a third digital signal, is electrically coupled to a second circuit node K2 via a third coupling impedance R32. The first output terminal of a fourth digitally controlled generator V32, for providing a fourth digital signal, is electrically coupled to the second circuit node K2 via a coupling impedance R33. The second output terminal of the third generator V31 is electrically coupled to the second output terminal of the fourth generator V32. Both the third digitally controlled generator V31 and the fourth digitally controlled generator V32 are configured to generate their respective digital signals depending on a digital control signal.The second circuit arrangement 200 with the third digitally controllable generator V32 and the fourth digitally controllable generator V33 is set up such that the third digital signal is coupled to the fourth digital signal in phase, in particular according to a phase angle of 180 degrees.

[0070] The second circuit node K2 is coupled to the first terminal of a filter circuit C32, which has a filter impedance C32. The respective second terminal of the filter circuit C32 is electrically coupled to the second terminal of the third generator V31 and the second terminal of the fourth generator V32. Thus, the analog signal can be provided in parallel with the filter impedance C32 as the output terminal by means of the second circuit arrangement.

[0071] The second circuit arrangement 200 can have a first coupling impedance R32 and a second coupling impedance R33 of 200 kΩ, with the filter circuit C32 being determined to be 2.5 µF. The third generator V31 can have a pulse-width modulated voltage with a maximum voltage of 1 V, a clock frequency of 200 Hz, and a duty cycle resolution of 15 bits. The fourth generator V32 can also have a pulse-width modulated voltage with a maximum voltage of 1 V, a clock frequency of 200 Hz, and a duty cycle resolution of 15 bits. The third digitally controllable generator V31 and the fourth digitally controllable generator V32 can be configured such that the third digital signal is phase-coupled with the fourth digital signal, with a phase difference of 180 degrees between the two digital signals, particularly to achieve minimal ripple.The third digital signal and the fourth digital signal are chained together at the second node K2, based on the network of third coupling impedance R32 and fourth coupling impedance R33, to form a resulting signal, so that the voltage resolution of the analog signal has 16 bits.

[0072] The residual ripple of the analog output voltage of the second circuit arrangement in the described dimensioning is shown in diagram 400 of the Fig. Figure 4 shows the analog voltage waveform of the analog signal of the second circuit arrangement 420 over time. If there is a phase difference of, for example, 100 degrees between the third digital signal and the fourth digital signal, a larger residual ripple of the analog output signal 410 results, as shown in the voltage waveform over time in Figure 4. Fig. 4 of diagram 400 is indicated.

[0073] The Fig. Figure 5 schematically outlines a third circuit arrangement for converting a digital signal into an analog signal, wherein the circuit arrangement comprises four digitally controllable generators. A first output terminal of a fifth digitally controllable generator V52, providing a fifth digital signal, is electrically coupled to a third circuit node K3 via a fifth coupling impedance R52. A first output terminal of a sixth digitally controllable generator V53, providing a sixth digital signal, is electrically coupled to the third circuit node K3 via a coupling impedance R53. A first output terminal of a seventh digitally controllable generator V54, providing a seventh digital signal, is electrically coupled to the third circuit node K3 via a seventh coupling impedance R54.A first output terminal of an eighth digitally controllable generator V55 is electrically coupled to the third circuit node K3 by means of an eighth coupling impedance R55 to provide an eighth digital signal.

[0074] The third circuit node K3 is electrically coupled to a filter circuit, which has two filter capacitors Cga and Cgb coupled to a filter coupling impedance R5F. A first terminal of the first filter impedance Cga is electrically coupled to a first terminal of the second filter impedance Cgb via a two-terminal first filter coupling impedance R5F. The respective second terminals of the first filter impedance Cga and the second filter impedance Cgb are electrically coupled to each other and to a second terminal of the fifth generator V52, the sixth generator V53, the seventh generator V54, and the eighth generator V55. This connection can be on the common ground of the circuit arrangement.The third circuit arrangement is configured to digitally control the four digitally controlled generators such that the corresponding four digital signals are chained together at the third node K3, based on the network of the four coupling impedances V52 to V55, to form a resulting analog signal. The resolution of the analog signal at an output of the filter circuit, i.e., in parallel with impedance Cgb, is based on the resolution of the respective generators and / or the number of appropriately coupled generators.

[0075] The four coupling impedances R52 to R55 can each be dimensioned at 400 kΩ. The first filter impedance Cga and the second filter impedance Cgb can each be dimensioned at 0.625 µF. The filter coupling impedance R5F can be dimensioned at 100 kΩ. The digital signals of the four digitally controllable generators V52 to V55 can each have a pulse-width modulated signal with a clock frequency of 400 Hz and a duty cycle resolution of 13 bits, whereby the clock frequency of the controller of the respective digitally controllable generators V52, V53, V54, and V55 can remain constant due to the reduced duty cycle resolution.The analog signal of the third circuit arrangement 300, due to the cascaded connection of the four digitally controllable generators based on a network of the four coupling impedances R52 to R55, exhibits an analog signal at an output of the filter circuit of the third circuit arrangement 300, which has a voltage resolution of 16 bits. For a given residual ripple of the analog signal of the third circuit arrangement, a higher rise time results, which is proportional to the clock frequency of the respective digitally controllable generator and proportional to the number of cascaded digitally controllable generators. In this case, this means that the rise time is 16 times higher than with a corresponding voltage source with a PWM generator according to [reference missing]. Fig. 1a.

[0076] The Fig.Figure 6 sketches in diagram 600 the time course of the voltages of the data signals of the four digitally controllable generators V52, V53, V54 and V55, namely the course of the voltage U 610, 620, 630 and 640 over time t, whereby due to the symmetry of the third circuit arrangement with respect to the generators, the assignment to the different generators is freely selectable.

[0077] The phase shift between the four pulse-width modulated signals of the generators is 360 degrees divided by 4 generator branches, i.e., 90 degrees, in order to achieve the lowest possible residual ripple of the analog output voltage.

Claims

[1] Circuit arrangement (100, 200, 300) for converting a digital signal into an analog signal, comprising: a first digitally controllable generator (V1) to provide a first digital signal; a second digitally controllable generator (D1, V2) to provide a second digital signal; wherein a circuit node (K1, K2) of the circuit arrangement (100, 200, 300) is electrically coupled to an output terminal of the first digitally controllable generator by means of a first coupling impedance (R1); and wherein the circuit node (K1, K2) is coupled to an output terminal of the second digitally controllable generator (D1, V2) by means of a second coupling impedance (R2); wherein the circuit arrangement comprises a plurality of digitally controllable generators (V52, V53, V54, V55) which are each electrically coupled to the circuit node (K1, K2, K3) by means of a respective coupling impedance (R52, R53, R54, R55), wherein the multiple digitally controllable generators (V52, V53, V54, V55) each provide a pulse-width modulated signal, and wherein the respective digitally controllable generators (V52, V53, V54, V55) are configured such that the respective pulse-width modulated signals have a clock shift relative to each other of 360 degrees divided by a number of the multitude of digitally controllable generators; and a filter circuit (C1, C32) coupled to the circuit node (K1, K2) to provide the analog signal; wherein the first digitally controllable generator (V1) and the second digitally controllable generator (D1, V2) are coupled such that there is a fixed phase relationship between the first digital signal and the second digital signal in order to achieve the lowest possible residual ripple of the analog signal with the circuit arrangement (100, 200, 300). [2] Circuit arrangement (100, 200, 300) according to claim 1, wherein the circuit arrangement (100, 200, 300) is configured to digitally control the first digitally controllable generator (V1) and the second digitally controllable generator (D1, V2) such that the first digital signal and the second digital signal are coupled at the first node (K1) based on the network of first (R1) and second coupling impedance (R2) to form a resulting signal. [3] Circuit arrangement (100, 200, 300) according to one of the preceding claims, wherein the first digitally controllable generator (V1) is configured to generate a first digital signal pulse-width modulated with a first clock rate; or that the first digital signal consists of the first pulse-width modulated signal with the first clock rate. [4] Circuit arrangement (100, 200, 300) according to one of the preceding claims, wherein the second digitally controllable generator (D1, V2) is configured to generate a second digital signal which is pulse-width modulated with a second clock rate; or the second digital signal consists of the second pulse-width modulated signal with the second clock rate. [5] Circuit arrangement (100, 200, 300) according to claim 4, wherein the first clock rate of the first digitally controllable generator (V1) is equal to the second clock rate of the second digitally controllable generator (D1, V2), or wherein the second clock rate of the second digitally controllable generator is an integer multiple of the first clock rate. [6] Circuit arrangement (100, 200, 300) according to one of the preceding claims, wherein the circuit arrangement (100, 200, 300) is configured such that the first digital signal is phase-shifted by 180 degrees relative to the second digital signal. [7] Circuit arrangement (100, 200, 300) according to one of the preceding claims, wherein the circuit arrangement (100, 200, 300) is configured such that a duty cycle of the first digital signal is equal to a duty cycle of the second digital signal. [8] Circuit arrangement (100, 200, 300) according to any one of claims 1 to 3, wherein the second generator (D1, V2) is configured to provide the second digital signal selectively with a first potential or with a second potential, or wherein the second generator is configured such that the second digital signal selectively consists of the first potential or the second potential. [9] Circuit arrangement (100, 200, 300) according to claim 1, wherein the number of the plurality of digitally controllable generators (V52, V53, V54, V55) is determined based on a predetermined rise time for the analog signal. [10] Circuit arrangement (100, 200, 300) according to one of the preceding claims, wherein each digitally controllable generator (V1, V2, D1, V52, V53, V54, V55) has a respective timer circuit of a microcontroller. [11] Circuit arrangement (100, 200, 300) according to claim 10, wherein the respective digitally controllable generator (V1, V2, D1, V52, V53, V54, V55) is set up by means of the respective timer circuit of the microcontroller to generate the respective pulse width modulated signal. [12] Including an integrated circuit: a network controller, especially for a fieldbus; and a circuit arrangement (100, 200, 300) according to claims 1-11 for converting a digital signal into an analog signal. [13] Use of a circuit arrangement (100, 200, 300) according to claims 1 to 11 in a fieldbus system.

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