POWER SEMICONDUCTOR COMPONENT WITH METAL STRUCTURE PASSIVATION AND METHOD FOR MANUFACTURING THE POWER SEMICONDUCTOR COMPONENT

Abstract

Power semiconductor device (100) comprising: a semiconductor substrate (110); a metal structure (120) arranged above the semiconductor substrate (110), wherein one metal of the metal structure (120) is Cu or a Cu-based alloy; and a passivation layer (130) arranged above the metal structure (120), wherein the passivation layer (130) comprises a first layer (130_1) comprising CuSiN, and a second layer (130_2) comprising Si, N and H, wherein the ratio of Si to N, expressed in atomic numbers, is equal to or greater than 3.3 / 4, wherein the power semiconductor device (100) comprises an active region (102), a chip edge (104) and an edge termination region (103) that separates the active region (102) from the chip edge (104), wherein the second layer (130_2) extends over at least a part of the edge termination region (103) to near the chip edge (104) or to the chip edge (104).

Description

Technical field

[0001] This disclosure relates generally to the field of power semiconductor devices and in particular to a power semiconductor device with a metal structure passivation. background

[0002] Power semiconductor devices, in particular, are often sensitive to environmental influences such as humidity and temperature fluctuations. These influences can lead to changes in material properties and electrical characteristics, for example, a deviation in the breakdown voltage of the device. Furthermore, the lifetime of the power semiconductor device can be shortened.

[0003] Passivation layers on metal structures are used to improve the component's resistance to environmental influences. However, integrating a passivation layer onto metal can be challenging with regard to the required high adhesion and compliance with electrical requirements, particularly its suitability for chip edge termination.

[0004] Document CN 1 15 483 216 A describes a NAND flash memory device comprising a copper structure and an overlying copper diffusion barrier layer. The copper diffusion barrier layer consists of a CuSiN film, an overlying SiC:N layer, and a silicon nitride layer. Document US 2003 / 0 218 220 A1 describes a semiconductor device in which an n-substrate surface and a p+ region are arranged side by side, with an insulating layer, a shield, and a conductor formed on their upper surfaces in that order. Document DE 10 2013 109 297 A1 concerns semiconductor devices with support patterns in interstitial areas between conductive patterns and methods for manufacturing them.Document US 7 755 202 B2 describes an integrated switching device comprising spaced conductive patterns on a substrate surface and a support pattern on the substrate surface between adjacent conductive patterns and separated from them by respective interspace areas.

[0005] According to one aspect of the disclosure, a semiconductor device comprises a semiconductor substrate according to the features of claim 1.

[0006] According to another aspect of the disclosure, a method for manufacturing a semiconductor device comprises providing a semiconductor substrate according to the features of claim 15. Brief description of the drawings

[0007] The elements in the drawings are not necessarily to scale. Identical reference numerals denote corresponding similar parts. The features of the various embodiments shown may be combined, provided they are not mutually exclusive, and / or they may be selectively omitted if they are not described as absolutely necessary. Embodiments are illustrated in the drawings and are further explained by way of example in the following description. Fig. Figure 1 is a schematic cross-sectional representation of an example of a semiconductor substrate, a metal structure arranged on the substrate, and a passivation layer arranged on the metal structure of a semiconductor device. Fig. Figure 2 is a schematic top view of an example of a semiconductor device showing an active region, a chip edge and an intermediate edge termination region. Fig. Figure 3 is a schematic cross-sectional partial view of a semiconductor device, showing an active area, a chip edge and an intermediate edge termination area. Fig. Figure 4 is a schematic cross-sectional partial view of an exemplary semiconductor device with a power pad and other metal structures, such as a signal guidance structure or a field plate of an exemplary semiconductor device. Fig. Figure 5 is a flowchart showing exemplary steps of a process for manufacturing a semiconductor device with a metal structure and a passivation layer arranged on the metal structure. Fig. 6 is a flowchart showing exemplary steps of a process for forming a passivation layer according to stage S3 of Fig. 5 shows. Detailed description

[0008] It is understood that the features of the various exemplary embodiments and examples described here can be combined with each other, unless expressly stated otherwise.

[0009] The terms “applied”, “covered by”, “connected”, and / or “electrically connected” used in this description do not imply that the elements or layers must be in direct contact with one another; intermediate elements or layers may be provided between the “applied”, “covered by”, “connected”, and / or “electrically connected” elements. However, according to the disclosure, the above terms may also have the specific meaning that the elements or layers are in direct contact with one another, i.e., that no intermediate elements or layers are provided between the “applied”, “covered by”, “connected”, and / or “electrically connected” elements.

[0010] Furthermore, the word "over," when used in reference to a part, element, or layer of material that is formed or arranged "over" a surface, can be used here to mean that the part, element, or layer of material is arranged "directly on," i.e., in direct contact with, the indicated surface (e.g., placed, formed, arranged, deposited, etc.). The word "over," when used in reference to a part, element, or layer of material that is formed or arranged "over" a surface, can also be used here to mean that the part, element, or layer of material is arranged "indirectly" on the indicated surface (e.g., placed, formed, arranged, deposited, etc.), with one or more additional parts, elements, or layers positioned between the indicated surface and the part, element, or layer of material.

[0011] Fig. Figure 1 shows an example of a power semiconductor device 100 with a semiconductor substrate 110. A metal structure 120 is arranged over the semiconductor substrate 110. A metal of or containing in the metal structure 120 is Cu or a Cu-based alloy.

[0012] A passivation layer 130 is arranged over the metal structure 120. The passivation layer 130 comprises a first layer 130_1 and a second layer 130_2. The first layer 130_1 comprises or consists of CuSiN. The second layer 130_2 comprises or consists of Si, N, and H. In terms of atomic numbers, the ratio of Si to N is equal to or greater than 3.3 / 4.

[0013] As described in more detail below, the passivation layer 130 can have various functions. First, the passivation layer 130 can be highly suitable for passivation, e.g., for moisture protection of the underlying structures. Second, the passivation layer 130 can provide good adhesion to underlying structures, such as the metal structure 120, and / or to overlying structures, such as an imide layer (in Fig. (1 not shown). Thirdly, the passivation layer 130 can be used, for example, for electrical contacting the chip edge. In power semiconductor devices, the chip edge can be under high voltage. The passivation layer 130 can, for example, perform an electrical function to compensate for the voltage drop between the chip edge and the active area, so that it does not negatively affect the electrical properties of the device. For this purpose, the passivation layer 130 can have a specific electrical conductivity that is neither too high nor too low. In addition, the passivation layer 130 can form a charge shielding layer to protect the chip edge termination from external charges.

[0014] In the semiconductor device 100, the second layer 130_2, which contains Si, N, and H in the composition described above, can meet the requirements regarding protection against environmental influences, adhesion, and electrical conductivity. However, as described in more detail below, the second layer 130_2 cannot be directly and controllably deposited onto the metal structure 120.

[0015] The first layer 130_1 contains CuSiN to suppress the formation of CuSi, thus enabling the controlled deposition of the second layer 130_2. In other words, by combining the first layer 130_1 and the second layer 130_2, a metal structure 120 containing or consisting of Cu can be effectively passivated by a passivation layer 130, which can meet all requirements, and in particular the electrical and protection requirements, e.g., for chip edge termination.

[0016] The first layer 130_1 can, for example, comprise or consist of two layers, namely an (optional) CuSi layer 130_1a and a CuSiN layer 130_1b, which is arranged above the CuSi layer 130_1a and represents, for example, the surface of the first layer 130_1.

[0017] Optionally, at least one intermediate layer 130_x can be arranged between the first layer 130_1 and the second layer 130_2. The intermediate layer 130_x can comprise or consist of aluminum oxide, e.g., Al₂O₃. The (optional) intermediate layer 130_x can be deposited by ALD (Atomic Layer Deposition). The intermediate layer 130_x can have a small thickness, e.g., less than one or a few nm.

[0018] The metal structure 120 can be, for example, a chip pad or another metal structure used in the power semiconductor device 100. The metal structure 120 could, for example, be a gate runner or a field plate of the power semiconductor device 100.

[0019] Depending on whether the semiconductor device 100 is a power device or not, and depending on the type of metal structure 120, the metal structure 120 can, for example, have a thickness between 1 and 30 µm, in particular between 4 and 14 µm. The first layer 130_1 can, for example, have a thickness between 1 and 115 nm (depending on whether and, if so, how thick a CuSi layer 130_1a is contained in the first layer 130_1; see the following more detailed description). The thickness of the first layer 130_1 can be small because the first layer 130_1 does not need to provide volume-dependent functionality. Rather, the first layer 130_1 can form a nitrided copper silicide surface that prevents excessive CuSi growth during the formation of the second layer 130_2 of the passivation layer stack 130.

[0020] The second layer 130_2 can have a thickness between 40 and 500 nm. In particular, a thickness between 200 nm, 250 nm, or 300 nm as a lower limit and 500 nm or 400 nm as an upper limit may be suitable. The second layer 130_2 can provide the moisture-protective and / or electrical properties of the passivation layer 130, i.e., it can offer volume-dependent functionality.

[0021] The semiconductor substrate 110 can be, for example, a Si substrate, an SOI substrate (Si-on insulator), a GaN substrate, a SiC substrate, a GaAs substrate, or a substrate made of another IV-IV, III-V, or II-VI semiconductor material, such as SiGe, GaAs, AlGaN, InGaAs, InAlAs, etc. The semiconductor substrate 110 can be a semiconductor body or a semiconductor chip made, for example, of one or more of the materials mentioned above.

[0022] The semiconductor device 100 can be, for example, a vertical or a horizontal device. In a vertical device, the main direction of the load current is vertical, while in a horizontal (or lateral) device, the main direction of the load current is horizontal (lateral).

[0023] The power semiconductor device 100 (e.g., a semiconductor chip) can be designed, for example, as an IGBT (Insulated Gate Bipolar Transistor), as a FET (Field-Effect Transistor), in particular as a MOSFET (Metal Oxide Semiconductor FET), such as a P-FET (P-Channel FET), an N-FET (N-Channel FET), an AFET (Array FET), a JFET (Junction-Gate FET), a Planar-Gate Transistor, a Field-Plate Trench Transistor, or an SJ Transistor (Super-Junction). Furthermore, the semiconductor device 100 can, for example, be designed as a diode.

[0024] Fig. Figure 2 shows a top view of a semiconductor device 100, in which the functional areas of the device 100 are illustrated. In the example shown, the semiconductor device 100 can be a power and / or high-voltage device 100.

[0025] The semiconductor device 100 can contain an active region 102. The active region 102 can be bounded by an edge 102B, at which the active region 102 transitions into an edge termination region 103. The edge termination region 103 can surround the active region 102 and terminate at the chip edge 104.

[0026] The primary purpose of the active region 102 is to ensure the conduction of the load current. The edge termination region 103 can be configured to reliably terminate the active region 102. More precisely, the edge termination region 103 is typically not used for conducting the load current, but rather to securely terminate the active region 102 and ensure robust blocking characteristics of the semiconductor device 100.

[0027] Fig. Figure 3 shows a cross-sectional view of part of an exemplary semiconductor device 100. In the example shown, the semiconductor device 100 is a vertical device.

[0028] The semiconductor device 100 can comprise the semiconductor substrate 110, which is connected to a first load terminal 310 and a second load terminal 320. Within the active area 102, a load current can be conducted between the first load terminal 310 and the second load terminal 320. The semiconductor substrate 110 can, for example, include a drift zone for conducting the load current. In the example shown, the load current path runs in a vertical direction.

[0029] The first load connection 310 can, for example, correspond to the metal structure 120, as used in connection with Fig. As described in section 1. That is, the metal structure 120 can be at least partially superimposed by the passivation layer 130. The first load terminal 310 can, for example, be a source (or emitter) terminal of the semiconductor (transistor) device 100. The second load terminal 320 can, for example, be a drain (or collector) terminal of such a semiconductor device 100.

[0030] Within the edge termination area 103, the semiconductor device 100 can have an edge termination structure 330. The edge termination structure 330 can, for example, be arranged partially or completely within the semiconductor substrate 110.

[0031] The electrical potentials of both load terminals 310, 320 can be present on an upper surface 110A of the semiconductor substrate 110. For example, the electrical potential of the second load terminal 320 can be present along the entire vertical extent of the semiconductor substrate 110 at the chip edge 104. If, for example, a metal structure 120 is arranged adjacent to the chip edge 104 (as in the example of Fig. 3) The metal structure at chip edge 104 is at the same electrical potential as the second load terminal 320. This potential can be, for example, a high-voltage potential equal to or greater than 0.2 kV, 0.5 kV, 0.7 kV, 1 kV, 1.5 kV, 2 kV, 3 kV, 5 kV, or 7 kV.

[0032] On the other hand, the electrical potential at the metal structure 120 forming the first load terminal 310 can be significantly lower, e.g., approximately 0 V or equal to or less than 10 V, 20 V, or 30 V. Therefore, in a high-voltage or power semiconductor device 100, a voltage applied between the first load terminal 310 and the second load terminal 320 can have essentially the same values ​​as those mentioned above for the potential of the second load terminal 320. The voltage applied between the first load terminal 310 and the second load terminal 320 can be referred to, for example, as the "emitter-collector voltage" or the "source-drain voltage".

[0033] The edge termination area 103 can be configured to equalize these electrical potentials, for example, to prevent electrical breakdown. Along the edge termination area 103, or along the (optional) edge termination structure 330, the electrical potential can transition from the potential of the first load terminal 310 to the potential of the second load terminal 320 (located at the chip edge 104). For example, the potential on a first side of the edge termination area 103, or the (optional) edge termination structure 330, can be equal to or similar to the potential of the first load terminal 310, and on a second side of the edge termination area 103, or the (optional) edge termination structure 330, the potential can be equal to or similar to the potential of the second load terminal 320. The first side of the edge termination area 103, orThe edge termination structure 330 is closer to the active area 102, while the second side of the edge termination area 103 or the edge termination structure 330 is closer to the chip edge 104.

[0034] The passivation layer 130 can be located, for example, within a portion of the active region 102 and / or within a portion or across the entire extent of the edge termination region 103. For instance, the second layer 130_2 of the passivation layer 130 can extend as a continuous layer from the chip edge 104 into the active region 102. The passivation layer 130 extends at least partially over the metal structure 120. The second layer 130_2 can, for example, extend partially over a non-metallic structure such as the edge termination structure 330. The first layer 130_1 does not extend over non-metallic structures. In other words, the passivation layer 130 can include the second layer 130_2, but not the first layer 130_1, in areas that lie vertically over non-metallic structures. As shown in Fig. As shown in Figure 3, the passivation layer 130 can be arranged above the metal structure 120 within the active area 102 and / or above the metal structure 120 within the edge termination area 103.

[0035] The edge termination structure 330 can be implemented in various ways. For example, the edge termination structure 330 can comprise or embody a VLD zone (variation of lateral doping). A VLD zone can comprise a semiconductor region with a laterally decreasing dopant concentration towards the chip edge 104. Alternatively or additionally, the edge termination structure 330 can contain or consist of an insulating layer, such as an oxide layer. For example, the edge termination structure 330 can contain or be formed from a LOCOS layer (locally oxidized silicon), which can optionally overlay an underlying VLD zone in the semiconductor substrate 110. In this case, the insulating layer of the edge termination structure 330 can electrically isolate the passivation layer 130 from the semiconductor substrate 110 or, in particular, from a VLD zone formed in the semiconductor substrate 110.The insulating layer can extend over the entire area between the metal structure 120 in the active area 102 and, if present, the metal structure 120 in the edge termination area 103 or the chip edge 104.

[0036] Since the passivation layer 130 can extend continuously from the metal structure 120 of the active area 102 to the chip edge 104 (or the metal structure 120 near or at the chip edge 104), the passivation layer 130 can provide a homogeneous high-impedance conduction path between the first load terminal 310 and the chip edge 104 (and / or the metal structure 120 near or at the chip edge 104). For example, the passivation layer 130 can have a conductivity of 1 × 10⁻⁶ or greater. -4 S or 2×10 -4 S and / or equal to or less than 5×10 -3S within a temperature range of 273 K to 473 K. Such a high-resistance conduction path is suitable for equalizing the electrical potentials between the active area 102 and the chip edge 104.

[0037] The electrical properties of the passivation layer 130 are caused by the second layer 130_2. The second layer 130_2 comprises or consists of silicon nitride in a modified form that is not stoichiometric but has an increased silicon content.

[0038] More precisely, (stoichiometric) silicon nitride Si3N4 is an insulator. If the silicon content in the second layer 130_2 is increased so that the ratio of Si to N in atomic numbers is equal to or greater than 3.3 / 4, the silicon nitride has a superstoichiometric Si content. The passivation properties of the superstoichiometric silicon nitride layer are (still) high. However, integrating such a superstoichiometric silicon nitride layer onto a metal structure containing or consisting of Cu or a Cu-based alloy is difficult because the deposition process leads to thick CuSi layers and poor adhesion. The addition of the first layer 130_1, which contains, for example, a thin CuSiN layer beneath the superstoichiometric silicon nitride layer (second layer 130_2), enables the integration of the second layer 130_2 onto a Cu or Cu-based metal structure 120 with high adhesion of the passivation layer 130 to the metal structure 120.

[0039] For example, in at least part of the second layer 130_2 (or in the entire second layer 130_2), the ratio of silicon to nitride is equal to or greater than 3.3 / 4, expressed in atomic numbers. In other examples, the ratio of silicon to nitride in the second layer 130_2 may be equal to or greater than 3.6 / 4, 3.8 / 4, or 1, expressed in atomic numbers. For example, the number of silicon atoms may be equal to or greater than 82.5%, 90%, or 100% of the number of nitrogen atoms in the second layer 130_2. In some examples, the number of silicon atoms may be greater than the number of nitrogen atoms in the second layer 130_2. In this case, the number of silicon atoms can be equal to or greater than 110%, 120%, 130%, 140%, or 150% of the number of nitrogen atoms in the second layer 130_2.

[0040] In some examples, the second layer 130_2 may contain 40 to 55 at% Si. In these or other examples, the second layer 130_2 may contain 30 to 45 at% N. The second layer 130_2 may also contain H at a concentration of, for example, 12 to 17 at%. Typical values, from which, however, considerable deviations are possible, are 48 at% Si, 36 at% N, and 15 at% H.

[0041] Fig. Figure 4 shows a partial cross-sectional view of an example of a 400 series semiconductor device. The in Fig. The part shown in Figure 4 of the semiconductor device 400 can be compared to part D of Fig. 3 corresponds. In other words, the figure shows a transition from the active area 102 to the edge termination area 103. The chip edge 104 is not shown.

[0042] The first load terminal 310 (e.g. source pad) and a control terminal, e.g. a gate pad (not shown), can be arranged above the upper surface 110A of the semiconductor substrate 110.

[0043] The semiconductor substrate 110 can have a highly doped region 412 for contacting the second load terminal 320 and a plurality of highly doped regions 414 near the upper surface 110A of the semiconductor substrate 110. The highly doped regions 414 can be located in the active region 102 and / or in the edge terminal region 103.

[0044] In the active area 102, the semiconductor device 400 can have a plurality of gate contacts 410. The gate contacts 410 are in Fig. Figure 4 is shown as an example of trench gates. For instance, gate contacts 410 made of polysilicon can be used. The reference numeral 440 refers to a gate dielectric that insulates the gate contacts 410, for example, from channel regions (not shown) of the (transistor) semiconductor device 400. The channel regions can be arranged, for example, along the gate contacts 410 in a vertical direction in the highly doped regions 414.

[0045] The gate contacts 410 can be connected, for example, to a gate runner 420. The gate runner 420 can be insulated from the semiconductor substrate 110 by an insulating layer 430. The insulating layer 430 can be, for example, an oxide layer. The insulating layer 430 can be, for example, a LOCOS layer. The insulating layer 430 can, for example, form part of the edge termination structure 330.

[0046] The semiconductor device 400 may also contain signal guidance structures and / or field plates. The reference numeral 450 refers to such a signal guidance structure and / or field plate.

[0047] The semiconductor device 400 can contain a metallization M. The metallization M can, for example, contain or consist of Cu or a Cu-based alloy.

[0048] The semiconductor device 400 can, for example, contain a dielectric layer 480, which can also be referred to as an interlayer dielectric. The dielectric layer 480 can comprise or consist of an organic or inorganic dielectric material. The dielectric layer 480 is an electrically insulating layer.

[0049] A barrier layer 460 can be applied over the dielectric layer 480. The barrier layer 460 can be structured such that it covers only a portion of the surface of the dielectric layer 480. In areas where the metallization M (e.g., the metal structure 120 formed by structuring the metallization M) overlaps the dielectric layer 480, the barrier layer 460 can completely cover the dielectric layer 480 to fully separate it from the metallization M. In other areas where the dielectric layer 480 is not covered by the metallization M, the barrier layer 460 can either be omitted or structured such that it covers only parts of the dielectric layer 480, as shown in Fig. 4 shown.

[0050] The barrier layer 460 can consist of a copper barrier material, such as TiW and / or TiN and / or W. Other types of barrier layers 460 can also be used.

[0051] The passivation layer 130 is formed, for example, over the metallization M and / or the dielectric layer 480. It can also be formed over the barrier layer 460. As shown in Fig. As shown in Figure 4 and already mentioned, the passivation layer 130 can be a continuous layer extending from the metal structure 120 (e.g., the source pad) across the edge termination area 103 to the chip edge 104 (not shown). In other words, the entire chip surface, with the exception of the contact areas of the metal structure 120, can be effectively sealed against environmental influences by the passivation layer 130.

[0052] Furthermore, an organic insulating layer 470, e.g., an imide layer, can be arranged over the passivation layer 130. The organic insulating layer 470 can be a continuous layer extending, e.g., over the entire edge termination region 103 to the chip edge 104 (not shown). The organic insulating layer 470 can, e.g., extend over a portion of the metal structure 120 of the metallization M and over the entire extent of the passivation layer 130 outside the metal structure 120.

[0053] The organic insulating layer 470 may contain, for example, a polyimide (PI) - usually referred to as imide - and / or polybenzoxazole (PBO) and / or epoxide and / or similar organic dielectrics.

[0054] The organic insulating layer 470 can have a thickness of 5 µm, 8 µm, or 10 µm or more, and of 20 µm, 15 µm, or 12 µm or less. For example, the thickness of the organic insulating layer 470 can be 11 µm.

[0055] The organic insulating layer 470 and / or the passivation layer 130 cannot, for example, extend into the area between the dielectric layer 480 and the metallization M. Furthermore, in some areas only the organic insulating layer 470 and the passivation layer 130 can be used, for example, to cover the dielectric layer 480.

[0056] In Fig. Section 5 describes exemplary stages of the fabrication of a semiconductor device 100, 400. In S1, a semiconductor substrate 110 is provided. The semiconductor substrate 110, e.g., a silicon body, may have undergone FEOL (front-end-of-line) processing to form an integrated circuit.

[0057] In S2, a metal structure 120 is formed over the semiconductor substrate 110. The metal structure 120 can comprise or consist of copper or a copper-based alloy. As described above, an insulating layer 430 and / or a barrier layer 460 can be formed before the metal structure 120 is formed.

[0058] The metal structure 120 can be formed by applying a metal layer and structuring this layer, e.g., by chemical wet etching of copper. The layer can be formed by sputtering or electroplating the metal (e.g., copper or a copper-based alloy). Optionally, a chemical-mechanical polishing (CMP) process can follow.

[0059] In S3, the passivation layer 130 is formed over the metal structure 120. The formation of the passivation layer 130 comprises the formation of a first layer 130_1 with CuSiN and the formation of a second layer 130_2 with Si, N and H.

[0060] Before forming the passivation layer 130 over the metal structure 120, a metal oxide (e.g., copper oxide) can be removed from the metal structure 120. The oxide removal can be carried out, for example, by plasma treatment with a hydrogen precursor. The hydrogen precursor can contain, for example, NH3 and / or H2.

[0061] For example, a process chamber (also referred to as a reaction chamber in technical jargon), into which the semiconductor substrate 110 with the exposed metal structure 120 has been placed, is filled with a mixture of NH3 and N2. The oxide is removed by ignition of the hydrogen plasma.

[0062] The formation of the first layer 130_1, containing CuSiN, can be initiated by setting a controlled low flow of a gaseous Si compound (e.g., silane) without plasma treatment at this stage. Silane reacts thermally with copper to form copper silicide (CuSi) on the surface of the metal structure 120. For example, a flow of 34 sccm of silane (e.g., monosilane SiH4) and a flow of 4500 sccm of N2 can be used.

[0063] All flow rates given here are examples. They may refer, for example, to 300 mm wafers.

[0064] The silicidal treatment of the metal surface can be followed by plasma treatment. The plasma treatment is used for the subsequent nitriding of the silicidal metal surface. For example, plasma treatment with NH3 is performed to produce a nitrided copper silicide (CuSiN) of the first layer 130_1.

[0065] The CuSiN surface thus formed is stable and appears to be inert towards many chemical substances. In particular, the CuSiN surface does not react thermally with silane. In other words, when the metal structure 120 coated with the first layer 130_1 (including the CuSiN layer) is exposed to silane or another gaseous Si compound for silicon deposition, no silicon is thermally deposited on this surface.

[0066] Only a small portion of the CuSi can be converted to CuSiN. For example, a CuSiN layer 130_1b with a thickness in the range of 1 to 15 nm, particularly between 3 and 9 nm, can be formed over the (optional) CuSi layer 130_1a. The CuSi layer 130_1a can have a thickness in the range of 0 nm to 200 nm, particularly between 0 and 100 nm.

[0067] This means that the first layer 130_1 can comprise two layers: the CuSi layer 130_1a and the CuSiN layer 130_1b. The (optional) CuSi layer 130_1a can have a thickness in the range of 0 nm to 200 nm, 0 nm to 150 nm, 50 ± 50 nm, 50 ± 40 nm, 50 ± 30 nm, 50 ± 20 nm, 50 ± 10 nm, or 50 ± 0 nm. A deterioration in adhesion was observed at thicknesses above 100 nm. It should be noted that the term "CuSi" used here refers to CuSi x This means that the stoichiometry (specified by x) can be changed depending on the gas flow rates used.

[0068] The gas flow in the process chamber is then adjusted to prepare for the formation of the second layer 130_2 of the passivation layer 130. This includes adjusting the flow rate of the gaseous silicon compound (e.g., silane). A significantly higher flow rate (e.g., approximately 700 sccm) is required for the silicon precursor gas (i.e., the gaseous silicon compound). Adjusting the appropriate gas flows typically takes several seconds to achieve stable flow conditions in the process chamber, e.g., approximately 10 s. During this time, the CuSiN layer 130_1b prevents any thermal reaction between the copper surface and the silicon precursor gas. In other words, CuSi does not grow during the gas flow adjustment process. Optionally, further processes (e.g., deposition of the intermediate layer 130_x) can be performed before the deposition of the second layer 130_2.

[0069] Once stable flow conditions are reached, the formation of the second layer 130_2, containing Si, N, and H in the aforementioned composition, can be initiated by plasma ignition. The thickness of the second layer 130_2 depends on the flow rate of the process gases and the process duration in the process chamber. For example, a relatively high gas flow rate of the gaseous Si compound, between 500 sccm and 1200 sccm, can be used. The flow rate of a gaseous N compound (e.g., N2 and / or NH3) can be set, for example, between 3000 and 5000 sccm or even 8000 sccm. The first layer 130_1 (especially the CuSiN it contains) enables the controlled deposition of the second layer 130_2 with a superstoichiometric Si content.

[0070] Fig. Figure 6 is a flowchart showing exemplary stages of the formation of the passivation layer 130 over the metal structure 120 according to S3.

[0071] In S3_1, a CuSi layer 130_1a can be formed by the thermal decomposition of a gaseous Si compound, in particular silane. No plasma is ignited in this stage.

[0072] In S3_2, the CuSi layer 130_1a can be exposed to a nitrogen-containing plasma. As mentioned previously, the nitrogen-containing plasma passivates (nitrides) the surface of the CuSi layer 130_1a by forming the CuSiN layer 130_1b to prevent the thermal decomposition of the silicon on it.

[0073] In S3_3, the first layer 130_1 (which contains the CuSiN layer 130_1b) can be exposed to a silicon- and nitrogen-containing plasma. In this processing stage, the second layer 130_2 is formed. EXAMPLES

[0074] The following examples relate to other aspects of the revelation:

[0075] Example 1 is a semiconductor device with a semiconductor substrate. A metal structure is arranged over the semiconductor substrate, the metal of the metal structure being Cu or a Cu-based alloy. A passivation layer is arranged over the metal structure, the passivation layer comprising a first layer comprising CuSiN and a second layer comprising Si, N, and H, where, expressed in atomic numbers, the ratio of Si to N is equal to or greater than 3.3 / 4.

[0076] In Example 2, the subject of Example 1 can optionally include the fact that the ratio of Si to N is equal to or greater than 1.

[0077] In Example 3, the item from Example 1 or 2 can optionally include the second layer containing 40 to 55 at% Si.

[0078] In Example 4, the subject of any preceding example may optionally include that the second layer contains 30 to 45 at% N.

[0079] In Example 5, the subject of any preceding example may optionally include that the second layer contains 12 to 17 at% H.

[0080] In Example 6, the subject of any preceding example may optionally include the first layer comprising a CuSiN layer with a thickness of 1 to 15 nm.

[0081] In Example 7, the subject of Example 6 may optionally include that the first layer further comprises a CuSi layer with a thickness of 0 to 200 nm, wherein the CuSi layer is arranged below the CuSiN layer.

[0082] In Example 8, the subject of any preceding example may optionally include the fact that the second layer has a layer thickness of 40 to 500 nm.

[0083] In Example 9, the subject of any preceding example may optionally include that the semiconductor device comprises an active region, a chip edge and an edge termination region separating the active region from the chip edge, wherein the second layer extends over at least a portion of the edge termination region to near or to the chip edge.

[0084] In Example 10, the object of any preceding example may optionally contain a third layer arranged between the first layer and the second layer, the third layer comprising aluminium oxide.

[0085] In Example 11, the subject of any preceding example may optionally include an imide layer arranged above the passivation layer.

[0086] In Example 12, the subject of any preceding example may optionally include that the semiconductor device is a high-voltage device.

[0087] In Example 13, the subject of any preceding example may optionally include the metal structure comprising one or more of the following components: a chip pad, a gate runner, and / or a field plate of the semiconductor device.

[0088] In Example 14, the subject of any preceding example may optionally include that the semiconductor device is a vertical device or a lateral device.

[0089] In Example 15, the subject of any preceding example may optionally include that the semiconductor device is an IGBT, MOSFET, JFET, P-FET, N-FET, AFET, planar gate transistor, field plate trench transistor, super junction transistor, or diode.

[0090] Example 16 is a method for fabricating a semiconductor device, the method comprising: providing a semiconductor substrate; forming a metal structure over the semiconductor substrate, wherein the metal of the metal structure is Cu or a Cu-based alloy; and forming a passivation layer over the metal structure, wherein the formation of the passivation layer comprises: forming a first layer comprising CuSiN, and forming a second layer comprising Si, N and H, wherein, expressed in atomic numbers, the ratio of Si to N is equal to or greater than 3.3 / 4.

[0091] In Example 17, the subject of Example 16 may optionally include the formation of the first layer comprising: forming an initial CuSi layer; and exposing the CuSi layer to a nitrogen-containing plasma.

[0092] In Example 18, the subject of Example 16 or 17 may optionally include the formation of the CuSi layer by thermal decomposition of a gaseous Si compound, in particular silane.

[0093] In Example 19, the subject of one of Examples 16 to 18 may optionally include the formation of the second layer involving the exposure of the first layer to a Si- and N-containing plasma.

[0094] Although specific embodiments have been presented and described herein, those skilled in the art will recognize that a multitude of alternative and / or equivalent embodiments can be used instead of the specific embodiments presented and described without departing from the scope of the present invention. The present application is intended to cover all adaptations or variations of the specific embodiments described herein. Therefore, it is intended that this invention be limited only by the claims and their equivalents.

Claims

[1] Power semiconductor device (100) comprising: a semiconductor substrate (110); a metal structure (120) arranged above the semiconductor substrate (110), wherein one metal of the metal structure (120) is Cu or a Cu-based alloy; and a passivation layer (130) arranged above the metal structure (120), wherein the passivation layer (130) comprises a first layer (130_1) comprising CuSiN, and a second layer (130_2) comprising Si, N and H, wherein the ratio of Si to N, expressed in atomic numbers, is equal to or greater than 3.3 / 4, wherein the power semiconductor device (100) comprises an active region (102), a chip edge (104) and an edge termination region (103) that separates the active region (102) from the chip edge (104), wherein the second layer (130_2) extends over at least a part of the edge termination region (103) to near the chip edge (104) or to the chip edge (104). [2] Power semiconductor device (100) according to claim 1, wherein the ratio of Si to N is equal to or greater than 1. [3] Power semiconductor device (100) according to claim 1 or 2, wherein the second layer (130_2) has 40 to 55 at% Si. [4] Power semiconductor device (100) according to one of the preceding claims, wherein the second layer (130_2) has 30 to 45 at% N. [5] Power semiconductor device (100) according to one of the preceding claims, wherein the second layer (130_2) has 12 to 17 at% H. [6] Power semiconductor device (100) according to one of the preceding claims, wherein the first layer (130_1) contains a CuSiN layer with a thickness of 1 to 15 nm. [7] Power semiconductor device (100) according to claim 6, wherein the first layer (130_1) further comprises a CuSi layer having a thickness of 0 to 200 nm, wherein the CuSi layer is arranged below the CuSiN layer. [8] Power semiconductor device (100) according to one of the preceding claims, wherein the second layer has a layer thickness of 40 to 500 nm. [9] Power semiconductor device (100) according to any one of the preceding claims, further comprising: a third layer arranged between the first layer (130_1) and the second layer (130_2), the third layer comprising aluminium oxide. [10] Power semiconductor device (100) according to any one of the preceding claims, further comprising: an imide layer arranged above the passivation layer (130). [11] Power semiconductor device (100) according to any of the preceding claims, wherein the power semiconductor device (100) is a high-voltage device. [12] Power semiconductor device (100) according to any of the preceding claims, wherein the metal structure (120) comprises one or more of the following elements: a chip pad, a gate runner and / or a field plate of the power semiconductor device (100). [13] Power semiconductor device (100) according to any of the preceding claims, wherein the power semiconductor device (100) is a vertical device or a lateral device. [14] Power semiconductor device (100) according to any of the preceding claims, wherein the power semiconductor device (100) is an IGBT, MOSFET, JFET, P-FET, N-FET, AFET, planar gate transistor, field plate trench transistor or super junction transistor or a diode. [15] Method for manufacturing a power semiconductor device (100), comprising: Providing a semiconductor substrate (110) (S1); Forming a metal structure (120) over the semiconductor substrate (110) (S2), wherein one metal of the metal structure (120) is Cu or a Cu-based alloy; and Forming a passivation layer (130) over the metal structure (120) (S3), wherein forming the passivation layer (130) comprises: Forming a first layer (130_1) that contains CuSiN, and Forming a second layer (130_2) comprising Si, N and H, wherein the ratio of Si to N in atomic numbers is equal to or greater than 3.3 / 4, wherein the power semiconductor device (100) comprises an active region (102), a chip edge (104) and an edge termination region (103) separating the active region (102) from the chip edge (104), wherein the second layer (130_2) extends over at least a part of the edge termination region (103) to near the chip edge (104) or to the chip edge (104). [16] Method according to claim 15, wherein forming the first layer (130_1) comprises: Formation of an initial CuSi layer (130_1a) (S3_1); and Exposure of the CuSi layer (130_1a) to a nitrogen-containing plasma. [17] Method according to claim 16, wherein the CuSi layer (130_1a) is formed by thermal decomposition of a gaseous Si compound, in particular silane. [18] Method according to any one of claims 15 to 17, comprising forming the second layer (130_2): Exposure of the first layer (130_1) to a Si- and N-containing plasma.

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