Method for diagnosing power cables, test device for diagnosing the same and computer program

Abstract

A method for diagnosing a power cable, the method comprising receiving test data relating to a measurement on the power cable; providing an equivalent circuit (1) of the power cable having a plurality of equivalent circuit blocks (2, 3, 6, 7), each having series-connected first and second conductor networks (4, 5), wherein the first conductor network (4) takes into account the skin effect of the power cable and the second conductor network (5) takes into account the proximity effect of the power cable; determining the parameters of the equivalent circuit (1) based on the received test data; and performing the diagnosis using the determined parameters (R, L, M, G, C).

Description

TECHNICAL FIELDThe invention relates to a method for diagnosing power cables, preferably high-power cables, having the features of the preamble of claim 1, in particular a fault diagnosis method, as well as a test device for diagnosing such a power cable, as well as a computer program and a data carrier in connection therewith.The following background is intended merely to provide information necessary to understand the context of the inventive concepts and concepts disclosed herein. Therefore, this background section may contain patentable articles and should not be considered as prior art per se.BACKGROUNDThe use of high-current cables in energy transmission systems poses various technical challenges which can be addressed by a precise modeling of these cables. Modeling plays a key role in identifying, analyzing, and solving problems that may arise in connection with high current transmission.A central technical problem that can be solved by modeling is the overheating of high-current cables. As a result of the intensive current flow through these cables, heat is generated, which can lead to an increase in the operating temperature. The modeling enables the simulation of thermal effects and the analysis of heat generation in different operating scenarios. By identifying overheating risks, suitable measures can be taken to protect the cables from damage and ensure reliable power transmission.Another problem concerns the electromagnetic fields generated by high current cables. These fields may affect adjacent electronic systems and result in disturbances. Modeling allows for the accurate prediction of these electromagnetic effects and allows for the development of appropriate shielding measures to minimize interference and optimize overall performance of the transmission system.Power losses in high-current cables also present a technical challenge. Modeling allows for analysis of various factors that contribute to power losses, including the ohmic resistance of the cable and the capacitive effects. On this basis, optimizations may be made to increase energy transfer efficiency and minimize energy loss.Modeling also plays a key role in predicting the transient behavior of high-current cables, especially during switching operations. Transient currents can result in voltage spikes that affect the stability of the system. By creating models that take account of the dynamic behavior of the cables under different operating conditions, protection mechanisms can be designed to ensure the integrity of the system and prevent undesirable effects.A further area in which modeling of high-current cables is of decisive importance relates to the selection of suitable materials. The physical properties of the materials directly affect the performance and reliability of the cables. By integrating material models into the overall models, different scenarios can be analyzed and the optimal material composition for the specific requirements identified.In summary, the precise modeling of high-current cables helps to solve technical problems associated with, for example, overheating, electromagnetic fields, power losses, transient behavior, or material selection. These models allow for informed decisions to be made to improve the efficiency and reliability of high current transmission systems while accommodating the challenges associated with the transmission of large amounts of electrical energy.The object of the invention is to eliminate disadvantages from the prior art, in particular to provide a better diagnosis of power cables.SUMMARYThis summary serves to introduce a selection of features and concepts of the invention that are discussed further below in the specification. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.According to the invention, the above object is achieved by the features of the independent claims.Specifically, the object is achieved by a method for diagnosing (high) diagnostic signals, preferably remote diagnosis and / or fault diagnosis. The method includes receiving test data related to a measurement at the power cable. The method includes providing an equivalent circuit of the power cable having a plurality of equivalent circuit blocks. Each spare circuit block of the plurality of spare circuit blocks has first and second ladder networks connected in series. The first conductor network takes into account the skin effect of the power cable. The second conductor network takes into account the proximity effect of the power cable. The method includes determining the parameters of the equivalent circuit based on the received test data. The method includes performing the diagnostic using the determined parameters.The invention has the advantage that accuracy and prediction of the state of the dimensioned power cable can be improved.By way of illustration, the skin effect refers to the concentration of electric current at the outer surface of a conductor of the power cable at higher frequencies. This occurs due to the interaction of electric fields that force the current density to concentrate on the outer layers of the conductor of the power cable. Thus, as the frequency increases, the current in the conductor of the power cable may tend to be confined to the outer layers, resulting in less utilization of the entire conductor cross-section. The proximity effect occurs when multiple parallel conductors of the power cable carry high frequency currents. In this case, the electric fields of the adjacent conductors of the power cable influence each other. This may result in the current in the conductor tending to concentrate on the side closer to the adjacent conductor of the power cable. As a result, the usable cross section of the conductor is divided non-uniformly, which can lead to an increase in the effective resistance and to additional losses.Said measurement may comprise impedance measurements having a frequency dependence. The impedance measurement values resulting from the impedance measurements can be present in a time- and / or frequency-resolved manner.The test data can be provided by the impedance measurement device mentioned below. The test data can be converted by the impedance measuring device directly from the impedance measurement values as raw data into a corrected / prefiltered format which contains corrected / prefiltered time- and / or frequency-resolved impedance measurement values. The cleaning or prefiltering can in particular filter out measured values which are below a first threshold value and / or above a second threshold value. The first threshold may correspond to a minimum value of possible impedance values of the power cable, and the second threshold may correspond to a maximum value of possible impedance values of the power cable.The term conductor network can be understood here to mean that it is not the term "line" per se, but rather a type of step conductor or layer conductor. In this case, the stages, or also layers mentioned herein, can be similar to one another, for example in that the same number and / or type of elements occurs therein, in this case resistance and coil (inductance in the first conductor network or mutual inductance in the second conductor network).The parameters can be the values occurring in the equivalent circuit for resistors, self-inductances, mutual inductances, conductances and / or capacitances.Advantageous embodiments of the invention are specified in the dependent claims.The first conductor network may comprise a resistor-inductor conductor network. The second conductor network may comprise a resistor-mutual inductance conductor network. The resistor-inductor conductor network and the resistor-mutual-inductor conductor network can each have the same number of inductors and resistors. In the case of the first conductor network, the inductances can be self-inductances. In the case of the second conductor network, the inductances can be mutual inductances.Modeling can thereby be simplified.A number of elements of the first ladder network may correspond to or be unequal to a number of elements of the second ladder network. The number of elements of the respective first conductor networks of the plurality of spare circuit blocks may be the same. The number of elements of the respective second conductor networks of the plurality of spare circuit blocks may be the same.Thus, a simple model for improved power cable diagnosis can be provided.The respective second conductor networks of series-connected standby switching blocks of the plurality of standby switching blocks can have mutual inductances coupled. The mutual inductances can form the inductances of the respective second conductor networks.With the mutual inductances, the proximity effect can be modeled better and the energy system can be adapted thereto.Both the first conductor network and the second conductor network may be parameterized in the low frequency range and high frequency range based on the measurement on the power cable. The low frequency range may include a range of 10 Hz to 50 Hz or 500 kHz. The high frequency range may comprise a range above 1 kHz, for example up to 10 kHz.Negative influences can thus be divided into different regions and analyzed better.The first conductor network may comprise two, three or more stages / layers of a combination of resistor and inductor. The second conductor network may comprise two, three or more stages / layers of a combination of resistor and mutual inductance. A stage / layer number of the first and / or second conductor networks may be the same.Each stage / layer of the first and / or second conductor networks may comprise exactly two elements, resistance and inductance. An input terminal of each first conductive network may be connected to each resistor of the corresponding first conductive network. An output terminal of each first conductor network may be connected to exactly one (self) inductance of the corresponding first conductor network.An input terminal of each second conductive network may be connected to each resistor of the corresponding second conductive network. An output terminal of each second conductor network can be connected to exactly one (mutual) inductance of the corresponding second conductor network.A first stage / layer resistor of the first / second ladder network may be connected to an inductance of the first and second stage / layers of the first / second ladder network. Generally speaking, a resistor of the nth stage / layer of the first / second ladder network may be connected to an inductance of the nth and n+1th stage / layer of the first / second ladder network. Herein, n may be a positive integer >1. Further, it may be said that an inductance of the n-th stage / layer of the first / second ladder network may be connected to an inductance of the n+1-th stage / layer of the first / second ladder network and an inductance of the n-1-th stage / layer of the first / second ladder network.For example, the power cable may be a multi-phase high-current cable. The application range can thereby be accurately defined.The above-mentioned object is also achieved by a computer program. The computer program comprises instructions which, when the computer program is executed by a computer or by the test apparatus mentioned below, cause the computer or the test apparatus to execute or initiate the method described above or at least one of the steps thereof. The computer program can be, for example, a module for starting / operating the computer or the test apparatus as described herein.The above-mentioned object is also achieved by a data carrier. The computer program can be stored on the machine-, processor- or computer-readable data carrier, for example on a permanent or rewritable storage medium. This also includes the computer program being able to be provided on a server or a cloud server for download, e.g. via a data network such as the Internet or a communication connection such as a wireless connection.The above object is also achieved by a test apparatus for diagnosing a power cable. The test apparatus has an impedance measuring device. The impedance measuring device is designed to apply a test signal to the power cable. The impedance measurement device is configured to acquire or provide test data based on the test signal in response to the power cable. The test apparatus has a processor. The processor is configured to determine parameters of an equivalent circuit of the power cable based on the test data. The processor is configured to perform the diagnostic using the determined parameters. The equivalent circuit has a plurality of equivalent circuit blocks. The plurality of spare circuit blocks each have first and second ladder networks connected in series. The first ladder network takes into account the skin effect. The second conductor network takes into account the proximity effect of the power cable.This can improve the reliability and accuracy in the diagnosis of power cables and, in particular, the effect on high-power source and electric machine.In other words, the invention relates to a modelling method for power cables in electric drives. In particular, a high-frequency model in the form of an electrical circuit for modelling power cables with an outer shield is created. The cable model takes into account both capacitive and inductive coupling. In comparison with conventional techniques, the frequency-dependent mutual inductances between the different phases of the cable system are realized by a so-called resistor-mutual inductance conductor network. The method presented herein may also model other components with frequency dependent mutual inductance due to inductive coupling, including electric machines.A high frequency model in the form of an electrical circuit for power cables with an outer shield can be created. The high frequency model takes into account both capacitive and inductive coupling. Thus, frequency dependent mutual inductances can be implemented under different phases. The cable model can be used to predict the overvoltage behavior at motor connections in inverter-fed operation.For explanation, a cable system including three-phase conductors and an outer shield is used as an example. The cable model may consist of circuits for differential mode (differential mode) and common mode (common mode). The push-pull mode circuits for each phase and the shield of the cable system may extend from one cable end to another cable end and each include a plurality of push-pull units (also referred to herein as push-pull circuit blocks) connected in series. Each of the push-pull units described above has a circuit branch structure that takes into account the skin effect and another circuit branch structure that takes into account the proximity effect. The circuit branch structure taking into account the skin effect is referred to as a resistor-inductor-conductor network and is intended to model an impedance varying with frequency. In contrast, the circuit branch structure taking into account the proximity effect is referred to as a resistor-mutual inductance conductor network and is intended to model a frequency-varying mutual inductance (mutual impedance). The circuit branch structure taking into account the proximity effect may consist of a network of resistors and mutual inductances. The network of resistors and mutual inductances may include resistors and mutual inductances connected in series and in parallel. Here, a resistor and a mutual inductance may be connected in series to form a first branch circuit and a first layer of the network, respectively. The resistor of the first layer can be connected in parallel to a second branch circuit of resistor and mutual inductance or form a second layer of the network. The resistor of the second branch circuit may be connected in parallel to a third branch circuit or form a third layer of the network. In general, it can be stated that the resistor of the n-th branch circuit can be connected in parallel to the n+1-th branch circuit or can form an n+1-th layer.The common mode circuit can be established for the three phases of the conductors of the cable. For each phase, the common mode units (also referred to herein as common mode circuit blocks) extend from the terminals of the cable system or the connection points between the differential mode units for shielding. The common mode unit comprises resistors and capacitors.In the implementation of models, each phase conductor in the cable and the outer shield may have two or three push-pull units connected in series, respectively. The resistor-mutual inductance conductor network in each push-pull unit may comprise two or three layers of resistors and mutual inductances in each push-pull unit. Similarly, the Skin effect resistor-inductor conductor network may comprise two or three layers of resistors and inductors in each push-pull unit.The parameters of the individual elements of the equivalent circuit can first be preestimated based on the actually measured impedance spectrum. Subsequently, the deviation of the impedance spectrum from the measured impedance spectrum calculated on the basis of the preestimated circuit model can be used as a cost function. Finally, using a parameter optimization algorithm, the values of all parameters can be iterated and a minimum value of the cost function determined, wherein an optimum value of all parameters can be determined. The parameter optimization method may take into account the similarity among different phases and different push-pull units as follows. For similarity among different push-pull units, the scaling factor between the parameters of the same phase at corresponding locations in the different push-pull units may be in a range of 0.8 to 1.2. To ensure similarity among the three phases, the initial parameter values of a phase are first estimated for the components in that phase. Then, the parameters of the components at the same locations in the other phases become proportional to the parameters of the component in the one phase. The proportionality coefficients are in a range from 0.8 to 1.2. in particular, the method for constructing the high-frequency models for power cables with an outer shield can be used.In still other words, the invention relates to modeling methodology for power cables (herein referred to as power cables) in electric machines. For example, a method is proposed for determining the maximum voltage at motor connections in order to avoid defects due to overvoltage behavior. In shielded power cables having multiple phases, the following effects can influence the voltage behavior: self-inductance (skin effect), mutual inductance (proximity effect) and capacitive couplings between the phases of the power cable and the shield. In this case, in particular the frequency-dependent mutual inductance of the different phases of a three-phase cable system can be taken into account. Likewise, the frequency dependence of the capacitive couplings can be taken into account herein, integrated in the model. For a full description of these effects, a network structure, including frequency dependencies, can be modeled and parameterized. In order to be able to predict the overvoltage behavior more accurately, for example at motor connections, the power cables are measured and the model of the network structure is then parameterized. The results can then be used to accurately design the parameters for the control technology.Thus, a method may be envisioned that may determine the voltage response on shielded multiple phase power cables. In this case, for example, cable parameters measured in order, b) parameterizing the model of the network structure, determining an overvoltage behavior taking into account the frequency-dependent variables of self-inductances, mutual inductances and capacitive couplings, e), and f) a control technique can be designed to be applied, for example, to motor connections (for electric mobility, wind turbines, etc... ).Although some of the aspects described above relate to the method or the test apparatus, these aspects can also correspondingly apply to the respective other aspects.In one example, the test device may be implemented using hardware circuits, software means, or a combination thereof. Thus, a plurality of units of the test apparatus can each be realized in a single physical unit, for example if a plurality of functions are implemented in software. The units of the test apparatus can also be implemented in hardware modules. The units of the test apparatus are each to be understood as functional units which are not necessarily physically separated from one another. Thus, the test device may be implemented at least partially as a computer, field programmable logic array (FPGA), field programmable gate array (FPGA), microcontroller, CPU (e.g., with multiple cores), graphics processor unit (GPU), application specific integrated circuit (ASIC), and / or digital signal processor (DSP).In the test apparatus, for example, methods related to pipelining of the test data can be used. In this case, instead of an entire instruction in one clock cycle of the processor used in the test apparatus, only a sub-task thereof, for example a part of the test data, is processed. In this case, the different sub-tasks of a plurality of commands are processed simultaneously. Furthermore, methods in the sense of multithreading can be applied to the test data and further developments thereof, for example simultaneous multithreading of the test data. This allows better utilization of the processors due to parallel use of a plurality of processor cores. In this case, the test device can be designed to be scalar or superscalar. The processor contained in the test device can be connected to a buffer memory of the test device, which can temporarily store the test data before and / or after the processing of the test data or the part thereof. The buffer memory may be integrated in a volatile memory of the test device, e.g. a (D)RAM, or in a permanent memory of the test device, e.g. a non-volatile memory device such as an SSD. As a result, a performance of the test apparatus can be increased.All technical and scientific terms used herein have the meaning that corresponds to the general understanding of the person skilled in the art in the technical field of electrical energy technology; they are to be interpreted on the basis of the definitions found in the dictionary or the technical jargon about this technical field. Where technical terms are used incorrectly herein and thus do not express the technical idea of the present invention, these can be replaced by technical terms that provide a person skilled in the art with a correct understanding.The terms "first", "second" are intended to distinguish components from one another only. For example, a first component may be referred to as a second component and a second component may be referred to as a first component. It should be noted that these terms and all numerical data ("one", "two", etc.) are to be understood as not exhaustive of the scope of protection, but are also to be understood as exhaustive of the disclosure content. For example, the term "two ABC" may mean either "exactly two ABC" or "two or more ABC". For example, this can also make it possible to disclose a sequence.If it is stated here that one component is "connected" to another component or "communicates" therewith, this can mean, for the purpose of the present disclosure, that these components can also be directly connected or communicate with one another. The term "direct" indicates that no further component is present therebetween.The method steps described herein should not be construed as requiring them to be performed in a particular order unless expressly or implicitly stated otherwise, for example, if these method steps cannot be interchanged for technical reasons. The method steps can also be carried out directly one after the other (without further intermediate steps) and / or continuously.BRIEF DESCRIPTION OF THE DRAWINGSFurther objectives, features, advantages and possible applications will become apparent from the following description of embodiments, which are to be understood as non-limiting, with reference to the associated drawings. Shown therein are: FIG. 1 is a view showing an equivalent circuit of a power cable; FIG. 2 is another view showing an equivalent circuit of a power cable in a three-phase system; FIG. 3 is a view of a method for diagnosing the power cable; and FIG. 4 is a view of a test apparatus for diagnosing the power cable.The reference numerals used in the drawings and their meaning are summarized in the list of reference numerals at the end of this description. The same or similar components in the drawings are always provided with the same or similar reference numerals. Detailed explanations of known functions and structures will be omitted as far as they depart from the invention.DETAILED DESCRIPTION OF THE DRAWINGSThe method and test apparatus will now be described with reference to the embodiments. Without being limited thereto, specific details are set forth in order to provide a further understanding of the invention.FIG. 1 is a view showing an equivalent circuit 1 of a power cable. FIG. 2 is another view exemplarily showing an equivalent circuit of a power cable in a three-phase system to make the application of the embodiments shown in FIG. 1 comprehensible.FIG. 3 shows a view of a method S 0 for diagnosing the power cable. In connection with FIG. 1, FIG. 3 will be explained below.The method S 0 begins in S 1 with receiving test data relating to a measurement at the power cable.Before, during or as a result thereof, an equivalent circuit 1 of the power cable is established or provided in S 2. The equivalent circuit 1 has a plurality of equivalent circuit blocks, here shown in the form of the first and second common mode circuit blocks 2 and 6 (common mode equivalent circuit blocks) and the first and second differential mode circuit blocks 3 and 7 (differential mode equivalent circuit blocks). The first and second common mode circuit blocks 2 and 5 may be connected respectively in front of and behind the first and second common mode circuit blocks 3 and 7. Each of the first and second push-pull circuit blocks 3 and 7 has series-connected first and second conductor networks 4 and 5. the first conductor network 4 relates to the skin effect of the power cable and the second conductor network 5 relates to the proximity effect of the power cable.In S 3, the parameters of the equivalent circuit 1 are determined based on the received test data. The parameters include R1-R6, L1-L3, M1-M3, G1-G3, C1-C4, R1λ-R6λ, L1λ-L3λ, M1λ-M3λ, G1λ-G3λ, and C1λ-C4λ. Here, λ indicates a coefficient of proportionality that is obtained based on the parameters of the equivalent circuit 1 assumed before the determination in S 3 and the impedance measurement on the power cable.In S 4, a diagnosis is then performed using the determined parameters. In this case, a prediction can be made about a voltage behavior, in particular overvoltage behavior, for example at motor connections in inverter-fed operations. In this case, a possible application, production or use of the power cable can be adapted or improved. Thus, future predictions due to the extended equivalent circuit 1 of the power cable may become more accurate and thereby more reliable. Overall, costs, for example production costs, can thus also be saved.The method steps illustrated as blocks of the block diagram in FIG. 3 can be depicted, for example, essentially in a machine-, processor- or computer-readable data carrier and can thus be executed by a computer, in particular a test apparatus 8 or a processor 9, as described, for example, below with reference to FIG. 4. Examples can furthermore be or relate to a computer program which contains a program code for executing at least part of the method steps from FIG. 3 when the computer program is executed on the computer, in particular the test apparatus 8 or the processor 9. An example may also include volatile memory 10 or persistent memory 11, also described below with respect to FIG. 4, for example, that are machine, processor, or computer readable and encode machine-executable, processor-executable, or computer-executable programs with instructions that cause execution of some or all of the method steps.FIG. 4 is a schematic block diagram illustrating the test apparatus 8 for diagnosing the power cable. The test apparatus 8 implements one or more steps of the method S 0 as illustrated in FIG. 3. In particular, the test device 8 provides functionality, such as computer software, running on the test device 8 and executing one or more steps of the method S 0.The term test data used herein can contain, in particular, frequency-dependent impedance measurements or impedance measured values.In particular, the test device 8 may execute instructions related to the test data, which are contained in the computer program described herein, and cause the test device 8 to execute or initiate the one or more steps of the method S 0.It is contemplated herein that the test device 8 will take any suitable physical form. As an example, the test device 8 may be embodied at least in part as an embedded computer, system on chip (SOC), single board computer (SBC), server, and / or user equipment (UE). The test device 8 may be unified or distributed; span one or more locations; span one or more machines or data centers; or be located in a cloud that may include cloud components in a network. The test device 8 can execute or initiate one or more steps of the method S 0 without substantial spatial or temporal limitation. As an example, the test device 8 may execute or initiate one or more steps of the method S 0 in real time, in parallel or in batch mode. The test device 8 can execute or initiate at different times or at different locations, step(s) of the method S 0.The test device 8 has at least one or more of the following components: the processor 9, the volatile memory 10, the permanent memory 11, a bus 12, an arbiter 13, one or more interface(s) 14, an impedance measurement device 15, a main power supply 16 and an auxiliary power supply 17. The interconnection of the components of the test device 8 is structured as in FIG. 4 merely for the sake of simplicity. In particular, the interconnection and connection can differ in the implementation on the basis of signal processing and signaling.The processor 9 has means for executing instructions related to the test data, e.g., the computer program described herein. For example, the processor 9 may load the instructions associated with the test data included in the computer program described herein, e.g., from the volatile memory 10 and / or the persistent memory 11, and then execute the instructions, which in turn causes the processor 9 to execute or initiate the one or more steps of the method S 0 as illustrated, e.g., in FIG. 3. The processor 9 may have an internal register / cache for the test data, for the instructions associated with the test data and / or for associated addresses. The processor 9 may comprise an FPGA, ASIC, DSP, microcontroller, CPU and / or GPU for accessing the internal register / cache. As an example, to execute the instructions associated with the test data, processor 9 may fetch, decrypt, and execute them from internal register / cache of processor 9, volatile memory 10, or persistent memory 11; and then write a result to internal register / cache of processor 9, volatile memory 10, or persistent memory 11.As an example, processor 9 may include an instruction cache, a data cache, and / or a translation buffer (TLB). The instructions associated with the test data in the instruction cache may be copies of instructions in the volatile memory 10 and / or persistent memory 11, and the instruction cache may accelerate the fetch of these instructions associated with the test data by the processor 9. The test data in the data cache may be copies of data for the instructions currently executing on the processor 9 and related to the test data in the volatile memory 10 and / or persistent memory 11. The results of the previous instructions executed on the processor 9 and associated with the test data can be provided for access by subsequent instructions to be executed on the processor 9 and associated with the test data, or for writing to the volatile memory 10 and / or permanent memory 11. The data cache may speed up the read or write operations of the processor 9. The addresses in the TLB associated with the test data may be address references to addresses in the volatile memory 10 and / or persistent memory 11 to speed up virtual address translation for the processor 9.The volatile memory 10 may be a dynamic RAM (DRAM) or a static RAM (SRAM). The volatile memory 10 can be embodied in particular as the data carrier described herein, on which the computer program described herein can be stored at least temporarily. Moreover, the volatile memory 10 may be a single or multi-channel RAM. Volatile memory 10 may include main memory for storing instructions related to the test data for processor 9, which then executes these instructions; or may include the test data for processor 9 that processor 9 uses to operate on. As an example, the test device 8 may load these commands from persistent storage 11 or another source (such as another computer, network, or cloud) into volatile storage 10. Processor 9 may then load these instructions from volatile memory 10 into the internal register / cache of processor 9. To execute these instructions, processor 9 may fetch and decode these instructions from the corresponding internal register / cache. During or after execution of these instructions, processor 9 may write a result (which may be intermediate or final results) to the internal register / cache. The processor 9 can then write the result to the volatile memory 10.For example, processor 9 only executes the instructions associated with the test data in internal register / cache of processor 9 or volatile memory 10 (as opposed to persistent memory 11), and only operates on the test data in internal register / cache of processor 9 or volatile memory 10 (as opposed to persistent memory 11).The permanent memory 11 has a mass storage device, for example a non-volatile mass storage device (NVM), for the test data or the commands associated with the test data. The permanent memory 11 can be designed in particular as the data carrier described herein, on which the computer program described herein can be stored. As an example, the persistent memory 11 may be a flash memory, in particular SSD or eMMC. The permanent memory 11 can store the test data in an erasable or non-erasable manner. The permanent memory 11 can be located in the test device 8, i.e. internally or externally thereto.The processor 9 can be connected directly or indirectly, for example via the arbiter 13, to the permanent memory 11. In this case, the connection can be configured via a clock bus, command bus and data bus. This is shown only schematically with reference to the bus 12 in FIG. 4. The permanent memory 11 receives instructions related to the test data and the test data related to a clock signal which is specified by the processor 9 on the clock bus. In this case, the clock signal clocks the reception of the commands associated with the test data and the test data. The processor 9 sends a command related to the test data to the persistent memory 11 via the command bus. Further, the processor 9 sends the test data corresponding to the command to the persistent memory 11 via the data bus or receives the test data from the persistent memory 11 via the data bus.In one example, the persistent memory 11 may have a clock pin via which the clock signal is received at the persistent memory 11. The clock signal may be a write enable signal and / or read enable signal. The persistent memory 11 may further have first and second input / output (I / O) pins. The test data is received at the permanent memory 11 synchronously with the clock signal via the first I / O pin. The persistent memory 11 may further include a command / address buffer, control logic, and an I / O buffer. The command / address buffer operates at a first speed of operation and, in synchronism with the clock signal, buffers the command and corresponding address received via the second I / O pin and associated with the test data. The one I / O buffer operates at the first operation speed and buffers the test data as read data from the NVM and writes the test data as write data into the NVM, respectively. The first and second I / O pins may be coincident. Here, the clock signal may be formed by first and second clock signals, in which the first clock signal switches only in a period in which the command and the address (both related to the test data) are received from the persistent memory 11, and the second clock signal switches only in a period in which the test data are received from the persistent memory 11. The first operation speed corresponds to a data input speed between the persistent memory 11 and the processor 9. the control logic controls an operation with respect to the NVM based on the buffered command and the buffered address (both related to the test data). Here, the control logic operates at a second operating speed, which is lower than the first operating speed, and corresponds to an internal operating speed of the permanent memory 11.The bus 12 may be understood herein as a test device 8 subsystem that transfers the test data and / or electrical power between the test device 8 components. The (one) bus 12 can connect the components of the test device 8 to one another via the same set of lines. The bus 12 may be configured for dedicated communication of the test data between two or more of the components of the test device 8. The bus 12 may be a system bus via which the processor 9 is connected to the other components of the test device 8. In this case, the bus 12 can be synchronous-the acceptance of the test data takes place bidirectionally with a clock edge of a clock of the bus 12-and / or asynchronous-no clock pulse, but a handshake takes place to accept the test data. In such a semi-synchronous system bus, bus 12 is clocked, but control lines allow wait cycles to also use slow components, such as persistent memory 11, over bus 12.Arbiter 13 may be provided for at least partial control over bus 12. The arbiter 13 can be understood as a coprocessor subordinate to the processor 9. The arbiter 13 controls the access to the bus 12 associated with the test data based on a two-way handle or three-way handle. Arbiter 13 simultaneously receives multiple BREQs from different components of test device 8 via bus 12, Arbiter 13 sorts the BREQs by priority and passes them sequentially-in a pipeline-to processor 9. Once the processor 9 has received the BREQ, the processor 9 sends the BGRT to the arbiter 13 or directly to the component of the test device 8 sending the BREQ. A subordinate BREQ of the BREQs in the pipeline-e.g. from another component of the test device 8-is forwarded to the processor 9 in response to a BGRT sent by the processor 9 with respect to the BREQ that is predominant in the pipeline and is related to at least a part of the test data. The BGRT related to the subordinate BREQ is sent from the processor 9 to the arbiter 13 after the at least a part of the test data is processed. For example, arbiter 13 may, in turn, send a pipeline-more-down BREQ-e.g., referring to another portion of the test data-of the BREQs to processor 9 in response to the BGRT referring to the down stream BREQ. Similarly, in response to each BGRT from processor 9, arbiter 13 may send a respective related BGA to processor 9. In the case of the procedure described herein, a BGA can also be completely dispensed with. This saves overhead in communication between the components of the test device 8.Bus 12 may also include a data bus, address bus, and control bus. In this case, the test data between the components of the test device 8 are transmitted bidirectionally via the data bus. The address bus is served solely by the processor 9 and transmits memory addresses which are unidirectionally related to the test data. The control bus is controlled solely by the arbiter 13, e.g. in the sense of a watchman, and passes control of it to the processor in the pipelined manner described above to control the transfer of test data.The interface(s) 14 may enable frequency dependent impedance measurements at the power cable, for example, in a vicinity of the test device 8. The interface(s) 14 may be connected to an impedance measurement device (e.g., external) that couples to the processor 9 of the test device 8. The interface(s) 14 may have device and / or software drivers, which allow the processor 9 to drive the interface(s) 14 in order to obtain measured values (the frequency-dependent impedance measured values) from the impedance measuring device, on which the test data are based or which are represented by the test data.The interface(s) 14 enable the test device 8 to communicate with a network, e.g. Bluetooth, WLAN, mobile radio system and / or at least part of the Internet. The interface(s) 14 provide means for communicating (such as packet-based communication) the test data between the test device 8 and other communication participants, e.g., to the network connected to the test device 8 (wired-via cable, e.g., optical connection-and / or wireless-via antenna).The test device 8 as New Radio (NR) UE can be used in narrow band (NB) internet of things (IoT) applications, in which only occasional and small amounts of data are transmitted in uplink (UL), such as the test data. For example, the test data may be transmitted when the test device 8 is in a Radio Resource Control (RRC) state that requires a considerable amount of electrical power from the main power supply 16 or the auxiliary power supply 17. However, since the amount of NB-IOT data is small, the test data can be transmitted less frequently and more efficiently. In particular, the different RRC states of the test device 8 consume different amounts of resources, and therefore the transition between the RRC states can efficiently reduce the network resources. The test device 8 may be in one of the following states, respectively: (NR) RRC_CONNECTED state, (NR) RRC_INACTIVE state, and (NR) RRC_IDLE state.When the test device 8 is off (e.g., when no electric power is supplied from the main power supply 16 and / or the auxiliary power supply 17), the test device 8 is in a disconnected state and is not in any of the three RRC states. After the test device 8 is switched on, the test device 8 can first transition into the RRC_IDLE state. In the RRC_IDLE state, the test device 8 may attempt to establish a wireless connection with a serving base station (e.g., gNB - not shown) and transition to the RRC_CONNECTED state. After the transition of the tester 8, the tester 8 may also be released from the RRC_CONNECTED state to return to the RRC_IDLE state. However, after the initial transition to the RRC_CONNECTED state, the test device 8 may transition to the RRC_INACTIVE state to more efficiently utilize the network resources. The RRC_INACTIVE state of the test device 8 may be enabled, resumed, or suspended to transition back to the RRC_CONNECTED state. In addition, the test device 8 can be released from the RRC_INACTIVE state and again transition to the RRC_IDLE state. The RRC_INACTIVE state minimizes the latency and reduces the signaling load, thereby more efficiently utilizing the network resources and reducing the power consumption of the test device 8 in the transmission of the test data.For example, the test device 8 may be part of a 4-stage random access channel (RACH) transmission scheme that includes transmitting four messages (Msg1, Msg2, Msg3, and Msg4) prior to transmitting the test data to the serving base station. Here, the tester 8 may perform random access by the tester 8 transmitting a RACH preamble - e.g., Msg1 - on a RACH resource. The serving base station may respond with a random access response (RAR), e.g., Msg2. The test device 8 may then transmit a radio resource control (RRC) connection request - e.g. Msg3 - in the physical uplink shared channel (PUSCH) (e.g. NR-PUSCH). The serving base station may then respond with an RRC Connection Setup - e.g. Msg4 - which completes the initial access process of the test device 8. This RACH mode is an inefficient way of transmitting the test data, since only after the four messages is there a transmission of the test data between the test device 8 and the serving base station.As another example, the test device 8 may be part of an early data transmission (EDT) method that includes transmitting two messages (Msg1 and Msg2) prior to transmitting the test data to the serving base station. That is, in this EDT mode, the tester 8 may transmit the test data in message 3 (Msg3), and the serving base station may transmit the downlink (DL) data in message 4 (Msg4) of the (legacy) 4-step RACH mode. This manner of transmitting the test data is more efficient than the 4-step RACH mode. The test device 8 may continue to transmit / receive UL / DL data packets in EDT mode after Msg4 in the RRC_IDLE state or RRC_INACTIVE state.The test device 8 can also transmit the test data at a predefined event via the interface(s) 14. This predefined event may be termination of successful establishment of a communication connection with a network. In this case, the test device 8 can retrieve the test data located in the volatile memory 10 and forward them via the interface(s) 14 in packets via the mobile radio system.The main power supply 16 supplies at least one or more of the components of the test device 8 with electrical power, e.g. via the bus 12. In particular, the main power supply 16 charges the auxiliary power supply 17 with electrical power, for example from outside the test device 8, e.g. in case the main power supply 16 is connected to the power source outside the test device 8. Here, the main power supply 16 may be a preferred component used for supplying power to the components of the test apparatus 8, and may include, for example, an accumulator or a battery. The main power supply 16 can have further components such as voltage regulators, DC voltage stabilizers, series regulators, buck converters and / or boost converters in order to meet the corresponding requirements of the components of the test apparatus 8. Here, the main power supply 16 may have either a dedicated fixed power supply connection to the external power source such as a power grid or a detachable power supply connection for charging the battery or the battery of the main power supply 16. To this end, the main power supply 16 may include an inverter to provide a predetermined DC power supply from a connected AC power source as the external power source. The predetermined DC power supply can also already be provided by a connected DC power source as the external power source. The DC power supply can be regulated via the above-mentioned voltage regulators and supplied to the components of the test apparatus 8 as set DC power supplies.The auxiliary power supply 17 is connected via the bus 12 to the volatile memory 10 and / or the permanent memory 11. The auxiliary power supply 17 is charged by the electric power of the main power supply 16. The auxiliary power supply 17 can be arranged inside or outside the test apparatus 8, or inside or outside the volatile memory 10 and / or the permanent memory 11. For example, the auxiliary power supply 17 may be accommodated on a main board of the test apparatus 8 in order to supply the volatile memory 10 and / or the permanent memory 11 with an auxiliary power. The auxiliary power supply 17 can be embodied in particular in the form of a supercapacitor, an accumulator and / or a battery. The power capacity / energy capacity of the main power supply 16 may be many times, for example, at least 10 times or 50 times larger than the power capacity / energy capacity of the auxiliary power supply 17.The processor 9 monitors changes in the electric power supplied from the main power supply 16. In the event of a sudden power failure, e.g., when the power source outside the test device 8 is disconnected from the main power supply 16 or the main power supply 16 subsides or fails for another reason, and the processor 9 determines that the electrical power supplied from the main power supply 16 to one or more of the components of the test device 8 has fallen below a threshold, e.g., 0.8 or 0.75 of an operating power of the main power supply 16, the processor 9 causes the auxiliary power supply 17 to take over a remaining supply power for a shutdown operation of the test device 8. The shutdown process comprises supplying at least the processor 9, the volatile memory 10 and / or the permanent memory 11 with electric power for the time of the shutdown process. During the shutdown process, the test data currently located in the volatile memory 10 and / or the test data currently processed in the processor 9, for example in the register / cache of the processor 9, are transferred from the volatile memory 10 and / or the processor 9 into a meta area of the permanent memory 11. For this purpose, the meta range of the permanent storage 11 can be reserved separately for the shutdown process.The processor 9, in the case of a starting operation of the test apparatus 8 in which the main power supply 16 again provides the operating power, loads the test data from the meta region of the permanent memory 11 in order to enable a faster data processing. After the starting process, the meta region of the permanent memory or successively during the starting process can be released.At this point, it should be pointed out that all the parts described above, viewed alone and in any combination, in particular the details shown in the drawings, are claimed as essential to the invention. Modifications thereof will be apparent to those skilled in the art.LIST OF REFERENCE CHARACTERS1 Equivalent circuit 2 First push-pull circuit block 3 First push-pull circuit blocks 4 First conductor network 5 Second conductor network 6 Second push-pull circuit block 7 Second push-pull circuit blocks 8 Test device 9 Processor 10 Volatile memory 11 Permanent memory 12 13 Bus arbiter 14 Interface(s) 15 Impedance measurement device 16 Main power supply 17 Auxiliary power supply R Resistor L Self-inductance M Mutual inductance G Conductance C GND Capacitance λ Scaling factor U First phase V Second phase W Third phase Ground p parallel s serial λ Proportionality coefficient

Claims

A method (S0) for diagnosing a power cable, the method (S0) comprising: receiving (S1) test data relating to measurement on the power cable; providing (S2) an equivalent circuit (1) of the power cable having a plurality of equivalent circuit blocks (2, 3, 6, 7) each having first and second conductor networks (4, 5) connected in series, wherein the first conductor network (4) takes into account the skin effect of the power cable and the second conductor network (5) takes into account the proximity effect of the power cable; determining (S3) the parameters (R, L, M, G, C) of the equivalent circuit (1) based on the received test data; and performing (S4) the diagnosis using the determined parameters (R, L, M, G, C).Method (S0) according to claim 1, characterized in that the first conductor network (4) comprises a resistor-inductor conductor network and the second conductor network (5) comprises a resistor-mutual-inductor conductor network, and that the resistor-inductor conductor network and the resistor-mutual-inductor conductor network each comprise the same number of inductors and resistors.Method (S0) according to claim 1 or 2, characterized in that a number of elements of the first conductor network (4) corresponds to or is unequal to a number of elements of the second conductor network (5), and that the number of elements of the respective first conductor networks (4) of the plurality of spare switch blocks (2, 3, 6, 7) is equal and / or the number of elements of the respective second conductor networks (5) of the plurality of spare switch blocks (2, 3, 6, 7) is equal.Method (S0) according to one of the preceding claims, characterized in that the respectively second conductor networks (5) of series-connected replacement circuit blocks of the plurality of replacement circuit blocks (2, 3, 6, 7) have mutual inductances (M) coupled to one another.Method (S0) according to any of the preceding claims, characterized in that both the first conductor network (4) and the second conductor network (5) are parameterized on the basis of a measurement on the power cable in the low frequency range and high frequency range.Method (S0) according to one of the preceding claims, characterized in that the first conductor network (4) has two, three or more layers of a combination of resistance and inductance, and in that the second conductor network (5) has two, three or more layers of a combination of resistance and mutual inductance.Method (S0) according to one of the preceding claims, characterized in that the power cable is a polyphase high-current cable.A computer program, characterized in that the computer program comprises instructions which, when the computer program is executed by a computer, cause the computer to execute or initiate the method (S0) according to any one of the preceding claims or at least one of the steps thereof.Data carrier (10, 11), characterized in that the computer program according to claim 8 is stored on the data carrier (10, 11).Test device (8) for diagnosing a power cable, the test device (8) comprising: an impedance measurement device (15) configured to apply a test signal to the power cable and to acquire or provide test data based on the test signal in response to the power cable; A processor (9) configured to determine parameters (R, L, M, G, C) of an equivalent circuit (1) of the power cable based on the test data and to perform the diagnosis using the determined parameters (R, L, M, G, C), wherein the equivalent circuit (1) comprises a plurality of equivalent circuit blocks (2, 3, 6, 7) each comprising first and second conductor networks (4, 5) connected in series, and wherein the first conductor network (4) takes into account the skin effect of the power cable and the second conductor network (5) takes into account the proximity effect of the power cable.

Images