METHOD FOR MANUFACTURING SEMICONDUCTOR COMPONENTS AND VERTICAL POWER SEMICONDUCTOR DEVICE

Abstract

A method for fabricating semiconductor devices in a magnetic Czochralski semiconductor body made of silicon MCZ is proposed. The method involves processing the silicon MCZ semiconductor body (102) by an oxidation process at temperatures above 1150 °C and below 1220 °C. Subsequently, platinum (Pt) is introduced into the silicon MCZ semiconductor body (102).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a method for manufacturing semiconductor devices, in particular to a method for manufacturing semiconductor devices in a magnetic Czochralski semiconductor body made of silicon MCZ. Furthermore, the present disclosure relates to a vertical power semiconductor device. BACKGROUND

[0002] Semiconductor devices, such as power semiconductor diodes or field-effect switching devices such as a junction field-effect transistor (JFET), a metal-oxide-semiconductor field-effect transistor (MOSFET), and an insulated-gate bipolar transistor (IGBT), are typically used for various applications, including, but not limited to, switches in power supplies and power converters, electric vehicles, and air conditioning systems. Such semiconductor devices are typically manufactured at the wafer level. As wafer size increases, the manufacturing cost per chip typically decreases. Larger silicon wafers, i.e., silicon wafers with a diameter of at least 12", are currently only available as magnetic Czochralski-grown silicon wafers.8" diameter silicon wafers are also available as float-zone grown silicon wafers, but they are comparatively expensive and can exhibit comparatively large resistance variation due to banding. During single crystal growth using the Czochralski (CZ) process and high-temperature processing of the wafers, crystal defects such as crystal-derived particles (COPs) or dislocation loops or slip lines can form. Agglomerated vacancy-related defects are commonly known as D-defects or COPs. Such defects can facilitate the formation of generation centers in the wafer, leading to enhanced leakage current and weakening of subsequently formed gate dielectrics.

[0003] Accordingly, there is a need to improve a method for manufacturing semiconductor devices in a silicon semiconductor body. SUMMARY

[0004] One example of the present disclosure relates to a method for fabricating semiconductor devices in a magnetic Czochralski semiconductor body made of silicon MCZ. The method includes processing the silicon MCZ semiconductor body through an oxidation process at temperatures above 1120°C and below 1220°C or at temperatures above 1150°C and below 1210°C. Thereafter, the method further includes introducing platinum into the silicon MCZ semiconductor body.

[0005] Another example relates to a vertical power semiconductor device. The vertical power semiconductor device includes a magnetic Czochralski semiconductor body made of silicon MCZ, which has a first surface and a second surface opposite the first surface. The vertical power semiconductor device further includes an anode electrically connected to the silicon MCZ semiconductor body via the first surface. The vertical power semiconductor device further includes a cathode electrically connected to the silicon MCZ semiconductor body via the second surface. The vertical power semiconductor device further includes a drift region in the silicon MCZ semiconductor body. The drift region includes platinum and oxygen. An oxygen concentration in the drift region has a value in a range of 1.0 × 10 17 cm- 3 up to 4 × 10 17 cm- 3The concentration of crystal-derived particles, COPs, is a maximum of 3000 per 300 mm wafer. The size of the COPs, for example, is between 0.1 µm and 0.3 µm.

[0006] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate examples of fabricating semiconductor devices in a silicon MCZ semiconductor body and, together with the description, serve to explain principles of the examples. Further examples are described in the following detailed description and claims. Fig. 1A and Fig. 1B are schematic views illustrating a method of manufacturing semiconductor devices in a silicon MCZ semiconductor body. Fig. 2A to Fig. 2D are schematic views illustrating configuration examples of furnace supports of a thermal processing apparatus and associated slide line arrangements in processed semiconductor bodies. Fig. 3 is a schematic cross-sectional view illustrating the formation of semiconductor device elements in a silicon MCZ semiconductor body. Fig. Figure 4 is a schematic cross-sectional view illustrating the formation of a barrier structure in the silicon MCZ semiconductor body. Fig. 5A to Fig. 5C are schematic cross-sectional views for illustrating configuration examples for forming the barrier structure by forming a trench extending into the silicon MCZ semiconductor body. Fig. 6 is a schematic plan view illustrating a configuration example for forming the barrier structure by a closed loop trench in the silicon MCZ semiconductor body. Fig. 7 is a schematic plan view illustrating a configuration example of an arrangement of a barrier substructure aligned with a support or contact point of a furnace support supporting the silicon MCZ semiconductor body. Fig. 8 is a partial cross-sectional view illustrating a configuration example of a vertical power device. DETAILED DESCRIPTION

[0008] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific examples of methods of fabricating semiconductor devices in a silicon MCZ semiconductor body. It should be understood that other examples may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. For example, features illustrated or described for one example may be used in conjunction with other examples to yield yet another example. It is intended that the present disclosure include such modifications and variations. The examples are described using specific language that should not be construed as limiting the scope of the appended claims.The drawings are not to scale and are for illustrative purposes only. Corresponding elements are designated by the same reference numerals throughout the various drawings unless otherwise indicated.

[0009] The terms "having," "containing," "including," "comprising," and the like are open-ended and indicate the presence of the specified structures, elements, or features, but do not preclude the presence of additional elements or features. The articles "a," "an," and "the" are intended to include both the plural and the singular, unless the context clearly indicates otherwise.

[0010] Ranges specified for physical dimensions include the limits. For example, a range for a parameter y from a to b is a ≤ y ≤ b. The same applies to ranges with a limit such as "at most" and "at least."

[0011] The terms "on" and "over" should not be construed to mean only "directly on" and "directly above." Rather, when an element is positioned "on" or "over" another element (e.g., a layer is positioned "on" or "over" another layer, or "on" or "over" a substrate), another component (e.g., another layer) may be positioned between the two elements (e.g., another layer may be positioned between a layer and a substrate if the layer is "on" or "over" the substrate).

[0012] The adjectives "first" and "second" may be used herein to distinguish between features designated by the same term, e.g., first / second modifications or first / second parting surface. The adjectives do not exclude the order of fabrication of the features. Thus, the first modifications may be formed before or after the second modifications are formed.

[0013] The term "crystal-derived particles" (COPs), as used in this specification, is intended to describe a cavity in the semiconductor material, typically formed by an agglomeration of vacancies during crystal growth and may include an outer silicon oxide shell. The risk of forming slip lines in the semiconductor substrate typically increases with the concentration and size of the COPs. Furthermore, COPs decorated with in-diffused heavy metals, such as Fe, Cu, Ni, can act as generation centers, improving the leakage current of the devices. The diameter of the COPs is typically below about 300 nm, more typically below 20 nm.

[0014] The description and drawings merely illustrate the principles of the disclosure. Furthermore, any examples provided herein are expressly intended to be illustrative only to assist the reader in understanding the principles of the disclosure and the concepts contributed by the inventor(s) to the advancement of the art. All statements describing principles, aspects, and examples of the disclosure, as well as specific examples thereof, are intended to include equivalents thereof.

[0015] It should be understood that the disclosure of multiple steps, processes, operations, steps, or functions disclosed in the specification or claims may not be construed as being in the specific order unless expressly or implicitly indicated otherwise, e.g., by terms such as "thereafter," for technical reasons. Therefore, the disclosure of multiple steps or functions does not limit them to any particular order unless those steps or functions are not interchangeable for technical reasons. Further, in some examples, a single step, function, process, operation, or step may include or be broken down into multiple sub-steps, functions, processes, operations, or steps.Such sub-steps may be included and be part of the disclosure of that single step unless they are expressly excluded.

[0016] One example of the present disclosure relates to a method for fabricating semiconductor devices in a magnetic Czochralski semiconductor body made of silicon MCZ. The method may include processing the silicon MCZ semiconductor body through an oxidation process at temperatures above 1120°C and below 1230°C or at temperatures above 1150°C and below 1210°C. Thereafter, the method may further include incorporating platinum, Pt, into the silicon MCZ semiconductor body.

[0017] The semiconductor devices may be arranged in chips. Each of the semiconductor devices may, for example, be an integrated circuit or a discrete semiconductor device. The integrated circuit or semiconductor device may be or include a power semiconductor device, e.g., a vertical power semiconductor device having a load current flow between the first surface and the second surface. The chips may be used, for example, in automotive, industrial power control, power management, metering solutions, and Internet of Things security applications. The chips may be or include a power semiconductor diode or a reverse-conducting power semiconductor insulated-gate bipolar transistor (power semiconductor RC-IGBT). For example, a power semiconductor device in the chips may be configured to conduct currents of more than 1 A, more than 10 A, or even more than 30 A.The semiconductor device in the chips may be further configured to block voltages between load terminals, e.g., between the emitter and collector of an RC-IGBT, or between the cathode and anode of a diode, in the range of several tens or several hundred or up to several thousand volts, e.g., 30 V, 40 V, 60 V, 80 V, 100 V, 400 V, 650 V, 1.2 kV, 1.7 kV, 3.3 kV, 4.5 kV, 5.5 kV, 6 kV, 6.5 kV, 10 kV.

[0018] During the oxidation process of the silicon MCZ semiconductor body, interstitial silicon atoms can be generated at the oxidizing surface and diffuse into the crystalline silicon MCZ semiconductor body. The generated interstitial silicon atoms, which move into a bulk of the crystalline silicon MCZ semiconductor body, occupy vacancies in the crystal lattice, thereby dissolving COPs by filling clusters of vacancies or voids of the COPs. The process can also lead to the rupture of an oxide layer lining an inner surface of the COPs. For this to happen, the temperature must be high enough to dissolve this oxide layer, which depends on the oxygen concentration within the wafer. For example, the oxidation process can be carried out for a duration of at least 20 minutes or even at least 1 hour. According to one example, the oxidation process can be carried out in a wet environment.

[0019] For example, platinum can be introduced into the silicon MCZ semiconductor body by diffusion from a Pt silicide layer and / or platinum implantation followed by annealing. The introduction of platinum can, for example, enable an improvement in switching properties by tuning the lifetime of minority charge carriers.

[0020] By combining the oxidation process at temperatures above 1120 °C and below 1230 °C or at temperatures above 1150 °C and below 1210 °C with a later introduction of platinum, the COPs can be effectively dissolved, but on the other hand, so-called slip lines can be created at such high temperatures, which can act as gettering centers for platinum, leading to higher leakage currents of the devices.

[0021] For example, the method may further include forming semiconductor device elements in the silicon MCZ semiconductor body at a first surface of the silicon MCZ semiconductor body by processing the silicon MCZ semiconductor body at the first surface. Forming semiconductor device elements in the silicon MCZ semiconductor body at the first surface may be performed after the oxidation process at temperatures above 1120°C and below 1230°C or at temperatures above 1150°C and below 1210°C and before introducing platinum into the silicon MCZ semiconductor body from the front or back of the wafer.

[0022] The first surface may, for example, be a front surface or a top surface of the silicon MCZ semiconductor body, and the second surface may be a back surface or a rear surface of the silicon MCZ semiconductor body. High-temperature processing of the chips at temperatures above 600°C on the first surface of the silicon MCZ semiconductor body may, for example, be completed or completed before introducing platinum into the silicon MCZ semiconductor body and / or before processing the silicon MCZ semiconductor body on a second surface opposite the first surface.

[0023] Forming the semiconductor device elements may include processes for defining the chips adjacent to the first surface of the silicon MCZ semiconductor body. The processes may, for example, include at least one doping process for forming doped regions in the silicon MCZ semiconductor body at the first surface. The at least one doping process may include an ion implantation process followed by thermal activation of dopants, a diffusion process that introduces the dopants into the silicon MCZ semiconductor body from a dopant source (e.g., a solid or gaseous diffusion source), an in-situ doping process during the formation of a semiconductor layer, e.g., by a layer deposition process, on a semiconductor base substrate, such as a wafer. The example doping processes may be combined in any way and repeated in any way, e.g.,depending on a desired number and profile of the doped regions to be formed in the silicon MCZ semiconductor body at the first surface. Example doped regions are emitter and collector regions, body region(s), body contact region(s), field stop region(s), anode region(s), cathode region(s). The processes may also include trench etching processes. The trench etching processes may be used to form trenches, such as gate electrode trenches, field electrode trenches, multi-electrode trenches (e.g., combining gate and field electrodes in one trench), trenches for edge termination structures, contact trenches for providing electrical contact to doped regions in the silicon MCZ semiconductor body. The processes may also include forming insulating layer(s), conductive layer(s), or any combination thereof in the trenches.Example insulating or conductive layers include, but are not limited to, gate or field electrodes formed by doped semiconductor layers (e.g., doped polycrystalline silicon or metal or metal alloy), oxide layers (e.g., silicate glass, deposited SiO2, thermal SiO2), nitride layers (e.g., Si3N4), high-k dielectric layers, low-k dielectric layers, dielectric spacers, or any combination thereof.

[0024] For example, the method may further include forming a wiring region over the first surface of the silicon MCZ semiconductor body after introducing platinum into the silicon MCZ semiconductor body.

[0025] Forming the wiring region may involve forming one or more than one, e.g., two, three, four, or even more, wiring levels. Each wiring level may be formed by a single or a stack of conductive layers, e.g., metal layer(s). For example, the wiring levels may include at least one of Cu, Au, AlCu, Ag, or alloys thereof. The wiring levels may, for example, be patterned lithographically. A dielectric interlayer structure may be formed between stacked wiring levels. Openings may be formed in the dielectric interlayer structure for electrically connecting different wiring layers. For example, contact plug(s) or contact via(s) or contact line(s) may be formed in the openings in the dielectric interlayer structure to connect parts, e.g.,Metal lines or contact areas of different wiring levels to electrically connect to each other. The wiring area may be arranged above an active area of ​​chips formed in the silicon MCZ semiconductor body. In some examples, the chips may include, in addition to the active area, an edge termination area at least partially surrounding the active area. The edge termination area may include a termination structure. In a blocking mode or in a reverse biased mode of the semiconductor devices formed in the chips, the blocking voltage between the active area and a field-free region drops laterally across the termination structure. The termination structure may, for example, include a junction termination extension (JTE) with or without a variation of lateral doping (VLD), one or more laterally separated guard rings, or any combination thereof.

[0026] For example, the method may further include forming a barrier structure in the silicon MCZ semiconductor body prior to the oxidation process at temperatures above 1120°C and below 1230°C, or at temperatures above 1150°C and below 1210°C. The barrier structure may prevent slip lines from undesirably propagating from their source region, e.g., support points of a furnace support supporting the silicon MCZ semiconductor body, into the active region of the semiconductor devices. Slip lines in the active region of the semiconductor devices may lead to undesirable electrical effects, such as a reduction in minority carrier lifetime and / or an increase in leakage currents caused by the decoration of the slip lines with heavy metal atoms.

[0027] For example, the silicon MCZ semiconductor body may include a chip region comprising active regions of the semiconductor devices. The silicon MCZ semiconductor body may further include a peripheral region disposed between the chip region and an edge of the silicon MCZ semiconductor body. The barrier structure may be disposed in the peripheral region outside the chip region.

[0028] For example, a lateral distance between the barrier structure and an edge of the silicon MCZ semiconductor body can have a value in a range of 500 µm to 5 mm or in a range of 1 mm to 3 mm. This can enable minimization of unwanted chip area losses and can further enable minimization of undesirable large widths or lateral extensions of the barrier structures. A specific width or lateral extension of the barrier structure, for example, makes it possible to effectively prevent the propagation of slip lines depending on the distance from the origin of the slip lines.

[0029] For example, the barrier structure can be a trench barrier structure. The trench barrier structure can partially or completely penetrate the silicon MCZ semiconductor body. For example, the trench(es) of the trench barrier structure can be formed by trench etching or laser processing. A surface of the trench(es) can subsequently be treated by an overetching process and / or by hydrogen treatment or by further etching processes. The trench(es) can stop the propagation of slip lines that, for example, impinge on the trench(es).

[0030] For example, the width of the barrier structure may have a value in a range from 100 nm to 10 µm or in a range from 200 nm to 5 µm. For example, the barrier structure may partially penetrate the silicon MCZ semiconductor body and may have a circular shape. The barrier structure may extend at least partially parallel to a perimeter or edge of the silicon MCZ semiconductor body.

[0031] For example, the barrier structure may include n barrier substructures laterally spaced from each other, where n is an integer in a range from 2 to 4. The number of barrier substructures may depend on the number of support or contact points between the silicon MCZ semiconductor body and a furnace support for performing the oxidation process according to the configuration examples described herein.

[0032] For example, an arrangement of the barrier substructures is configured to align with support points of a furnace support that supports the silicon MCZ semiconductor body during the oxidation process at temperatures above 1120 °C and below 1230 °C or at temperatures above 1150 °C and below 1210 °C. The arrangement may depend on the type of furnace used for the oxidation process, e.g., horizontal furnace or vertical furnace.

[0033] For example, a lateral extension of each of the barrier substructures exceeds three times a lateral distance to the edge of the silicon MCZ semiconductor body plus a lateral extension of a corresponding one of the support points. For example, a shape of the barrier substructures may be adapted to a wafer diameter of the silicon MCZ semiconductor body and may be slightly curved in the region of the contact or support points, for example. By adjusting a lateral extension (e.g., in the azimuthal direction) of the barrier substructures, a possible misalignment can be taken into account, as well as the lateral broadening of the sliding lines on their path from the origin point to the barrier substructures. For example, a lateral extension of the barrier substructures may have a value in a range of 5 mm to 2 cm, depending on the lateral distance to the edge of the silicon MCZ semiconductor body.

[0034] For example, forming the barrier structure may include forming a trench extending from a first surface of the silicon MCZ semiconductor body into the silicon MCZ semiconductor body. The trench may be formed by laser processing and / or etching.

[0035] For example, the method may further include reducing a thickness of the silicon MCZ semiconductor body by removing material of the silicon MCZ semiconductor body from a second surface opposite the first surface. The thickness may be reduced by grinding process(es), e.g., grinding, and / or etching process(es). Reducing the thickness may also be used to form a stabilizing ring at the wafer edge, for example, for thin wafer processing.

[0036] For example, the material of the silicon MCZ semiconductor body may be removed from the second surface at least to a bottom of the trench.

[0037] For example, forming the barrier structure may involve forming a trench extending from the second surface of the silicon MCZ semiconductor body into the silicon MCZ semiconductor body. For example, the trenches may be formed in the region of a stabilization ring geometry and the technology edge exclusion, if available. This may allow avoiding undesired interactions with the entire FEOL process chain. For example, the trenches may be placed where the stabilization ring will be ground for thin wafer processing at a later stage. This avoids sacrificing additional chip area for the barrier structure, which can instead be used for the semiconductor devices in the chips. For technologies that are not based on stabilization rings, e.g.In thick wafer technologies, the barrier structure can be positioned, for example, in the area of ​​the technology edge exclusion underneath.

[0038] For example, the method may further include reducing a thickness of the silicon MCZ semiconductor body by removing material of the silicon MCZ semiconductor body from the second surface opposite the first surface in a region where the trench is disposed.

[0039] For example, forming the barrier structure may include forming one or more vias in the silicon MCZ semiconductor body.

[0040] For example, forming the barrier structure may include forming a closed loop trench in the silicon MCZ semiconductor body. The closed loop trench may, for example, extend at least partially parallel to an edge of the silicon MCZ semiconductor body.

[0041] Details regarding structure or function or technical benefits of features described above with respect to a method of fabricating semiconductor devices in the silicon MCZ semiconductor body equally apply to the exemplary devices described herein, e.g., diodes or RC-IGBTs.

[0042] According to one configuration example, a vertical power semiconductor device may be formed by one of the methods described herein. The vertical power semiconductor device may include a drift region containing platinum and oxygen. An oxygen concentration in the drift region may have a value in a range of 1.0 × 10 17 cm -3 up to 4 × 10 17 cm -3The oxygen concentration can be achieved through the oxidation process according to the configuration examples described herein. The vertical power semiconductor device can be a diode or a reverse-conducting insulated-gate bipolar transistor.

[0043] A configuration example of a vertical power semiconductor device may include a magnetic Czochralski semiconductor body made of silicon MCZ, having a first surface and a second surface opposite the first surface. The vertical power semiconductor device may further include an anode electrically connected to the silicon MCZ semiconductor body via the first surface. The vertical power semiconductor device may further include a cathode electrically connected to the silicon MCZ semiconductor body via the second surface. The vertical power semiconductor device may further include a drift region in the silicon MCZ semiconductor body. The drift region may include platinum and oxygen. An oxygen concentration in the drift region may have a value in a range of 1.0 × 10 17 cm - 3 up to 4 × 10 17 cm -3The concentration of crystal-derived particles, COPs, may not exceed 3000 per 300 mm wafer.

[0044] For example, the oxygen concentration can have a maximum gradient in a region of 15 µm below the anode of 2 × 10 21 cm -4 or less than 5 × 10 20 cm -4 have.

[0045] Further details and aspects are mentioned in connection with the examples described above or below. Processing a silicon MCZ semiconductor body may include one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more examples described above or below.

[0046] The description and drawings merely illustrate the principles of the disclosure. Furthermore, any examples provided herein are expressly intended to be illustrative only to assist the reader in understanding the principles of the disclosure and the concepts contributed by the inventor(s) to the advancement of the art. All statements describing principles, aspects, and examples of the disclosure, as well as specific examples thereof, are intended to include equivalents thereof.

[0047] Further examples of structural or process features are explained below in conjunction with the accompanying drawings. Functional and structural details described with reference to the above examples apply equally to the exemplary embodiments illustrated in the figures and further described below.

[0048] Fig. 1A and Fig. 1B show schematic and exemplary views illustrating process features of fabricating semiconductor devices in a magnetic Czochralski semiconductor body 102 made of silicon MCZ.

[0049] The view of Fig. 1A shows a thermal processing tool 101, e.g., a horizontal or vertical furnace, for illustrating a feature of processing the silicon MCZ semiconductor body 102 through an oxidation process at temperatures T above 1120°C and below 1230°C or at temperatures above 1150°C and below 1210°C. The view is simplified, among other things, by illustrating a single silicon MCZ semiconductor body 102. In the thermal processing tool 101, a plurality of silicon MCZ semiconductor bodies 102 may be processed in parallel by arranging the plurality of silicon MCZ semiconductor bodies 102, for example, on a furnace support.

[0050] After the Fig. One or more processes may be performed during the oxidation process illustrated in Figure 1A. For example, the one or more processes may include front end of line (FEOL) processes for forming semiconductor device elements in the silicon MCZ semiconductor body 102.

[0051] After the one or more processes and with reference to Fig. 1B, platinum, Pt, is introduced into the silicon MCZ semiconductor body 102.

[0052] After introducing platinum into the silicon MCZ semiconductor body 102, as in Fig. 1B, one or more processes may be performed. For example, the one or more processes may include processes for forming a wiring region over the silicon MCZ semiconductor body 102.

[0053] The schematic side view of Fig. 2A illustrates a configuration example of a thermal processing tool 101 implemented as a horizontal furnace including a horizontal furnace support 1011 configured to support silicon MCZ semiconductor bodies 102. Referring to the schematic top view of the MCZ semiconductor body 102 of Fig. 2B, the heat processing in the heat processing system 101 may result in sliding lines 112 being formed at support or contact points between the silicon MCZ semiconductor bodies 102 and the horizontal furnace support 1011.

[0054] The schematic side view of Fig. 2C illustrates a configuration example of a thermal processing tool 101 implemented as a vertical furnace including a vertical furnace support 1012 configured to support silicon MCZ semiconductor bodies 102. Contact regions between the silicon MCZ semiconductor bodies 102 and the vertical furnace support 1012 are indicated by arrows. Referring to the schematic top view of the MCZ semiconductor body 102 of Fig. 2D, the heat processing in the heat processing system 101 can lead to sliding lines 112 that are formed at support or contact points between the silicon MCZ semiconductor bodies 102 and the horizontal furnace support 1011.

[0055] The schematic cross-sectional view of Fig. 3 is a simplified and exemplary illustration of the formation of semiconductor device elements 106 in the silicon MCZ semiconductor body 102 at the first surface 104 of the silicon MCZ semiconductor body 102 by processing the silicon MCZ semiconductor body 102 at the first surface 104. The semiconductor device elements 106 in the silicon MCZ semiconductor body 102 are illustrated in a simplified manner by a dashed line surrounding the portion of the silicon MCZ semiconductor body 102 where the semiconductor device elements are formed. The formation of the semiconductor device elements 106 in the silicon MCZ semiconductor body 102 at the first surface 104 may be carried out after the oxidation process at temperatures above 1120°C and below 1230°C or at temperatures above 1150°C and below 1210°C (see, for example, Fig. 1A) and before introducing platinum into the silicon MCZ semiconductor body 102 (see for example Fig. 1B).

[0056] The schematic cross-sectional view of Fig. Figure 4 is a simplified and exemplary illustration of the formation of a barrier structure 108 in the silicon MCZ semiconductor body 102 prior to the oxidation process at temperatures above 1150 °C and below 1220 °C (see, for example, Fig. 1A). The barrier structure 108 is configured to stop the propagation of slip lines. The silicon MCZ semiconductor body 102 includes a chip region 1101 with active regions of the semiconductor devices and a peripheral region 1102 disposed between the chip region 1101 and an edge E of the silicon MCZ semiconductor body 102. Wafer dicing at a later stage may result in the separation of the semiconductor devices (chips) from each other. The barrier structure 108 is disposed in the peripheral region 1102 outside the chip region 1101. For example, the peripheral region may be a region in which a stabilization ring geometry and / or a technology edge exclusion are located. For example, a lateral distance I1 between the barrier structure 108 and the edge E of the silicon MCZ semiconductor body 102 may have a value in a range from 500 µm to 5 mm.

[0057] With reference to the schematic cross-sectional view of Fig. 5A, forming the barrier structure 108 may include forming a trench 1081 extending from the first surface 104 of the silicon MCZ semiconductor body 102 into the silicon MCZ semiconductor body 102.

[0058] With reference to the schematic cross-sectional view of Fig. 5B, forming the barrier structure 108 may include forming a via 1082 in the silicon MCZ semiconductor body 102. The via 1082 penetrates the silicon MCZ semiconductor body 102 from the first surface 104 to the second surface 105 of the silicon MCZ semiconductor body 102.

[0059] With reference to the schematic cross-sectional view of Fig. 5C, forming the barrier structure 108 may include forming a trench 1083 extending from a second surface 105 of the silicon MCZ semiconductor body 102 into the silicon MCZ semiconductor body 102.

[0060] The schematic top view of Fig. 6 is based on one of the configuration examples of Fig. 5A or Fig. 5C and illustrates the formation of the barrier structure 108 by a closed loop trench in the silicon MCZ semiconductor body 102.

[0061] The schematic top view of Fig. 7 illustrates a configuration example of an arrangement of a barrier substructure 1084 aligned with a support or contact point P of a furnace support that supports the silicon MCZ semiconductor body 102 during the oxidation process at temperatures above 1120 °C and below 1230 °C or at temperatures above 1150 °C and below 1210 °C. The top view of Fig. 7 illustrates a portion of the silicon MCZ semiconductor body 102. The number of barrier substructures 1084 may depend on a number of support or contact points P of the furnace support that supports the silicon MCZ semiconductor body 102 during the oxidation process. For example, a lateral extent I3 of each of the barrier substructures 1084 may exceed three times a lateral distance I1 to the edge E of the silicon MCZ semiconductor body 102 plus a lateral extent I2 of a corresponding one of the support points.

[0062] A partial cross-sectional view of a configuration example of a vertical power semiconductor device 100 is shown in Fig. 8. The vertical power semiconductor device 100 may be, for example, a diode or a reverse-conducting insulated-gate bipolar transistor.

[0063] The vertical power semiconductor device 100 may include a silicon MCZ semiconductor body 102 having a first surface 104 and a second surface 104 opposite the first surface 104. The vertical power semiconductor device 100 further includes an anode A electrically connected via the first surface 104 to an anode region 114 in the silicon MCZ semiconductor body 102. The vertical power semiconductor device 100 further includes a cathode C electrically connected via the second surface 105 to a cathode region 116 in the silicon MCZ semiconductor body 102. The vertical power semiconductor device 100 further includes a drift region 1161 in the silicon MCZ semiconductor body 102. The drift region 1161 may be part of the cathode region 116. The cathode region 116 may include further doped regions, e.g., a field stop region and / or a cathode contact region.The drift region 1161 may contain platinum and oxygen. An oxygen concentration in the drift region 1161 may have a value in a range of 1.0 × 10 17 cm -3 up to 4 × 10 17 cm -3A concentration of crystal-derived particles, COPs, may be at most 3000 per 300 mm wafer. Thus, an upper limit for the average number of COPs within the power semiconductor device 100 can be calculated from the chip size of the power semiconductor device 100 and its proportion to the total wafer surface (300 mm × 300 mm × π). Alternatively, an upper limit for the average number of COPs within the power semiconductor device 100 can be calculated by dividing the above-specified wafer upper limit (3000 COPs per wafer) by the number of power semiconductor devices 100 that are sliced ​​from the wafer. It should be noted that the number of COPs per power semiconductor device 100 can vary considerably depending on the position on the wafer from which the respective power semiconductor device 100 is sliced.

[0064] The aspects and features mentioned and described together with one or more of the examples and figures described above may also be combined with one or more of the other examples to replace a similar feature of the other example or to additionally incorporate the feature into the other example.

[0065] Although specific embodiments have been illustrated and described herein, those skilled in the art will recognize that a variety of alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.

Claims

[1] A method of manufacturing semiconductor devices in a magnetic Czochralski semiconductor body (102) made of silicon MCZ, the method comprising: Processing the silicon MCZ semiconductor body (102) by an oxidation process at temperatures above 1120 °C and below 1230 °C; and thereafter Incorporation of platinum (Pt) into the silicon MCZ semiconductor body (102). [2] The method of the preceding claim, further comprising forming semiconductor device elements (106) in the silicon MCZ semiconductor body (102) at a first surface (104) of the silicon MCZ semiconductor body (102) by processing the silicon MCZ semiconductor body (102) at the first surface (104), wherein the forming of semiconductor device elements (106) in the silicon MCZ semiconductor body (102) at the first surface (104) is performed after the oxidation process at temperatures above 1120 °C and below 1230 °C and before introducing platinum (Pt) into the silicon MCZ semiconductor body (102). [3] The method of any preceding claim, further comprising forming a wiring region over the first surface (104) of the silicon MCZ semiconductor body (102) after introducing platinum (Pt) into the silicon MCZ semiconductor body (102). [4] The method of any preceding claim, further comprising forming a barrier structure (108) in the silicon MCZ semiconductor body (102) prior to the oxidation process at temperatures above 1120°C and below 1230°C, wherein the barrier structure (108) is configured to stop the propagation of slip lines (112). [5] The method according to the preceding claim, wherein the silicon MCZ semiconductor body (102) includes a chip region (1101) comprising active regions of the semiconductor devices, and a peripheral region (1102) arranged between the chip region (1101) and an edge (E) of the silicon MCZ semiconductor body (102), wherein the barrier structure (108) is arranged in the peripheral region (1102) outside the chip region (1101). [6] Method according to one of the two preceding claims, wherein a lateral distance (I1) between the barrier structure (108) and an edge (E) of the silicon MCZ semiconductor body (102) has a value in a range of 500 µm to 5 mm. [7] Method according to one of the three preceding claims, wherein the barrier structure (108) is a trench barrier structure. [8] Method according to the preceding claim, wherein a width of the barrier structure (108) has a value in a range of 100 nm to 10 µm. [9] The method of any one of the five preceding claims, wherein the barrier structure (108) includes n barrier substructures laterally spaced from each other, where n is an integer in a range of 2 to 4. [10] The method of the preceding claim, wherein an array of the barrier substructures is configured to be aligned with support points of a furnace support supporting the silicon MCZ semiconductor body (102) during the oxidation process at temperatures above 1120°C and below 1230°C. [11] The method of any one of the two preceding claims, wherein a lateral extent of each of the barrier substructures exceeds three times a lateral distance (I1) to the edge (E) of the silicon MCZ semiconductor body (102) plus a lateral extent of a corresponding one of the support points. [12] The method of any one of claims 4 to 11, wherein forming the barrier structure (108) includes forming a trench (1081) extending from a first surface (104) of the silicon MCZ semiconductor body (102) into the silicon MCZ semiconductor body (102). [13] Method according to the preceding claim, wherein the trench (1081) is formed by laser processing and / or etching. [14] The method of any one of the two preceding claims, further comprising reducing a thickness of the silicon MCZ semiconductor body (102) by removing material of the silicon MCZ semiconductor body (102) from a second surface (105) opposite the first surface (104). [15] Method according to the preceding claim, wherein the material of the silicon MCZ semiconductor body (102) is removed from the second surface (105) at least to a bottom of the trench. [16] The method of any one of claims 4 to 15, wherein forming the barrier structure (108) includes forming a trench (1083) extending from a second surface (104) of the silicon MCZ semiconductor body (102) into the silicon MCZ semiconductor body (102). [17] The method of any preceding claim, further comprising reducing a thickness of the silicon MCZ semiconductor body (102) by removing material of the silicon MCZ semiconductor body (102) from the second surface opposite the first surface in a region in which the trench (1081) is arranged. [18] The method of any one of claims 4 to 17, wherein forming the barrier structure (108) includes forming one or more through holes (1082) in the silicon MCZ semiconductor body (102). [19] The method of any one of claims 4 to 18, wherein forming the barrier structure (108) includes forming a closed loop trench in the silicon MCZ semiconductor body (102). [20] A vertical power semiconductor device formed by the method according to any one of the preceding claims, comprising a drift region including platinum (Pt) and oxygen, wherein an oxygen concentration in the drift region has a value in a range of 1.0 × 10 17 cm- 3 up to 4 × 10 17 cm -3 has. [21] A vertical power semiconductor device according to the preceding claim, wherein the vertical power semiconductor device is a diode or a reverse conducting insulated gate bipolar transistor. [22] Vertical power semiconductor diode, comprising: a magnetic Czochralski semiconductor body (102) made of silicon MCZ having a first surface (104) and a second surface (105) opposite the first surface (104); an anode electrically connected to the silicon MCZ semiconductor body (102) via the first surface (104); a cathode electrically connected to the silicon MCZ semiconductor body (102) via the second surface (105); a drift region in the silicon MCZ semiconductor body (102), wherein the drift region includes platinum (Pt) and oxygen, wherein an oxygen concentration in the drift region has a value in a range of 1.0 × 10 17 cm -3 up to 4 × 10 17 cm -3 and a concentration of crystal-derived particles (COPs) of no more than 3000 per 300 mm wafer. [23] Vertical power semiconductor device according to the preceding claim, wherein the oxygen concentration has a maximum gradient in a region of 15 µm below the anode of 2 × 10 21 cm -4 has.

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