High-speed memory chip and storage device

Abstract

The invention relates to a high-speed memory chip (2) with a high-speed data interface having parallel address lines and separate parallel data lines. According to the invention, it is characterized by an additional interface that uses combined address and data lines. The invention also relates to a storage device (1) with such a high-speed memory chip (2), the high-speed data interface of which is connected via a circuit board (5) to a system on a chip (6), for which purpose the connection points (4) of the high-speed data interface are soldered to connection elements of the circuit board (5).

Description

[0001] The invention relates to a high-speed memory chip with a high-speed data interface comprising parallel address lines and separate parallel data lines. The invention also relates to a storage device comprising such a high-speed memory chip.

[0002] High-speed memory chips with suitable high-speed data interfaces are known from the prior art. For example, these can be DRAM (Dynamic Random Access Memory) chips or SDRAM (Synchronous DRAM) with a high-speed data interface, such as LPDDR4 (Low Power Double Data Rate) according to the JEDEC standard.

[0003] In the realm of SRAM (Static Random Access Memory) chips, which are relatively slow from today's perspective, the use of multiple identical data interfaces on a single SRAM is a known principle. This is referred to as dual-ported RAM. US patent 10 019 401 B1 also discloses a configuration in which electronics with multiple parallel PCIe (Peripheral Component Interconnect Express) interfaces can be connected to a DRAM.

[0004] Typical high-speed memory chips usually have a high-speed data interface with parallel address lines and separate parallel data lines. This can, for example, be implemented as an LPDDR4 interface. If, for example, the stored data needs to be read out during operation via a measurement device for development purposes or to monitor functionality, this typically occurs via or at the so-called System on a Chip (SOC), i.e., ultimately at the device utilizing the memory chip or at its data connection. The problem here, however, is that this consumes bandwidth and thus already affects the device's functionality. Reading data from the high-speed memory chip via a measurement device used in parallel with its actual functionality is therefore not possible without causing interference, which represents a significant disadvantage.

[0005] A high-speed memory chip of this type is known from the 70V631S, High-Speed ​​3.3V 256K x 18 Asynchronous Dual-Port Static RAM, Datasheet, Renesas Electronics Corporation, September 2019. URL: https: / / www.renesas.com [accessed on 04.04.2025].

[0006] The object of the present invention is to further develop a high-speed memory chip with a high-speed data interface according to the preamble of claim 1 in such a way that the memory content can be accessed without affecting the bandwidth or speed of the data transmission through the high-speed data interface.

[0007] According to the invention, this problem is solved by a high-speed memory chip with the features of claim 1. Furthermore, a storage device according to claim 10 solves the problem. Further advantageous embodiments of the high-speed memory chip and / or the storage device are also described in the respective dependent claims.

[0008] The high-speed memory chip, as is common in the prior art, has a high-speed data interface with parallel address lines and separate parallel data lines. According to the invention, an additional interface is provided on the high-speed memory chip, which uses combined address and data lines. This implements an additional connection on the high-speed memory chip, allowing direct access to the memory cells of the high-speed memory chip. This enables access to the contents of the memory cells in parallel with the high-speed data interface and without affecting the data connection to the SoC. The high-speed memory chip is thus essentially given a lower-speed parallel interface to read the contents of its memory cells without impacting its actual functionality.

[0009] The requirements for high-speed data interfaces with parallel address lines and separate parallel data lines, such as LPDDR4, are relatively high, for example, regarding the length of the lines and their relative lengths. Designing an additional interface with combined address and data lines, such as PCIe, offers the advantage of significantly simpler handling in this respect. Such an interface is therefore considerably more robust. This allows the additional interface to be used only temporarily, for example, to connect it for a debugging process and then remove it again.

[0010] According to the invention, an implemented logic, which is typically present and configured to perform or initiate cyclic refreshes of the memory cells, is now additionally configured to enable access to the memory cells via the additional interface in parallel with access via the high-speed data interface. Therefore, in addition to the constructive implementation of the connection points for the additional interface, it is sufficient to slightly modify the existing chip-integrated logic.

[0011] According to the invention, this is achieved such that access to the memory cells via the additional interface is configured as a read-only access. This is entirely sufficient for the intended access and, at the same time, ensures that no manipulated data can be introduced into the system via the additional interface. This is of crucial importance, particularly in safety-critical applications, such as in the automotive sector.

[0012] Each chip typically comprises a chip package, which can be designed, for example, as a plastic package or simply as a coating on the silicon of the chip. A particularly advantageous embodiment of the high-speed memory chip according to the invention provides that this chip package has connection points for the high-speed data interface, with all these connection points being arranged on a first side of the chip package. Thus, in intended use, the connection points for the high-speed data interface are arranged, for example, on the underside, as is also common with high-speed memory chips from the prior art. According to an advantageous further development, they can be configured as a ball grind array.

[0013] A particularly advantageous embodiment of the high-speed memory chip according to the invention can provide that the chip package has additional connection points for the additional interface, these additional connection points being arranged on a second side of the chip package opposite the first side. The additional connection points for the additional interface are thus independently located on the other side, e.g., the top side of the chip or chip package, in its intended use. The high-speed memory chip can therefore be used like a conventional chip without requiring any modifications to the circuit board it is mounted on. Depending on the requirements, a chip with or without the functionality of the additional interface can then be used.If the chip with the additional interface could be manufactured at a sufficiently low cost, it would be conceivable to produce all chips with this additional interface in the future. The chip package could then be designed as needed to include the additional connection points or not.

[0014] If the additional connection points are present, a very advantageous design of the high-speed memory chip allows them to be configured such that they can be contacted via at least one attached contact element with spring-loaded poles. Such contact elements, or rather their poles, are commonly known as pogo pins. The contact element with these pogo pins can then simply be pressed onto the additional connection points to connect the additional interface. This represents a significant advantage, particularly when the additional interface is only temporarily connected, for example, for debugging purposes.

[0015] As mentioned above, the additional interface can be designed as a PCIe slot. This offers the advantage of easy handling with excellent connectivity options, for example via a USB cable.

[0016] A particularly advantageous embodiment of the 9th high-speed memory chip according to the invention further provides that the high-speed data interface is configured as a DDR (Double Data Rate) interface. It is particularly preferred that it be configured as one of the following interfaces: - LPDDR4 or higher generation LPDDR4; - DDR3 or higher generation DDR; - GDDR3 or higher generation GDDR3; - HBM (High Bandwidth Memory).

[0017] The term "higher generation" refers to the next generations of the respective interface. For example, for LPDDR4, JEDEC has now defined an LPDDR5 standard, which would be the next higher generation to LPDDR4.

[0018] The high-speed memory chip itself is preferably designed as DRAM or SDRAM of generation 3 or higher.

[0019] The storage device according to the invention utilizes such a high-speed memory chip with a chip package. The high-speed data interface of the high-speed memory chip is connected to a system-on-a-chip (SoC) via a circuit board, with the connection points of the high-speed data interface being soldered to connection elements on the circuit board. This corresponds to the previously common use of such high-speed memory chips. The high-speed memory chip does not necessarily need to have the additional connection points and can, in this case, be used like a conventional high-speed memory chip. It is soldered to the circuit board to ensure a durable and reliable electrical connection.

[0020] However, it is particularly advantageous if, in such a storage device, the additional connection points for accessing the additional interface are located on the second side of the high-speed memory chip opposite the connection points for the high-speed data interface.

[0021] A highly advantageous embodiment of the memory device according to the invention can further provide a heat sink on this second side, which has at least one recess in the area of ​​the additional connection points for the additional interface. This ensures the cooling of the high-speed memory chip. In the area of ​​the additional connection points, it is typically sufficient for the heat to be dissipated via these connection points and an optionally attached contact element with the pogo pins. This allows for sufficiently uniform cooling of the entire surface of the high-speed memory chip.

[0022] In a further, highly advantageous embodiment of the memory device, the additional interface can be connected to a measuring instrument via at least one contact element with spring-loaded poles and a connecting cable. The contact element with the pogo pins can thus be placed on the surface of the high-speed memory chip and pressed down, preferably together with the heat sink, to ensure both the contact of the additional interface and cooling.

[0023] Further advantageous embodiments of the high-speed memory chip and / or the storage device result from the exemplary embodiment, which is described in more detail below with reference to the figure.

[0024] The only accompanying figure shows a schematic side view of a storage device according to the invention.

[0025] In Fig. Figure 1 shows a schematic side view of a storage device 1. In the embodiment shown here, this storage device 1 comprises a high-speed memory chip 2, of which essentially only its housing 3 is visible. The high-speed memory chip 2 can be, for example, a DRAM or an SDRAM, preferably of the third generation or higher. It has a known high-speed data interface, the connection points 4 of which are configured as a so-called ball grid array according to the JEDEC standard. In the representation of the Fig. In each case, only some of the identically depicted connection points 4 are marked with a reference symbol. These connection points 4 of the Ball Grid Array are now soldered to a circuit board 5 in a known manner and thus electrically contacted with the connection elements and conductor tracks located on this circuit board 5. The high-speed memory chip 2 can therefore be connected to a SoC 6 via its high-speed data interface, i.e., via the circuit board 5, which utilizes the high-speed memory chip 2 in a conventional and generally known manner.

[0026] To now discuss a representation of the Fig.To read data from the measurement technology indicated by point 7, it was previously always necessary to intervene in the area of ​​the connection on the circuit board 5 or in other connections of the SoC 6 in order to, for example, read the data stored in the high-speed memory chip 2 in parallel with the actual function of the storage device 1. This represents a significant disadvantage because bandwidth of the data connection and / or the SoC 6 is always required, meaning that the measurement technology always has a feedback effect on the storage device 1 and thus does not enable feedback-free measurement.

[0027] For this reason, it is now provided that additional connection points 10 are provided on the side 9 opposite the first side 8 of the chip package 3 with the connection points 4. These additional connection points 10 on the chip package 3, of which again only some are marked with a reference symbol, are now designed as endpoints for an additional interface.

[0028] The high-speed data interface can, for example, be implemented as conventional LPDDR4. It is connected to the SoC 6 via the connection points 4 in a standard manner through the circuit board 5. The connection points 10 for the additional interface can now be configured, for example, as PCIe interfaces. Parallel access to the memory cells of the high-speed memory chip 2 is now possible via such a PCIe interface as an additional interface on the high-speed memory chip 2, whose connection points 10 are located here on the second side 9, i.e., the top side, of the chip package 3. This can be achieved by slightly extending the logic integrated into the high-speed memory chip 2, which is already present for the cyclic refresh of the memory cells. A simple read access to the contents of the memory cells is sufficient.The slower access time of the PCIe interface compared to the LPDDR4 data interface is of minor importance for its functionality, as the primary purpose is to transfer the contents of memory cells to the measurement system (7) to, for example, verify processes, particularly for development work or troubleshooting. The robustness and simpler design of the PCIe interface compared to LPDDR4 offer significant advantages for practical use. For instance, it can be implemented with a relatively simple wiring harness.

[0029] In the embodiment shown here, a contacting element 11, equipped with so-called pogo pins 12, serves to connect the additional connection points 10 of the PCIe interface. These pogo pins 12 are spring-loaded contacts, so that pressing the contacting element 11 onto the chip housing 3 reliably establishes the electrical connection between the pogo pins 12 and the additional connection points 10. The contacting element 11 itself is then connected to the corresponding measuring equipment 7 via a cable or a circuit board, which is designated here by 13.

[0030] A heat sink 14, as is generally known and common practice, can now be attached to the chip housing 3. This heat sink 14 is specially designed here and has a recess in the area where the additional connection points 10 are located on the chip housing 3, so that the contact element 11 can be pressed onto the chip housing 3 despite the heat sink 14 being attached. Typically, the surface area of ​​the additional connection points 10 and the thermal conductivity of the pogo pins 12 are sufficient to adequately cool this area of ​​the high-speed memory chip 2 as well.

Claims

[1] High-speed memory chip (2) with a high-speed data interface with parallel address lines and separate parallel data lines and with an additional interface which uses combined address and data lines, characterized by an implemented logic which is configured to perform or initiate cyclic refreshes of the memory cells, and which is further configured to allow access to the memory cells via the additional interface in parallel to access via the high-speed data interface, wherein access via the additional interface to the memory cells is configured as a read-only access. [2] High-speed memory chip (2) according to claim 1 characterized by a chip package (3) which has connection points (4) for the high-speed data interface, wherein these connection points are all arranged on a first side (8) of the chip package (3). [3] High-speed memory chip (2) according to claim 2, characterized by , that the chip package (3) has additional connection points (10) for the additional interface, wherein these additional connection points (10) are arranged on a second side (9) of the chip package (3) opposite the first side (8). [4] High-speed memory chip (2) according to claim 3, characterized by , that the additional connection points (10) for the additional interface are designed in such a way that they can be contacted via at least one attached contacting element (11) with spring-loaded poles (12). [5] High-speed memory chip (2) according to claim 2, 3 or 4, characterized by , that the connection points (4) for the high-speed data interface are configured as a ball grind array. [6] High-speed memory chip (2) according to any one of the preceding claims, characterized bythat the additional interface is designed as a PCIe interface. [7] High-speed memory chip (2) according to any one of the preceding claims, characterized by that the high-speed data interface is designed as a DDR (Double Data Rate) interface. [8] High-speed memory chip (2) according to any one of the preceding claims, characterized by , that the high-speed data interface is configured as one of the following interfaces: - LPDDR4 or higher generation LPDDR4; - DDR3 or higher generation DDR; - GDDR3 or higher generation GDDR3; - HBM (High Bandwidth Memory). [9] High-speed memory chip (2) according to any one of the preceding claims characterized by its training as a DRAM or SDRAM chip of generation 3 or higher. [10] Storage device (1) comprising a high-speed memory chip (2) according to any one of claims 2 to 9, characterized by , that the high-speed data interface of the high-speed memory chip (2) is connected to a SoC (6) via a circuit board (5), for which the connection points (4) of the high-speed data interface are soldered to connection elements of the circuit board (5). [11] Storage device (1) according to claim 10, characterized by , that on the second side (9) of the chip housing (3) opposite the connection points (4) for the high-speed data interface a heat sink (14) is arranged which has at least one recess in the area of ​​the additional connection points (10) for the additional interface. [12] Storage device (1) according to claim 10 or 11, characterized by , that the additional interface can be connected to a measuring instrument (7) via at least one contacting element (11) with spring-loaded poles (12) and a wiring or circuit board (13) connected to it.

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