SYSTEM FOR ELIMINATIVE INDUCTIVITY IN T-TYPE MULTI-STAGE CONVERTERS

Abstract

A multiphase inverter for an electric drive system comprises multiple T-type multi-stage power converters positioned between a high-voltage DC power supply and an electric machine. Each of the multiple T-type multi-stage power converters is an integrated solid-state circuit containing a positive DC power bus, a negative DC power bus, a neutral bus, and multiple semiconductor switches arranged in a stacked configuration. The multiple semiconductor switches are interconnected via the positive DC power bus, the negative DC power bus, and the neutral bus.

Description

INTRODUCTION

[0001] The concepts described here generally refer to vehicles with electrified powertrains or propulsion systems equipped with DC power supplies that deliver electrical energy to multi-phase inverters to control the operation of one or more electrical machines.

[0002] High-voltage, high-power multilevel inverters (MLIs) have gained attention due to the rapidly accelerating electrification trend of the transportation sector toward high-capacity mass transit systems, such as electric aircraft, trains, and ships. MLIs such as NPC and bidirectional three-phase / three-level (T-type) inverters offer high-voltage and high-power capabilities, but require stacked DC link capacitors with a zero-sequence connection for the zero-sequence voltage vector. This zero-sequence connection to the stacked DC link capacitor can generate a zero-sequence current oscillating at three times the fundamental frequency, which can lead to capacitor voltage imbalance and overvoltage stress on capacitors and switching devices.

[0003] A multiphase inverter circuit can create an inherent power loop in which a high current flows from a DC link capacitor to a high side of the multilevel inverter and then to a low side of the multilevel inverter and back. The power loop can generate a magnetic field that forms a parasitic inductance.

[0004] Because multiphase inverters operate at higher switching frequencies, even small parasitic inductances can cause problems such as, but not limited to, ringing and / or electromagnetic interference (EMI).

[0005] The current flow path determines the size of the power loop, which in turn determines the size of the generated magnetic field and thus the size of the parasitic inductance, and the current flow path is defined by the topology of the circuit, where the topology of the circuit can affect the size of the parasitic inductance. DESCRIPTION

[0006] In view of the above discussion, it is reasonable to develop a system and method for canceling mutual inductance for a multiphase inverter including a plurality of T-type multilevel power converters with a topology that reduces the parasitic inductance within the multiphase inverter.

[0007] The concepts disclosed herein relate to a system for a multi-phase inverter for an electric powertrain comprising a plurality of T-type multi-level power converters arranged between a high-voltage direct current (DC) supply and an electric machine, wherein each of the plurality of T-type multi-level power converters is a solid-state integrated circuit (IC) comprising: a positive DC power bus; a negative DC power bus; a neutral bus; and a plurality of semiconductor switching switches arranged in a stacked arrangement. The plurality of semiconductor switches are interconnected via the positive DC power bus, the negative DC power bus, and the neutral bus, the plurality of semiconductor switches comprising: a first semiconductor switch connected to a first node;a second semiconductor switch connected to the first semiconductor switch at the first node, the first semiconductor switch being arranged in series with the second semiconductor switch between the positive DC power bus and the negative DC power bus; a third semiconductor switch connected to the first node; a fourth semiconductor switch arranged in series with the third semiconductor switch across the neutral bus; a third semiconductor switch connected to the first node; a fourth semiconductor switch arranged in series with the third semiconductor switch across the neutral bus; and an alternating current (AC) bus connected to the first node, the AC bus connected to the electric machine;a first heat sink connected to at least one of the positive DC power bus and / or the negative DC power bus of the semiconductor IC via a first direct bonded copper substrate (DBC); and a second heat sink connected to the neutral bus of the semiconductor IC via a second DBC substrate.

[0008] Another aspect of the disclosure may include the stacked arrangement comprising a first layer consisting of the first semiconductor switch arranged coplanar with the second semiconductor switch and a second layer consisting of the third semiconductor switch arranged coplanar with the fourth semiconductor switch, wherein the first layer is arranged parallel to the second layer.

[0009] Another aspect of the disclosure may include the positive DC power bus and the negative DC power bus being disposed at a first end of the T-type multi-level power converter, and the AC bus being disposed at a second end of the T-type multi-level power converter.

[0010] Another aspect of the disclosure may be that the AC bus is arranged in parallel with at least one of the positive DC power bus, the negative DC power bus and / or the neutral bus.

[0011] Another aspect of the disclosure may include that the first semiconductor switch and the second semiconductor switch are each a gallium nitride (GaN) device.

[0012] Another aspect of the disclosure may include that the third semiconductor switch and the fourth semiconductor switch are each an insulated gate bipolar transistor (IGBT).

[0013] Another aspect of the disclosure may include the stack comprising: a first level consisting of the first semiconductor switch; a second level consisting of the third semiconductor switch arranged coplanar with the fourth semiconductor switch, the second level being arranged parallel to the first level; and a third level consisting of the second semiconductor switch, the third level being arranged parallel to the second level.

[0014] Another aspect of the disclosure may include the positive DC power bus and the negative DC power bus being disposed at a first end of the T-type multi-level power converter, and the AC bus being disposed at a second end of the T-type multi-level power converter.

[0015] Another aspect of the disclosure may be that the AC bus is arranged in parallel with at least one of the positive DC power bus, the negative DC power bus, and / or the neutral bus.

[0016] Another aspect of the disclosure may include a T-type multi-level power converter for a multi-phase power inverter for an electric drive system, including a solid-state integrated circuit (IC) having: a positive DC power bus; a negative DC power bus; a neutral bus; a plurality of semiconductor switches arranged in a stacked arrangement, the plurality of semiconductor switches interconnected via the positive DC power bus, the negative DC power bus, and the neutral bus, the plurality of semiconductor switches comprising: a first semiconductor switch connected at a first node;a second semiconductor switch connected to the first semiconductor switch at the first node, the first semiconductor switch being arranged in series with the second semiconductor switch between the positive DC power bus and the negative DC power bus; a third semiconductor switch connected to the first node; a third semiconductor switch connected to the first node; a fourth semiconductor switch arranged in series with the third semiconductor switch via the neutral bus; and an AC bus connected to the first node; a first heat sink connected to the positive DC power bus and / or the negative DC power bus of the solid-state IC via a first direct-bonded copper (DBC) substrate; and a second heat sink connected to the neutral bus of the solid-state IC via a second DBC substrate.

[0017] Another aspect of the disclosure may include an electrified vehicle having an electric propulsion system including: an electric motor configured to power a drivetrain of the vehicle; a multi-phase inverter including a plurality of T-type multi-level power converters disposed between a high-voltage direct current (DC) supply and the electric motor, wherein each of the plurality of T-type multi-level power converters is a solid-state integrated circuit (IC) including: a positive DC power bus; a negative DC power bus; a neutral bus;a plurality of semiconductor switches arranged in a stacked arrangement, the plurality of semiconductor switches being interconnected via the positive DC power bus, the negative DC power bus, and the neutral bus. The plurality of semiconductor switches includes a first semiconductor switch connected to a first node; a second semiconductor switch connected to the first semiconductor switch at the first node, the first semiconductor switch arranged in series with the second semiconductor switch between the positive DC power bus and the negative DC power bus; a third semiconductor switch connected to the first node; a third semiconductor switch connected to the first node; and a fourth semiconductor switch arranged in series with the third semiconductor switch across the neutral bus.and an AC bus connected to the first node; a first heat sink connected to the positive DC power bus and / or the negative DC power bus of the solid-state IC via a first direct-bonded copper (DBC) substrate; and a second heat sink connected to the neutral bus of the solid-state IC via a second DBC substrate.

[0018] Another aspect of the disclosure may include a method for inductance cancellation in a multi-phase inverter, including: arranging a plurality of semiconductor switches in a T-type multi-stage stack; assembling the plurality of semiconductor switches arranged in the T-type multi-stage stack into a solid-state integrated circuit (IC) having: a positive DC power bus; a negative DC power bus; and a neutral bus; and connecting the plurality of semiconductor switches across the positive DC power bus, the negative DC power bus, and the neutral bus.

[0019] Another aspect of the disclosure may include arranging the plurality of semiconductor switches in a first layer and a second layer, wherein the first layer consists of the first semiconductor switch arranged coplanar with the second semiconductor switch, and the second layer consists of the third semiconductor switch arranged coplanar with the fourth semiconductor switch, and wherein the first layer is arranged parallel to the second layer.

[0020] The above features and advantages, as well as other features and associated advantages of this disclosure, will become readily apparent from the following detailed description of illustrative examples and modes for carrying out the present disclosure, when considered in conjunction with the accompanying drawings and the appended claims. Furthermore, this disclosure expressly includes combinations and subcombinations of the elements and features presented above and below. BRIEF DESCRIPTION OF THE CHARACTERS

[0021] The accompanying drawings, which are incorporated in this specification, illustrate embodiments of the disclosure which, together with the description, serve to explain the principles of the disclosure. Fig. 1 schematically shows an electric drive system with a multi-phase inverter arranged between a high-voltage DC power supply and an electric machine, according to the disclosure. Fig. 2 schematically shows an electric drive system with a multiphase inverter including a plurality of T-type multilevel power converters arranged between a high voltage DC power supply and an electric machine, according to the disclosure. Fig. 3 schematically shows a T-type multi-level power converter according to one aspect of the disclosure. Fig. 4 schematically shows a side view of a T-type multi-level power converter according to one aspect of the disclosure. Fig. 5 schematically shows a side view of a T-type multi-level power converter according to another aspect of the disclosure. Fig. 6 schematically shows an isometric view of an arrangement of elements of a T-type multi-level power converter according to one aspect of the disclosure. Fig. 7 schematically shows an isometric view of an arrangement of elements of a T-type multi-level power converter according to another aspect of the disclosure.

[0022] The accompanying figures are not necessarily to scale and present a somewhat simplified representation of various preferred features of the present disclosure as disclosed herein, including, for example, specific dimensions, orientations, positions, and shapes. Details besides such features will be determined in part by the particular intended application and environment of use. DETAILED DESCRIPTION

[0023] The components of the embodiments described and illustrated herein can be arranged and configured in a variety of different configurations. Therefore, the following detailed description is not intended to limit the scope of the claimed disclosure, but is merely representative of possible embodiments thereof. Moreover, while numerous specific details are set forth in the following description to provide a thorough understanding of the embodiments disclosed herein, some embodiments may be practiced without some of these details. For clarity, certain technical details that are well known in the art have not been described in detail so as not to unnecessarily obscure the disclosure. Furthermore, the disclosure as shown and described herein may be practiced without any element not expressly disclosed herein.

[0024] The present disclosure may be embodied in many different forms. Representative examples of the disclosure are illustrated in the drawings and described in detail herein as non-limiting examples of the disclosed principles. To this end, elements and limitations described herein but not expressly recited in the claims are not to be incorporated into the claims, either individually or collectively, by implication, inference, or otherwise.

[0025] For the purposes of this description, the use of the singular includes the plural and vice versa, unless expressly excluded; the terms "and" and "or" apply both subjunctive and disjunctive; and the words "including," "containing," "comprising," "having," and the like mean "including without limitation." Furthermore, words of approximation such as "approximately," "almost," "substantially," "generally," "about," etc., may be used herein to mean "at, near, or almost at," or "within 0-5% of," or "within acceptable manufacturing tolerances," or logical combinations thereof.

[0026] As used herein, the term "system" refers to mechanical and electrical hardware, software, firmware, electronic control components, processing logic and / or processors, individually or in combination, including without limitation: application specific integrated circuit (ASIC), an electronic circuit, a processor (common, dedicated or group) that executes one or more software or firmware programs, memory device(s) that electrically store software or firmware instructions, a combinational logic circuit and / or other components that provide the described functionality.

[0027] Terms such as "vertical," "horizontal," "left," "right," "top," "bottom," and similar expressions are non-limiting terms that merely describe the various elements as illustrated in the figures and are not intended to limit the scope of the disclosure.

[0028] The term “electric machine” as used herein refers to an electric motor / generator with a rotor and a stator that is capable of converting electrical energy into mechanical energy and / or converting mechanical energy into electrical energy by electromagnetic force.

[0029] With reference to the figures, in which like reference numbers refer to like or similar components in the different figures, the Fig. 1 and Fig. 2 schematically illustrates elements of an electric powertrain 100 consisting of a high-voltage direct current source 101, a multi-phase inverter 104, a multi-phase electric rotary motor / generator (electric machine) 10, and a torque actuator 120, the operation of which is monitored and controlled by a controller 30. According to one aspect of the present disclosure, the electric powertrain 100 is arranged to generate and transmit torque to the actuator 120 in the form of one or more drive wheels to perform work. The controller 30 executes control routines to control and manage the operation of the multi-phase inverter 104. According to another aspect of the present disclosure, the electric powertrain 100 is arranged on an electrified vehicle, shown schematically at 20, and is capable of generating traction torque for vehicle propulsion.When disposed on the electrified vehicle 20, the electrified vehicle 20 may include, but is not limited to, a mobile platform in the form of a commercial vehicle, an industrial vehicle, an agricultural vehicle, a passenger vehicle, an aircraft, a watercraft, a train, an off-road vehicle, a personal mobility device, a robot, and the like to fulfill the purposes of this disclosure. Alternatively, the electric powertrain 100 may also be an element of a stationary system.

[0030] The controller 30 may be embodied as one or more digital computing devices and may include one or more processors 34 and a memory 32. A control routine 36 may be stored as an executable instruction set in the memory 32 and executed by one of the processors 34 of the controller 30. The controller 30 communicates with the multiphase inverter 104 to control its operation in response to the execution of the control routine 36 to operate the electric machine 10.

[0031] The term "control unit" and related terms such as microcontroller, control module, module, controller, control unit, processor and similar terms refer to one or various combinations of application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), electronic circuits, central processing units, e.g., microprocessors and associated memory components in the form of transient and / or non-transitory memory components and storage devices (read-only, programmable read-only, random access, hard disk devices, etc.).The non-transitory memory component is capable of storing machine-readable instructions in the form of one or more software or firmware programs or routines, combinational logic circuits, input / output circuits and devices, signal conditioning and buffering circuits, and other components accessible by one or more processors to provide the described functionality. Input / output circuits and devices include analog-to-digital inverters and related devices that monitor inputs from sensors, where these inputs are monitored at a preset sampling frequency or in response to a triggering event. Software, firmware, programs, instructions, control routines, code, algorithms, and similar terms refer to sets of instructions executable by the controller, including calibrations and lookup tables.

[0032] The electric machine 10 includes a cylindrically shaped rotor assembly mounted on a rotor shaft and located within an annular stator, the rotor assembly being coaxial with a rotor opening formed in the stator. Other elements of the electric machine 10, such as end caps, shaft bearings, electrical terminals, etc., are included but not shown. The stator's electrical windings are arranged with a number of electrical phases and a number of electrical turns per phase. Depending on the specific arrangement, the number of electrical phases can range from 3 to 6, and the number of conductor layers can range from 4 to 12.

[0033] The multiphase inverter 104 includes a plurality of semiconductor switches (illustrated with reference to Fig. 3 et seq.), which are arranged and controllable by the controller 130 to convert DC electrical power to AC electrical power and to convert AC electrical power to DC electrical power using a pulse width modulation signal 108 or other control technique. The multi-phase inverter 104 is arranged and controllable to convert DC energy from the high-voltage DC power source 101 to AC energy to actuate the electric machine 10 by electromagnetic force. The electric machine 10 is controllable to rotate and generate mechanical torque, which is transmitted to the actuator 120 via a rotatable member 12 and a gear train 114 when operated in a torque-generating mode.The electric machine 10 is controllable by the controller 130 to generate alternating current from the mechanical torque provided by the actuator 120 by electromagnetic force, which is converted by the multi-phase inverter 104 to direct current for storage in the high-voltage direct current source 101 when operating in a power generation mode. According to one aspect of the disclosure, the actuator 120 includes a vehicle wheel that transmits torque to a ground surface to effect forward motion as part of a traction drive system. The high-voltage direct current source 101 may be in the form of a rechargeable electrochemical battery device, a fuel cell, an ultracapacitor, and / or other electrical energy storage / generation technology.

[0034] The high-voltage DC power source 101 may be a rechargeable electrochemical battery device, a fuel cell, an ultracapacitor, and / or other electrical energy storage / generation technology. The high-voltage DC power source 101 is connected to the multi-phase inverter 104 via a high-voltage DC power bus having a positive terminal 102 and a negative terminal 103, and the multi-phase inverter 104 is connected to the electric machine 10 via a plurality of first AC buses 121 and second AC buses 122 for transmitting the pulse-width modulation signal 108.

[0035] As in Fig. 2, the multi-phase inverter 104 of the electric powertrain 100 is comprised of a plurality of T-type multi-level power converters 150 disposed between the high-voltage DC power source 101 and the electric machine 10, with a single DC link capacitor 105 between the high-voltage DC power source 101 and the multi-phase inverter 104 of the electric powertrain 100. As illustrated, and in one non-limiting aspect of the present disclosure, the multi-phase inverter 104 of the electric powertrain 100 is constructed with a number of three T-type multi-level power converters 150.

[0036] Each of the T-type multi-level power converters 150 is implemented as a solid-state integrated circuit (IC) having a plurality of semiconductor switches arranged in a stacked or stepped arrangement.

[0037] Other components of the T-type multi-level power converter 150 include a positive DC power bus 110, a neutral bus 111, a negative DC power bus 112, and an AC bus 121, as well as other elements described herein.

[0038] The topology of each of the T-type multilevel power converters 150 is implemented as a multilevel inverter (MLI) (see Fig. ). According to one aspect of the present disclosure and as described herein, each of the T-type multilevel power converters 150 employs a no-neutral-point (NPL) MLI topology. Topology refers to the physical arrangement of the constituent elements, including the network bus interconnections, dielectrics, semiconductor switches, and other elements.

[0039] In one aspect of the present disclosure and as shown, the plurality of semiconductor switches comprises a first semiconductor switch S1 151, a second semiconductor switch S2 152, a third semiconductor switch S3 153, and a fourth semiconductor switch S4 154. According to one aspect of the present disclosure, at least some of the semiconductor switches are field-effect transistors (FETs). According to another aspect of the present disclosure, the FETs are gallium nitride (GaN) transistors. According to another aspect of the present disclosure, at least some of the semiconductor switches are insulated-gate bipolar transistors (IGBTs).

[0040] The first semiconductor switch S1 151 is arranged in series with the fourth semiconductor switch S4 154 between the positive DC power bus 110 and the negative DC power bus 112, wherein the first semiconductor switch S1 151 is connected to the fourth semiconductor switch S4 154 at a first node 161. The third semiconductor switch S3 153 is also connected to the first node 161. The first node 161 is connected to the AC bus 121 to transmit power to the electric machine 10 (see Fig. 2). The third semiconductor switch S3 153 is arranged in series with the second semiconductor switch S2 152, wherein the second semiconductor switch S2 152 is connected to the neutral bus 111.

[0041] A positive DC power bus 110, a neutral power bus 111 and a negative DC power bus 112 are shown schematically.

[0042] By configuring the topology within each T-type multilevel converter 150 so that both the positive DC power bus 110 and the negative DC power bus 112 are in parallel with the neutral bus 111, mutual inductance cancellation minimizes parasitic inductance by coupling the positive mutual inductance and the negative mutual inductance for the commutation loop currents within each of the T-type multilevel converters 150.

[0043] According to one aspect of the disclosure, illustrated in (I), the buses are configured from top 33 to bottom 34 such that the positive DC power bus 110 is parallel to the neutral bus 111, which in turn is parallel to the negative DC power bus 112.

[0044] According to another aspect of the disclosure, as shown in (II), the buses are configured from top 33 to bottom 34 such that the positive DC power bus 110 is in parallel with the negative DC power bus 112, which is then in parallel with the neutral bus 111.

[0045] According to another aspect of the disclosure, as shown in (III), the buses are configured from top 33 to bottom 34 such that the neutral bus 111 is in parallel with the positive DC power bus 110, which is then in parallel with the negative DC power bus 112.

[0046] According to another aspect of the disclosure, as shown in (IV), the positive DC power bus 110 is coplanar with the negative DC power bus 112, while both the positive DC power bus 110 and the negative DC power bus 112 are in parallel with the neutral bus 111.

[0047] Although several topologies were discussed above, these are merely exemplary and non-limiting aspects of the disclosure. Accordingly, it should be understood that in each of the T-type multilevel converters 150, mutual inductance cancellation minimizes parasitic inductance by coupling the positive mutual inductance and the negative mutual inductance for the commutation loop currents in each of the T-type multilevel converters 150, i.e., by configuring the topology of the T-type multilevel inverter 150 such that both the positive DC power bus 110 and the negative DC power bus 112 are in parallel with the neutral bus 111.

[0048] Back to Fig. 3: Activations and deactivations of the first semiconductor switch S1 151, the second semiconductor switch S2 152, the third semiconductor switch S3 153, and the fourth semiconductor switch S4 154 are controlled by the control unit 130 to convert DC to AC and AC to DC using the pulse width modulation signal 108.

[0049] One aspect of the present disclosure of the T-type multi-level power converter 150 includes a first semiconductor switch S1 151, a second semiconductor switch S2 152, a third semiconductor switch S3 153, a fourth semiconductor switch S4 154, a positive DC power bus 110, a negative DC power bus 112, a neutral bus 111, a first node 161, a first direct bonded copper plate (DBC) 143, a second DBC plate 144, a third DBC plate 145, a plurality of conductive spacers 146, a first heat sink 141, and a second heat sink 142. The positive DC power bus 110 and the negative DC power bus are located at a first end 131 of the T-type multi-level power converter 150, and the AC bus 121 is located at a second end 132, opposite the first end 131 of the T-type multi-stage power converter 150.The first node 161 is connected to the AC bus 121 to transfer power to one of the phases of the electric machine 10 included in the . Fig. 1 and Fig. 2 is shown.

[0050] As in Fig. As shown in Figure 4, the first semiconductor switch S1 151, the second semiconductor switch S2 152, the third semiconductor switch S3 153, and the fourth semiconductor switch S4 154 are arranged in a stacked or multi-layer configuration including a first (bottom) layer 135, a second (middle) layer 136, and a third (top) layer 137. The first layer 135 includes the fourth semiconductor switch S4 154 and the negative DC power bus 112 disposed on the first DBC plate 143. The second layer 136 includes the second semiconductor switch S2 152 and the third semiconductor switch S3 153 (which are coplanar), the second DBC plate 144, the neutral bus 111, and the AC bus 121. The third level 137 includes the first semiconductor switch S1 151 and the positive DC power bus 110 disposed on the third DBC plate 145.

[0051] The complete stacked assembly includes, in ascending order from bottom 134 to top 133: the first heat sink 141; the first DBC plate 143; the negative DC power bus 112; the first layer 135 with the second semiconductor switch S2 152 and the fourth semiconductor switch S4 154; the neutral bus 111; the second layer 136 with the fifth semiconductor switch S5 155 and the sixth semiconductor switch S6 156, the AC bus 121, a second AC bus 122, the second DBC plate 144, and the plurality of conductive spacers 146; the third layer 137 with the first semiconductor switch S1 151, the third semiconductor switch S3 153, and the positive DC power bus 110; the third DBC plate 145; and the second heat sink 142.

[0052] The first semiconductor switch S1 151, the third semiconductor switch S3 153, and the fourth semiconductor switch S4 154 are connected to the first node 161, which is connected to the AC bus 121. The first heat sink 141 is connected via the first DBC plate 143, and the second heat sink is connected via the third DBC plate 145.

[0053] Another aspect of the present disclosure of the T-type multi-level power converter 250 includes a first semiconductor switch S1 251, a second semiconductor switch S2 252, a third semiconductor switch S3 253, a fourth semiconductor switch S4 254, a positive DC power bus 210, a negative DC power bus 212, a neutral bus 211, a first node 261, a first DBC plate 243, a third DBC plate 245, a plurality of conductive spacers 246, a first heat sink 241, and a second heat sink 242. The positive DC power bus 210 and the negative DC power bus 212 are located at a first end 231 of the T-type multi-level power converter 250, and an AC bus 221 is located at a second end 232, opposite the first end 231 of the T-type multi-level power converter 250. The first node 261 is connected to the AC bus 221 to transfer power to one of the phases of the electric machine 10, which is in the Fig. is shown.

[0054] Again referring to Fig. 5, the first semiconductor switch S1 251, the second semiconductor switch S2 252, the third semiconductor switch S3 253, and the fourth semiconductor switch S4 254 are arranged in a stacked or multi-layer configuration, including a first (bottom) layer 235, a second (middle) layer 236, and a third (top) layer 237. The first layer 235 includes the second semiconductor switch S2 252 and the third semiconductor switch S3 253 (which are coplanar), as well as the neutral bus 211 arranged on the first DBC board 243.

[0055] The second level 236 includes the first node 261, which is connected to the AC bus 221.

[0056] The third level 237 includes the first semiconductor switch S1 251 and the fourth semiconductor switch S4 254, the positive DC power bus 210 and the negative DC power bus 212, which are arranged on the third DBC plate 245.

[0057] The complete stack assembly includes, in ascending order from bottom 234 to top 233, the first heat sink 241, the first DBC plate 243; the first layer 235 with the neutral bus 211, the third semiconductor switch S3 253, and the fourth semiconductor switch S4 254; the second layer 236 with the first node 261 connected to the AC bus 121; the conductive spacer 246; the third layer 237 with the first semiconductor switch S1 251 and the fourth semiconductor switch S4 254 arranged coplanar with each other, the positive DC power bus 210 and the negative DC power bus 212 arranged coplanar with each other; the third DBC plate 245; and the second heat sink 242.

[0058] The first semiconductor switch S1 251, the third semiconductor switch S3 253, and the fourth semiconductor switch S4 254 are connected to the first node 261, which is connected to the AC bus 221. The first heat sink 241 is connected via the first DBC plate 243, and the second heat sink is connected via the third DBC plate 245.

[0059] Fig. 6 schematically illustrates the T-type multi-level power converter 350 aspect of the present disclosure and includes the first semiconductor switch S1 351, the second semiconductor switch S2 352, the third semiconductor switch S3 353, the fourth semiconductor switch S4 354, the positive DC power bus 310, and the negative DC power bus 312 connected to the AC bus 321. It should be understood that other elements previously described have been omitted but are included in one aspect of the present disclosure of the T-type multi-level power converter 350 when reduced to practice.

[0060] The first semiconductor switch S1 351, the second semiconductor switch S2 352, the third semiconductor switch S3 353, and the fourth semiconductor switch S4 354 are arranged in a stacked or multi-layer configuration including a first (bottom) layer 335, a second (middle) layer 336, and a third (top) layer 337. The first layer 335 includes the second semiconductor switch S2 352 and the third semiconductor switch S3 353, which are coplanar. The second layer 336 includes the first node 361, which is connected to the AC bus 321. The third layer 337 includes the first semiconductor switch S1 351 and the fourth semiconductor switch S4 354, which are in a plane. The AC bus 321, the positive DC power bus 310 and the negative DC power bus 312 are connected as shown, which corresponds to the arrangement of the circuit described with reference to Fig. 3 is shown.

[0061] Fig. 7 schematically illustrates one aspect of the present disclosure of the T-type multi-level power converter 450 and includes the first semiconductor switch S1 451, the second semiconductor switch S2 452, the third semiconductor switch S3 453, the fourth semiconductor switch S4 454, the positive DC power bus 410, and the negative DC power bus 412 connected to the AC bus 421. It should be understood that other elements previously described have been omitted but are included in one aspect of the present disclosure of the T-type multi-level power converter 450 when reduced to practice.

[0062] The first semiconductor switch S1 451, the second semiconductor switch S2 452, the third semiconductor switch S3 453, and the fourth semiconductor switch S4 454 are arranged in a stacked or multi-layer configuration including a first (bottom) layer 435, a second (middle) layer 436, and a third (top) layer 437. The first layer 435 includes the fourth semiconductor switch S4 454 and the negative DC power bus 412. The second layer includes the second semiconductor S2 452 and the third semiconductor switch S3 453, which are coplanar, and the AC bus 421 connected to a first node. The third layer 437 comprises the first semiconductor switch S1 451 and the positive DC power bus 410. The AC bus 421, the positive DC power bus 410 and the negative DC power bus 412 are connected as shown, which corresponds to the arrangement of the circuit described with reference to Fig. 3 is shown.

[0063] The presented aspects of the present disclosure of the T-type multi-level power converter provide for overlapping the positive DC power bus, the neutral bus, and the negative DC power bus to reduce mutual inductance. This arrangement includes overlaying the AC bus with the second AC bus to compensate dV / dt and reduce or eliminate electromagnetic interference, and achieving field compensation across the P, O, and N currents to minimize parasitic loop and stray inductances.

[0064] The concepts and aspects of the present disclosure described herein facilitate the optimal design of the positive DC power bus, the negative DC power bus, the neutral bus, and the DC link capacitor to achieve mutual inductance cancellation.

[0065] The concepts and aspects of the present disclosure described herein facilitate various heat transfer and cooling systems, including direct cooling, indirect cooling, immersion cooling, single-sided cooling, or double-sided cooling.

[0066] The concepts and aspects of the present disclosure described herein facilitate the reduction of voltage / current overshoots when stressing devices, including the chip / power module, power rails, and DC link capacitor.

[0067] The concepts and aspects of the present disclosure described herein facilitate downsizing and increasing power density compared to current systems.

[0068] The concepts and aspects of the present disclosure described herein facilitate the use of lower voltage semiconductor switch chips for lower conduction losses and a wider EV range compared to current systems.

[0069] The concepts and aspects of the present disclosure described herein enable reduction of ringing and radiated / conductive electromagnetic interference with other subsystems.

[0070] The concepts and aspects of the present disclosure described herein enable higher switching speed, which reduces losses and thus increases the range and current carrying capacity of the vehicle.

[0071] These and other advantages of the present disclosure will be appreciated by those skilled in the art in view of the foregoing disclosure.

[0072] The detailed description and the drawings or figures are supportive and descriptive of the present teachings, but the scope of the present teachings is defined solely by the claims. While some of the best modes and other examples for carrying out the present teachings have been described in detail, various alternative designs and aspects of the present disclosures for carrying out the present teachings exist, as defined in the appended claims.

Claims

[1] A multi-phase inverter for an electric powertrain, the multi-phase inverter comprising: a plurality of T-type multi-level power converters arranged between a high-voltage DC power supply and an electric machine, each of the plurality of T-type multi-level power converters being a solid-state integrated circuit (IC) comprising: a positive DC power bus; a negative DC power bus; a neutral bus; a plurality of semiconductor switches arranged in a stacked arrangement, the plurality of semiconductor switches being interconnected via the positive DC power bus, the negative DC power bus, and the neutral bus, the plurality of semiconductor switches comprising: a first semiconductor switch connected to a first node; a second semiconductor switch connected to the first semiconductor switch at the first node, the first semiconductor switch being arranged in series with the second semiconductor switch between the positive DC power bus and the negative DC power bus; a third semiconductor switch connected to the first node; a fourth semiconductor switch arranged in series with the third semiconductor switch across the neutral bus; and an AC bus connected to the first node, the AC bus connected to the electric machine; a first heat sink connected to the positive DC power bus and / or the negative DC power bus of the solid-state IC via a first directly bonded copper substrate, DBC substrate; and a second heat sink connected to the neutral bus of the semiconductor IC via a second DBC substrate. [2] The multi-phase inverter of claim 1, wherein the stacked assembly comprises a stack comprising: a first layer consisting of the first semiconductor switch arranged coplanar with the second semiconductor switch; and a second layer consisting of the third semiconductor switch arranged coplanar with the fourth semiconductor switch, wherein the first layer is arranged parallel to the second layer. [3] The multi-phase inverter of claim 2, wherein the positive DC power bus and the negative DC power bus are disposed at a first end of the T-type multi-level power converter, and wherein the AC bus is disposed at a second end of the T-type multi-level power converter. [4] A multi-phase inverter according to claim 3, wherein the AC bus is arranged in parallel with at least one of the positive DC power bus, the negative DC power bus and / or the neutral bus. [5] The multi-phase inverter of claim 2, wherein the first semiconductor switch and the second semiconductor switch each comprise a gallium nitride, GaN, device. [6] The multi-phase inverter of claim 2, wherein the third semiconductor switch and the fourth semiconductor switch each comprise an insulated gate bipolar transistor, IGBT. [7] The multi-phase inverter of claim 1, wherein the stacked assembly comprises a stack comprising: a first layer consisting of the first semiconductor switch; a second layer consisting of the third semiconductor switch arranged coplanar with the fourth semiconductor switch, the second layer being arranged parallel to the first layer; and a third layer consisting of the second semiconductor switch, wherein the third layer is arranged parallel to the second layer. [8] The multi-phase inverter of claim 7, wherein the positive DC power bus and the negative DC power bus are disposed at a first end of the T-type multi-level power converter, and wherein the AC bus is disposed at a second end of the T-type multi-level power converter. [9] A multi-phase inverter according to claim 8, wherein the AC bus is arranged in parallel with at least one of the positive DC power bus, the negative DC power bus and / or the neutral bus. [10] The multi-phase inverter of claim 7, wherein the first semiconductor switch and the second semiconductor switch each comprise a gallium nitride, GaN, device.

Images