System for eliminating mutual inductance in H-type multi-stage converters

Abstract

A multiphase inverter for an electric drive system comprises a multitude of H-type multilevel power converters arranged between a high-voltage direct current (HVDC) supply and an electric machine. Each of the multitude of H-type multilevel power converters is an integrated solid-state circuit (IC) comprising a positive DC power bus, a negative DC power bus, a neutral bus, and a multitude of semiconductor switches arranged in a stacked configuration. The multitude of semiconductor switches are interconnected via the positive DC power bus, the negative DC power bus, and the neutral bus.

Description

Technical field

[0001] The concepts described herein generally refer to vehicles with electrified powertrains or drive systems equipped with DC power supplies that deliver electrical energy to multi-phase inverters to control the operation of one or more electric machines. introduction

[0002] High-voltage and high-power multilevel inverters (MLIs) have gained attention as the trend toward electrifying the transportation sector into high-capacity mass transit systems, such as electric aircraft, trains, and ships, rapidly increases. MLIs like neutral point clamped (NPC) and T-type inverters offer high-voltage and high-power capabilities but require stacked DC link capacitors with a neutral point connection for the zero-voltage vector. This zero-point connection to the stacked DC link capacitor can generate a zero-voltage current that oscillates at three times the fundamental frequency, potentially leading to capacitor voltage imbalance and / or overvoltage loading of the capacitors and switching devices.

[0003] A multiphase inverter circuit can create an inherent power loop in which a high current flows from a DC link capacitor to the high side of the multilevel inverter, then to the low side, and back. This power loop can generate a magnetic field that forms a parasitic inductance.

[0004] Since multi-phase inverters operate at higher switching frequencies, even small parasitic inductances can cause problems, such as ringing and / or electromagnetic interference (EMI), but are not limited to these.

[0005] The current flow path determines the size of the power loop, which in turn determines the size of the generated magnetic field and thus the size of the parasitic inductance, and the current flow path is defined by the topology of the circuit, whereby the topology of the circuit can influence the size of the parasitic inductance. Description of the invention

[0006] In light of the above discussion, it makes sense to develop a system and method for eliminating mutual inductance for a multi-phase inverter that incorporates a variety of H-type multi-level power converters with a topology that reduces parasitic inductance within the multi-phase inverter.

[0007] The concepts disclosed here relate to a system for a multiphase inverter with a plurality of H-type multilevel power converters that achieve mutual inductance cancellation. Such a system can be used in a vehicle with an electrified propulsion system, e.g., but not limited to, a motor vehicle with an electrified powertrain or propulsion system, such as an electric vehicle (EV) or plug-in hybrid electric vehicle (PHEV), or any other mobile platform that can be powered by an electric propulsion system, to reduce parasitic inductance within the multiphase inverter.

[0008] Each multiphase inverter can contain multiple H-type multilevel power converters, which are placed between a high-voltage DC supply and an electric machine. The number of H-type multilevel power converters required depends on the application.

[0009] Each H-type multilevel power converter is an integrated solid-state circuit (IC) containing a variety of circuit components, such as, but not limited to, semiconductor switches, buses, and busbars, interconnected to form a network of connections through which current can flow. The shape of this network of interconnected circuits is called the circuit topology.

[0010] The concepts described herein provide a multiphase inverter advantageously arranged to minimize stray inductance and loop inductance through magnetic field cancellation. This involves the use of field cancellation by arranging positive, neutral, and negative buses and a variety of H-type multilevel power converters in integrated solid-state circuits with stacked or layered elements. The arrangement of each H-type multilevel power converter with stacked or layered elements allows for either single-sided or double-sided cooling to reduce thermal impedance. The consequences of reduced stray inductance include lower switching losses, less ringing, less electromagnetic interference (EMI), and reduced thermal stress on the devices.

[0011] One aspect of the disclosure may include a multiphase inverter for an electric drive train, wherein the multiphase inverter converts high-voltage direct current electrical power into multiphase alternating current power, which is transmitted to the electric drive train. The multiphase inverter comprises a plurality of H-type multilevel power converters arranged between a high-voltage direct current supply and an electric machine.

[0012] Each of the multiple H-type multilevel power converters is a solid-state integrated circuit (IC) with multiple semiconductor switches, a positive DC power bus, a negative DC power bus, and a neutral bus, arranged in a stacked or layered configuration between a first direct-bonded copper (DBC) plate and a second DBC plate. The IC also includes a first AC bus, a second AC bus, a first heat sink, and a second heat sink. The multiple semiconductor switches are interconnected via the positive DC power bus, the negative DC power bus, and the neutral bus. The multiple semiconductor switches comprise a first semiconductor switch, a second semiconductor switch, a third semiconductor switch, a fourth semiconductor switch, a fifth semiconductor switch, and a sixth semiconductor switch.

[0013] The first semiconductor switch is arranged in series with the second semiconductor switch between the positive DC power bus and the negative DC power bus, with the first semiconductor switch being connected to the second semiconductor switch at a first node. The third semiconductor switch is arranged in series with the fourth semiconductor switch between the positive DC power bus and the negative DC power bus, with the third semiconductor switch being connected to the fourth semiconductor switch at a second node. The fifth semiconductor switch is connected in series with the sixth semiconductor switch via the neutral bus, with the fifth semiconductor switch being connected to the first node and the sixth semiconductor switch being connected to the second node. The first node is connected to the first AC bus, and the second node is connected to the second AC bus.

[0014] The first heat sink is connected to the semiconductor IC via the first DBC substrate; and the second heat sink is connected to the semiconductor IC via the second DBC substrate.

[0015] Another aspect of the disclosure may include the stacked arrangement with a stack comprising: a first layer composed of the first semiconductor switch arranged to be coplanar with the second semiconductor switch; a second layer composed of the fifth semiconductor switch arranged to be coplanar with the sixth semiconductor switch, the first layer being arranged parallel to the second layer; and a third layer composed of the third semiconductor switch arranged to be coplanar with the fourth semiconductor switch, the second layer being arranged parallel to the third layer.

[0016] Another aspect of the disclosure may include the fact that the positive DC power bus and the negative DC power bus are arranged at a first end of the H-type multilevel power converter, and wherein the first AC bus and the second AC bus are arranged at a second end of the H-type multilevel power converter.

[0017] Another aspect of the revelation may include the fact that the second AC bus protrudes outwards from a lower part of the semiconductor IC.

[0018] Another aspect of the disclosure may include the stacked arrangement with a stack comprising: a first layer composed of the first semiconductor switch, the second semiconductor switch, the third semiconductor switch and the fourth semiconductor switch arranged so that they are coplanar to each other; and a second layer composed of the fifth semiconductor switch arranged so that it is coplanar to the sixth semiconductor switch, the first layer being arranged parallel to the second layer.

[0019] Another aspect of the disclosure may include the fact that the positive DC power bus and the negative DC power bus are arranged at a first end of the H-type multilevel power converter, and wherein the first AC bus and the second AC bus are arranged at a second end of the H-type multilevel power converter.

[0020] Another aspect of the disclosure may include the stacked arrangement with a stack comprising: a first layer composed of the second semiconductor switch arranged coplanar with the fourth semiconductor switch; a second layer composed of the fifth semiconductor switch arranged coplanar with the sixth semiconductor switch; and a third layer composed of the first semiconductor switch arranged coplanar with the third semiconductor switch, the first layer being arranged parallel to the second layer.

[0021] Another aspect of the disclosure may include the fact that the positive DC power bus and the negative DC power bus are arranged at a first end of the H-type multilevel power converter, and wherein the first AC bus and the second AC bus are arranged at a second end of the H-type multilevel power converter.

[0022] Another aspect of the disclosure may include the stacked arrangement with a stack comprising: a first layer composed of the first semiconductor switch arranged coplanar with the second semiconductor switch; a second layer composed of the fifth semiconductor switch arranged coplanar with the sixth semiconductor switch; and a third layer composed of the third semiconductor switch arranged coplanar with the fourth semiconductor switch, the first layer being arranged parallel to the second layer.

[0023] Another aspect of the revelation may include that the first semiconductor switch, the second semiconductor switch, the third semiconductor switch and the fourth semiconductor switch are each a gallium nitride (GaN) device.

[0024] Another aspect of the disclosure may include that the fifth semiconductor switch and the sixth semiconductor switch are each an insulated-layer bipolar transistor (IGBT).

[0025] Another aspect of the disclosure may include a method for inductance cancellation in a multiphase inverter, comprising: arranging a plurality of semiconductor switches in an H-type multilevel stack; assembling the plurality of semiconductor switches arranged in the H-type multilevel stack into a solid-state integrated circuit (IC) comprising: a positive DC power bus; a negative DC power bus; and a neutral bus; and connecting the plurality of semiconductor switches via the positive DC power bus, the negative DC power bus, and the neutral bus.

[0026] Another aspect of the disclosure may include a vehicle with an electric drive system, wherein the vehicle includes an electric drive system comprising: an electric motor configured to supply power to the electric drive system; a multiphase inverter comprising a plurality of H-type multilevel power converters arranged between a high-voltage direct current (H-DC) supply and the electric motor, each of the plurality of H-type multilevel power converters being an integrated solid-state circuit (IC) comprising: a positive DC power bus; a negative DC power bus; a neutral bus;a plurality of semiconductor switches arranged in a stacked configuration, wherein the plurality of semiconductor switches are interconnected via the positive DC power bus, the negative DC power bus, and the neutral bus.

[0027] The above features and advantages, as well as other features and associated advantages of this disclosure, will be readily apparent from the following detailed description of illustrative examples and methods for carrying out the present disclosure when considered in conjunction with the accompanying drawings and claims. Furthermore, this disclosure expressly includes combinations and subcombinations of the elements and features described above and below. Brief description of the drawings

[0028] The accompanying drawings, which form part of this description, illustrate embodiments of the disclosure, which, together with the description, serve to explain the principles of the disclosure. Fig. Figure 1 schematically shows an electrical drive system with a multi-phase inverter arranged between a high-voltage direct current supply and an electrical machine, according to the disclosure. Fig. Figure 2 schematically shows an electrical drive system with a multiphase inverter containing a plurality of H-type multilevel power converters arranged between a high-voltage DC power supply and an electrical machine, according to the disclosure. Fig. Figure 3 schematically shows an H-type multilevel power converter according to one aspect of the revelation. Fig. Figure 4 schematically shows a side view of an H-type multilevel power converter according to one aspect of the disclosure. Fig. Figure 5 schematically shows a side view of an H-type multilevel power converter according to another aspect of the disclosure. Fig. Figure 6 schematically shows an isometric view of an arrangement of elements of an H-type multilevel power converter according to one aspect of the disclosure. Fig. Figure 7 schematically shows an isometric view of an arrangement of elements of an H-type multilevel power converter according to another aspect of the disclosure. Fig. Figure 8 schematically shows an isometric view of another arrangement of elements of an H-type multilevel power converter according to another aspect of the disclosure. Fig. Figure 9 schematically shows an isometric view of another arrangement of elements of an H-type multilevel power converter according to another aspect of the disclosure. Fig. Figure 10 schematically shows an isometric view of another arrangement of elements of an H-type multilevel power converter according to another aspect of the disclosure.

[0029] The accompanying drawings are not necessarily to scale and represent a somewhat simplified depiction of various preferred features of the present disclosure as disclosed herein, including, for example, certain dimensions, orientations, positions, and shapes. Details other than such features are partly determined by the intended application and operating environment. Detailed description

[0030] The components of the embodiments described and illustrated herein can be arranged and designed in a multitude of different configurations. Therefore, the following detailed description is not intended to limit the scope of the claimed disclosure, but is merely representative of possible embodiments thereof. Furthermore, while numerous specific details are included in the following description to facilitate a comprehensive understanding of the embodiments disclosed herein, some embodiments can also be implemented without some of these details. For the sake of clarity, certain technical details known from the prior art have not been described in detail to avoid unnecessarily complicating the disclosure. Moreover, the disclosure as presented and described herein can also be implemented without any element not expressly disclosed herein.

[0031] The present disclosure can be realized in many different forms. Representative examples of the disclosure are illustrated in the drawings and are described in detail herein as non-restrictive examples of the disclosed principles. For this purpose, elements and restrictions described herein but not expressly included in the claims are not to be considered as being incorporated into the claims, either individually or collectively, by implication, by inference, or otherwise.

[0032] For the purposes of this description, the use of the singular includes the plural and vice versa, unless expressly excluded. The terms "and" and "or" apply in both the subjunctive and disjunctive forms, and the words "including," "containing," "comprehensive," "exhibiting," and the like mean "including without limitation." Furthermore, words of approximation such as "approximately," "almost," "essentially," "generally," "approximately," etc., may be used here to mean "at, close to, or almost at" or "within 0-5% of" or "within acceptable manufacturing tolerances," or logical combinations thereof.

[0033] As used herein, the term “system” refers to mechanical and electrical hardware, software, firmware, electronic control components, processing logic and / or processors, individually or in combination, including but not limited to: application-specific integrated circuit (ASIC), an electronic circuit, a processor (common, dedicated or group) executing one or more software or firmware programs, storage device(s) electrically storing software or firmware instructions, a combinational logic circuit and / or other components providing the described functionality.

[0034] Terms such as “vertical”, “horizontal”, “left”, “right”, “above”, “below”, “upper”, “lower” and similar expressions as used herein are non-limiting terms that merely describe the various elements as they are represented in the illustrations and are not intended to limit the scope of the disclosure.

[0035] The term "electric machine" as used herein refers to an electric motor, generator or motor-generator device having a rotor and a stator, which is capable of converting electrical energy into mechanical energy and / or converting mechanical energy into electrical energy by electromagnetic force.

[0036] Referring to the drawings, in which the same reference numerals refer to identical or similar components in the various illustrations, the Fig. 1 and Fig. 2 schematically an electric drive train 100, which is constructed from a high-voltage direct current source 101 (high-voltage DC current source 101), a multi-phase inverter 104, a multi-phase electric rotary motor, generator or motor-generator (electric machine) 10 and a torque actuator 120, the operation of which is monitored and controlled by a control unit 130.

[0037] According to one aspect of the disclosure, the electric drive train 100 is arranged to generate torque and transmit it to the torque actuator 120 in the form of one or more drive wheels 120 to perform work. The controller 130 executes control routines 36 to control and manage the operation of the multiphase inverter 104.

[0038] The electric powertrain 100 is mounted on an electrified vehicle, schematically represented as 20, and is capable of generating a tractive torque for the vehicle's propulsion. When mounted on the electrified vehicle 20, the electrified vehicle 20 can comprise, but is not limited to, a mobile platform in the form of a commercial vehicle, industrial vehicle, agricultural vehicle, passenger vehicle, aircraft, watercraft, train, all-terrain vehicle, personal mobility device, robot, and the like, to fulfill the purposes of this disclosure. Alternatively, the electric powertrain 100 can also be an element of a stationary system.

[0039] The controller 130 can be implemented as one or more digital computing devices and may include one or more processors 134 and a memory 132. A control routine 36 can be stored as an executable instruction set in the memory 132 and executed by one of the processors 134 of the controller 130. The controller 130 communicates with the multiphase inverter 104 to control its operation in response to the execution of the control routine 36 for the operation of the electric machine 10.

[0040] The term "controller" and related terms such as microcontroller, control module, module, control unit, control device, processor and similar terms refer to one or more combinations of application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), electronic circuits, central processing units, e.g. microprocessors and associated memory components in the form of volatile and / or non-volatile memory components and storage devices (read-only, programmable read-only, direct access, hard disk devices, etc.).The non-volatile memory component is capable of storing machine-readable instructions in the form of one or more software or firmware programs or routines, combinational logic circuits, input / output circuits and devices, signal conditioning and buffering circuits, and other components that one or more processors can access to provide the described functionality. Input / output circuits and devices include analog-to-digital converters and related devices that monitor sensor inputs, either at a preset sampling frequency or in response to a triggering event. Software, firmware, programs, instructions, control routines, code, algorithms, and similar terms refer to sets of instructions executable by the controller, including calibrations and lookup tables.

[0041] The electric machine 10 comprises a cylindrical rotor assembly mounted on a rotor shaft and located within an annular stator, the rotor assembly being coaxial with a rotor opening formed in the stator. Other elements of the electric machine 10, such as end caps, shaft bearings, electrical connections, etc., are included but not shown. The stator's electrical windings are arranged with a number of electrical phases and a number of electrical turns per phase. Depending on the specific arrangement, the number of electrical phases can range from 3 to 6, and the number of conductor layers from 4 to 12.

[0042] The multi-phase inverter 104 comprises a variety of semiconductor switches (shown with reference to Fig. 2 ff.), which are arranged and controllable to convert direct current electrical power into alternating current electrical power and to convert alternating current electrical power into direct current electrical power, using a pulse width modulation signal 108 or other control technology. The multiphase inverter 104 is arranged and controllable to convert direct current energy from the high-voltage direct current source 101 into alternating current energy to actuate the electric machine 10 by electromagnetic force. The electric machine 10 is controllable to rotate and generate a mechanical torque which, when operated in a torque-generating mode, is transmitted to the torque actuator 120 via a rotatable element 12 and a gear train 114.The electric machine 10 is controllable in such a way that it generates alternating current from the mechanical torque emanating from the torque actuator 120 via electromagnetic force, which is converted into direct current by the multi-phase inverter 104 and stored in the high-voltage direct current source 101 when it is operated in a power generation mode.

[0043] According to one aspect of the disclosure, the torque actuator 120 comprises a vehicle wheel that transmits torque to a ground surface to effect forward motion as part of a traction drive system. The high-voltage direct current source 101 can be in the form of a rechargeable electrochemical battery device, a fuel cell, an ultracapacitor, and / or another technology for storing / generating electrical energy.

[0044] The high-voltage direct current source 101 can be a rechargeable electrochemical battery device, a fuel cell, an ultracapacitor, and / or another technology for storing / generating electrical energy. The high-voltage direct current source 101 is connected to the multiphase inverter 104 via a high-voltage direct current bus (high-voltage DC bus) with a positive connection 102 and a negative connection 103, and the multiphase inverter 104 is connected to the electric machine 10 via a plurality of first AC buses 121 and second AC buses 122 to transmit the pulse-width modulation signal 108.

[0045] As in Fig. As shown in Figure 2, the multiphase inverter 104 of the electric drive train 100 is constructed from a plurality of H-type multilevel power converters 150 arranged between the high-voltage DC source 101 and the electric machine 10, with a single DC intermediate circuit capacitor 105 between the high-voltage DC source 101 and the multiphase inverter 104 of the electric drive train 100. As shown, and in a non-limiting aspect of the disclosure, the multiphase inverter 104 of the electric drive train 100 is constructed with a plurality of three H-type multilevel power converters 150.

[0046] With reference to Fig. Figure 3 shows the topology of each of the H-type multilevel power converters 150 as a multilevel inverter (MLI).

[0047] According to one aspect of the disclosure and as described herein, each of the H-type multilevel power converters 150 uses a non-neutral-point (NPL) MLI topology. The topology refers to the physical arrangement of the constituent elements, including the network bus connections, dielectrics, semiconductor switches, and other elements.

[0048] Each of the H-type multilevel power converters 150 is arranged as an integrated solid-state circuit (IC) with a plurality of semiconductor switches arranged in a stacked or stepped configuration. The plurality of semiconductor switches includes, in one aspect of the disclosure and as shown, a first semiconductor switch S1 151, a second semiconductor switch S2 152, a third semiconductor switch S3 153, a fourth semiconductor switch S4 154, a fifth semiconductor switch S5 155, and a sixth semiconductor switch S6 156.

[0049] According to one aspect of the disclosure, at least some of the semiconductor switches are field-effect transistors (FETs). According to another aspect of the disclosure, the FETs are gallium nitride (GaN) transistors. According to yet another aspect of the disclosure, at least some of the semiconductor switches are insulated-layer bipolar transistors (IGBTs).

[0050] Further components of the H-type multilevel power converter 150 include the positive DC power bus 110, the neutral bus 111, the negative DC power bus, the first AC bus 121, and the second AC bus 122. The first semiconductor switch S1 151 is arranged in series with the second semiconductor switch S2 152 between the positive DC power bus 110 and the negative DC power bus 112, with the first semiconductor switch S1 151 being connected to the second semiconductor switch S2 at a first node 161. The fifth semiconductor switch S5 155 is also connected to the first node 161. The first node 161 is connected to the first AC bus 121 to transfer power to the electric machine 10 (as shown in Fig. 2 shown).

[0051] The third semiconductor switch S3 153 is arranged in series with the fourth semiconductor switch S4 154 between the positive DC power bus 110 and the negative DC power bus 112, with the third semiconductor switch S3 153 being connected to the fourth semiconductor switch S4 154 at a second node 162. The sixth semiconductor switch 156 is also connected to the second node 162. The second node 162 is connected to the second AC bus 122 to transfer power to the electric machine 10 (see Fig. 2) The fifth semiconductor switch S5 155 is arranged in series with the sixth semiconductor switch S6 156 between the first node 161 and the second node 162 via the neutral bus 111.

[0052] A positive DC power bus 110, a neutral power bus 111 and a negative DC power bus 112 are shown schematically.

[0053] By configuring the topology in each of the H-type multilevel power converters 150 such that both the positive DC power bus 110 and the negative DC power bus 112 are in parallel to the neutral bus 111, the cancellation of mutual inductance minimizes the parasitic inductance by coupling the positive mutual inductance and the negative mutual inductance for the commutation loop currents in each of the H-type multilevel power converters 150.

[0054] According to one aspect of the disclosure, which is shown in (I), the buses from top 33 to bottom 34 are configured such that the positive DC power bus 110 runs in parallel to the neutral bus 111, which in turn is in parallel to the negative DC power bus 112.

[0055] According to another aspect of the disclosure, as shown in (II), the buses from top 33 to bottom 34 are configured such that the positive DC power bus 110 is in parallel with the negative DC power bus 112, which is then in parallel with the neutral bus 111.

[0056] According to another aspect of the disclosure, as shown in (III), the buses from top 33 to bottom 34 are configured such that the neutral bus 111 is in parallel with the positive DC power bus 110, which is then in parallel with the negative DC power bus 112.

[0057] According to another aspect of the disclosure, as shown in (IV), the positive DC power bus 110 is coplanar with the negative DC power bus 112, while both the positive DC power bus 110 and the negative DC power bus 112 are parallel with the neutral bus 111.

[0058] Although several topologies have been discussed above, these are merely exemplary and non-limiting aspects of the disclosure. Accordingly, it should be recognized that in each of the H-type multilevel power converters 150, the cancellation of mutual inductance minimizes the parasitic inductance by coupling the positive mutual inductance and the negative mutual inductance for the commutation loop currents in each of the H-type multilevel power converters 150, i.e., by configuring the topology of the H-type multilevel power converter 150 such that both the positive DC power bus 110 and the negative DC power bus 112 are in parallel with the neutral bus 111.

[0059] Now, referring to Fig. Figure 4 is illustrated according to one aspect of the disclosure of the H-type multilevel power converter 150, comprising a first semiconductor switch S1 151, a second semiconductor switch S2 152, a third semiconductor switch S3 153, a fourth semiconductor switch S4 154, a fifth semiconductor switch S5 155, a sixth semiconductor switch S6 156, a positive DC power bus 110, a negative DC power bus 112, a neutral bus 111, a first AC bus 121, a second AC bus 122, a first direct-bonded copper plate (DBC plate) 143, a second DBC plate 144, a third DBC plate 145, a plurality of conductive spacers 146, a first heat sink 141, and a second heat sink 142.

[0060] The first semiconductor switch S1 151, the second semiconductor switch S2 152, the third semiconductor switch S3 153, the fourth semiconductor switch S4 154, the fifth semiconductor switch S5 155, and the sixth semiconductor switch S6 156 are arranged in a stacked or multilayer configuration comprising a first (bottom) layer 135, a second (middle) layer 136, and a third (top) layer 137. The first layer 135 comprises the second semiconductor switch S2 152 and the fourth semiconductor switch S4 154, which are coplanar. The second layer 136 comprises the fifth semiconductor switch S5 155 and the sixth semiconductor switch S6 156, which are coplanar. The third layer 137 comprises the first semiconductor switch S1 151 and the third semiconductor switch S3 153, which are coplanar.

[0061] The complete stacked arrangement comprises, in ascending order from bottom 134 to top 133: the first heat sink 141; the first DBC plate 143; the negative DC power bus 112; the first layer 135 with the second semiconductor switch S2 152 and the fourth semiconductor switch S4 154; the neutral bus 111; the second layer 136 with the fifth semiconductor switch S5 155 and the sixth semiconductor switch S6 156, the second AC bus 122, the first AC bus 121, the second DBC plate 144 and various conductive spacers 146; the third layer 137 with the first semiconductor switch S1 151, the third semiconductor switch S3 153 and the positive DC power bus 110; the third DBC plate 145; and the second heat sink 142.

[0062] The first semiconductor switch S1 151, the second semiconductor switch S2 152, and the fifth semiconductor switch S5 155 are connected to the first node 161, which is connected to the second AC bus 122. The third semiconductor switch S3 153, the fourth semiconductor switch S4 154, and the sixth semiconductor switch S6 156 are connected to the second node 162, which is connected to the first AC bus 121. The first heat sink 141 is connected via the first DBC board 143, and the second heat sink is connected via the third DBC board 145.

[0063] Referring to Fig. Figure 5 is shown according to another aspect of the disclosure of the H-type multilevel power converter 250, which includes a first semiconductor switch S1 251, a second semiconductor switch S2 252, a third semiconductor switch S3 253, a fourth semiconductor switch S4 254, a fifth semiconductor switch S5 255, a sixth semiconductor switch S6 256, a positive DC power bus 210, a negative DC power bus 212, a neutral bus 211, a first AC bus 221, a second AC bus 222, a first DBC bonded copper plate 243, a second DBC plate 244, a plurality of conductive spacers 246, a first heat sink 241 and a second heat sink 242.

[0064] The first semiconductor switch S1 251, the second semiconductor switch S2 252, the third semiconductor switch S3 253, the fourth semiconductor switch S4 254, the fifth semiconductor switch S5 255, and the sixth semiconductor switch S6 256 are arranged in a stacked or multilayer configuration comprising a first (bottom) layer 235, a second (middle) layer 236, and a third (top) layer 237. The first layer 235 comprises the second semiconductor switch S2 252, the fifth semiconductor switch S5 255, the sixth semiconductor switch S6 256, and the fourth semiconductor switch S4 254, which are coplanar. The second semiconductor switch S2 252 and the fourth semiconductor switch S4 254 are located on the negative DC power bus 212, which is located on the first DBC plate 243. The fifth semiconductor switch S5, 255 and the sixth semiconductor switch S6 256 are arranged on the neutral bus 211, which is located on the first DBC plate 243.The second layer 236 comprises the second AC bus 222 and the first AC bus 221, as well as various conductive spacers 246. The third layer 237 comprises the first semiconductor switch S1 251 and the third semiconductor switch S3 253, which are coplanar and arranged on the positive DC power bus 210.

[0065] The complete stacked arrangement comprises, in ascending order from bottom 234 to top 233: the first heat sink 241; the first DBC plate 243; the negative DC power bus 212 and the neutral bus 211; the first layer 235 with the second semiconductor switch S2 252, the fifth semiconductor switch S5 255, the sixth semiconductor switch S6 256 and the fourth semiconductor switch S4 254; the second layer 236 with the second AC bus 222, the first AC bus 221 and various conductive spacers 246; the third layer 237 with the first semiconductor switch S1 251 and the third semiconductor switch S3 253; the positive DC power bus 210; the second DBC plate 244; and the second heat sink 242.

[0066] The first semiconductor switch S1 251, the second semiconductor switch S2 252, and the fifth semiconductor switch S5 255 are connected to a first node 261, which is connected to the first AC bus 221. The third semiconductor switch S3 253, the fourth semiconductor switch S4 254, and the sixth semiconductor switch S6 256 are connected to a second node 262, which is connected to the second AC bus 222. The first heat sink 241 is connected via the first DBC board 243, and the second heat sink is connected via the second DBC board 244.

[0067] According to another aspect of the revelation, with reference to Fig. Figure 6 shows the H-type multilevel power converter 350, which includes a first semiconductor switch S1 351, a second semiconductor switch S2 352, a third semiconductor switch S3 353, a fourth semiconductor switch S4 354, a fifth semiconductor switch S5 355, a sixth semiconductor switch S6 356, a positive DC power bus 310, a negative DC power bus 312, a neutral bus 311, a first AC bus 321, and a second AC bus 322. It is understood that other elements previously described have been omitted but are included in some aspect of the H-type multilevel power converter 350 when reduced to practical application.

[0068] The first semiconductor switch S1 351, the second semiconductor switch S2 352, the third semiconductor switch S3 353, the fourth semiconductor switch S4 354, the fifth semiconductor switch S5 355, and the sixth semiconductor switch S6 356 are arranged in a stacked or multilayer configuration comprising a first (bottom) layer 335, a second (middle) layer 336, and a third (top) layer 337. The first layer 335 comprises the first semiconductor switch S1 351 and the second semiconductor switch S2 352, which are coplanar. The second layer 336 comprises the fifth semiconductor switch S5 355 and the sixth semiconductor switch S6 356, which are in the same plane. The third layer 337 comprises the fourth semiconductor switch S4 354 and the third semiconductor switch S3 353, which are in the same plane.

[0069] The positive DC power bus 310 and the negative DC power bus 312 are located at a first end 358 of the H-type multilevel power converter 350, while the first AC bus 321 and the second AC bus 322 are located at a second end 360 of the H-type multilevel power converter. The first AC bus 321, the second AC bus 322, the positive DC power bus 310, the negative DC power bus 312, and the neutral bus 311 are connected as shown, according to the circuit diagram referred to in Fig. 3 is shown.

[0070] According to this aspect of the disclosure, both the first AC bus 321 and the second AC bus 322 are located at the same end, i.e., at the second end 360, of the H-type multilevel power converter 350. This configuration enables improved electromagnetic coupling, thereby reducing parasitic inductance.

[0071] According to another aspect of the revelation, with reference to Fig. Figure 7 shows the H-type multilevel power converter 450, which includes a first semiconductor switch S1 451, a second semiconductor switch S2 452, a third semiconductor switch S3 453, a fourth semiconductor switch S4 454, a fifth semiconductor switch S5 455, a sixth semiconductor switch S6 456, a positive DC power bus 410, a negative DC power bus 412, a neutral bus 411, a first AC bus 421, and a second AC bus 422. It is understood that other elements previously described have been omitted but are included in some aspect of the H-type multilevel power converter 450 when reduced to practical application.

[0072] The first semiconductor switch S1 451, the second semiconductor switch S2 452, the third semiconductor switch S3 453, the fourth semiconductor switch S4 454, the fifth semiconductor switch S5 455, and the sixth semiconductor switch S6 456 are arranged in a stacked or multilayer configuration comprising a first (lower) layer 435, a second (middle) layer 436, and a third (upper) layer 437. The first layer 435 includes the sixth semiconductor switch S6 456 and the fifth semiconductor switch S5 455, which are coplanar. The second layer 436 includes the first AC bus 421 and the second AC bus 422. The third layer 437 includes the fourth semiconductor switch S4 454, the third semiconductor switch S3 453, the second semiconductor switch S2 452, and the first semiconductor switch S1 451, which are coplanar.

[0073] The positive DC power bus 410 and the negative DC power bus 412 are located at a first end 458 of the H-type multilevel power converter 350, while the first AC bus 421 and the second AC bus 422 are located at a second end 460 of the H-type multilevel power converter. The first AC bus 421, the second AC bus 422, the positive DC power bus 410, the negative DC power bus 412, and the neutral bus 411 are connected as shown, in accordance with the circuit diagram referred to in Fig. 3 is shown.

[0074] According to another aspect of the revelation, with reference to Fig. Figure 8 shows the H-type multilevel power converter 550, comprising a first semiconductor switch S1 551, a second semiconductor switch S2 552, a third semiconductor switch S3 553, a fourth semiconductor switch S4 554, a fifth semiconductor switch S5 555, a sixth semiconductor switch S6 556, a positive DC power bus 510, a negative DC power bus 512, a first AC bus 521, and a second AC bus 522. It is understood that other elements previously described have been omitted but are included in some aspect of the disclosure of the H-type multilevel power converter 550 when reduced to practical application.

[0075] The first semiconductor switch S1 551, the second semiconductor switch S2 552, the third semiconductor switch S3 553, the fourth semiconductor switch S4 554, the fifth semiconductor switch S5 555, and the sixth semiconductor switch S6 556 are arranged in a stacked or multilayer configuration comprising a first (bottom) layer 535, a second (middle) layer 536, and a third (top) layer 537. The first layer 535 includes the second semiconductor switch S2 552 and the fourth semiconductor switch S4 554, which are coplanar. The second layer 536 includes the fifth semiconductor switch S5 555 and the sixth semiconductor switch S6 556. The third layer 537 includes the first semiconductor switch S1 551 and the third semiconductor switch S3 553, which are in the same plane.The first AC bus 521, the second AC bus 522, the positive DC power bus 510 and the negative DC power bus 512 are connected as shown, according to the arrangement of the circuit referred to in . Fig. 3 is shown.

[0076] According to this aspect of the disclosure, the first AC bus 521 is located at a first end 558 of the H-type multilevel power converter 550, while the second AC bus 522 is located at a second end 560 of the H-type multilevel power converter 550. The first AC bus 521 and the second AC bus 522 each extend across a width W of two semiconductor switches S2 552, S4 554 and S1 551, S3 553, respectively, of the H-type multilevel power converter 550. This configuration allows for a wider parallel connection of the first AC bus 521 and the second AC bus 522, which facilitates current flow and reduces both resistance and parasitic inductance.

[0077] According to another aspect of the revelation, now referring to Fig. Figure 9 shows the H-type multilevel power converter 650, which includes a first semiconductor switch S1 651, a second semiconductor switch S2 652, a third semiconductor switch S3 653, a fourth semiconductor switch S4 654, a fifth semiconductor switch S5 655, a sixth semiconductor switch S6 656, a positive DC power bus 610, a negative DC power bus 612, a first AC bus 621, and a second AC bus 622. It is understood that other elements previously described have been omitted but are included in an embodiment of the H-type multilevel power converter 650 when reduced to practical application.

[0078] The first semiconductor switch S1 651, the second semiconductor switch S2 652, the third semiconductor switch S3 653, the fourth semiconductor switch S4 654, the fifth semiconductor switch S5 655, and the sixth semiconductor switch S6 656 are arranged in a stacked or multilayer configuration comprising a first (bottom) layer 635, a second (middle) layer 636, and a third (top) layer 637. The first layer 635 includes the first semiconductor switch S1 651 and the second semiconductor switch S2 652, which are coplanar. The second layer 636 includes the fifth semiconductor switch S5 655 and the sixth semiconductor switch S6 656. The third layer 637 includes the third semiconductor switch S3 653 and the fourth semiconductor switch S4 654, which are in the same plane.The first AC bus 621, the second AC bus 622, the positive DC power bus 610 and the negative DC power bus 612 are connected as shown, which corresponds to the arrangement of the circuit referred to in . Fig. 3 is shown.

[0079] According to this aspect of the disclosure, both the first AC bus 621 and the second AC bus 622 extend vertically downwards from the H-type multilevel power converter 650. This configuration allows the H-type multilevel power converter to be mounted directly on the electric machine 10, thereby reducing the length of the AC buses 621, 622 between the H-type multilevel power converter 650 and the electric machine 10 and minimizing voltage overshoot.

[0080] According to another aspect of the revelation, with reference to Fig. Figure 10 shows the H-type multilevel power converter 750, comprising a first semiconductor switch S1 751, a second semiconductor switch S2 752, a third semiconductor switch S3 753, a fourth semiconductor switch S4 754, a fifth semiconductor switch S5 755, a sixth semiconductor switch S6 756, a positive DC power bus 710, a negative DC power bus 712, a first AC bus 721, and a second AC bus 722. It is understood that other elements previously described have been omitted but are included in some aspect of the disclosure of the H-type multilevel power converter 750 when reduced to practical application.

[0081] The first semiconductor switch S1 751, the second semiconductor switch S2 752, the third semiconductor switch S3 753, the fourth semiconductor switch S4 754, the fifth semiconductor switch S5 755, and the sixth semiconductor switch S6 756 are arranged in a stacked or multilayer configuration comprising a first (bottom) layer 735, a second (middle) layer 736, and a third (top) layer 737. The first layer 735 includes the first semiconductor switch S1 751 and the second semiconductor switch S2 752, which are coplanar. The second layer 736 includes the fifth semiconductor switch S5 755 and the sixth semiconductor switch S6 756. The third layer 737 includes the third semiconductor switch S3 753 and the fourth semiconductor switch S4 754, which are in the same plane.The first AC bus 721, the second AC bus 722, the positive DC power bus 710, the negative DC power bus 712 and the neutral bus 711 are connected as shown, according to the arrangement of the circuit referred to in . Fig. 3 is shown.

[0082] According to this aspect of the disclosure, both the negative DC power bus 712 and the positive DC power bus 710 are located at a first end 758 of the H-type multilevel power converter 750, while the first AC bus 721 and the second AC bus 722 are located at a second end 760 of the H-type multilevel power converter 750. The first AC bus 720 and the second AC bus 722 each extend over a width W of two semiconductor switches S1 751, S2 752 and S3 753, S4 754, respectively, of the H-type multilevel power converter 750. This configuration facilitates current flow and reduces both resistance and parasitic inductance.

[0083] The presented aspects of the disclosure of the H-type multilevel power converter involve an overlap of the positive DC power bus, the neutral bus, and the negative DC power bus to reduce mutual inductance. This arrangement includes the superposition of the first AC bus with the second AC bus to balance dV / dt and reduce or eliminate electromagnetic interference, and to achieve field cancellation across the P, 0, and N currents to minimize parasitic loop and stray inductances.

[0084] This arrangement facilitates the optimal design of the positive DC power bus, the negative DC power bus, the neutral bus and the DC intermediate circuit capacitor to achieve mutual inductance cancellation.

[0085] This arrangement allows for various heat transfer and cooling systems, including direct cooling, indirect cooling, immersion cooling, single-sided or double-sided cooling.

[0086] This arrangement enables a reduction in voltage and current overshoot when the devices, including chip / power module, bus bars and DC link capacitor, are under load.

[0087] This arrangement allows for a reduction in size and a higher power density than current systems.

[0088] This arrangement allows the use of lower voltage semiconductor switching tools for lower conduction losses and a larger EV range compared to current systems.

[0089] This arrangement facilitates the reduction of ringing and radiating / conducting electromagnetic interference with other subsystems and enables a higher switching speed, which reduces losses and thus increases the vehicle's range and current carrying capacity.

[0090] These and other advantages of the present disclosure will be recognized by those skilled in the art in view of the preceding disclosure.

[0091] The detailed description and the drawings or figures are supporting and descriptive of the present teaching, but the scope of the present teaching is defined exclusively by the claims. While some of the best modes and other examples for carrying out the present teaching have been described in detail, there are various alternative designs and aspects of the disclosure for carrying out the present teaching, which are defined in the attached claims.

Claims

[1] Multi-phase inverter for an electric drive system, the multi-phase inverter comprising: a plurality of H-type multilevel power converters arranged between a high-voltage direct current supply, high-voltage DC supply, and an electric machine of the electric drive system, wherein each of the plurality of H-type multilevel power converters is a solid-state integrated circuit, IC, including: a positive DC power bus; a negative DC power bus; a neutral bus; a plurality of semiconductor switches arranged in a stacked arrangement, the plurality of semiconductor switches being interconnected via the positive DC power bus, the negative DC power bus, and the neutral bus, the plurality of semiconductor switches including: a first semiconductor switch connected to a first node; a second semiconductor switch connected to the first semiconductor switch at the first node, the first semiconductor switch being arranged in series with the second semiconductor switch between the positive DC power bus and the negative DC power bus; a third semiconductor switch connected to a second node; a fourth semiconductor switch connected to the third semiconductor switch at the second node, the third semiconductor switch being arranged in series with the fourth semiconductor switch between the positive DC power bus and the negative DC power bus; a fifth semiconductor switch connected to the first node; and a sixth semiconductor switch connected to the second node, the fifth semiconductor switch being arranged in series with the sixth semiconductor switch via the neutral bus; and a first alternating current bus, AC bus, connected to the first node; a second AC bus connected to the second node; a first heat sink connected to the positive DC power bus of the IC via a first directly bonded copper substrate, DBC substrate; and a second heat sink connected to the negative DC power bus of the IC via a second DBC substrate. [2] The multi-phase inverter of claim 1, wherein the stacked assembly comprises a stack comprising: a first layer composed of the first semiconductor switch arranged to be coplanar with the second semiconductor switch; a second layer composed of the fifth semiconductor switch arranged coplanar to the sixth semiconductor switch, wherein the first layer is arranged parallel to the second layer; and a third layer composed of the third semiconductor switch arranged coplanar to the fourth semiconductor switch, wherein the second layer is arranged parallel to the third layer. [3] The multi-phase inverter of claim 2, wherein the positive DC power bus and the negative DC power bus are arranged at a first end of the H-type multilevel power converter, and wherein the first AC bus and the second AC bus are arranged at a second end of the H-type multilevel power converter. [4] The multi-phase inverter of claim 3, wherein the second AC bus projects outwardly from a lower portion of the IC. [5] The multi-phase inverter of claim 1, wherein the stacked assembly comprises a stack comprising: a first layer composed of the first semiconductor switch, the second semiconductor switch, the third semiconductor switch, and the fourth semiconductor switch arranged to be coplanar with each other; and a second layer composed of the fifth semiconductor switch arranged coplanar with the sixth semiconductor switch, wherein the first layer is arranged parallel to the second layer. [6] The multi-phase inverter of claim 5, wherein the positive DC power bus and the negative DC power bus are disposed at a first end of the H-type multilevel power converter, and wherein the first AC bus and the second AC bus are disposed at a second end of the H-type multilevel power converter. [7] The multi-phase inverter of claim 1, wherein the stacked assembly comprises a stack comprising: a first layer composed of the second semiconductor switch arranged to be coplanar with the fourth semiconductor switch; a second layer composed of the fifth semiconductor switch arranged coplanar with the sixth semiconductor switch; and a third layer composed of the first semiconductor switch arranged to be coplanar with the third semiconductor switch, the first layer being arranged parallel to the second layer. [8] The multi-phase inverter of claim 7, wherein the positive DC power bus and the negative DC power bus are arranged at a first end of the H-type multilevel power converter, and wherein the first AC bus and the second AC bus are arranged at a second end of the H-type multilevel power converter. [9] The multi-phase inverter of claim 1, wherein the stacked assembly comprises a stack comprising: a first layer composed of the first semiconductor switch arranged to be coplanar with the second semiconductor switch; a second layer composed of the fifth semiconductor switch arranged coplanar with the sixth semiconductor switch; and a third layer composed of the third semiconductor switch arranged coplanar to the fourth semiconductor switch, wherein the first layer is arranged parallel to the second layer. [10] The multi-phase inverter of claim 1, wherein the first semiconductor switch, the second semiconductor switch, the third semiconductor switch, and the fourth semiconductor switch each comprise a gallium nitride, GaN, device.

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