SINTERABLE ELECTRICAL CONTACT ON A SEMICONDUCTOR SUBSTRATE

Abstract

A semiconductor device comprises a semiconductor substrate and a sinterable electrical contact disposed over the semiconductor substrate. The sinterable electrical contact comprises a copper-based layer disposed over the semiconductor substrate. The copper-based layer has a thickness between 50 nm and 1000 nm. The sinterable electrical contact further comprises a titanium-based layer disposed between the copper-based layer and the semiconductor substrate. A final functional layer for connecting the sinterable electrical contact by sintering is either the copper-based layer or a silver-based layer disposed over the copper-based layer.

Description

Technical area

[0001] This disclosure relates to semiconductor devices having sinterable electrical contacts, and more particularly to chip metallization techniques for providing high-quality sintered electrical contacts. background

[0002] In general, the problem with electrically bonding a semiconductor substrate by sintering is that the sintered joint is porous, meaning it is typically more susceptible to corrosion than, for example, a soldered joint. For this reason, a sintered joint requires protection from moisture and oxygen, which may not be necessary to the same extent for a soldered joint. For example, a nickel-vanadium layer is known to be used as a protective layer in the metallization stack that forms the sinterable contact.

[0003] Nevertheless, the quality of the subsequent sintered bond, e.g., robustness and / or corrosion resistance, is sensitive to changes in the sintering process parameters. Therefore, it is a constant challenge to provide a sinterable electrical contact on a semiconductor substrate that enables the creation of a high-quality sintered bond within a wide process window (i.e., even under suboptimal sintering conditions, especially in air). Summary

[0004] According to one aspect of the disclosure, a semiconductor device comprises a semiconductor substrate and a sinterable electrical contact disposed over the semiconductor substrate. The sinterable electrical contact comprises a copper-based layer disposed over the semiconductor substrate. The copper-based layer has a thickness between 50 nm and 1000 nm. The sinterable electrical contact further comprises a titanium-based layer disposed between the copper-based layer and the semiconductor substrate. A final functional layer for bonding the sinterable electrical contact by sintering is either the copper-based layer itself or a silver-based layer disposed over the copper-based layer.

[0005] According to another aspect of the disclosure, a system comprises a semiconductor device as specified above and a carrier for the device, which includes a contact pad. The sinterable electrical contact is connected to the contact pad by a sinter bond.

[0006] According to another aspect of the disclosure, a method for forming a sinterable electrical contact on a semiconductor substrate comprises depositing a titanium-based layer over the semiconductor substrate. A copper-based layer is formed over the titanium-based layer. The copper-based layer has a thickness between 50 nm and 1000 nm. A final functional layer for connecting the sinterable electrical contact by sintering is either the copper-based layer itself or a silver-based layer formed over the copper-based layer, wherein the silver-based layer is the final functional layer for connecting the sinterable electrical contact by sintering.

[0007] According to another aspect of the disclosure, a method for attaching a semiconductor device as stated above to a device carrier comprising a contact pad comprises sintering the sinterable electrical contact to the contact pad. Short description of the drawings

[0008] Like reference numerals indicate like or similar elements. The features of the various illustrated embodiments may be combined, provided they are not mutually exclusive, and / or may be selectively omitted unless described as essential. The embodiments are illustrated in the drawings and are detailed by way of example in the following description. Fig. 1 is a schematic cross-sectional view of an example of a semiconductor device including a semiconductor substrate and a sinterable electrical contact. Fig. 2 is a schematic cross-sectional view of a specific example of the semiconductor device of Fig. 1. Fig. 3 is a schematic cross-sectional view of another specific example of the semiconductor device of Fig. 1. Fig. 4 is a schematic cross-sectional view of an example of a system including a semiconductor device bonded to a device carrier by sintering. Fig. 5 is a flowchart illustrating the steps of an exemplary method for forming a sinterable electrical contact on a semiconductor substrate. Fig. 6 is a flowchart illustrating the steps of an exemplary method for attaching a semiconductor device to a carrier by sintering. Detailed description

[0009] It is understood that the features of the various exemplary embodiments and examples described herein may be combined with one another unless expressly stated otherwise.

[0010] In this description, the terms "electrically connected" or "electrically coupled" or similar terms do not imply that the elements are directly connected to each other; intermediate elements may be provided between the "electrically connected" or "electrically coupled" elements. However, according to the disclosure, the above and similar terms may optionally also have the specific meaning that the elements are directly connected to each other, i.e., that no intermediate elements are provided between the "electrically connected" or "electrically coupled" elements.

[0011] Furthermore, the words "over" or "under" or similar terms used herein with respect to a part, element, or layer of material formed or disposed "over" or "under" a surface may be used to mean that the part, element, or layer of material is disposed (e.g., placed, shaped, arranged, deposited, etc.) "directly on" or "directly under" the implied surface, i.e., is in direct contact with it. However, the words "over" or "under" or similar terms used with respect to a part, element, or layer of material formed or disposed "over" or "under" a surface may also be used herein to mean that the part, element, or layer of material is disposed (e.g., placed, shaped, arranged, deposited, etc.) "indirectly on" or "indirectly under" the implied surface.), with one or more additional parts, elements or layers arranged between the implied surface and the part, element or layer of material.

[0012] With reference to Fig. 1, a semiconductor device 100 comprises a semiconductor substrate 110. The semiconductor device 100 further comprises a sinterable electrical contact 120 arranged above the semiconductor substrate 110. The meaning of "sinterable electrical contact" is that the electrical contact is configured to be connected to an electrically conductive structure (such as a contact pad on a carrier of the device) through a sintering process.

[0013] The semiconductor substrate 110 may have a front side 110A and a back side 110B. For example, the sinterable electrical contact 120 is arranged on the back side 110B of the semiconductor substrate 110. In this case, the sinterable electrical contact 120 is also referred to in the art as backside metallization.

[0014] In other examples (not shown), the sinterable electrical contact 120 may be additionally or exclusively arranged on the front side 110A of the semiconductor substrate 110. The sinterable electrical contact 120 may then be referred to as a front side metallization of the semiconductor substrate 110. For illustration, the sinterable electrical contact 120 is in Fig. 1 as the backside metallization, but it can also represent the frontside metallization of the semiconductor substrate 110.

[0015] The semiconductor substrate 110 may, for example, be a semiconductor chip or a semiconductor wafer. The semiconductor substrate 110 may include one or more electrical components, such as one or more integrated circuits (not shown), which individually or in combination control a current flow between the front side 110A and the back side 110B of the semiconductor substrate 110. Such semiconductor devices 110 are also referred to as vertical devices. In other examples, the semiconductor substrate 110 may include one or more electrical components which individually or in combination control a current flow in a lateral direction. Such semiconductor devices 100 are also referred to as lateral (or horizontal) devices. In lateral devices, one or more sinterable electrical contacts 120 may, for example, be provided only on one main side (either the front side 110A or the back side 110B) of the semiconductor substrate 110.

[0016] The electrical component can be, for example, a power component. In this case, the semiconductor device 100 is a power semiconductor device 100. Power semiconductor devices 100 can, for example, control voltages of 50 V, 100 V, 500 V, 750 V, or 1000 V or more.

[0017] The electrical component (not shown) integrated into the semiconductor substrate 110 can be, for example, a transistor or a transistor group. The semiconductor device 100 can be, for example, a discrete transistor. The electrical component integrated into the semiconductor substrate 110 can be, for example, a MOSFET (metal oxide semiconductor field-effect transistor) or an IGBT (insulated gate bipolar transistor).

[0018] In other examples, the electrical component (not shown) integrated into the semiconductor substrate 110 may include or be a diode. In this case, the semiconductor device 100 may be a discrete diode device, e.g., a power diode. For example, the semiconductor device 100 may include or be a fast-switching EMCON (emitter-controlled) diode.

[0019] In other words, the semiconductor substrate 110 may be, for example, a diode or transistor power chip and / or the semiconductor device 100 may be, for example, a (discrete) diode or transistor power package.

[0020] The semiconductor substrate 110 includes or consists of a semiconductor material, such as Si, SiC, SiGe, Ge, GaN, GaAs, InAs, etc., and other compound semiconductors. In particular, the semiconductor substrate 110 may include or consist of Si or a wide bandgap (WBG) semiconductor material, such as SiC, GaN, and many III-V and II-VI compound semiconductors with a wide bandgap.

[0021] In some examples, the sinterable electrical contact 120 may form a load contact of the semiconductor device 100. For example, the sinterable electrical contact 120 may form a source contact or an emitter contact of the semiconductor device 100 (e.g., a MOSFET or an IGBT, respectively). Additionally or alternatively, the sinterable electrical contact 120 may form a drain contact or a collector contact of the semiconductor device 100 (e.g., a MOSFET or an IGBT, respectively).

[0022] The sinterable electrical contact 120 comprises a titanium-based layer 122 and a copper-based layer 124. Here and below, the term "X-based layer" means that the layer is made of material X or of an alloy containing material X as the main alloying material.

[0023] The copper-based layer 124 is disposed over the semiconductor substrate 110. The titanium-based layer 122 is disposed between the copper-based layer 124 and the semiconductor substrate 110. In some examples, the copper-based layer 124 may directly adjoin the titanium-based layer 122.

[0024] In a first case, the copper-based layer 124 is a final functional layer for connecting the sinterable electrical contact 120 by sintering. In this case, a surface of the final functional layer facing away from the substrate 110 can be formed, for example, by a surface 124A of the copper-based layer 124. That is, the final functional layer can provide an exposed surface for connecting the sinterable electrical contact 120 by a sintering process.

[0025] The final functional layer of the sinterable electrical contact 120 is the layer that interacts with the sinter bond material (not shown) during the sintering process. While in many examples, the final functional layer (therefore) provides the exposed surface of the sinterable electrical contact 120, it is also possible for the final functional layer to be coated with a cover layer (not shown), which may, for example, serve as a protective layer that facilitates sintering, for example, because it does not form a stable metal oxide at the sintering process temperature, even when processed in air.

[0026] In a second case, a silver-based layer 126 can be arranged, for example, over the copper-based layer 124. In this case, the silver-based layer 126 is the final functional layer for connecting the sinterable electrical contact 120 by sintering. Similar to the first case, a surface 126A of the silver-based layer 126 facing away from the substrate 110 can be an exposed surface of the sinterable electrical contact 120 or can be covered, for example, by a coating that does not impair the functionality for sintering the final functional layer (here: the silver-based layer 126).

[0027] The copper-based layer 124 has a thickness T3 between 50 nm and 1000 nm. In concrete examples, the thickness T3 of the copper-based layer 124 can be, for example, between 100 nm and 500 nm, in particular between 200 nm and 400 nm.

[0028] It should be noted that the thickness T3 of the copper-based layer 124 may be significantly smaller compared to the thickness of a copper layer in an electrical contact that is a solderable contact. Copper layers in solderable electrical contacts are typically at least partially "consumed" during the soldering process and therefore must have a higher minimum thickness.

[0029] The sinterable electrical contact 120 may, for example, be a non-solderable contact. This means that the sinterable electrical contact 120 cannot be connected to an electrically conductive structure (e.g., a contact pad on a device carrier) by a soldering process.

[0030] The titanium-based layer 122 may have a thickness T2 between 100 nm and 500 nm, in particular between 200 nm and 400 nm.

[0031] The titanium-based layer 122 acts as a diffusion barrier and (optionally) as an adhesion promoter (at least when a Ti-Cu interface is present). In many examples, the copper-based layer 124 and the titanium-based layer 122 are in direct contact with each other, i.e., they provide such an interface. However, in other examples, one or more other layers (e.g., a tungsten layer, not shown) may optionally be disposed between the titanium-based layer 122 and the copper-based layer 124.

[0032] The silver-based layer 126, if present, may have a thickness T4 between 20 nm and 1500 nm, in particular between 100 or 200 nm and 400 or 1000 nm.

[0033] Conventional sinterable electrical contacts often use a nickel-vanadium-based layer sandwiched between the semiconductor substrate 110 and a final silver-based layer 126. Nickel-vanadium-based layers are weakened by oxygen that may enter the layer during or after the sintering process. A final silver layer 126 does not prevent oxygen from reaching the nickel-vanadium-based layer, as oxygen can permeate the silver layer 126.

[0034] It was found that the interface between a copper-based layer 124 and a final silver layer is not mechanically weakened by oxygen to the same extent as the conventional nickel-vanadium-based layer. This could possibly be due to the fact that the cohesion between a final silver layer and a copper oxide is stronger than that between a final silver layer and a nickel oxide.

[0035] In some examples, the sinterable electrical contact 120 does not include a nickel-vanadium-based layer. In other words, the copper-based layer 124 can be used to replace layers such as the nickel-vanadium-based layer commonly used in sinterable electrical contacts. By avoiding a nickel-vanadium-based layer, the robustness of the sinterable electrical contact is improved.

[0036] Furthermore, the copper-based layer 124, in contrast to a (conventional) nickel-vanadium-based layer, can form the final functional layer for sintering (see the first case described above). This may be particularly attractive when switching from a silver paste sintering process to a copper paste sintering process, since a copper-based final functional layer 124 sintered with a copper paste is likely to provide particularly high mechanical stability of the sintered bond (as described in more detail below).

[0037] Furthermore, a contact layer (in Fig. 1 not shown, see for example layer 210 in the Fig. 2 and Fig. 3) be arranged between the semiconductor substrate 110 and the titanium-based layer 122. The contact layer may contain or be made of a material that establishes good electrical contact between the sinterable electrical contact 120 and the semiconductor substrate 110.

[0038] Fig. 2 shows a specific example of the semiconductor device 100 of Fig. 1. In this example, the semiconductor substrate 110 may, for example, contain or consist of silicon (Si). The sinterable electrical contact 120 includes or consists of the titanium-based layer 122, the copper-based layer 124, and the silver-based layer 126. In the specific example shown, the titanium-based layer 122 is made of titanium with, for example, T2 = 400 nm, the copper-based layer 124 is made of copper with, for example, T3 = 300 nm, and the silver-based layer 126 is made of silver with, for example, T4 = 200 nm.

[0039] In particular, if the semiconductor substrate 110 is made of silicon, a contact layer formed by an aluminum-based layer 210 can also be arranged between the sinterable electrical contact 120 and the substrate 110. The aluminum-based layer 210 can, for example, have a thickness T0 between 100 nm and 500 nm, in particular between 200 nm and 400 nm. The aluminum-based layer 210 can serve as an electrical contact to the silicon substrate 110. The aluminum-based layer 210 can, for example, be made of aluminum. In the example shown, T0 = 400 nm.

[0040] With reference to Fig. Figure 3 shows another specific example of the semiconductor device 100. In this example, the semiconductor substrate 110 comprises or is made of silicon carbide (SiC), for example.

[0041] In this case, an aluminum-based layer is not required to form an electrical contact with the semiconductor substrate 110. Rather, the electrical contact with the semiconductor substrate 110 can be formed, for example, by a nickel-silicon (NiSi)-based layer 310.

[0042] The nickel-silicon-based layer 310 may, for example, be arranged between the titanium-based layer 122 and the semiconductor substrate 110. The nickel-silicon-based layer 310 may have a thickness T0 between 20 nm and 200 nm, in particular between 30 nm and 80 nm. In the specific example shown, the nickel-silicon-based layer 310 may, for example, have a thickness T0 = 40 nm.

[0043] The sinterable electrical contact 120 in Fig. 3 comprises the titanium-based layer 122, the copper-based layer 124, and (optionally) the silver-based layer 126. The titanium-based layer 122 may, for example, be made of titanium and have, for example, a thickness T2 = 200 nm. The copper-based layer 124 may, for example, be made of copper and have, for example, a thickness T3 = 300 nm. The silver-based layer 126 (if present) may, for example, be made of silver and have, for example, a thickness T4 = 200 nm.

[0044] All specific thickness values specified in the Fig. 2 and Fig. 3 may be varied within the above-mentioned limits and / or within ranges of, for example, ±50%, ±30%, ±10%.

[0045] In all examples, it is possible to avoid a nickel-vanadium-based layer, which is commonly used for contact formation. This eliminates the risk of a sintered bond with poor mechanical properties due to oxygen degradation of a nickel-vanadium-based layer.

[0046] Furthermore, the sinterable electrical contact in all examples may be tin-free and / or may not contain a tin-based layer. Tin-based layers are commonly used in solderable electrical contacts.

[0047] Fig. 4 shows a system 400 with a semiconductor device 100 that is connected to a device carrier 410 by sintering.

[0048] The device carrier 410 may be any device carrier for mounting a semiconductor device 100, in particular a device carrier 410 configured for mounting a power semiconductor device 100. For example, the semiconductor device carrier 410 may be, e.g., a lead frame, a printed circuit board (PCB), or a ceramic-based carrier, such as a copper-plated ceramic carrier, e.g., a DBC (Direct-Bonded-Copper) carrier. The device carrier 410 includes a contact pad 420. The contact pad 420 may, but need not, be a standalone part of the carrier 410, but may, e.g., merely represent a zone or region of the carrier 410 on which the semiconductor device 100 is to be mounted.

[0049] The sinterable electrical contact 120 is connected to the contact pad 420 by a sintered bond 450. The sintered bond 450 contains sintered metal particles 452. The sintered metal particles 452 are in contact with each other and are electrically connected to both the final functional layer of the sinterable electrical contact 120 and the contact pad 420. As previously mentioned, the final functional layer of the sinterable electrical contact 120 can be formed by the copper-based layer 124 or by the silver-based layer 126 (and can, for example, be provided with an exposed surface 124A of the copper-based layer 124 or with an exposed surface 126A of the silver-based layer 126).

[0050] The metal sintered particles 452 of the sintered bond 150 may contain silver or be made of silver. In this case, the final functional layer may be, for example, the silver-based layer 126. However, it is also possible to use a sintered bond 450 made of silver sintered particles 452 for a sinterable electrical contact 120, in which the final functional layer is the copper-based layer 124.

[0051] In other examples, the sintered bond 450 includes copper-based sintered particles 452. In one possibility, the copper-based sintered particles 452 may be bonded to a silver-based final functional layer, e.g., to the surface 126A of the silver-based layer 126.

[0052] In other examples, the sinterable electrical contact 120 may be provided with a copper-based final functional layer. In this case, the copper-based sintered particles 452 may be directly bonded to the surface 124A of the copper-based layer 124. A direct copper-to-copper connection may provide high mechanical properties for the sintered bond connection 450. In particular, oxygen degradation of the mechanical properties of the sinterable electrical contact 120 may be greatly reduced by combining a copper-based sintered bond connection 450 with a copper-based terminal of the sinterable electrical contact 120.

[0053] In relation to Fig. 5, a method for forming a sinterable electrical contact 120 on a semiconductor substrate 110 at A1 includes depositing a titanium-based layer 122 over the semiconductor substrate 110. Prior to depositing the titanium-based layer 122, several processes may be performed, which may depend on the material of the semiconductor substrate 110.

[0054] For Si-based technologies (cf. Fig. 2) A pre-cleaning process can first be performed. The pre-cleaning can be performed, for example, as in-situ H2 reactive plasma etching or as ex-situ RF wet etching. The pre-cleaning process removes native SiO2 from the exposed surface of the semiconductor substrate 110.

[0055] Subsequently, the aluminum-based layer 210 (or another contact layer) can be deposited, for example, on the cleaned surface of the semiconductor substrate 110. The deposition of aluminum can be performed, for example, by physical vapor deposition (PVD) such as sputter deposition. During aluminum deposition, the wafer temperature can be increased to approximately 200-400°C, for example, by increasing the temperature of the chuck and / or the sputtering power of the deposition process. The increased substrate temperature leads to the recrystallization of the silicon at the interface with the aluminum-based layer 210 and the formation of an ohmic contact between the silicon substrate 110 and the aluminum-based layer 210.

[0056] After the deposition of the titanium-based layer 122 at A1, the copper-based layer 124 is formed over the titanium-based layer 122 at A2. The copper-based layer 124 can be formed, for example, by sputter deposition or electroplating. The copper-based layer 124 has a thickness between 50 nm and 1000 nm.

[0057] The aluminum-based layer 210, the titanium-based layer 122, and the copper-based layer 124 can be applied by sputter deposition, for example, in different modules (process chambers) of a PVD cluster system. In this case, the semiconductor substrate 110 can be kept under vacuum between the application of the various layers to prevent contamination and oxidation of the interfaces. This can prevent the risk of delamination of adjacent layers.

[0058] For silicon carbide technologies (SiC) (cf. Fig. 3) Contact formation can occur prior to the deposition of the titanium-based layer 122 at A1 by depositing the NiSi-based layer 310. The NiSi-based layer 310 can have a composition of, for example, 11 wt% Si and 89 wt% Ni. The formation of the NiSi-based layer 310 can be performed in combination with a laser thermal treatment (LTA) process.

[0059] Subsequently, one or more ex-situ cleaning processes can be performed prior to the deposition of the titanium-based layer at A1. The ex-situ cleaning process(es) can be used to remove carbon resulting from a Ni / SiC reaction or to remove oxide layer(s). Furthermore, an in-situ H2 plasma etch pre-cleaning of the surface of the NiSi-based layer 310 can be performed prior to the deposition of the titanium-based layer 122 at A1.

[0060] Subsequently, the titanium-based layer 122 (at A1) and the copper-based layer 124 (at A2) can be deposited, e.g., by sputter deposition without vacuum interruption. The deposition of the individual layers 122, 124, and 126 can be performed in the same manner as described above for the silicon-based technology.

[0061] According to the first case, the copper-based layer 124 (at A3_1) is the final functional layer for connecting the sinterable electrical contact 120 by sintering. Alternatively, according to the second case, the silver-based layer 126 is subsequently applied over the copper-based layer 124. In this case, the final functional layer for connecting the sinterable electrical contact by sintering is the silver-based layer 126 (at A3_2).

[0062] As mentioned above, A3_1 can enable a bare copper connection of the sinterable electrical contact 120 in combination with copper sintering. This special option allows for the elimination of the silver-based layer 126 and can ensure high mechanical quality during sintering.

[0063] In all examples where a silver-based layer 126 is used, the provision of the copper-based layer 124 allows for a reduction in the thickness T4 of the silver-based layer 126 compared to a situation where no copper-based layer 124 were present. For example, without a copper-based layer 124, a thicker silver-based layer 126 (e.g., T4 3 800 nm) is required to achieve the desired robustness of the sinterable electrical contact 120. However, high T4 values lead to longer deposition cycle times and thus higher costs.

[0064] In relation to Fig.6, a method for attaching the semiconductor device 100 to a device carrier 410 may include: at B1, a semiconductor device 100 as described above is provided, and at B2, a device carrier 410 comprising a pad 420 is provided.

[0065] At B3, the sinterable electrical contact 120 is sintered to the contact pad 420. Sintering may include applying the sintering material (e.g., silver particles or copper particles or a mixture of silver and copper particles) to the contact pad 420 to which the semiconductor device 100 is to be sintered.

[0066] The sintering material (silver and / or copper particles 452) can be contained, for example, in a sintering paste. If the metal sintering particles 452 are dispersed in a volatile solution, the (porous) sintered bond compound 450 can contain or consist of only the metal sintering particles 452 after sintering. If the metal sintering particles 452 are dispersed in an epoxy material, the epoxy material can cure during sintering, so that the sintering bond compound 450 contains a cured epoxy matrix in which the metal sintering particles 452 are embedded.

[0067] During the sintering process, which can be performed by applying pressure to the semiconductor substrate 110 and the device carrier 410 and / or by supplying energy (e.g., heat, radiation, etc.), the metal particles 452 bond together. Typically, the metal particles 452 are not melted during the sintering process, and no intermetallic phases form between the sintered material and the surface of the final functional layer and / or the surface of the contact pad 420.

[0068] A process window for sintering can contain parameters (sintering specifications) that must be met. These parameters can include, for example, the pressure to be applied, the heat to be applied (sintering temperature), the atmosphere under which the sintering process is to be carried out (e.g., under vacuum or air), and the sintering time. The wider the process window, the simpler and more reliable the sintering process. This is particularly important for customers who receive bare chips, where the chip manufacturer has no control over the subsequent sintering process. For example, the sintering specifications may allow sintering in air due to the improved stability of the sinterable electrical contact 120. EXAMPLES

[0069] The following examples refer to further aspects of the revelation: Example 1 is a semiconductor device comprising a semiconductor substrate and a sinterable electrical contact disposed over the semiconductor substrate. The sinterable electrical contact comprises a copper-based layer disposed over the semiconductor substrate. The copper-based layer has a thickness between 50 nm and 1000 nm. The sinterable electrical contact further comprises a titanium-based layer disposed between the copper-based layer and the semiconductor substrate. A final functional layer for connecting the sinterable electrical contact by sintering is either the copper-based layer itself or a silver-based layer disposed over the copper-based layer. In Example 2, the subject matter of Example 1 can optionally comprise: wherein the sinterable electrical contact is a non-solderable contact. In Example 3, the subject matter of Example 1 or 2 can optionally comprise: wherein the semiconductor substrate is a silicon substrate or a silicon carbide substrate. In Example 4, the subject matter of any preceding example can optionally include wherein the semiconductor device is a power device and the sinterable electrical contact is a load contact of the power device. In Example 5, the subject matter of any preceding example can optionally include wherein the copper-based layer and the titanium-based layer are in direct contact with each other. In Example 6, the subject matter of any preceding example may optionally comprise wherein the copper-based layer has a thickness between 100 nm and 500 nm, in particular between 200 nm and 400 nm. In Example 7, the subject matter of any preceding example may optionally comprise wherein the titanium-based layer has a thickness between 100 nm and 500 nm, in particular between 200 nm and 400 nm. In Example 8, the subject matter of any preceding example can optionally comprise: wherein the final functional layer provides an exposed surface for connecting the sinterable electrical contact by sintering. In Example 9, the subject matter of any preceding example may optionally comprise: wherein the silver-based layer has a thickness between 20 nm and 1500 nm, in particular between 200 nm and 400 nm. In Example 10, the subject matter of any preceding example may optionally further comprise an aluminum-based layer disposed between the titanium-based layer and the semiconductor substrate, in particular a silicon substrate. In Example 11, the subject matter of Example 10 may optionally comprise: wherein the aluminum-based layer has a thickness between 100 nm and 500 nm, in particular between 200 nm and 400 nm. In Example 12, the subject matter of any preceding example can optionally further comprise: wherein a nickel-silicon-based layer is disposed between the titanium-based layer and the semiconductor substrate, in particular a silicon carbide substrate. In Example 13, the subject matter of Example 12 may optionally comprise: wherein the nickel-silicon-based layer has a thickness between 20 nm and 200 nm, in particular between 30 nm and 80 nm. In Example 14, the subject matter of any preceding example can optionally comprise: wherein the sinterable electrical contact does not comprise a nickel-vanadium-based layer and / or a tin-based layer. In Example 15, the subject matter of any preceding example can optionally include wherein the sinterable electrical contact is or forms part of a backside metallization and / or a frontside metallization of the semiconductor device. Example 16 is a system comprising a semiconductor device as described above and a carrier for the device having a contact pad. The sinterable electrical contact is connected to the contact pad by a sinter bond. In Example 17, the subject matter of Example 16 can optionally comprise wherein the sintered bond compound comprises silver-based sintered particles. In Example 18, the subject matter of Example 17 may optionally comprise wherein the last functional layer is the silver-based layer. In Example 19, the subject matter of Example 19 can optionally comprise wherein the sintered bond compound comprises copper-based sintered particles. In Example 20, the subject matter of Example 16 can optionally comprise: wherein the last functional layer is the copper-based layer. Example 21 is a method for forming a sinterable electrical contact on a semiconductor substrate, comprising depositing a titanium-based layer on the semiconductor substrate. A copper-based layer is formed over the titanium-based layer. The copper-based layer has a thickness between 50 nm and 1000 nm. A final functional layer for connecting the sinterable electrical contact by sintering is the copper-based layer or a silver-based layer formed over the copper-based layer, wherein a final functional layer for connecting the sinterable electrical contact by sintering is the silver-based layer. In Example 22, the subject matter of Example 21 can optionally comprise: wherein the semiconductor substrate is a silicon substrate, the method further comprising depositing an aluminum-based layer over the silicon substrate prior to depositing the titanium-based layer, wherein the silicon substrate is heated to a temperature between 200°C and 400°C during deposition of the aluminum-based layer. In Example 23, the subject matter of Example 21 can optionally comprise: wherein the semiconductor substrate is a silicon carbide substrate, the method further comprising depositing a nickel-silicon-based layer over the silicon carbide substrate prior to depositing the titanium-based layer and annealing the silicon carbide substrate and the nickel-silicon-based layer. In Example 24, the subject matter of Example 21 can optionally comprise: wherein the copper-based layer is formed by sputtering or electroplating. Example 25 is a method of attaching a semiconductor device according to any one of Examples 1 to 15 to a device carrier comprising a contact pad. The method includes sintering the sinterable electrical contact to the contact pad.

[0070] Although specific embodiments have been shown and described herein, it will be apparent to those skilled in the art that the specific embodiments shown and described may be replaced with a variety of alternative and / or equivalent implementations without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, this invention is to be limited only by the claims and their equivalents.

Claims

[1] Semiconductor device comprising: a semiconductor substrate; and a sinterable electrical contact disposed over the semiconductor substrate, the sinterable electrical contact comprising: a copper-based layer disposed over the semiconductor substrate, the copper-based layer having a thickness between 50 nm and 1000 nm; and a titanium-based layer disposed between the copper-based layer and the semiconductor substrate, wherein a final functional layer for bonding the sinterable electrical contact by sintering is either the copper-based layer or a silver-based layer disposed over the copper-based layer. [2] A semiconductor device according to claim 1, wherein the sinterable electrical contact is a non-solderable contact. [3] A semiconductor device according to claim 1 or 2, wherein the semiconductor substrate is a silicon substrate or a silicon carbide substrate. [4] Semiconductor component according to one of the preceding claims, wherein the semiconductor component is a power component and the sinterable electrical contact is a load contact of the power component. [5] A semiconductor device according to any one of the preceding claims, wherein the copper-based layer and the titanium-based layer are in direct contact with each other. [6] Semiconductor component according to one of the preceding claims, wherein the copper-based layer has a thickness between 100 nm and 500 nm, in particular between 200 nm and 400 nm. [7] Semiconductor component according to one of the preceding claims, wherein the titanium-based layer has a thickness between 100 nm and 500 nm, in particular between 200 nm and 400 nm. [8] A semiconductor device according to any one of the preceding claims, wherein the last functional layer provides an exposed surface for bonding the sinterable electrical contact by sintering. [9] Semiconductor component according to one of the preceding claims, wherein the silver-containing layer has a thickness between 20 nm and 1500 nm, in particular between 200 nm and 400 nm. [10] A semiconductor device according to any one of the preceding claims, further comprising: an aluminum-containing layer arranged between the titanium-containing layer and the semiconductor substrate, in particular a silicon substrate. [11] Semiconductor component according to claim 10, wherein the aluminum-based layer has a thickness between 100 nm and 500 nm, in particular 200 nm and 400 nm. [12] A semiconductor device according to any one of the preceding claims, further comprising: a nickel-silicon-based layer arranged between the titanium-based layer and the semiconductor substrate, in particular a silicon carbide substrate. [13] Semiconductor component according to claim 12, wherein the nickel-silicon-based layer has a thickness between 20 nm and 200 nm, in particular between 30 nm and 80 nm. [14] Semiconductor component according to one of the preceding claims, wherein the sinterable electrical contact does not comprise a nickel-vanadium-based layer and / or a tin-based layer. [15] Semiconductor component according to one of the preceding claims, wherein the sinterable electrical contact is a backside metallization and / or a frontside metallization of the semiconductor component or forms a part thereof. [16] A system comprising a semiconductor device according to any one of the preceding claims and a carrier for the device comprising a pad, wherein the sinterable electrical contact is connected to the pad by a sinter bond. [17] The system of claim 16, wherein the sintered bond compound comprises silver-based sintered particles. [18] The system of claim 17, wherein the final functional layer is a silver-based layer. [19] The system of claim 16, wherein the sintered bond compound comprises copper-based sintered particles. [20] The system of claim 19, wherein the final functional layer is the copper-based layer. [21] A method of forming a sinterable electrical contact on a semiconductor substrate, the method comprising: Depositing a titanium-based layer over the semiconductor substrate; and Forming a copper-based layer over the titanium-based layer, wherein the copper-based layer has a thickness between 50 nm and 1000 nm, wherein a final functional layer for connecting the sinterable electrical contact by sintering is the copper-based layer; or Forming a silver-based layer over the copper-based layer, wherein a final functional layer for connecting the sinterable electrical contact by sintering is the silver-based layer. [22] The method of claim 21, wherein the semiconductor substrate is a silicon substrate, the method further comprising: Depositing an aluminum-based layer over the silicon substrate prior to depositing the titanium-based layer, wherein the silicon substrate is heated to a temperature between 200 °C and 400 °C during the deposition of the aluminum-based layer. [23] The method of claim 21, wherein the semiconductor substrate is a silicon carbide substrate, the method further comprising: Depositing a nickel-silicon-based layer over the silicon carbide substrate before depositing the titanium-based layer and Annealing the silicon carbide substrate and the nickel-silicon-based layer. [24] A method according to any one of claims 21 to 23, wherein the copper-based layer is formed by sputtering or electroplating. [25] A method of attaching a semiconductor device according to any one of claims 1 to 15 to a device carrier comprising a contact pad, the method comprising: Sintering the sinterable electrical contact on the contact pad.

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