Enabling threshold voltage adjustments in stacked CFETS with shared gates

Abstract

Procedure with the following steps: Forming a first semiconductor channel region (26'L) and a second semiconductor channel region (26'U), wherein the second semiconductor channel region overlaps the first semiconductor channel region; forming a first gate dielectric (78) on the first semiconductor channel region; forming a second gate dielectric (78) on the second semiconductor channel region; Forming a first dipole layer (82-1) and a second dipole layer (82-2) on the first gate dielectric and the second gate dielectric, respectively; Driving dipole dopants in the first dipole layer and the second dipole layer into the first gate dielectric and the second gate dielectric, respectively, whereby the first and second gate dielectrics receive the same dipole dopant; Removing the first dipole layer and the second dipole layer; and Producing a gate electrode (80) on both the first gate dielectric and the second gate dielectric, wherein the gate electrode and the first gate dielectric are included in a first transistor, and the gate electrode and the second gate dielectric are included in a second transistor, wherein work function layers (80WF) in the gate electrode have p-type work functions, and wherein the first transistor is a p-type transistor and the second transistor is an n-type transistor, and wherein the second dipole layer is thicker than the first dipole layer, or wherein the first transistor is an n-type transistor and the second transistor is a p-type transistor, and wherein the second dipole layer is thinner than the first dipole layer.

Description

BACKGROUND

[0001] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers over a semiconductor substrate. The various material layers are patterned by lithography to create circuit components and elements on the substrate.

[0002] The semiconductor industry is continually improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, allowing more components to be integrated into a given area. However, reducing the minimum feature size creates additional problems that need to be addressed: US 2022 / 0165731 A1 discloses: A semiconductor device structure comprising first semiconductor layers and second semiconductor layers disposed beneath and aligned with the first semiconductor layers. Each first semiconductor layer is surrounded by a first and a fourth layer. The first layer is disposed between the first semiconductor layer and the fourth layer and comprises first and a second material. The fourth layer comprises third and a fourth material. Each second semiconductor layer is surrounded by a second and a third layer. The second layer is disposed between the second semiconductor layer and the third layer and comprises the first and a fifth material. The third layer comprises the third and a sixth material.The second and fourth materials are a dipole material with a first polarity, and the fifth and sixth materials are a dipole material with a second polarity opposite to the first polarity. Further state of the art is known from SUN, Chong-Jhe [et al.]: Threshold voltage adjustment by varying Ge content in SiGe p-channel for single metal shared gate complementary FET (CFET). In: Nanomaterials, Vol. 12, 2022, No. 20, pp. 1-10 (3712).

[0003] The invention relates to possibilities for threshold voltage adjustment in stacked complementary transistors with a common gate electrode. This is particularly advantageous for providing arrangements with multiple CFETs with different threshold voltages. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1 shows a perspective view of example complementary field-effect transistors (CFETs) according to some embodiments. The Fig. 2 to 24A and 24B are views of intermediate stages in the fabrication of CFETs according to some embodiments. Fig. 25 shows the relationship between effective work functions, threshold voltages, and dipole layer thicknesses of PFETs and NFETs according to some embodiments. The Fig. 26-1, 26-2, and 26-3 illustrate schematic dipole dopant atomic percents in the gate dielectrics of a plurality of FETs, according to some embodiments. Fig. 27 shows a flow diagram for fabricating CFETs according to some embodiments. DETAILED DESCRIPTION

[0005] The invention is defined in the independent claims. Further developments emerge from the subclaims. The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the manufacture of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are manufactured in direct contact, and may also include embodiments in which additional elements may be manufactured between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present invention, reference numerals and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0007] A complementary field-effect transistor (CFET) structure and the method of fabricating the same are provided. Throughout the specification, the terms "FET" and "transistor" are used interchangeably. According to some embodiments, a CFET structure includes a plurality of NFETs and PFETs fabricated to have multiple threshold voltages. A plurality of common p-type metal gates are each shared by a pair of FETs (comprising an NFET and a PFET) in a same CFET structure. An n-type dipole dopant is used. The threshold voltages of the PFETs and NFETs are adjusted by doping the gate dielectrics of the NFETs and PFETs to different atomic percents.Although the p-type metal is also used for the NFETs, the effective work function values ​​of the work function layers of the NFETs are lowered to the range of n-type work functions by heavily doping the gate dielectrics of the NFETs with the dipole dopant.

[0008] It should be understood that although p-type metal gates and n-type dipole dopants are used as an example, n-type metal gates and p-type dipole dopants can also be used to fabricate a plurality of CFETs with different threshold voltages. Although gate-all-around (GAA) transistors (such as nanostructure FETs) are discussed, the concept of the present disclosure can also be applied to the fabrication of other types of transistors, such as planar transistors, fin field-effect transistors (FinFETs), or the like.

[0009] Fig. 1 shows an example of CFETs 10 (including FETs (transistors) 10U and 10L) according to some embodiments. Fig. Figure 1 is a three-dimensional view, with some features of the CFETs omitted for clarity.

[0010] The CFETs include multiple vertically stacked FETs. For example, a CFET may include a bottom nanostructure FET 10L of a first device type (e.g., n-type / p-type) and an upper nanostructure FET 10U of a second device type (e.g., p-type / n-type) opposite to the first device type. The nanostructure FETs 10U and 10L include semiconductor nanostructures 26' (comprising bottom semiconductor nanostructures 26'L and top semiconductor nanostructures 26'U), with the semiconductor nanostructures 26' acting as the channel regions for the nanostructure FETs. The bottom semiconductor nanostructures 26'L are for the bottom nanostructure FET 10L, and the top semiconductor nanostructures 26'U are for the top nanostructure FET 10U.

[0011] Gate dielectrics 78 enclose the respective semiconductor nanostructures 26'. Gate electrodes 80 (including a lower gate electrode 80L and an upper gate electrode 80U) are located above the gate dielectrics 78. Source / drain regions 62 (including lower source / drain regions 62L and upper source / drain regions 62U) are arranged on opposite sides of the gate dielectrics 78 and the respective gate electrodes 80. Depending on the context, the source / drain region may refer to a source or a drain, individually or collectively. Isolation structure elements (not shown) may be formed to separate desired ones of the source / drain regions 62 and / or desired ones of the gate electrodes 80.

[0012] Fig. 1 further shows reference cross-sections used in later figures. Cross-section AA' is a vertical cross-section parallel to a longitudinal axis of the semiconductor nanostructures 26' of a CFET and extending in a direction of, for example, current flow between the source / drain regions 62 of the CFET. Cross-section BB' is a vertical cross-section perpendicular to cross-section AA' and extending along a longitudinal axis of a gate electrode 80 of the CFET. Cross-section CC' is a vertical cross-section parallel to cross-section BB' and extending through the source / drain regions 62 of the CFETs. Subsequent figures may refer to these reference cross-sections for clarity.

[0013] The Fig. 2 to 24A and 24B show the cross-sectional views of intermediate stages in the fabrication of CFETs (shown schematically in Fig. 1) according to some embodiments. The corresponding processes are also schematically shown in the process flow shown in Fig. 27. Unless otherwise indicated, in the following discussion, the figures whose numbers are followed by a letter 'A' show the vertical cross-sectional views along a similar cross-section to the vertical reference cross-section AA' in Fig. 1. The figures, whose numbers are followed by a letter “B”, show the cross-sectional views along a similar cross-section to the vertical reference cross-section BB’ in Fig. 1. The figures, whose numbers are followed by a letter “C”, show the vertical cross-sectional views along a similar cross-section to the vertical reference cross-section CC' in Fig. 1.

[0014] In Fig. 2, a wafer 2 comprising a substrate 20 is provided. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The SOI substrate may comprise a layer of semiconductor material formed on an insulator layer. The insulator layer may, for example, be a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, such as a silicon or a glass substrate. Other substrates, such as a multilayer or a gradient substrate, may also be used.In some embodiments, the semiconductor material of the substrate 20 may comprise silicon, germanium, carbon-doped silicon, a III-V compound semiconductor, or the like, or combinations thereof.

[0015] A multilayer stack 22 is fabricated over the substrate 20. The respective process is designated as process 202 in the process flow 200 shown in Fig. 27. The multilayer stack 22 includes alternating dummy semiconductor layers 24 (including dummy semiconductor layers 24A and a dummy semiconductor layer 24B) and semiconductor layers 26 (including lower semiconductor layers 26L and upper semiconductor layers 26U). The lower semiconductor layers 26L and the upper semiconductor layers 26U are for fabricating a lower FET and an upper FET, respectively.

[0016] Corresponding wells (not shown separately) can be formed in the lower semiconductor layers 26L and the upper semiconductor layers 26U. For example, the semiconductor layers 26L and 26U (when grown epitaxially) can be doped in situ and / or implanted to exhibit desirable conductivity types.

[0017] In the illustrated example, the multilayer stack 22 includes six of the dummy semiconductor layers 24 and six of the semiconductor layers 26. It is understood that the multilayer stack 22 may include any number of the dummy semiconductor layers 24 and the semiconductor layers 26. Each layer of the multilayer stack 22 may be grown using a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), deposited using a process such as a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process, or the like.

[0018] The dummy semiconductor layers 24A are made of a first semiconductor material, and the dummy semiconductor layer 24B is made of a second semiconductor material that is different from the first semiconductor material. The first and second semiconductor materials can be selected from the candidate semiconductor materials of the substrate 20. The first and second semiconductor materials have a high etch selectivity with respect to each other. Therefore, the dummy semiconductor layer 24B can be removed at a faster speed than the dummy semiconductor layers 24A in later processes.

[0019] The semiconductor layers 26 (including the lower semiconductor layers 26L and the upper semiconductor layers 26U) are made of one or more semiconductor materials. The one or more semiconductor materials may be selected from the candidate semiconductor materials of the substrate 20. The lower semiconductor layers 26L and the upper semiconductor layers 26U may be made of the same semiconductor material or may be made of different semiconductor materials.

[0020] In some embodiments, the dummy semiconductor layers 24A are made of or include silicon germanium, the semiconductor layers 26 are made of silicon, and the dummy semiconductor layer 24B may be made of germanium or silicon germanium having higher atomic percent germanium than in the semiconductor layer 24A.

[0021] In Fig. 3, the multilayer stack 22 and the substrate 20 are patterned to produce semiconductor strips 28. Each of the semiconductor strips 28 comprises a semiconductor strip 20' (the portions of the original substrate 20) and a multilayer stack 22', which is the remaining portion of the multilayer stack 22. The remaining portions 22' of the multilayer stack 22 are hereinafter referred to as nanostructures, which are designated using the corresponding reference numeral followed by a "" symbol. Accordingly, the multilayer stack 22' comprises dummy nanostructures 24'A, dummy nanostructures 24'B, bottom semiconductor nanostructures 26'L, middle semiconductor nanostructures 26'M, and top semiconductor nanostructures 26'U. The etching can be performed using any suitable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching can be anisotropic.The dummy nanostructures 24'A and the dummy nanostructures 24'B may further be collectively referred to as dummy nanostructures 24'. The lower semiconductor nanostructures 26'L and the upper semiconductor nanostructures 26'U may further be collectively referred to as semiconductor nanostructures 26'.

[0022] The lower semiconductor nanostructures 26'L will function as channel regions for the lower nanostructure FETs of the CFETs. The upper semiconductor nanostructures 26'U will function as channel regions for the upper nanostructure FETs of the CFETs. The middle semiconductor nanostructures 26'M are the semiconductor nanostructures 26' that are immediately above / below (e.g., in contact with) the dummy nanostructures 24'B. The middle semiconductor nanostructures 26'M can be used for isolation and can serve as channel regions for the CFETs or not. The dummy nanostructures 24'B will be replaced later with isolation structures. The isolation structures and the middle semiconductor nanostructures 26'M can define boundaries of the lower nanostructure FETs and the upper nanostructure FETs.

[0023] In Fig. 4, isolation regions 32 are formed over the substrate 20 and between adjacent semiconductor strips 28. The isolation regions 32 may comprise a dielectric coating and a dielectric material over the dielectric coating. The isolation regions 32 are then recessed. Some upper portions of the semiconductor strips 28 (comprising the multilayer stacks 22') protrude beyond the remaining isolation regions 32 and form protruding fins 34.

[0024] A dummy dielectric layer 36 is then formed on the protruding fins 34. The dummy dielectric layer 36 may be formed of, or comprise, silicon oxide, silicon nitride, a combination thereof, or the like, for example, and may be deposited or thermally grown using suitable methods. A dummy gate layer 38 is formed over the dummy dielectric layer 36. The dummy gate layer 38 may be deposited, for example, using physical vapor deposition (PVD), CVD, or other methods and then planarized, for example, using a chemical-mechanical polishing (CMP) process. The material of the dummy gate layer 38 may be conductive or non-conductive and may be selected from a group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), or the like.A mask layer 40 is formed over the planarized dummy gate layer 38 and may comprise, for example, silicon nitride, silicon oxynitride, or the like.

[0025] Then, the mask layer 40 is patterned using photolithographic and etching processes to produce a mask, which is then used to etch and pattern the dummy gate layer 38 and possibly the dummy dielectric layer 36. A resulting structure is shown in Fig. 5. The remaining portions of the mask layer 40, the dummy gate layer 38, and the dummy dielectric layer 36 form the dummy gate stack 42.

[0026] In Fig. 5, gate spacers 44 are formed over the multilayer stacks 22' and on exposed sidewalls of the dummy gate stacks 42. The gate spacers 44 may be formed by conformally forming one or more dielectric layers and subsequently anisotropically etching the dielectric layers. Suitable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like, which may be formed using a deposition process such as CVD, ALD, or the like. Fin spacers 45 are also formed.

[0027] Source / drain recesses 46 are then formed in the semiconductor strips 28. The source / drain recesses 46 are formed by etching and may extend through the multilayer stacks 22' and into the semiconductor strips 20'. The bottom surfaces of the source / drain recesses 46 may be level with the top surfaces of the isolation regions 32, or at a lower level or higher level than these. During the etching processes, the gate spacers 44 and the dummy gate stacks 42 mask some portions of the semiconductor strips 28. The etching may comprise a single etching process or multiple etching processes. Timed etching processes may be used to stop the etching of the source / drain recesses 46 once the source / drain recesses 46 reach a desired depth.

[0028] The dummy nanostructures 24'A are laterally recessed, and a dielectric material is filled into the respective recesses to produce internal spacers 54, which are dielectric spacers. The resulting structure is shown in Fig. 6 shown.

[0029] Subsequently, lower epitaxial source / drain regions 62L are formed in the lower parts of the source / drain recesses 46 ( Fig. 5). The lower epitaxial source / drain regions 62L are in contact with the lower semiconductor nanostructures 26'L and are not in contact with the upper semiconductor nanostructures 26'U. The inner spacers 54 isolate the lower epitaxial source / drain regions 62L from the dummy nanostructures 24'A, which will be replaced by replacement gates in later processes.

[0030] The lower epitaxial source / drain regions 62L are grown epitaxially and have a conductivity type appropriate for the device type (p-type or n-type) of the lower nanostructure FETs. When the lower epitaxial source / drain regions 62L are n-type source / drain regions, the respective material may comprise silicon or carbon-doped silicon doped with an n-type dopant, such as phosphorus, arsenic, or the like. When the lower epitaxial source / drain regions 62L are p-type source / drain regions, the respective material may comprise silicon or silicon germanium doped with a p-type dopant, such as boron, indium, or the like. The lower epitaxial source / drain regions 62L may be doped in situ with the corresponding p- or n-dopants and may or may not be implanted with the corresponding p- or n-dopants.

[0031] A first contact etch stop layer (CESL) 66 and a first interlayer dielectric (ILD) 68 are formed. The first CESL 66 may be formed from a dielectric material having high etch selectivity to the etch of the first ILD 68, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which may be formed using any suitable deposition process, such as CVD, ALD, or the like. The first ILD 68 may be formed from a dielectric material deposited using any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or flowable chemical vapor deposition (FCVD).The suitable dielectric material of the first ILD 68 may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, or the like.

[0032] The manufacturing processes may include depositing a conformal CESL layer, depositing a material for the ILD 68, followed by a planarization process, and then an etch-back process. In some embodiments, the first ILD 68 is etched first, leaving the first CESL 66 unetched. An anisotropic etch process is then performed to remove the portions of the first CESL 66 that are higher than the recessed first ILD 68. After the recessing, the sidewalls of the upper semiconductor nanostructures 26'U are exposed.

[0033] Then, the upper epitaxial source / drain regions 62U are formed in the upper parts of the source / drain recesses 46. The materials of the upper epitaxial source / drain regions 62U can be selected from the same candidate group of materials as used to form the lower source / drain regions 62L, depending on the desired conductivity type of the upper epitaxial source / drain regions 62U.

[0034] The conductivity type of the upper epitaxial source / drain regions 62U may be opposite to the conductivity type of the lower epitaxial source / drain regions 62L. In other words, the upper epitaxial source / drain regions 62U may be oppositely doped to the lower epitaxial source / drain regions 62L. The upper epitaxial source / drain regions 62U may be doped and / or implanted in situ with an n-type or p-type dopant.

[0035] Then, a second CESL 70 and a second ILD 72 are fabricated. The materials and fabrication methods may be similar to the materials and fabrication methods of the first CESL 66 and the first ILD 68, respectively, and are not discussed in detail here. The fabrication process may include depositing the layers for the CESL 70 and the ILD 72 and performing a planarization process to remove the excess portion of the respective layers. After the planarization process, the top surfaces of the second ILD 72, the gate spacer 44, and the dummy gate stack 42 are coplanar (within process variances). With the planarization process, the masks 40 may be removed, or the hard masks 40 may remain without being removed.

[0036] The dummy gate stacks 42 are then removed in one or more etching processes to form recesses 74 which are inserted into the Fig. 7A and Fig. 7B. The respective process is shown as process 230 in the process flow 200, which is shown in Fig. 27. Each of the recesses 74 exposes portions of the multilayer stacks 22' and / or is located over portions of the multilayer stacks 22'.

[0037] The remaining parts of the dummy nanostructures 24'A ( Fig. 6) are then removed by etching so that the recesses 74 extend between the semiconductor nanostructures 26'. In the etching process, the dummy nanostructures 24'A are etched at a faster rate than the semiconductor nanostructures 26', the dielectric insulation layers 56, and the inner spacers 54. The etching may be isotropic. For example, if the dummy nanostructures 24'A are made of silicon germanium and the semiconductor nanostructures 26' are made of silicon, the etching process may include a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like.

[0038] In the Fig. 8A and Fig. 8B, the gate dielectrics 78 are formed in the recesses 74 and are formed on the exposed semiconductor nanostructures 26'. The respective process is described as process 232 in the process flow 200 shown in Fig. 27. The gate dielectrics 78 are formed on the exposed surfaces of the exposed features comprising the semiconductor nanostructures 26' and the gate spacers 44. The gate dielectrics 78 enclose all (e.g., four) sides of the semiconductor nanostructures 26'.

[0039] The Fig. 9-15 show the details of the formation of the gate dielectrics 78 and the common gate electrodes 80 (with 80U and 80L) according to some embodiments. In Fig. 9, three device regions 400, 500, and 600 are shown. Each of the device regions is for the fabrication of a CFET having an upper FET and a lower FET. Each of the device regions 400, 500, and 600 can, as shown in Fig. 11, from the area 86, which in Fig. 8B. In the illustrated example, the upper FETs are PFETs with different threshold voltages, while the lower FETs are NFETs with different threshold voltages. The PFET and NFET in each of device regions 400, 500, and 600 are intended to share a common gate electrode. The common gate electrode of both the PFET and the NFET includes a work function layer made of a p-type work function metal having a high work function higher than the average work function of about 4.5 eV.

[0040] In Fig. 9, the gate dielectrics 78 are fabricated to enclose the nanostructures 26'U, 26M, and 26'L. Each of the gate dielectrics 78 may include an interfacial layer 78IL, which may be made of or include a Group IV element, a Group III element, and / or a Group V element. The interfacial layer 78IL may include an oxide, such as silicon oxide or a metal oxide, a silicate, such as a metal silicate, combinations thereof, multilayers thereof, or the like. The interfacial layer 78IL may have a thickness in the range between about 0.5 nm and about 2 nm. The interfacial layer 78IL may be fabricated using a thermal oxidation process and / or a deposition process.

[0041] The gate dielectrics 78 may also include high-k dielectric layers 78HK having a high dielectric constant (high-k value) greater than, for example, about 7.0, about 21, or higher. The high-k dielectric layers 78HK may be formed from, or may include, a metal oxide or silicate of a metal selected from hafnium, zirconium, barium, titanium, lead, and combinations thereof. The fabrication methods of the high-k dielectric layers 78HK may be selected from molecular beam deposition (MBD), ALD, PECVD, and the like. The high-k dielectric layers 78HK may have a thickness in the range between about 1 nm and about 5 nm. The gate dielectrics 78 in the device regions 400, 500, and 600 are fabricated in common processes.

[0042] For clarity, the 78 gate dielectrics are referred to as 78-400U and 78-400L, 78-500U and 78-500L, and 78-600U and 78-600L, with postfixes used to identify their corresponding device regions and positions (upper "U" or lower "L"). Accordingly, the 78HK high-k dielectric layers are also referred to as 78HK-400U and 78HK-400L, 78HK-500U and 78HK-500L, and 78HK-600U and 78HK-600L.

[0043] Dipole layers 82-1 and 82-2 are deposited on the gate dielectrics 78 in the device regions 500 and 400, respectively. The respective process is described as process 234 in the process flow 200, which is shown in Fig. 27. However, no dipole layer is formed in the device region 600.

[0044] Dipole layers 82-1 and 82-2 include an n-dipole dopant which, when incorporated into the gate dielectrics of n-FETs, can reduce the effective work functions and consequently the threshold voltages of the corresponding n-FETs. The n-dipole dopant, when incorporated into the gate dielectrics of p-FETs, can reduce the effective work functions and consequently increase the threshold voltages of the corresponding p-FETs. According to some embodiments, dipole layers 82-1 and 82-2 can comprise a material selected from one or more of one or more oxides, one or more nitrides, and / or one or more carbides of one or more n-dipole dopants, such as La, Sr, Y, Er, Sc, Mg, or the like, or combinations thereof.

[0045] The dipole layers 82-1 and 82-2 may be formed using a plurality of conformal deposition processes (such as ALD, CVD, or the like) and a plurality of patterning processes. The dipole layers 82-1 and 82-2 have thicknesses T2 and T1, respectively, where the thickness T2 is greater than the thickness T1. An exemplary manufacturing process may include: depositing a first dipole layer having a thickness (T2-T1) on the gate dielectrics 78 in the device regions 400, 500, and 600; performing a first patterning process to remove the first dipole layer from the device region 500; depositing a second dipole layer having the thickness T1 on the gate dielectrics 78 in the device regions 400, 500, and 600; and performing a second patterning process to remove both the first dipole layer and the second dipole layer from the device region 600.

[0046] In Fig. 10, dummy filling areas 84 are produced in the device areas 400, 500 and 600. The respective process is designated as process 236 in the process flow 200, which is shown in Fig. 27. According to some embodiments, the dummy fill regions 84 are formed from a material having a high etch selectivity for the exposed features of the structure formed in the Fig. 8A, Fig. 8B and Fig. 10. For example, the dummy filler regions 84 may be made of SiN, SiOC, SiO, SiOCN, SiCN, AlO, AlN, CoN, or the like. The manufacturing process may include: depositing a filler material to completely fill the recesses 74 ( Fig. 8B); performing a planarization process to flatten the top surface of the fill material; and etching back the fill material. The etching process is controlled such that the top surfaces of the dummy fill region 84 are at a level between the top surface and the bottom surface of the dielectric isolation layers 56, although the top surface may be slightly higher or lower. The dummy fill region 84 may have a flat top surface within process variations.

[0047] An isotropic etching process is then carried out, as in Fig. 11. The etching process may be a wet etching process or a dry etching process, which are isotropic. The etching chemical is selected such that the dipole layers 82-1 and 82-2 are etched and the process is stopped on the high-k dielectric layers 78HK. The respective process is designated as process 238 in the process flow 200, which Fig. 27. Accordingly, the portions of the dipole layers 82-1 and 82-2 on the upper semiconductor nanostructures 26'U and the upper of the middle semiconductor nanostructures 26'M are removed. The portions of the dipole layers 82-1 and 82-2 on the lower semiconductor nanostructures 26'L and the lower of the middle semiconductor nanostructures 26'M are protected and not removed.

[0048] In Fig. 12, dipole layers 82-3, 82-4 and 82-5 are deposited on the gate dielectrics 78 in the device regions 400, 500 and 600, respectively. The respective process is designated as process 240 in the process flow 200, which is shown in Fig. 27. The dipole layers 82-1, 82-2, 82-3, 82-4, and 82-5 are hereinafter referred to individually and collectively as dipole layers 82. The dipole layers 82-3, 82-4, and 82-5 have thicknesses T3, T4, and T5, respectively.

[0049] According to some embodiments, the relationship T5 > T4 > T3 > T2 > T1 exists. The thicknesses T1 to T5 can be between about 0.3 nm and about 1.5 nm, and the specific range of each of the thicknesses T1 to T5 is selected based on the desirable atomic percentage of the dipole dopant in the respective high-k dielectric layers 78HK. According to some embodiments, the thickness T1 is in the range between about 0.3 nm and about 0.4 nm, and the thickness T5 is in the range between about 1.3 nm and about 1.6 nm. The thicknesses T2, T3, and T4, which are greater than the thickness T1 and less than the thickness T5, are selected based on the desirable atomic percentage of the dipole dopant in the respective high-k dielectric layers 78HK.

[0050] It should be understood that although the thicknesses T3, T4 and T5 are present in the device regions 400, 500 and 600, respectively, in the illustrated example, each of the thicknesses T3, T4 and T5 may be present in any combination in each of the device regions 400, 500 and 600, depending on the circuit requirement.

[0051] Dipole layers 82-3, 82-4, and 82-5 also include an n-dipole material that can be selected from the same group of candidate materials as used to form dipole layers 82-1 and 82-2. For example, dipole layers 82-3, 82-4, and 82-5 can include the oxides, nitrides, and / or carbides of one or more n-dipole dopants, such as La, Sr, Y, Er, Sc, Mg, or the like, or combinations thereof. The n-dipole material of dipole layers 82-3, 82-4, and 82-5 can also be the same as or different from the n-dipole material of dipole layers 82-1 and 82-2.

[0052] The dipole layers 82-3, 82-4, and 82-5 may be formed using a plurality of conformal deposition processes and a plurality of patterning processes. For example, the fabrication process may include: depositing a first dipole layer into the device regions 400, 500, and 600; removing the first dipole layer from the device regions 400 and 500; depositing a second dipole layer into the device regions 400, 500, and 600; removing the first dipole layer and the second dipole layer from the device region 400; and depositing a third dipole layer into the device regions 400, 500, and 600. The thicknesses of the first dipole layer, the second dipole layer, and the third dipole layer are selected to achieve desirable thicknesses T3, T4, and T5.

[0053] In a later process, the dummy filler region 84 is removed to expose the dipole layers 82-1 and 82-2 and to expose the high-k gate dielectric layer 78HK-600L. The respective process is described as process 242 in the process flow 200 shown in Fig. 27. The resulting structure is shown in Fig. 13. Some horizontal portions of the dipole layer material are present on the dummy fill regions 84. These portions of the dipole layer material can be removed using an anisotropic etching process or a physical removal process (which is anisotropic), such as sputtering, where, for example, argon can be used.

[0054] After removing the dummy filler regions 84, all dipole layers 82-1, 82-2, 82-3, 82-4, and 82-5 are exposed. In device region 400, dipole layers 82-3 and 82-2 have thicknesses T3 and T2, respectively. In device region 500, dipole layers 82-4 and 82-1 have thicknesses T4 and T1, respectively. In device region 600, dipole layers 82-5 have thicknesses T5, and no dipole layer is formed on the high-k gate dielectric layer 78HK-600L.

[0055] Further with reference to Fig. 13, an annealing process 88 is carried out to drive the dipole dopants in the dipole layers 82 into the respective underlying high-k dielectric layers 78HK. The respective process is described as process 244 in the process flow 200 shown in Fig. 27. The annealing process 88 may be performed in a process gas, such as N2, He, NH3, Ar, or the like, or the mixture thereof. According to some embodiments, the annealing process 88 is performed using a soak annealing process, a rapid thermal spike annealing process, or the like. When the soak annealing process is used, the annealing time may be in the range between about 5 seconds and about 5 minutes. The annealing temperature may be in the range between about 500°C and about 850°C. When the rapid thermal spike annealing process is used, the annealing time may be in the range between about 0.5 seconds and about 3.5 seconds. The annealing temperature may be in the range between about 700°C and about 850°C.

[0056] Annealing results in the dipole dopant in the dipole layers 82 being driven into the respective underlying high-k dielectric layer 78HK. The atomic percentages of the dipole dopant in the high-k dielectric layers 78HK-400U(T3), 78HK-400L(T2), 78HK-500U(T4), 78HK-500L(T2), and 78HK-600U(T5) are indicated as AP78-400U(T3), AP78-400L(T2), AP78-500U(T4), AP78-500L(T1), and AP78-600U(T5), respectively. The thickness values ​​(in parentheses) following the reference designations of the high-k dielectric layers and the atomic percentage values ​​are used to indicate the thicknesses of the respective dipole layers for clarity and easy correspondence.

[0057] It is understood that thicker dopant layers result in the respective underlying high-k dielectric layers having higher dopant atomic percentages of the dipole dopant, and vice versa. Accordingly, the relationship AP78-600U(T5) > AP78-500U(T4) > AP78-400U(T3) > AP78-400L(T2) > AP78-500L(T1) exists. Furthermore, since no dipole layer is formed on the 78HK-600L high-k dielectric layer, the 78HK-600L high-k dielectric layer may or may not contain the dipole dopant, depending on whether the 78HK-600L high-k dielectric layer (as deposited) contains the dipole dopant. There is also the relationship AP78-500L(T1) > AP78-600L.

[0058] Assuming that the dipole dopant atomic percentage AP78-500L(T2) is considered a base (reference) atomic percentage APB, the dipole dopant atomic percentage AP78-400L(T2) can range between about 1.5 APB and about 2.0 APB. The dipole dopant atomic percentage AP78-400U(T3) can range between about 3.0 APB and about 3.5 APB. The dipole dopant atomic percentage AP78-500U(T4) can range between about 7.0 APB and about 7.5 APB. The dipole dopant atomic percentage AP78-600U(T5) can range between about 10.0 APB and about 10.5 APB. The dipole dopant atomic percentages and their ratios can be determined by energy dispersive X-ray spectroscopy (EDS), electron energy loss spectroscopy (EELS), and / or secondary ion mass spectrometry (SIMS).The desirable dipole dopant atomic percentages can be achieved by fabricating the dipole layers 82 with suitable thicknesses.

[0059] The dipole layers 82 are then removed in an isotropic etching process. The resulting structure is shown in Fig. 14, with the high-k dielectric layers 78HK exposed.

[0060] Fig. 15 shows the production of gate electrodes 80. The respective process is shown as process 246 in the process flow 200, which is shown in Fig. 27. The gate dielectrics 78 and the respective gate electrodes 80 are collectively referred to as gate stacks 90, which include an upper gate stack 90U and a lower gate stack 90L. The upper FET and the lower FET in each of the device regions 400, 500, and 600 share a common gate electrode 80. The upper portions of the gate electrodes 80 that are higher than the dielectric insulation layers 56 are referred to as upper gate electrodes 80U. The lower portions of the gate electrodes that are deeper than the dielectric insulation layers 56 are referred to as lower gate electrodes 80L. The gate electrodes 80 may include a plurality of layers comprising TiN, TaN, or the like, and may include one or more work function layers 80WF. The thickness of each of the layers in the gate electrodes 80 may range between about 2 nm and about 5 nm.

[0061] The work function layers 80WF surrounding each of the gate dielectrics 78 may be physically separated from the work function layers 80WF surrounding other gate dielectrics 78. In this case, a (non-work function) fill metal region 80FM (such as tungsten, cobalt, ruthenium, or the like) may fill the spaces between the work function layers 80WF on the adjacent gate dielectrics 78. Alternatively, the work function layers 80WF surrounding each of the gate dielectrics 78 may be physically connected to the work function layers 80WF surrounding other gate dielectrics 78.

[0062] According to some embodiments, the work function layers 80WF have a p-type work function that is higher than about 4.8 eV and may be in the range between about 4.8 eV and about 5.2 eV.

[0063] The resulting FETs include an upper FET 10U-400 and a lower FET 10L-400 in device region 400, an upper FET 10U-500 and a lower FET 10L-500 in device region 500, and an upper FET 10U-600 and a lower FET 10L-600 in device region 600. The upper FETs 10U-400, 10U-500, and 10U-600 are NFETs, and the lower FETs 10L-400, 10L-500, and 10L-600 are PFETs.

[0064] As mentioned above, the gate electrodes 80 of the upper n-FETs 10U-400, 10U-500, and 10U-600 have p-type work function layers with high work function values, for example, higher than 4.8 eV. However, the n-FETs prefer n-type work functions that have low work function values, for example, less than about 4.5 eV, such as between about 4.0 eV and about 4.5 eV. According to embodiments of the present disclosure, this conflict is resolved by heavily doping the high-k dielectric layers 78HK of the NFETs with the n-type dipole dopant, such that the effective work functions of the p-type work functions layers 80WF in the NFETs are reduced to the n-type work function range, for example, between about 4.0 eV and about 4.5 eV.

[0065] Fig. Figure 25 shows the effect of doping with n-type dipole dopants on reducing the effective work function and the effect of doping on the threshold voltages of the respective FETs. In the direction of an arrow labeled "eWF" (effective work function), the thickness of the dopant layers decreases, and the effective work functions increase more and more, even though the same work function material is used. It is understood that increasing the thickness of the n-type dopant layers has the effect of reducing the work function of the respective work function layer from a high p-type work function PWF-0 to a medium p-type work function PWF-1 and then to a low p-type work function PWF-2.A further increase in the thickness of the n-dopant layer has the effect of reducing the work function of the respective work function layer from a high n-work function NWF-3, to a medium n-work function NWF-4 and then to a low n-work function NWF-5.

[0066] As in Fig. As shown in Figure 25, the PFETs have threshold voltages LVt-P, MVt-P, and LVT-P corresponding to having no dipole layer, having the dipole layer with thickness T1, and having the dipole layer with thickness T2, respectively. The NFETs have threshold voltages HVt-N, MVt-N, and LVT-N corresponding to dipole layers with thicknesses T3, T4, and T5, respectively. Accordingly, when the gate electrodes of multiple NFETs and PFETs are made of the same one or more p-type work functions, the effective work functions can be adjusted to appropriate values ​​by adjusting the thicknesses of the dipole layers, and both the effective n-type work functions and the effective p-type work functions can be achieved, resulting in desirable threshold voltages.

[0067] With further reference to Fig. 15, the NFETs 10U-400, 10U-500, and 10U-600 have a high threshold voltage HVt-N, a medium threshold voltage MVt-N, and a low threshold voltage LVt-N, respectively. The PFETs 10L-400, 10L-500, and 10L-600 have a high threshold voltage HVt-P, a medium threshold voltage MVt-P, and a low threshold voltage LVt-P, respectively.

[0068] It is understood that the dipole dopants are diffused from dipole layers that are removed after diffusion. Accordingly, after removing the dipole layers 82, the peak dipole dopant atom percentage can appear on the outside of the high-k dielectric layers 78HK, which will be in contact with the gate electrodes 80 fabricated later. Fig. Figure 26-1 schematically shows the dipole dopant atomic percentages as a function of positions, showing the dipole dopant distribution in the interface layer 78IL, the high-k dielectric layer 78HK, and the gate electrode 80. Lines 146-1, 146-2, 146-3, 146-4, and 146-5 correspond to the dipole layer thicknesses T1, T2, T3, T4, and T5, respectively. The peak dipole dopant atomic percentage may occur at the interface between the high-k dielectric layers 78HK and the corresponding gate electrodes 80. Alternatively, the peak dipole dopant atomic percentages in the high-k dielectric layers 78HK ( Fig. 26-2) or at or near the interface between the high-k dielectric layers 78HK and the corresponding interface layers 78IL ( Fig. 26-3). The peak position may shift slightly to the left or right, for example, with displacement distances smaller than about 1 nm.

[0069] By using the same materials for the gate electrodes of both the PFETs and the NFETs, there is no need to etch the gate electrodes of the upper FETs and then re-fabricate the gate electrodes for the upper FETs. Etching the gate electrodes can damage the high-k dielectric layers. Accordingly, according to embodiments of the present disclosure, damage to the high-k dielectric layers is avoided by using common gate electrodes.

[0070] The Fig. 16 to 22 illustrate the fabrication of CFETs according to alternative embodiments. These embodiments are similar to the embodiments in Fig. 9 to 15, except that the upper FETs are PFETs, while the lower FETs are NFETs. The gate electrodes of both the PFETs and the NFETs are also made of a similar work function material with a high p-type work function, and the effective work functions of the gate electrodes are adjusted to desirable values ​​by doping an n-type dipole dopant. Unless otherwise stated, the materials, structures, thicknesses, and fabrication processes according to these embodiments may be substantially the same as those described above with reference to the Fig. 9 to 15 are the same and are not repeated here.

[0071] With reference to Fig. 16, a plurality of gate dielectrics 78 are formed in device regions 400', 500', and 600', respectively. Dipole layers 82-3, 82-4, and 82-5 are formed, having thicknesses T3, T4, and T5, respectively, as discussed with reference to the previous embodiments.

[0072] With reference to Fig. 17, dummy fill regions 84 are fabricated and are etched back to mask the dipole layers 82-3, 82-4 and 82-5 in the lower FET regions, while the parts of the dipole layers 82-3, 82-4 and 82-5 in the upper FET regions are exposed.

[0073] Fig. Figure 18 shows the removal of the dipole layers 82-3, 82-4, and 82-5 from the upper FET regions. The high-k dielectrics 78HK (comprising 78HK-400, 78HK-500, and 78HK-600) in the upper FET regions are consequently exposed. Then, as shown in Fig. 19, dipole layers 82-2 and 82-1 are formed on the gate dielectrics 78 in the upper FET regions in device regions 400 and 500, respectively. No dipole layer is formed in device region 600. Dipole layers 82-2 and 82-1 have thicknesses T2 and T1, respectively, as discussed above with reference to the preceding embodiments.

[0074] Fig. Figure 20 shows the removal of the dummy fill regions 84, followed by the annealing process 88 for driving the dipole dopants in the dipole layers 82 into the respective underlying high-k dielectrics 78HK. Then, the dipole layers 82 are removed in an etching process, exposing the underlying high-k dielectric layers 78HK. The resulting structure is shown in Fig. 21 shown.

[0075] Fig. Figure 22 shows the fabrication of gate electrodes 80 for CFETs. The resulting upper FETs 10U-400, 10U-500, and 10U-600 are PFETs, and the lower FETs 10L-400, 10L-500, and 10L-600 are NFETs. The dipole dopant atomic percentages in the high-k dielectric layers 78HK-600U, 78HK-500U(T1), 78HK-400U(T2), 78HK-400L(T3), 78HK-500L(T4), and 78HK-600L(T5) progressively increase due to the increasingly thick dipole layers. The effective work function values ​​of the gate electrodes of 10U-600, 10U-500, and 10U-400, 10L-400, 10L-500, and 10L-600 become progressively lower. The threshold voltages of the upper FETs 10U-400, 10U-500, and 10U-600 are HVt-P, MVt-P, and LVt-P, respectively, which become progressively lower. The threshold voltages of the lower FETs 10L-400, 10L-500, and 10L-600 are HVt-N, MVt-N, and LVt-N, respectively, which also become progressively lower.The combination of the thicknesses of dipole dopant layers in the upper FETs and the thicknesses of dipole dopant layers in the lower FETs is again an example, and any combination can be used.

[0076] The Fig. 23A and Fig. 23B show cross-sectional views of an exemplary CFET fabricated in previous processes. Each of the CFETs in device regions 400, 500, and 600 can be formed by the Fig. 23A and Fig. 23B. The common gate electrode 80 includes the upper electrode 80U and the lower electrode 80L, which are fabricated using the same processes and materials.

[0077] As in the Fig. 23A and Fig. 23B, gate masks 92 are formed over the dummy gate stacks 42. The fabrication process may include: recessing the gate stacks 90; filling the resulting recesses with a dielectric material, such as silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, or the like; and performing a planarization process to remove the excess portions of the dielectric material over the second ILD 72. Silicide regions 94 and source / drain contact plugs 96U are formed to be electrically connected to the source / drain regions 62U.

[0078] With reference to the Fig. 24A and Fig.24B, an etch stop layer (ESL) 104 and a third ILD 106 are formed. In some embodiments, the ESL 104 may comprise a dielectric material having a high etch selectivity to the etching of the third ILD 106, such as aluminum oxide, aluminum nitride, silicon oxide carbide, or the like. The third ILD 106 may be formed using flowable CVD, ALD, or the like, and the material may comprise PSG, BSG, BPSG, USG, or the like, which may be deposited using any suitable method, such as CVD, PECVD, or the like.

[0079] The embodiments of the present disclosure have several advantageous features. A common work function material, such as a p-type work function material, is used to fabricate the gate electrodes of a multi-PFET and multiple PFETs. By doping dipole dopants (such as an n-type dipole dopant) into the gate dielectrics of the multiple FETs to different atomic percents, the effective work functions of the multiple FETs can be tuned to different levels, and different threshold voltages can be achieved.

[0080] According to some embodiments, a method comprises: forming a first semiconductor channel region and a second semiconductor channel region, wherein the second semiconductor channel region overlaps the first semiconductor channel region; forming a first gate dielectric on the first semiconductor channel region; forming a second gate dielectric on the second semiconductor channel region; forming a first dipole layer and a second dipole layer on the first gate dielectric and the second gate dielectric, respectively; driving dipole dopants in the first dipole layer and the second dipole layer into the first gate dielectric and the second gate dielectric, respectively; removing the first dipole layer and the second dipole layer;and forming a gate electrode on both the first gate dielectric and the second gate dielectric, wherein the gate electrode and the first gate dielectric are included in a first transistor, and the gate electrode and the second gate dielectric are included in a second transistor;

[0081] In one embodiment, work function layers in the gate electrode have p-type work functions, wherein a first one of the first transistor and the second transistor is a p-type transistor, and a second one of the first transistor and the second transistor is an n-type transistor. In one embodiment, the first transistor is the p-type transistor and the second transistor is the n-type transistor, and wherein the second dipole layer is thicker than the first dipole layer. In one embodiment, the first transistor is the n-type transistor and the second transistor is the p-type transistor, and wherein the second dipole layer is thinner than the first dipole layer. In one embodiment, the method further comprises: forming a first source / drain region adjacent to the first semiconductor channel region; and forming a second source / drain region adjacent to the second semiconductor channel region, the second source / drain region overlapping the first source / drain region.

[0082] In one embodiment, the method further comprises: forming a first contact plug located above and electrically connected to the first source / drain region; and forming a second contact plug located below and electrically connected to the second source / drain region. In one embodiment, the first transistor and the second transistor have opposite conductivity types.In one embodiment, the method further comprises: fabricating a plurality of transistors on a same level as the first transistor, wherein fabricating the plurality of transistors comprises: applying a plurality of dipole layers having a same dipole as the first dipole layer, wherein the plurality of dipole layers have thicknesses that are different from each other, and wherein gate electrodes of the plurality of transistors are fabricated in common processes and comprise the same materials.

[0083] In one embodiment, forming the first dipole layer and the second dipole layer comprises: depositing the first dipole layer on both the first gate dielectric and the second gate dielectric; removing the first dipole layer from the second gate dielectric; and forming the second dipole layer on the second gate dielectric. In one embodiment, the method further comprises: after the first dipole layer has been deposited, forming a sacrificial layer so that it contacts both the first gate dielectric and the second gate dielectric; recessing the sacrificial layer to a level deeper than the second gate dielectric, wherein the first dipole layer is removed from the second gate dielectric after the recessing, and the second dipole layer is deposited after the first dipole layer has been removed from the second gate dielectric; and removing the sacrificial layer.

[0084] According to some embodiments, a structure comprises: a lower transistor having: a first channel region; a first gate dielectric on the first channel region; and a first gate electrode on the first gate dielectric; and an upper transistor, wherein a first transistor in the lower transistor and the upper transistor is an n-type transistor, and wherein a second transistor in the lower transistor and the upper transistor is a p-type transistor, and wherein the upper transistor has: a second channel region overlapping the first channel region; a second gate dielectric on the second channel region; and a second gate electrode on the second gate dielectric, wherein the first gate electrode and the second gate electrode are parts of a same gate electrode.

[0085] In one embodiment, each of the first gate electrode and the second gate electrode includes a work function layer with a p-type work function. In one embodiment, the p-type transistor has an effective p-type work function, and the n-type transistor has an effective n-type work function. In one embodiment, the first gate dielectric and the second gate dielectric include the same dipole dopant, with a first dipole dopant atomic percentage in the n-type transistor being higher than a second dipole dopant atomic percentage in the p-type transistor.

[0086] In one embodiment, the same dipole dopant is selected from the group consisting of La, Sr, Y, Er, Sc, Mg, and combinations thereof. In one embodiment, a ratio of the first dipole dopant atomic percentage to the second dipole dopant atomic percentage is greater than about 3.0. In one embodiment, the upper transistor is the n-type transistor, and the lower transistor is the p-type transistor.

[0087] According to some embodiments, a structure comprises: a lower transistor having: a first channel region; a first gate dielectric on the first channel region; and a first source / drain region connected to the first channel region; and an upper transistor having: a second channel region overlapping the first channel region; a second gate dielectric on the second channel region; and a second source / drain region connected to the second channel region, wherein the second source / drain region overlaps the first source / drain region, and wherein the first source / drain region and the second source / drain region have opposite conductivity types; and a common gate electrode continuously extending from a first level deeper than the first channel region to a second level higher than the second channel region.

[0088] In one embodiment, the common gate electrode comprises: a lower portion acting as a first gate electrode of the lower transistor; and an upper portion acting as a second gate electrode of the upper transistor, wherein no interface is established between the lower portion and the upper portion. In one embodiment, the common gate electrode comprises p-type work function layers surrounding the first gate dielectric and the second gate dielectric, respectively.

Claims

[1] Procedure with the following steps: Forming a first semiconductor channel region (26'L) and a second semiconductor channel region (26'U), wherein the second semiconductor channel region overlaps the first semiconductor channel region; forming a first gate dielectric (78) on the first semiconductor channel region; forming a second gate dielectric (78) on the second semiconductor channel region; Forming a first dipole layer (82-1) and a second dipole layer (82-2) on the first gate dielectric and the second gate dielectric, respectively; Driving dipole dopants in the first dipole layer and the second dipole layer into the first gate dielectric and the second gate dielectric, respectively, whereby the first and second gate dielectrics receive the same dipole dopant; Removing the first dipole layer and the second dipole layer; and Producing a gate electrode (80) on both the first gate dielectric and the second gate dielectric, wherein the gate electrode and the first gate dielectric are included in a first transistor, and the gate electrode and the second gate dielectric are included in a second transistor, wherein work function layers (80WF) in the gate electrode have p-type work functions, and wherein the first transistor is a p-type transistor and the second transistor is an n-type transistor, and wherein the second dipole layer is thicker than the first dipole layer, or wherein the first transistor is an n-type transistor and the second transistor is a p-type transistor, and wherein the second dipole layer is thinner than the first dipole layer. [2] The method of claim 1, further comprising: forming a first source / drain region (62L) adjacent to the first semiconductor channel region; and Forming a second source / drain region (62U) adjacent to the second semiconductor channel region, wherein the second source / drain region overlaps the first source / drain region. [3] The method of claim 2, further comprising: Producing a first contact plug (96L) located over and electrically connected to the second source / drain region; and Producing a second contact plug (96U) located below and electrically connected to the first source / drain region. [4] A method according to any one of the preceding claims, further comprising: Fabricating a plurality of transistors on a same plane as the first transistor, wherein fabricating the plurality of transistors comprises: Applying a plurality of dipole layers (82-1, 82-2) having a same dipole as the first dipole layer, wherein the plurality of dipole layers have thicknesses that are different from each other, and wherein gate electrodes (80L, 80U) of the plurality of transistors are manufactured in common processes and have the same materials. [5] A method according to any one of the preceding claims, wherein the forming of the first dipole layer (82-1) and the second dipole layer (82-2) comprises: depositing the first dipole layer on both the first gate dielectric and the second gate dielectric; Removing the first dipole layer from the second gate dielectric; and Forming the second dipole layer on the second gate dielectric. [6] The method of claim 5, further comprising: after the first dipole layer (82-1) has been deposited, forming a sacrificial layer between the first gate dielectric (78) and the second gate dielectric (78; Recessing the sacrificial layer to a level deeper than the second gate dielectric, wherein the first dipole layer is removed from the second gate dielectric after the recessing, and the second dipole layer is deposited after the first dipole layer has been removed from the second gate dielectric; and Removing the sacrificial layer. [7] Structure with: a lower transistor which has the following: a first channel area (26'L); a first gate dielectric (78) on the first channel region; and a first gate electrode (80) on the first gate dielectric; and an upper transistor, wherein a first transistor of the lower transistor and the upper transistor is an n-type transistor, and wherein a second transistor of the lower transistor and the upper transistor is a p-type transistor, and wherein the upper transistor comprises: a second channel area (26'U) overlapping the first channel area; a second gate dielectric (78) on the second channel region; and a second gate electrode (80) on the second gate dielectric, wherein the first gate electrode and the second gate electrode are parts of a same gate electrode, wherein the first gate dielectric and the second gate dielectric have the same dipole dopant, and wherein a first dipole dopant atomic percentage in the n-type transistor is higher than a second dipole dopant atomic percentage in the p-type transistor. [8] The structure of claim 7, wherein each of the first gate electrode (78) and the second gate electrode (78) comprises a work function layer (80WF) having a p-type work function. [9] The structure of claim 7 or 8, wherein the p-type transistor has an effective p-type work function and the n-type transistor has an effective n-type work function. [10] The structure of any one of claims 7 to 9, wherein the same dipole dopant is selected from the group comprising La, Sr, Y, Er, Sc, Mg and combinations thereof. [11] The structure of any one of claims 7 to 10, wherein a ratio of the first dipole dopant atomic percentage to the second dipole dopant atomic percentage is higher than about 3.

0. [12] The structure of any one of claims 7 to 11, wherein the upper transistor is the n-type transistor and the lower transistor is the p-type transistor. [13] Structure with: a lower transistor which has the following: a first channel area (26'L); a first gate dielectric (78) on the first channel region; and a first source / drain region (62L) connected to the first channel region; and an upper transistor which has the following: a second channel area (26'U) overlapping the first channel area; a second gate dielectric (78) on the second channel region; and a second source / drain region (62U) connected to the second channel region, the second source / drain region overlapping the first source / drain region, and the first source / drain region and the second source / drain region having opposite conductivity types; and a common gate electrode (80) extending continuously from a first level that is deeper than the first channel region to a second level that is higher than the second channel region, wherein a first transistor of the lower transistor and the upper transistor is an n-type transistor, and a second transistor of the lower transistor and the upper transistor is a p-type transistor, the first gate dielectric (78) and the second gate dielectric (78) have the same dipole dopant, and a first dipole dopant atomic percentage in the n-type transistor is higher than a second dipole dopant atomic percentage in the p-type transistor. [14] The structure of claim 13, wherein the common gate electrode comprises: a lower part acting as a first gate electrode (80) of the lower transistor; and an upper part acting as a second gate electrode (80) of the upper transistor, wherein no interface is established between the lower part and the upper part. [15] The structure of claim 13 or 14, wherein the common gate electrode (80) comprises p-type work function layers surrounding the first gate dielectric (78) and the second gate dielectric (78), respectively.

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