Embedded passive devices for integrated circuits and methods for their manufacture

Abstract

Device comprising: a plurality of redistribution lines (124) over a semiconductor substrate (102), wherein the redistribution lines have conductor parts extending along the semiconductor substrate (102); a first passivation layer (132) over the redistribution lines (124), wherein the first passivation layer (132) fills an entirety of a region between the conductor parts of the redistribution lines (124); a passive device (136) over the first passivation layer (132), wherein the passive device (136) comprises: a first metal layer (138) over the first passivation layer (132), wherein the first metal layer (138) is unstructured; an insulating layer (140) over the first metal layer; and a second metal layer (138) over the insulating layer (140); and a dielectric layer (152) over the passive device (136).and a die connecting element (164) extending through the dielectric layer (152), wherein the die connecting element (164) is physically and electrically connected to the passive device (136).

Description

BackgroundThe semiconductor industry has experienced rapid growth due to continual improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, improvements in integration density are due to multiple reductions in smallest feature width, which allows more components to be integrated on a given area. As the demand for downsizing electronic devices has increased, a demand for faster semiconductor dies having more components has arisen.DE 10 2018 130 254 A1 describes a device including an integrated circuit die having an active side and a back side, the back side being opposite the active side, a molding compound encapsulating the integrated circuit die, and a first redistribution structure overlying the integrated circuit die and the molding compound, the first redistribution structure including a first metallization structure and a first dielectric layer, the first metallization structure being electrically coupled to the active side of the integrated circuit die, and at least a portion of the first metallization structure forming an inductor.DE 10 2018 124 689 A1 describes an integrated circuit comprising an induction coil with one or more turns arranged along vertical planes intersecting an underlying substrate. In some embodiments, the integrated circuit includes a plurality of conductive routing layers including conductive wires and conductive vias disposed within one or more dielectric structures abutting the first substrate. The plurality of conductive routing layers define an induction coil having one or more turns each including a vertically extending segment disposed along a plane intersecting the first substrate. The vertically extending segment includes a plurality of the conductive wires and the conductive vias.The invention is defined in the claims.Brief Description of the DrawingsAspects of the present disclosure may best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be appreciated that, in accordance with practice in the industry, various features are not drawn to scale. Rather, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.FIGS. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12-13 are cross-sectional views of intermediates in the manufacture of an integrated circuit die, in accordance with some examples.FIGS. 14A-14D are detailed diagrams of embedded passive devices, in accordance with some examples. FIG. 15 is a cross-sectional view of a die structure, according to some examples. FIG. 16 is a cross-sectional view of a die structure, in accordance with some embodiments.The examples of Figs. 8, 9, 10, 11, 12, 13, 14, 15-16 do not correspond to the claimed invention.Detailed DescriptionThe present disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements will be described below to simplify the present disclosure. For example, in the description below, the formation of a first element over or on a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements are not in direct contact. Moreover, in the present disclosure, reference numerals and / or letters may be repeated in the various examples. This repetition is for convenience and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Moreover, spatially relative terms such as "lower", "lower", "lower(r)" / "lower", "higher", "upper(r)" / "upper" and the like may be used herein to easily describe the relationship of an element or structural element to one or more other elements or structural elements illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90° or in another orientation) and the spatially relative descriptors used herein interpreted accordingly.According to various embodiments, a passivation layer is formed over redistribution lines of an integrated circuit die. The passivation layer may be formed to be thick and planar. For example, the passivation layer may be formed to first cover the redistribution lines and may then be planarized, still extending over and between the redistribution lines after planarization. A total of all individual respective regions between respective redistribution lines may be filled with the passivation layer. This can create much space for the fabrication of embedded passive devices during later processing. In this way, more passive devices may be embedded in an integrated circuit die, enabling a higher degree of device integration.FIGS. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12-13 are cross-sectional views of intermediates in the manufacture of an integrated circuit die 100 (see FIG. 13 ) in accordance with some embodiments. The integrated circuit die 100 may be a logic device [e.g., a central processing unit (CPU), a graphics processing unit (GPU), a microcontroller, etc.], a memory device [e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.], a power management device [e.g., a power management integrated circuit (PMIC) die], a radio frequency (RF) device, a sensor device, a microelectromechanical system (MEMS) device; a signal processing device [e.g., a DSP (Digital Signal Processing) die] ; a front-end device [e.g., an analog front-end die (AFE die)], or the like; or a combination thereof [e.g., a SoC (SoC) die]. The integrated circuit die 100 may be fabricated in a wafer that may have different device regions that are singulated in later steps to produce a plurality of integrated circuit dies.In FIG. 1, a semiconductor substrate 102 is manufactured or provided. The semiconductor substrate 102 may be a silicon substrate that is doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 102 may include: other semiconductor materials such as germanium; a compound semiconductor such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, Aluminiumgalliumarsenid gallium indium arsenide, gallium indium phosphide, and / or Galliumindiumarsenidphosphid; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The semiconductor substrate 102 has an active side (e.g., the side facing upward in FIG. 1 ) that is occasionally referred to as a front side, and an inactive side (e.g., the side facing downward in FIG. 1 ) that is occasionally referred to as a back side. Devices are fabricated on the active side of the semiconductor substrate 102. The devices may be active devices (e.g., transistors, diodes, etc.) or passive devices (e.g., capacitors, inductors, resistors, etc.). The inactive side may not have devices. The devices may be manufactured in a suitable FEOL (Front End of Line) process.An interconnect structure 104 is formed over the active side of the semiconductor substrate 102. The interconnect structure 104 interconnects the devices of the semiconductor substrate 102 to an integrated circuit. The interconnect structure 104 may be fabricated in a suitable Back End of Line (BEOL) process. The interconnect structure 104 may include one or more dielectric layers and respective metallization structures in the dielectric layers. Suitable dielectric materials for the dielectric layers are oxides such as silicon oxide, aluminum oxide, or the like; nitrides such as silicon nitride, silicon oxynitride, combinations thereof, or the like; or the like. The dielectric layers may be made of a low-k (LK) dielectric material such as carbon doped silicon oxide; an extreme low-k (ELK) material such as porous carbon doped silicon oxide; or the like. Other suitable dielectric materials may also be used. The metallization structures may include conductive vias and / or conductive lines for interconnecting the devices of the semiconductor substrate 102. The metallization structures may be made of a conductive material, such as a metal such as copper, cobalt, aluminum, gold, combinations thereof, or the like. The metallization structures may be formed using a damascene process, such as a single damascene process, a dual damascene process, or the like.Contact pads 106 are formed on the front side of the integrated circuit die 100. The contact pads 106 may be pads, conductive pillars, or the like, with which external terminals are formed. The contact pads 106 may be disposed in and / or on the interconnect structure 104. They may be part of an upper metallization structure of the interconnect structure 104, for example. The contact pads 106 may be made of a metal such as copper, aluminum, a copper alloy, combinations thereof, or the like, which may be deposited by plating or the like, for example.A dielectric layer 108 is disposed on the front side of the integrated circuit die 100. The dielectric layer 108 may be disposed in and / or on the interconnect structure 104. The dielectric layer 108 may be, for example, an upper dielectric layer of the interconnect structure 104. The dielectric layer 108 laterally encloses the contact pads 106. The dielectric layer 108 may be an oxide, a nitride, a polymer, or the like, or a combination thereof. The dielectric layer 108 may be formed by, for example, spin coating, lamination, chemical vapor deposition (CVD), or the like.In some embodiments (not individually shown), the integrated circuit die 100 is a stacking device that includes a plurality of semiconductor substrates 102. The integrated circuit die 100 may be, for example, a memory device including multiple memory dies, such as an HMC (hybrid memory cube) module, an HBM (high bandwidth memory) module, or the like. In these embodiments, integrated circuit die 100 includes a plurality of semiconductor substrates 102 interconnected by substrate vias (TSVs) such as through silicon vias. The semiconductor substrates 102 may (or may not) each include an interconnect structure 104.In FIG. 2, a passivation layer 114 is formed over the interconnect structure 104 (e.g., over the dielectric layer 108 and the contact pads 106). The passivation layer 114 may be made of one or more suitable dielectric materials, such as silicon nitride, silicon oxide, combinations thereof, or the like. Other suitable dielectric materials are polymers such as polyimide, solder resist, polybenzoxazole (PBO), a BCB-based polymer (BCB: benzocyclobutene), molding compound, or the like. The passivation layer 114 may be formed by deposition (e.g., CVD), spin coating, lamination, combinations thereof, or the like. The passivation layer 114 may be formed with a large thickness, such as a thickness of 200 nm to 1 μm (2 kÅ to 10 kÅ). Additionally, the passivation layer 114 may be planarized by, for example, chemical mechanical planarization (CMP).An etch stop layer 112 is formed between the passivation layer 114 and the interconnect structure 104. The etch stop layer 112 may be formed of a dielectric material having a high etch selectivity with respect to the etch of the passivation layer 114, such as silicon nitride, silicon oxynitride, or the like, which may be deposited by a suitable deposition method such as CVD, atomic layer deposition (ALD), or the like.In FIG. 3, passive devices 116 are optionally fabricated on the passivation layer 114. The passive devices 116 may be capacitors, resistors, and the like. The passive devices 116 are embedded passive devices and may be electrically connected to the devices of the semiconductor substrate 102. Details of the structure and fabrication of passive devices will be described later with reference to Figs. 8 and 9A to 9D.In FIG. 4, a passivation layer 118 is formed over the passive devices 116 (if present) and the passivation layer 114. The passivation layer 118 may be made of one or more suitable dielectric materials, such as silicon nitride, silicon oxide, combinations thereof, or the like. Other suitable dielectric materials are polymers such as polyimide, solder resist, PBO, a BCB-based polymer, molding compound, or the like. The passivation layer 118 may be formed by deposition (e.g., CVD), spin coating, lamination, combinations thereof, or the like. The passivation layer 118 may be formed with a large thickness, such as a thickness of 200 nm to 1 μm (2 kÅ to 10 kÅ). Additionally, the passivation layer 118 may be planarized by, for example, CMP.In FIG. 5, openings 122 are patterned through the passivation layer 118, the passivation layer 114, and the etch stop layer 112, thereby exposing the contact pads 106. The openings 122 may be formed using suitable photolithography and etching techniques. For example, the openings 122 may be formed through the various layers with one or more etch processes having a suitable etch selectivity. When the passive devices 116 are manufactured, the openings 122 may be patterned around the passive devices 116 such that the openings 122 are between adjacent passive devices 116.In Figure 6, redistribution lines 124 are formed. Redistribution lines 124 include line portions 124T disposed on and extending along a top surface of passivation layer 118. For example, the line portions 124T are conductive lines that extend longitudinally parallel to a main surface of the semiconductor substrate 102. Thus, redistribution lines 124 extend along semiconductor substrate 102 in respective longitudinal directions. A line part 124T of a redistribution line 124 has a length (in its longitudinal direction) and a width (in a direction perpendicular to the longitudinal direction), the length being larger than the width. Redistribution lines 124 may also include one or more via portions 124V in respective ones of openings 122 (through passivation layer 118, passivation layer 114, and etch stop layer 112) that are physically and electrically connected to contact pads 106. Redistribution lines 124 may physically contact the contact pads. Some of the via portions 124V may be used to electrically connect the passive devices 116 to the devices of the semiconductor substrate 102.As an example of forming redistribution lines 124, a seed layer 126 may be formed on top of passivation layer 118 and in openings 122 (e.g., on the exposed portions of contact pads 106). In some embodiments, the seed layer 126 is a metal layer, which may be a single layer or a composite layer having a plurality of sub-layers made of different materials. In some embodiments, the seed layer 126 includes a titanium layer and a copper layer over the titanium layer. The seed layer 126 may be formed by, for example, physical vapor deposition (PVD) or the like. Optionally, a liner (not individually shown), such as a diffusion barrier layer, an adhesion layer, or the like, may be formed in the openings 122 before forming the seed layer 126. The coating may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. A photoresist (not individually shown) is then formed on the seed layer 126, which is subsequently patterned. The photoresist may be formed by spin coating or the like and may be exposed for patterning. The pattern of the photoresist corresponds to redistribution lines 124. The patterning creates openings through the photoresist to expose the seed layer 126. A conductive material 128 is then deposited in the openings of the photoresist and on the exposed portions of the seed layer 126. The conductive material 128 may be deposited by plating, such as electroplating or electroless plating, or the like. The conductive material 128 may be a metal such as copper, silver, cobalt, titanium, tungsten, aluminum, a combination thereof, or the like. The conductive material 128 may be, for example, copper, a copper-silver alloy, or a copper-cobalt alloy plated using the seed layer 126. Then, the photoresist and the portions of the seed layer 126 on which the conductive material has not been deposited are removed. The photoresist may be removed by a suitable stripping method, for example, using an oxygen plasma or the like. After the photoresist is removed, the exposed portions of the seed layer 126 are removed with a suitable etching process, for example. Optionally, a tempering process may be performed. The remaining portions of the seed layer 126 and the conductive material 128 form the redistribution lines 124.Redistribution lines 124 may have any type of top side depending on the field of application of the integrated circuit die to be fabricated. In the illustrated embodiment, redistribution lines 124 have convex tops. In another embodiment, redistribution lines 124 may have concave tops, polygonal tops, or the like. In addition, the conductive portions 124T may have any type of sidewalls depending on the application area of the integrated circuit die to be manufactured. In the illustrated embodiment, the conductive portions 124T have side walls spaced apart by a tapered width decreasing in a direction away from the semiconductor substrate 102. In another embodiment, the conduit portions 124T have substantially vertical side walls spaced by a constant width.In FIG. 7, a passivation layer 132 is formed on redistribution lines 124 and passivation layer 118. The passivation layer 132 may be made of one or more suitable dielectric materials, such as silicon nitride, silicon oxide, combinations thereof, or the like. Other suitable dielectric materials are polymers such as polyimide, solder resist, PBO, a BCB-based polymer, molding compound, or the like. The passivation layer 132 may be formed by deposition (e.g., CVD), spin coating, lamination, combinations thereof, or the like.The passivation layer 132 may be formed with a large initial thickness, such as a thickness of 150 nm to 10 μm (1.5 kÅ to 100 kÅ). The initial thickness of the passivation layer 132 is so large that the passivation layer 132 covers the line portions 124T of the redistribution lines 124. Redistribution lines 124 may have a large height, such as a height of 150 nm to 10 μm (1.5 kÅ to 100 kÅ), which may result in the top surface of passivation layer 132 first having a low level of planarity. To compensate for this, the passivation layer 132 may be planarized after deposition, for example by a CMP. Through the planarization, the top surface of the passivation layer 132 may have a high degree of planarity, such as a planarity of 0 to 5 μm (0 kÅ to 50 kÅ). The top surface of the passivation layer 132 may have a higher degree of planarity than the top surface of the passivation layer 118. The thickness of the passivation layer 132 may be reduced during planarization. However, the initial thickness of the passivation layer 132 is so large that despite the reduction in its thickness, the passivation layer 132 still covers the redistribution lines 124. In some embodiments, after planarization, the portions of passivation layer 132 remaining over redistribution lines 124 have a thickness of 200 nm to 1 μm (2 kÅ to 10 kÅ). Thus, the passivation layer 132 (over and between redistribution lines 124) may be thick and planar, which may provide a lot of space for passive device fabrication at the later processing. The planar top surface of the passivation layer 132 extends continuously over the redistribution lines 124 and the regions between the redistribution lines 124. The entirety of the individual respective regions between the line portions 124T may be filled with the passivation layer 132. Redistribution lines 124 are spaced from passive devices to be subsequently fabricated by the portions of passivation layer 132 over redistribution lines 124.An etch stop layer 134 is formed on the passivation layer 132. The etch stop layer 134 is disposed between the passivation layer 132 and a higher level passivation layer to be subsequently formed. The etch stop layer 134 may be formed of a dielectric material having a high etch selectivity with respect to the etch of the higher level passivation layer, such as silicon nitride, silicon oxynitride, or the like, which may be deposited using a suitable deposition method such as CVD, ALD, or the like.In FIG. 8, passive devices 136 are optionally formed on the etch stop layer 134. The passive devices 136 may physically contact a top surface of the etch stop layer 134. The passive devices 136 may be capacitors, inductors, resistors, and the like. The passive devices 136 are embedded passive devices and may be electrically connected to the devices of the semiconductor substrate 102. As will be discussed in more detail below, a passive device 136 may include one or more metal layers and one or more insulating layers. FIGS. 9A through 9D are detailed representations of example passive devices 136 that may be fabricated. The integrated circuit die 100 may include a desired combination and number of the illustrated passive devices 136.The passive devices 136 are plate capacitors in some embodiments, as shown in FIG. 9A. The plate capacitors have a metal-insulator-metal (MIM) structure with a three-dimensional wavy stack of metal layers 138 separated by insulating layers 140. The metal layers 138 may be horizontal metal plates, wherein a plate capacitor includes at least two metal plates and a portion of an insulating layer 140 between the metal plates. For example, a plate capacitor may include a lower metal plate, an insulating layer on the lower metal plate, and an upper metal plate on the insulating layer. A plate capacitor may be a two-plate capacitor having two metal plates or a multi-plate capacitor having more than two metal plates.As an example of fabricating the plate capacitors, a patterned metal layer 138 may be fabricated. The metal layer 138 may be made of copper, cobalt, aluminum, gold, combinations thereof, or the like, for example, by plating or the like. The metal layer 138 may be patterned after its formation (e.g., using suitable photolithography and etching techniques) or may be selectively formed using a desired pattern (e.g., using suitable masking and plating techniques). The structure of the metal layer 138 defines metal plates. An insulating layer 140 may then be formed on the patterned metal layer 138 and in openings through the patterned metal layer 138. The insulating layer 140 may be formed of a dielectric material, such as silicon oxide, silicon oxynitride, silicon oxycarbide, or the like, which may be deposited by a suitable deposition method, such as CVD, ALD, or the like. Subsequently, a further patterned metal layer 138 may be formed on the insulating layer 140. In particular, a desired number of patterned metal layers 138 and insulating layers 140 may be formed by repeating the process described above.The passive devices 136 are deep trench capacitors in some embodiments, as shown in FIG. 9B. The deep trench capacitors may include a three-dimensional wavy stack of metal layers 138 separated by insulating layers 140. The metal layers 138 may be metal vias, where a deep trench capacitor includes at least two metal vias (one disposed in the other) and a portion of an insulating layer 140 between the vias. For example, a deep trench capacitor may include an outer metal via, an insulating layer on the outer metal via, and an inner metal via on the insulating layer. The metal vias may extend under the tops of redistribution lines 124. A deep trench capacitor may be a single trench capacitor including the metal vias in a single recess 142, or a multi-trench capacitor including the metal vias in multiple recesses 142.As an example of fabricating the deep trench capacitors, recesses 142 may be patterned through the etch stop layer 134 and the passivation layer 132, for example, using suitable photolithography and etching techniques. The recesses 142 may extend into but not through the passivation layer 132 and may extend under the tops of the redistribution lines 124. After the recesses 142 have been patterned, a patterned metal layer 138 may be formed therein. The metal layer 138 may be made of copper, cobalt, aluminum, gold, combinations thereof, or the like, for example, by plating or the like. The metal layer 138 may be patterned after its formation (e.g., using suitable photolithography and etching techniques) or may be selectively formed using a desired pattern (e.g., using suitable masking and plating techniques). The structure of the metal layer 138 defines metal vias. An insulating layer 140 may then be formed on the patterned metal layer 138, in openings therethrough, and in the recesses 142. The insulating layer 140 may be formed of a dielectric material, such as silicon oxide, silicon oxynitride, silicon oxycarbide, or the like, which may be deposited by a suitable deposition method, such as CVD, ALD, or the like. Subsequently, a further patterned metal layer 138 may be formed on the insulating layer 140. In particular, a desired number of patterned metal layers 138 and insulating layers 140 may be formed by repeating the process described above.The passive devices 136 are resistors in some embodiments, as shown in FIG. 9C. The resistors may comprise a three-dimensional planar stack of metal layers 138 separated by insulating layers 140. In particular, the metal layers 138 may include a bottom metal layer 138 and a patterned top metal layer 138. The patterned top metal layer 138 may include metal lines that function as resistive elements. A resistor may include, for example, a metal plane, an insulating layer on the metal plane, and a metal line on the insulating layer.As an example of making the resistors, a lower metal layer 138 may be made in the recesses 142. The lower metal layer 138 may be made of copper, cobalt, aluminum, gold, combinations thereof, or the like, for example, by plating or the like. The lower metal layer 138 may be a metal plane that is not patterned. An insulating layer 140 may then be formed on the lower metal layer 138. The insulating layer 140 may be formed of a dielectric material, such as silicon oxide, silicon oxynitride, silicon oxycarbide, or the like, which may be deposited by a suitable deposition method, such as CVD, ALD, or the like. The upper metal layer 138 may be made of copper, cobalt, aluminum, gold, combinations thereof, or the like, for example, by plating or the like. After being formed, the upper metal layer 138 may be patterned (e.g., using suitable photolithography and etching techniques) or may be selectively formed using a desired pattern (e.g., using suitable masking and plating techniques). The structure of the metal layer 138 defines metal lines that function as resistive elements. Each metal line has a width and a length selected based on the desired resistivity of the resistor.The passive devices 136 are inductors in some embodiments, as shown in FIG. 9D. The inductors may include a patterned metal layer 138 and an insulating layer 140 overlying it. The patterned metal layer 138 may include metal coils that function as inductive elements. An inductor may include, for example, a metal coil and an insulating layer on the metal coil. Each metal coil is wound based on the desired inductance of the inductor. A metal coil is a loop or coil that extends from a first end and terminates at a second end. The metal coils may have a desired shape in a top-down view. FIGS. 10A to 10D are top-down views of metal coils. A metal coil may be a square coil (as shown in FIG. 10A ), a hexagonal coil (as shown in FIG. 10B ), an octagonal coil (as shown in FIG. 10C ), a circular coil (as shown in FIG. 10D ), or the like.As an example of forming the inductors, a patterned metal layer 138 may be formed. The metal layer 138 may be made of copper, cobalt, aluminum, gold, combinations thereof, or the like, for example, by plating or the like. The metal layer 138 may be patterned after its formation (e.g., using suitable photolithography and etching techniques) or may be selectively formed using a desired pattern (e.g., using suitable masking and plating techniques). The structure of the metal layer 138 defines metal coils that function as inductive elements. An insulating layer 140 may then be formed on the patterned metal layer 138 and in openings through the patterned metal layer 138. The insulating layer 140 may be formed of a dielectric material, such as silicon oxide, silicon oxynitride, silicon oxycarbide, or the like, which may be deposited by a suitable deposition method, such as CVD, ALD, or the like.Further elements may be formed on the etch stop layer 134. For example, dummy metal layers may be formed in addition to the passive devices 136. A dummy metal layer may have a similar structure as the passive devices 136 (e.g., comprising one or more metal layers), and may be fabricated in the same process as the passive devices 136. The dummy metal layers may be formed if desired to adjust the flex of the integrated circuit die 100.In FIG. 11, a dielectric layer 152 is formed on the passive devices 136 and the etch stop layer 134. The dielectric layer 152 may be made of an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), a TEOS-based oxide (TEOS: tetraethylorthosilicate), or the like; a nitride such as silicon nitride or the like; or a combination thereof; or the like. The dielectric layer 152 may be formed by, for example, CVD, ALD, or the like. The dielectric layer 152 may be made of, for example, silicon oxide deposited using TEOS. The dielectric material of the dielectric layer 152 may be different from the dielectric material of the passivation layer 132. For example, the dielectric layer 152 may be made of silicon oxide, while the passivation layer 132 may be made of silicon nitride. Similar to the passivation layer 132, the dielectric layer 152 may be made thick and planar, which may provide a lot of space for the manufacture of passive devices in a later processing.An etch stop layer 154 may be formed on the dielectric layer 152. The etch stop layer 154 is disposed between the dielectric layer 152 and a higher level dielectric layer to be subsequently formed. The etch stop layer 154 may be formed of a dielectric material having a high etch selectivity with respect to the etch of the higher level passivation layer, such as silicon nitride, silicon oxynitride, or the like, which may be deposited using a suitable deposition method such as CVD, ALD, or the like.Passive devices 156 are optionally formed on the etch stop layer 154. The passive devices 156 may be capacitors, inductors, resistors, and the like. The passive devices 156 are embedded passive devices and may be electrically connected to the devices of the semiconductor substrate 102. The passive devices 156 may be some of the passive devices described above with reference to FIGS. 9A-9D. The integrated circuit die 100 may include a desired combination and number of the passive devices 156. As discussed in greater detail above, a passive device 156 may include one or more metal layers and insulating layers.A dielectric layer 158 may be formed on the passive devices 156 and the etch stop layer 154. The dielectric layer 158 may be made of an oxide such as silicon oxide, PSG, BSG, BPSG, a TEOS-based oxide, or the like; a nitride such as silicon nitride, or the like; a combination thereof; or the like. The dielectric layer 158 may be formed by, for example, CVD, ALD, or the like. The dielectric layer 158 may be made of, for example, silicon oxide deposited using TEOS.In FIG. 12, die interconnect openings (including via openings 160 and bond pad openings 162) are patterned in the dielectric layer 158, the etch stop layer 154, the dielectric layer 152, the etch stop layer 134, and the passivation layer 132, thereby exposing the redistribution lines 124. The die interconnect openings may be formed using suitable photolithography and etching techniques. When the passive devices 156 are fabricated, the bond pad openings 162 may be patterned therearound such that the bond pad openings 162 are disposed between adjacent passive devices 156. Similarly, via openings 160 may be patterned around passive devices 136, such that via openings 160 are disposed between adjacent passive devices 136.The die interconnect openings may be created using a damascene process. In this embodiment, the die interconnect openings are created using a single damascene process. In the single damascene process, bond pad openings 162 are formed through dielectric layer 159 and etch stop layer 154, while via openings 160 are formed through dielectric layer 152, etch stop layer 134, and passivation layer 132. Via openings 160 expose redistribution lines 124. In another embodiment, the etch stop layer 154 and the dielectric layer 158 are omitted, and the die interconnect openings are formed using a dual damascene process. In the dual damascene process, bond pad openings 162 are formed through an upper portion of dielectric layer 152, while via openings 160 are formed through a lower portion of dielectric layer 152, etch stop layer 134, and passivation layer 132.In FIG. 13, die connectors 164 (including vias 166 and bond pads 168) are fabricated in the die connector openings (including via openings 160 and bond pad openings 162, respectively). The die connectors 164 may be formed from a suitable conductive material such as copper, tungsten, aluminum, silver, gold, a combination thereof, or the like, for example, by plating or the like. Subsequently, the excess portions of the conductive material over the top surface of the dielectric layer 158 are removed. In some embodiments, a planarization process such as a CMP, an etch back process, a combination thereof, or the like may be used. After the planarization process, the tops of the die connectors 164 may be coplanar (within process variations) with the top of the dielectric layer 158. The die connectors 164 are physically and electrically connected to the redistribution lines 124. The die connectors 164 may physically contact the line portions 124T of the redistribution lines 124. Some of the die connectors 164 (e.g., vias 166) may be used to electrically connect the passive devices 136, 156 to the devices of the semiconductor substrate 102.The bond pads 168 of the die connectors 164 are disposed in the dielectric layer 158, while the vias 166 of the die connectors 164 are disposed in the dielectric layer 152 and the passivation layer 132. Vias 166 extend through the portions of passivation layer 132 that are over redistribution lines 124.FIGS. 14A-14D are detailed representations of embedded passive devices, in accordance with some embodiments. The passive devices may be the passive devices 136 or the passive devices 156 (described above). A passive device may be a plate capacitor (as shown in FIG. 14A ), a deep trench capacitor (as shown in FIG. 14B ), a resistor (as shown in FIG. 14C ), or an inductor (as shown in FIG. 14D ). The passive devices may be disposed around and / or connected to the die connectors 164. The die connectors 164 may be physically and electrically connected to input / output terminals of the passive devices as well as to the lower redistribution lines 124 (see FIG. 13 ).FIG. 15 is a cross-sectional view of a die structure 200 in accordance with some embodiments. The die structure 200 is a stack of integrated circuit dies 100 (including a first integrated circuit die 100A and a second integrated circuit die 100B). The die structure 200 is formed by bonding the integrated circuit dies 100 together. Some of the passive devices 136, 156 of the first integrated circuit die 100A may be bonded to some of the passive devices 136, 156 of the second integrated circuit die 100B.As an example of the bonding process, the second integrated circuit die 100B may be bonded to the first integrated circuit die 100A by hybrid bonding. The dielectric layer 158 of the second integrated circuit die 100B is directly bonded to the dielectric layer 158 of the first integrated circuit die 100A by dielectric-dielectric bonding without using an adhesive material (e.g., a die attach layer). The die connectors 164 of the second integrated circuit die 100B are directly bonded to the die connectors 164 of the first integrated circuit die 100A by metal-to-metal bonding without using a eutectic material (e.g., solder). The bonding may include pre-bonding and a anneal process. During the pre-bonding, a small pressing force is applied to press the second integrated circuit die 100B against the first integrated circuit die 100A. The pre-bonding is performed at a low temperature, e.g., about room temperature, and after the pre-bonding, the dielectric layer 158 of the second integrated circuit die 100B is bonded to the dielectric layer 158 of the first integrated circuit die 100A. Then, the bond strength is improved in a subsequent anneal step in which the dielectric layer 158 of the first integrated circuit die 100A, the die connectors 164 of the first integrated circuit die 100A, the dielectric layer 158 of the second integrated circuit die 100B, and the die connectors 164 of the second integrated circuit die 100B are annealed. After the anneal, direct bonds, such as fuse bonds, are formed that bond the dielectric layer 158 of the first integrated circuit die 100A to the dielectric layer 158 of the second integrated circuit die 100B. The bonding sites may be, for example, covalent bonds between the material of the dielectric layer 158 of the first integrated circuit die 100A and the material of the dielectric layer 158 of the second integrated circuit die 100B. The die connectors 164 of the first integrated circuit die 100A may be connected in one-to-one correspondence with the die connectors 164 of the second integrated circuit die 100B. The die connectors 164 of the first integrated circuit die 100A and the die connectors 164 of the second integrated circuit die 100B may be in physical contact after pre-bonding, or may expand to come into physical contact during the anneal. Additionally, during the anneal, the material of the die connectors 164 of the first integrated circuit die 100A mixes with the material of the die connectors 164 of the second integrated circuit die 100B (e.g., copper) to also form metal-to-metal bonds. Thus, the resulting bonds are dielectric-dielectric bonds and metal-metal bonds.FIG. 16 is a cross-sectional view of a die structure 200 in accordance with some embodiments. This embodiment is similar to the embodiment of FIG. 15 except that an anti-reflective layer 172 is formed between the dielectric layer 158 of the first integrated circuit die 100A and the dielectric layer 158 of the second integrated circuit die 100B. The antireflection film 172 may be made of a nitride such as silicon nitride, a metal oxide such as titanium oxide, or the like.Embodiments may achieve advantages. As discussed above, the passivation layer 132 may be thick and planar, such that much space may be provided for the fabrication of passive devices 136 during later processing. In this way, more passive devices may be embedded in an integrated circuit die 100, enabling a higher degree of device integration. This may require fewer passive devices to be externally attached to an integrated circuit die 100.In an embodiment, a device includes: a plurality of redistribution lines over a semiconductor substrate, the redistribution lines including line portions extending along the semiconductor substrate; a first passivation layer over the redistribution lines, the first passivation layer filling an entirety of an area between the line portions of the redistribution lines; a passive device over the first passivation layer; a dielectric layer over the passive device; and a die interconnect extending through the dielectric layer, the die interconnect being physically and electrically connected to the passive device. In some embodiments of the device, the first passivation layer has a planar top surface extending continuously over the redistribution lines and the region between the redistribution lines. In some embodiments, the device further includes a second passivation layer between the first passivation layer and the semiconductor substrate, wherein the planar top surface of the first passivation layer has a higher degree of planarity than a top surface of the second passivation layer. In some embodiments of the device, the passive device is a plate capacitor, wherein the plate capacitor includes a lower metal plate, an insulating layer on the lower metal plate, and an upper metal plate on the insulating layer. In some embodiments of the device, the passive device is a deep trench capacitor, the deep trench capacitor including an outer metal via, an insulating layer on the outer metal via, and an inner metal via on the insulating layer. In some embodiments of the device, the passive device is a resistor, the resistor including an insulating layer and a metal line on the insulating layer. In some embodiments of the device, the passive device is an inductor, the inductor including a metal coil and an insulating layer on the metal coil.In one embodiment, an apparatus includes: a redistribution line over a semiconductor substrate, the redistribution line extending along the semiconductor substrate; a passivation layer over the redistribution line; a deep trench capacitor having an outer metal via extending into the passivation layer, the outer metal via extending below a top surface of the redistribution line, an inner metal via over the outer metal via, and an insulating layer between the inner and outer metal vias; a first dielectric layer over the deep trench capacitor; and a die interconnect extending through the first dielectric layer, the die interconnect being physically and electrically connected to the deep trench capacitor. In some embodiments of the device, a dielectric material of the first dielectric layer is different from a dielectric material of the passivation layer. In some embodiments, the device further includes: a passive device over the first dielectric layer; and a second dielectric layer over the passive device. In some embodiments of the device, the die interconnect includes: a bond pad in the second dielectric layer; and a via in the first dielectric layer and in a portion of the passivation layer over the redistribution line. In some embodiments of the device, the portion of the passivation layer over the redistribution line has a thickness of 200 nm to 1 μm (2 kÅ to 10 kÅ). In some embodiments of the device, the deep trench capacitor is a single trench capacitor. In some embodiments of the device, the deep trench capacitor is a multi-trench capacitor.In an embodiment, a method includes: depositing a passivation layer over a redistribution line, the redistribution line extending along a semiconductor substrate; planarizing the passivation layer, wherein after the planarizing, a portion of the passivation layer remains over the redistribution line; forming a passive device over the passivation layer; depositing a dielectric layer over the passive device and the passivation layer; and forming a die interconnect through the dielectric layer and the portion of the passivation layer, wherein the die interconnect is physically and electrically connected to the passive device and the redistribution line. In some embodiments of the method, the portion of the passivation layer remaining over the redistribution line has a thickness of 200 nm to 1 μm (2 kÅ to 10 kÅ). In some embodiments of the method, forming the passive device comprises: forming a first metal layer over the passivation layer, wherein a first structure of the first metal layer defines a first metal plate; depositing an insulating layer over the first metal layer; and forming a second metal layer over the insulating layer, wherein a second structure of the second metal layer defines a second metal plate. In some embodiments of the method, forming the passive device comprises: forming a recess in the passivation layer; forming a first metal layer in the recess, wherein a first structure of the first metal layer defines a first metal via; depositing an insulating layer over the first metal layer; and forming a second metal layer over the insulating layer, wherein a second structure of the second metal layer defines a second metal via. In some embodiments of the method, forming the passive device comprises: forming a first metal layer over the passivation layer, wherein the first metal layer is not patterned; depositing an insulating layer over the first metal layer; and forming a second metal layer over the insulating layer, wherein a pattern of the second metal layer defines a metal line. In some embodiments of the method, forming the passive device comprises: forming a metal layer over the passivation layer, wherein a structure of the metal layer defines a metal coil; and depositing an insulating layer over the metal layer.

Claims

An apparatus comprising: a plurality of redistribution lines (124) over a semiconductor substrate (102), the redistribution lines having line portions extending along the semiconductor substrate (102); a first passivation layer (132) over the redistribution lines (124), the first passivation layer (132) filling an entirety of an area between the line portions of the redistribution lines (124); a passive device (136) over the first passivation layer (132), the passive device (136) comprising: a first metal layer (138) over the first passivation layer (132), the first metal layer (138) being non-patterned; an insulating layer (140) over the first metal layer; and a second metal layer (138) over the insulating layer (140); a dielectric layer (152) over the passive device (136); and a die interconnect (164) extending through the dielectric layer (152), the die interconnect (164) being physically and electrically connected to the passive device (136).The device of claim 1, wherein the first passivation layer (132) has a planar top surface extending continuously over the redistribution lines (124) and the region between the redistribution lines (124).The device of claim 1 or 2, further comprising a second passivation layer (114, 118) between the first passivation layer (132) and the semiconductor substrate (102), wherein the planar top surface of the first passivation layer (132) has a higher degree of planarity than a top surface of the second passivation layer (114, 118).The apparatus of any preceding claim, wherein the passive device (136) is a plate capacitor, the plate capacitor comprising a lower metal plate, an insulating layer (140) on the lower metal plate, and an upper metal plate on the insulating layer (140).The device of any of claims 1 to 3, wherein the passive device (136) is a resistor, the resistor comprising an insulating layer (140) and a metal line on the insulating layer (140).An apparatus comprising: a redistribution line (124) over a semiconductor substrate (102), the redistribution line (124) extending along the semiconductor substrate (102); a passivation layer (132) over the redistribution line (124); a deep trench capacitor comprising: an outer metal via (138) extending into the passivation layer (132), the outer metal via (138) extending below a top surface of the redistribution line (124), an inner metal via (138) over the outer metal via (138), and an insulating layer (140) between the inner and outer metal vias (138); a first dielectric layer (152) over the deep trench capacitor; and a die interconnect (164) extending through the first dielectric layer (152), the die interconnect (164) being physically and electrically connected to the deep trench capacitor.The apparatus of claim 6, wherein a dielectric material of the first dielectric layer (152) is different from a dielectric material of the passivation layer (132).The device of claim 6 or 7, further comprising: a passive device (136) over the first dielectric layer (152); and a second dielectric layer (158) over the passive device (136).The device of any of claims 6 to 8, wherein the die interconnect element comprises: a bond pad (168) in the second dielectric layer (158); and a via (166) in the first dielectric layer (152) and in a portion of the passivation layer (132) over the redistribution line (124).The device of claim 9, wherein the portion of the passivation layer (132) over the redistribution line (124) has a thickness of 200 nm to 1 μm.The apparatus of any of claims 6 to 10, wherein the deep trench capacitor is a single trench capacitor.The apparatus of any of claims 6 to 10, wherein the deep trench capacitor is a multi-trench capacitor.A method comprising: depositing a passivation layer (132) over a redistribution line (124), the redistribution line (124) extending along a semiconductor substrate (102); planarizing the passivation layer (132), wherein after the planarizing, a portion of the passivation layer (132) remains over the redistribution line (124); forming a passive device (136) over the passivation layer (132), wherein forming the passive device (136) comprises: forming a first metal layer over the passivation layer (132), wherein the first metal layer (138) is not patterned; depositing an insulating layer (140) over the first metal layer; and forming a second metal layer over the insulating layer (140); depositing a dielectric layer (152) over the passive device (136) and the passivation layer (132); and forming a die interconnect (164) through the dielectric layer (152) and the portion of the passivation layer (132), wherein the die interconnect (164) is physically and electrically connected to the passive device (136) and the redistribution line (124).The method of claim 13, wherein the portion of the passivation layer (132) remaining over the redistribution line (124) has a thickness of 200 nm to 1 μm.The method of claim 13 or 14, wherein forming the passive device comprises: creating a recess (142) in the passivation layer (132); forming the first metal layer in the recess (142), wherein the first metal layer (138) defines a first metal via, and wherein the second metal layer (138) defines a second metal via.The method of claim 13 or 14, wherein a structure of the second metal layer defines a metal line.

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