Method for manufacturing a semiconductor device, film thickness measuring method, temperature measuring method and temperature measuring substrate

Abstract

A method of manufacturing a semiconductor device, the method comprising: Producing a substrate (200), wherein the substrate (200) includes: a plurality of light-shielding layers (210) arranged at predetermined intervals to shield light having a predetermined wavelength; a workpiece film (110) disposed on the plurality of light-shielding layers (210) and including a plurality of first insulating layers (NL) and a plurality of second insulating layers (OL) alternately stacked one upon another; and a mask structure (120p) located on the workpiece film (110) and having a plurality of openings; and Etching the workpiece film (110) exposed by the plurality of openings, wherein etching the workpiece film (110) includes: irradiating a back side of the substrate (200) with the light during etching of the workpiece film (110); observing interference light (239sb) generated by interference between first reflected light (238s) reflected by the backside of the substrate (200) and second reflected light (238b) transmitted through the substrate (200) and reflected by undersides of the plurality of light-shielding layers (238b); Calculating a temperature of the substrate (200) during the etching process based on the interference light (239sb); and Regulating the temperature of the substrate (200) during the etching process based on the temperature of the substrate (200) calculated from the interference light (239sb).

Description

AREA

[0001] Embodiments described here generally relate to a method for manufacturing a semiconductor device, a film thickness measuring method, a temperature measuring method and a temperature measuring substrate. BACKGROUND

[0002] In the semiconductor device manufacturing process, plasma etching can be performed on a workpiece film of a substrate. In etching using plasma, it is desirable to achieve a desired machined shape by controlling various etching conditions with high precision. Therefore, the problem is how to accurately obtain various types of information during etching, such as the film thickness of a workpiece film on the substrate and the substrate temperature.

[0003] US 2012 / 0 084 045 A1 describes a temperature measurement method that can accurately measure the temperature of an object to be measured, even if a thin film has formed on the object, compared to a conventional method. The temperature measurement method includes: transmitting light from a light source to a measurement point of an object to be measured, the object being a substrate on which a thin film is formed; measuring a first interference wave caused by light reflected from a surface of the substrate and a second interference wave caused by light reflected from an interface between the substrate and the thin film and from a back side of the thin film; calculating an optical path length from the first interference wave to the second interference wave; and calculating a film thickness of the thin film based on an intensity of the second interference wave.Calculating an optical path difference between an optical path length of the substrate and the calculated optical path length based on the calculated film thickness of the thin film, compensating the optical path length from the first interference wave to the second interference wave based on the calculated optical path difference, and calculating a temperature of the object at the measurement point based on the compensated optical path length.

[0004] WO 2022 / 163484 A1 describes a temperature control method comprising: detecting a temperature TB of a temperature control medium before a temperature change during a plurality of processes n in which heat is supplied to a substrate placed on a placement surface of a stage, and a pressure Pn of a heat transfer gas supplied to an ejection opening of the stage, as well as a temperature TWn of the substrate for each of the processes n; detecting, after a temperature change, where the temperature of the temperature control medium is the temperature TB, for each of the processes n, a temperature TW'n,max of the substrate when the pressure of the heat transfer gas is reduced from the pressure Pn, and a temperature TW'n,min of the substrate when the pressure of the heat transfer gas is reduced from the pressure Pn; setting the temperature of the temperature control medium to a temperature TB'' that satisfies expression (1), and for each of the processes n,Adjust the pressure of the heat transfer gas so that the substrate temperature reaches the temperature TWn. (1): TB+max(TWn-TW'n,max) ≤ TB'' ≤ TB+min(TWn-TW'n,min).

[0005] US 2007 / 0 084 847 A1 describes a stage to which a substrate to be processed in a substrate processing apparatus is electrostatically attracted, the stage comprising: a temperature measuring unit that measures a temperature of the substrate to be processed, a temperature adjusting unit that performs temperature adjustment on the substrate to be processed to achieve a target temperature based on a preset parameter, and a substrate temperature controlling unit that controls the temperature of the substrate to be processed by controlling the temperature adjustment by the temperature adjusting unit on the basis of a temperature measured by the temperature measuring unit. BRIEF DESCRIPTION OF THE DRAWINGS Fig. is a cross-sectional view schematically illustrating an example of a configuration of a plasma processing apparatus according to a first example; Fig. is a schematic diagram showing an example of a configuration of an interferometer according to the first example; Fig. are cross-sectional views sequentially illustrating some procedures for a method of manufacturing a semiconductor device according to the first example; Fig. are cross-sectional views sequentially illustrating some procedures for a method of manufacturing a semiconductor device according to the first example; Fig. are graphical representations for explaining data obtained by the interferometer according to the first example; Fig. is a cross-sectional view illustrating an example of a configuration of a semiconductor device according to the first example; Fig. is a flowchart illustrating an example of procedures for plasma processing on a wafer according to the first example; Fig. is a cross-sectional view schematically illustrating an example of a configuration of a plasma processing apparatus according to an embodiment; Fig. are schematic views illustrating an example of a mechanism for adjusting the temperature of an electrostatic chuck included in the plasma processing apparatus according to the embodiment; Fig. are cross-sectional views sequentially illustrating some procedures for a method of manufacturing a semiconductor device according to the embodiment; Fig. are cross-sectional views sequentially illustrating some procedures for a method of manufacturing a semiconductor device according to the embodiment; Fig. are cross-sectional views sequentially illustrating some procedures for a method of manufacturing a semiconductor device according to the embodiment; Fig. is a schematic diagram illustrating a light-shielding layer and components positioned on and under the light-shielding layer according to the embodiment; Fig. are schematic diagrams each illustrating a state of a wafer during plasma processing according to the embodiment; Fig. is a flowchart illustrating an example of procedures for plasma processing on the wafer according to the embodiment; Fig. are diagrams illustrating optical characteristics of materials considered as candidates for a light-shielding layer according to a modification of the embodiment; and Fig. is a diagram illustrating a transmittance of a light-shielding layer according to a modification of the embodiment. DETAILED DESCRIPTION

[0006] Basically, a method for manufacturing a semiconductor device according to one embodiment includes: preparing a substrate, the substrate including: a plurality of light-shielding layers arranged at predetermined intervals to shield light having a predetermined wavelength; a workpiece film disposed on the plurality of light-shielding layers and including a plurality of first insulating layers and a plurality of second insulating layers alternately stacked one on top of the other; and a mask pattern disposed on the workpiece film and having a plurality of openings; and etching the workpiece film exposed by the plurality of openings, wherein etching the workpiece film includes: irradiating a back surface of the substrate with the light while etching the workpiece film;Observing interference light generated by interference between first reflected light reflected from the back side of the substrate and second reflected light passing through the substrate and reflected from undersides of the plurality of light-shielding layers; calculating a temperature of the substrate during the etching process based on the interference light; and adjusting the temperature of the substrate during the etching process based on the temperature of the substrate calculated from the interference light.

[0007] Embodiments of the present invention will be described in detail below with reference to the drawings. Note that the present invention is not limited to the following embodiments. Furthermore, components in the following embodiments include those readily conceived by those skilled in the art or those substantially identical thereto. [First example]

[0008] A first example will be described in detail below with reference to the drawings. (Example of the configuration of a plasma processing device)

[0009] Fig. 1 is a cross-sectional view schematically illustrating an example of the configuration of a plasma processing apparatus 1 according to the first example. The plasma processing apparatus 1 is configured, for example, as a plasma etching device that performs plasma etching on a workpiece film formed on a wafer 100.

[0010] As in Fig. As shown, the plasma processing device 1 includes a chamber 11, which is a processing vessel for processing the wafer 100. The chamber 11 is made of aluminum, for example, and can be hermetically sealed.

[0011] A gas supply port 13 is provided in an upper portion of the chamber 11. A gas supply device (not shown) is connected to the gas supply port 13 via a conduit to supply a processing gas to be used during processing of the wafer 100.

[0012] Below the gas supply port 13, a nozzle head 18 is provided, which functions as the upper electrode. The nozzle head 18 has a plurality of gas outlet ports 18g that penetrate the nozzle head 18 in the direction of the plate thickness. The processing gas supplied from the gas supply port 13 is introduced into the chamber 11 through the gas outlet ports 18g. An electrostatic chuck 20 is arranged below the nozzle head 18 so that it faces the nozzle head 18.

[0013] The electrostatic chuck 20 is configured to not only electrostatically attract and hold the wafer 100 to be processed in the chamber 11, but also to regulate the temperature of the wafer 100, and also functions as a lower electrode. An opening (not shown) for loading / unloading the wafer 100 is provided in a side surface of the chamber 11, and the wafer 100 is placed on the electrostatic chuck 20 in the chamber 11 by a transport arm (not shown) from the loading / unloading opening.

[0014] The electrostatic chuck 20 is mounted on a support 12, which protrudes vertically upward in a tubular manner from a bottom wall near the center of the chamber 11. The support 12 supports the electrostatic chuck 20 near the center of the chamber 11, which is separated from the nozzle head 18 by a predetermined distance, so that it faces the nozzle head 18 in parallel. With such a structure, the nozzle head 18 and the electrostatic chuck 20 form a pair of parallel plate electrodes.

[0015] The electrostatic chuck 20 includes a chuck mechanism that electrostatically attracts the wafer 100. The chuck mechanism includes a chuck electrode 24 serving as a power supply plate, a power supply line 45, and a power supply 46. The power supply 46 is connected to the chuck electrode 24 via the power supply line 45. With such a mechanism, direct current is supplied from the power supply 46 to the chuck electrode 24, and an upper surface of the electrostatic chuck 20 is electrostatically charged.

[0016] The power supply line 41 is connected to the electrostatic chuck 20. A separating capacitor 42, a matching device 43, and a high-frequency power supply 44 are connected to the power supply line 41. During plasma processing, high-frequency current at a predetermined frequency is supplied from the high-frequency power supply 44 to the electrostatic chuck 20. With such a mechanism, the electrostatic chuck 20 also functions as the lower electrode.

[0017] An insulator ring 15 is disposed on an outer periphery of the electrostatic chuck 20 so as to cover the side surface and a peripheral edge portion of the bottom surface of the electrostatic chuck 20. An outer peripheral ring 16 is provided on the insulator ring 15 so as to surround the outer periphery of the electrostatic chuck 20. The outer peripheral ring 16 regulates an electric field so that the electric field at a peripheral edge portion of the wafer 100 is not deflected in a vertical direction, that is, in a direction perpendicular to the surface of the wafer 100, during plasma processing on the wafer 100.

[0018] A baffle 17 is provided between the insulator ring 15 and the side wall of the chamber 11. The baffle 17 has a plurality of gas outlet holes 17e penetrating the baffle 17 in the direction of the plate thickness.

[0019] A gas exhaust port 14 is provided below the baffle 17 in the chamber 11. A vacuum pump 14p, which exhausts the atmosphere in the chamber 11, is connected to the gas exhaust port 14.

[0020] A region in the chamber 11, which is separated by the electrostatic chuck 20 and the guide plate 17 and the nozzle head 18, is a plasma processing chamber 61. An upper region in the chamber 11, which is separated by the nozzle head 18, is a gas supply chamber 62. A lower region in the chamber 11, which is separated by the electrostatic chuck 20 and the guide plate 17, is a gas outlet chamber 63.

[0021] The plasma processing device 1 includes a controller 50 that controls each part of the plasma processing device 1, such as the power supply 46, the adjustment device 43, the high-frequency power supply 44, and the gas supply device. The controller 50 is configured as a computer including a central processing unit (CPU), a read-only memory (ROM), a random access memory (RAM), and the like, which are not shown. The controller 50 may be configured as an application-specific integrated circuit (ASIC) or the like having a function for use in the plasma processing device 1.

[0022] At the time of plasma processing of the wafer 100, the wafer 100 to be processed is placed on the electrostatic chuck 20 and attracted by the chuck mechanism under the control of the controller 50. The interior of the chamber 11 is evacuated by the vacuum pump 14p connected to the gas exhaust port 14. When the interior of the chamber 11 reaches a predetermined pressure, a processing gas is supplied from the gas supply device (not shown) to the gas supply chamber 62 and supplied to the plasma processing chamber 61 via the gas outlet ports 18g of the nozzle head 18.

[0023] Furthermore, by applying a high-frequency voltage to the electrostatic chuck 20 as the lower electrode in a state where the nozzle head 18 as the upper electrode is grounded under the control of the controller 50, plasma is generated in the plasma processing chamber 61. On the lower electrode side, a potential gradient is generated between the plasma and the wafer 100 due to a self-bias by the high-frequency voltage, ions in the plasma are accelerated toward the electrostatic chuck 20, and anisotropic etching processing is performed. (Example of the configuration of an interferometer)

[0024] In the plasma processing apparatus 1 according to the first example described above, processing is performed, for example, by etching workpiece films of different materials and film thicknesses into a desired shape. The workpiece film is formed from a predetermined material with a predetermined film thickness as a target. However, the film thickness of the workpiece film can vary for each wafer 100.

[0025] Therefore, in the configuration according to the first example, a film thickness of a workpiece film is measured in advance for each wafer 100 using an interferometer 3 described below, and etching is performed after an etching condition such as a processing time is optimized based on a result of the film thickness measurement.

[0026] Fig. 1 is a schematic diagram showing an example of a configuration of the interferometer 3 according to the first example. The interferometer 3 according to the first example can measure a film thickness of a workpiece film to be measured, which is formed on a wafer 100, based on light interference.

[0027] As in Fig. As shown, the interferometer 3 includes a light source 31, an optocoupler 32, a collimator lens 33, a placement table 34, a sensor head 35, a spectroscope 36, a fiber optic cable 37, and an arithmetic device 30.

[0028] The fiber optic cable 37 connects the light source 31, the optocoupler 32, the collimator lens 33, the sensor head 35 and the spectroscope 36.

[0029] The light source 31 is a laser diode (LD) or the like that emits low-coherence laser light. Coherence is an index indicating the degree of coherence between optical waves, and low-coherence light is light with a small coherence length, i.e., a small difference in the optical path length that causes interference fringes. By performing a measurement using such light, it is possible to observe the measurement target with a resolution corresponding to the coherence length of the light.

[0030] With such a light source 31, the interferometer 3 according to the first example is configured as a low coherence interferometer (LCI).

[0031] Note that the light emitted from the light source 31 is infrared light, and, for example, light having a wavelength of 1,200 nm or more, preferably 1,250 nm or more and 1,350 nm or less, can be used.

[0032] The optocoupler 32 is a passive optical device that demultiplexes and multiplexes the light from the light source 31. The optocoupler 32 emits the light from the light source 31 to the collimator lens 33.

[0033] The collimator lens 33 is an aberration-corrected lens, allowing parallel light to be obtained. The collimator lens 33 focuses the light from the optocoupler 32 into a single point and emits the focused light.

[0034] The sensor head 35 is provided at the tip of the optical fiber cable 37 and is inserted into a through-hole provided in the placement table 34, onto which the wafer 100 can be placed. Thus, the back of the wafer 100 placed on the placement table 34 is irradiated with the light passing through the light source 31, the optocoupler 32, and the collimator lens 33.

[0035] The light emitted onto the back surface of wafer 100 is reflected by wafer 100 itself, a workpiece film provided on wafer 100, or the like. A plurality of light beams reflected by respective parts of wafer 100 interfere with each other, are detected by sensor head 35 as a plurality of types of interference light, and are emitted to spectroscope 36 via collimator lens 33 and optical coupler 32.

[0036] The spectroscope 36 measures an interference spectrum obtained by performing spectroscopic analysis of the interference light detected by the sensor head 35 for each wavelength. The interference spectrum obtained by the spectroscope 36 indicates the intensity of the interference light for each wavelength. That is, the interference spectrum is displayed as a graph in which the horizontal axis represents a light wavelength and the vertical axis represents a light intensity. The spectroscope 36 outputs the measured interference spectrum to the arithmetic device 30.

[0037] The arithmetic device 30 is configured as a computer including a CPU, a ROM, a RAM, and the like (not shown), and performs various calculations based on an interference spectrum. The arithmetic device 30 obtains a correlation signal, for example, by inverse fast Fourier transform (iFFT), and calculates a thickness or the like of each part of the wafer 100 from an optical path length of each part of the wafer 100 indicated by a peak of the correlation signal. (Method for manufacturing a semiconductor device)

[0038] Next, an example of a method for manufacturing a semiconductor device according to the first example will be described with reference to Fig. described. The method for manufacturing the semiconductor device according to the first example includes measuring a film thickness of a workpiece film using the above-described interferometer 3 and etching the workpiece film using the above-described plasma processing device 1.

[0039] Fig. are cross-sectional views sequentially illustrating some procedures for the method of manufacturing the semiconductor device according to the first example. Fig. mainly illustrate how a film thickness of a workpiece film 110 is measured by the interferometer 3 and how the workpiece film 110 is etched by the plasma processing apparatus 1.

[0040] As in Fig. As shown, a workpiece film 110 and a CVD carbon layer 120 are formed in this order on a wafer 100, such as a silicon wafer. A single layer or layered films may be provided between the wafer 100 and the workpiece film 110.

[0041] The workpiece film 110 is, for example, a film in which a plurality of different types of layers are stacked in multiple layers. For example, the workpiece film 110 is a film in which silicon nitride (SiN) layers NL as first insulating layers and silicon oxide (SiO) layers OL as second insulating layers are alternately stacked one on top of the other. Each of the number of silicon nitride layers NL and the number of silicon oxide layers OL included in the workpiece film 110 can be approximately 50 to 400.

[0042] The CVD carbon layer 120 is an organic layer consisting primarily of carbon and formed, for example, by plasma chemical vapor deposition (CVD) or the like. An example of such a CVD carbon layer 120 is an advanced patterning film (APF) manufactured by Applied Materials, Inc.

[0043] In addition, a film thickness of the workpiece film 110 is measured using the interferometer 3 described above. That is, the wafer 100 on which the workpiece film 110 and the CVD carbon layer 120 are formed is placed on the placement table 34, and the back surface of the wafer 100 is irradiated with laser light or the like from the light source 31 via the sensor head 35.

[0044] A portion of the laser light irradiated onto the back side of wafer 100 is reflected by the back side of wafer 100 and detected as reflected light 38s by the sensor head 35 of interferometer 3. Another portion of the laser light transmits through wafer 100, is reflected by a bottom surface of workpiece film 110, a surface in contact with the front side of wafer 100, and is detected by sensor head 35 as reflected light 38p. Another portion of the laser light transmits through wafer 100 and workpiece film 110, is reflected by a bottom surface, also referred to as the lower surface, of CVD carbon layer 120, a surface in contact with a top side of workpiece film 110, and is detected by sensor head 35 as reflected light 38c.

[0045] The spectroscope 36 of the interferometer 3 measures a spectrum of an interference wave obtained by interference between the reflected light 38s, the reflected light 38p, and the reflected light 38c. The arithmetic device 30 of the interferometer 3 calculates a film thickness of the workpiece film 110 by performing various calculations based on the interference spectrum measured by the spectroscope 36.

[0046] That is, the optical path length of the wafer 100 is obtained from the interference light 39sp between the reflected light 38s from the back surface of the wafer 100 and the reflected light 38p from the bottom surface of the workpiece film 110. The optical path length is a distance traveled by light in a vacuum within a time equal to the time the light travels in a predetermined substance and is expressed as a product of the refractive index of the target substance and the distance. Since the optical path length of the wafer 100 depends on the refractive index and the thickness of the wafer 100, the thickness of the wafer 100 can be obtained from the optical path length of the wafer 100 made of a known material.

[0047] Furthermore, a total optical path length of the wafer 100 and the workpiece film 110 is obtained from the interference light 39sc between the reflected light 38s from the back surface of the wafer 100 and the reflected light 38c from the bottom surface of the CVD carbon layer 120. When the above-described influence of the optical path length of the wafer 100 is subtracted from the total optical path length, the optical path length of the workpiece film 110 alone can be obtained, and the film thickness of the workpiece film 110 can be obtained from the optical path length of the workpiece film 110 made of a known material.

[0048] Note that the film thickness measurement is preferably performed at a plurality of points within a plane of the wafer 100. When a plurality of pieces of measurement data are obtained from a wafer 100, an average value or the like of these pieces of measurement data can be used as the film thickness of the workpiece film 110.

[0049] As in Fig. As shown, a silicon oxynitride (SiON) layer 130 and a resist pattern 140p are further formed in this order on the CVD carbon layer 120. The silicon oxynitride layer 130 is formed, for example, by plasma CVD or the like. The resist pattern 140p is formed by spin coating, exposure, and development of a resist layer and has a structure corresponding to the shape to be formed on the workpiece film 110 by the plasma processing described below. In the example of Fig. the resist pattern 140p has a structure including a plurality of hole-shaped openings to form through holes in the workpiece film 110.

[0050] Next, the silicon oxynitride layer 130 is etched using the resist pattern 140p as a mask, and the pattern of the resist pattern 140p is transferred to the silicon oxynitride layer 130. Further, the CVD carbon layer 120 is etched using the silicon oxynitride layer 130, to which the pattern is transferred, as a mask, and the pattern of the silicon oxynitride layer 130 is further transferred to the CVD carbon layer 120.

[0051] As in Fig. As shown, a mask pattern 120p is formed on the workpiece film 110 by transferring the pattern to the CVD carbon layer 120 through the etching process. Note that the resist pattern 140p and the silicon oxynitride layer 130 disappear sequentially through the etching process.

[0052] As in Fig. As shown, the workpiece film 110 exposed by the openings of the mask pattern 120p is etched and penetrated, for example, by the plasma processing device 1 described above. As a result, a plurality of through holes 111 are formed in the workpiece film 110. The front side of the wafer 100 is exposed from the bottom surfaces of the through holes 111.

[0053] Note that the etching of the silicon oxynitride layer 130 and the etching of the CVD carbon layer 120 can also be performed by the plasma processing apparatus 1. In this case, the silicon oxynitride layer 130, the CVD carbon layer 120, and the workpiece film 110 can be sequentially etched in one piece.

[0054] When the through holes 111 are formed by the above-described etching of the workpiece film 110, a film thickness measurement result of the interferometer 3 is used. That is, when etching the workpiece film 110, an etching condition is used under which the etching time or the like is adjusted based on the film thickness of the workpiece film 110 obtained by the interferometer 3, so that the workpiece film 110 is penetrated more reliably and the exposed front side of the wafer 100 is not unnecessarily etched away.

[0055] Now in Fig. More detailed examples of data obtained by Interferometer 3 are presented.

[0056] Fig. are graphical representations for explaining data obtained by the interferometer 3 according to the first example. Fig. is an example of spectral data over an optical path length of the wafer 100 obtained by the interferometer 3. Each of Fig. represents a state of the wafer 100 when the spectral data of the Fig. can be obtained.

[0057] In particular, Fig. a cross-sectional view of a wafer 100 alone. Fig. is a cross-sectional view of the wafer 100 after the workpiece film 110 and the CVD carbon layer 120 are formed. Fig. is a cross-sectional view of the wafer 100 after a pattern is transferred to the CVD carbon layer 120 and a mask pattern 120p is formed. Fig. is a cross-sectional view of the wafer 100 after etching on the workpiece film 110 is completed and through holes 111 are formed.

[0058] This means that the wafer 100 Fig. The spectral data obtained correspond to data used to measure a film thickness of the workpiece film 110 in the process of manufacturing the semiconductor device according to the first example described above. On the other hand, the spectral data obtained from the wafer 100 of Fig. spectral data obtained in Fig. shown as a reference.

[0059] As in Fig. As shown, interferometer 3 acquires spectral data from wafer 100 in each state, where the horizontal axis represents optical path length and the vertical axis represents intensity. The spectrum acquired by interferometer 3 varies greatly depending on the state of wafer 100.

[0060] For example, in a state of only wafer 100, when many wafers 100 are input, spectral data having a peak at a predetermined optical path length is obtained. The peak of the optical path length is obtained from interference light between the reflected light from the back side of wafer 100 and the reflected light reflected from the front side of wafer 100 but not transmitted.

[0061] In the wafer 100 alone, no workpiece film 110 and the like are formed on the wafer 100, and the front surface of the wafer 100 is in contact with the atmosphere such as air at the time of measurement by the interferometer 3. Since reflection and transmission of light occur at a plane of contact between substances with different refractive indices, interference light is observed due to reflected light reflected by the front and back surfaces of the wafer 100, even in the case where the wafer 100 is alone as described above. As described above, the peak of the spectral data of the wafer 100 alone indicates an optical path length of the wafer 100.

[0062] In addition, spectral data having two peaks are obtained from a wafer 100 on which the workpiece film 110 and the CVD carbon layer 120 have been formed.

[0063] One of the two peaks is a peak indicating an optical path length of the wafer 100, which is formed from the interference light 39sp between the reflected light 38s from the back side of the wafer 100 and the reflected light 38p from the bottom side of the wafer 100. Fig. shown workpiece film 110 is obtained.

[0064] It is assumed that the reason why the intensity of the peak indicating the optical path length of the wafer 100 is lower than the intensity of the peak obtained from the wafer 100 alone is that the workpiece film 110 formed on the wafer 100 weakens the reflection of light at the front surface of the wafer 100. That is, it is estimated that the reflected light 38s from the front surface of the wafer 100 is attenuated because part of the light from the wafer 100 is transmitted to the workpiece film 110.

[0065] The other of the two peaks included in the spectral data is a peak indicating a total optical path length of the wafer 100 and the workpiece film 110, which is obtained from the interference light 39sc between the reflected light 38s from the back surface of the wafer 100 and the reflected light 38c from the bottom surface of the CVD carbon layer 120.

[0066] Note that the CVD carbon layer 120 has a property that both an extinction coefficient, which indicates light attenuation in a substance, and a refractive index of light are large with respect to infrared light with a wavelength of 1,200 nm or more. That is, the CVD carbon layer 120 can function as a light-shielding layer that has low transmittance and high reflectance with respect to, for example, infrared light.

[0067] Therefore, most of the light emitted from the light source 31 of the interferometer 3 to the back surface of the wafer 100 and transmitted through the wafer 100 and the workpiece film 110 is reflected at an interface between the workpiece film 110 and the CVD carbon layer 120 without passing through the top surface of the workpiece film 110. Therefore, it is assumed that the reflected light 38p from the bottom surface of the workpiece film 110 is detected with a relatively high intensity.

[0068] In addition, spectral data obtained from the wafer 100 after a mask pattern 120p is formed by transferring the resist pattern 140p over the silicon oxynitride layer 130 to the CVD carbon layer 120 are substantially similar to those obtained from the wafer 100 provided with the CVD carbon layer 120 before the pattern is transferred thereto.

[0069] However, the mask pattern 120p has a plurality of openings. Therefore, the reflected light reflected without passing through the upper surface of the workpiece film 110 includes light that has passed through the workpiece film 110, reached portions of the mask pattern 120p without openings, and been reflected by the lower surface of the CVD carbon layer 120 contacting the workpiece film 110, and light that has passed through the workpiece film 110, reached the openings of the mask pattern 120p, and been reflected by air or the like contacting the upper surface of the workpiece film 110 exposed by the openings.

[0070] This is considered to be the reason why the spectral data obtained from the wafer 100 before the pattern is transferred to the CVD carbon layer 120 does not completely match that after the pattern is transferred to the CVD carbon layer 120.

[0071] In addition, after the plurality of through holes 111 are formed in the workpiece film 110 by etching through the mask pattern 120p, spectral data having a peak near the optical path length of the wafer 100 is obtained from the wafer 100.

[0072] The front side of the wafer 100 after etching is partially exposed compared to the state in which the front side of the wafer 100 before etching is completely covered with the workpiece film 110. That is, the wafer 100 after etching on the workpiece film 110 is in a state in which the Fig. shown condition and the one in Fig. shown state are mixed.

[0073] Therefore, it can be assumed that spectral data showing a peak such as that in Fig. can be obtained when two peak positions caused by the interference light 39sp and the interference light 39sc come close to each other by strengthening or weakening the interference light 39sp between the reflected light 38s from the back surface of the wafer 100 and the reflected light 38p from the bottom surface of the workpiece film 110 and the interference light 39sc between the reflected light 38s from the back surface of the wafer 100 and the reflected light 38c from the bottom surface of the CVD carbon layer 120.

[0074] As described above, the spectral data in the wafer 100 at each of the processing stages has a peak indicating an optical path length of the wafer 100 based on the interference light 39sp, and the spectral data in the wafer 100 at some of the processing stages has a peak indicating a total optical path length of the wafer 100 and the workpiece film 110 based on the interference light 39sc.

[0075] Since, as described above, these two peak positions move, the film thickness difference of the workpiece film 110 within the plane of the wafer 100 can be detected for each wafer 100 or for each batch, for example, as an optical path length difference of the workpiece film 110 obtained from spectral data.

[0076] However, the peak position, intensity, and the like of the spectrum are determined by the wafer 100 on which the workpiece film 110 and the like are formed, with complex factors including the reflection and attenuation of light in each configuration. The workpiece film 110 itself has a multilayer structure including the insulating layers NL and OL, and reflection and transmission are repeated for each of a large number of interfaces between the insulating layers NL and OL. The light repeatedly split into transmission and reflection components for all layers as described above exhibits complex behavior, which is also reflected in the peak position, intensity, and the like of the spectral data.

[0077] Therefore, the arithmetic device 30 of the interferometer 3 may include a database or the like of spectral data for each film thickness of the workpiece film 110. When actually calculating a film thickness of the workpiece film 110, the arithmetic device 30 may identify the film thickness of the workpiece film 110 based on the spectral data obtained from the wafer 100 to be measured, referring to the above-described database.

[0078] Thereafter, the formation of various films, etching, and other processing are repeated to manufacture the semiconductor device according to the first example. An example configuration of a semiconductor device 10 according to the first example is shown in Fig. shown.

[0079] Fig. is a cross-sectional view showing an example of a configuration of the semiconductor device 10 according to the first example. In Fig. However, the hatching has been omitted to make the drawing easier to view.

[0080] As in Fig. As shown, the semiconductor device 10 includes an electrode layer EL, a source line SL, and a plurality of word lines WL in this order from the bottom side of the paper. Furthermore, the semiconductor device 10 includes a peripheral circuit CBA provided on a semiconductor substrate SB above the plurality of word lines WL. In the following description, the side on which the semiconductor substrate SB is disposed is referred to as the top side of the semiconductor device 10.

[0081] The source line SL is disposed on the electrode layer EL via an insulating film 160. A plurality of plugs PG are disposed in the insulating film 160, and the source line SL and the electrode layer EL maintain electrical conductivity via the plugs PG. Consequently, a source potential can be applied to the source line SL from outside the semiconductor device 10 via the electrode layer EL and the plugs PG.

[0082] The plurality of word lines WL are stacked on the source line SL. In the semiconductor device 10, a region where the plurality of word lines WL are arranged corresponds to an element region ER. A storage region MR is arranged in a central portion of each of the plurality of word lines WL, and step regions SR are arranged at both ends of the storage region MR.

[0083] Note that although the semiconductor device 10 in the example of Fig. in the element region ER has only one stack structure of the word lines WL, the semiconductor device 10 may have in the element region ER a plurality of stack structures of the word lines WL, each of which has a memory region MR and step regions SR.

[0084] A plurality of pillars PL are arranged in the memory area MR, penetrating the word lines WL in a stacking direction. A plurality of memory cells are formed at intersection points between the pillars PL and the word lines WL. For this purpose, the semiconductor device 10 is configured, for example, as a three-dimensional non-volatile memory in which the memory cells are arranged three-dimensionally in the memory area MR.

[0085] In the step regions SR, the plurality of word lines WL are processed and terminated into a step shape. A contact CC connected to the word line WL of each layer is arranged in a terrace portion of each of the steps configured by the plurality of word lines WL.

[0086] The multi-layered word lines WL are individually led out from these contacts CC. From these contacts CC, a write voltage, a read voltage, and the like are applied to memory cells enclosed in the memory area MR in the central portion of each of the plurality of word lines WL via the word line WL at the same height position as the memory cells.

[0087] The plurality of word lines WL, pillars PL, and contacts CC are covered with the insulating film 150. The insulating film 150 also extends around the plurality of word lines WL. The peripheral circuit CBA provided on the semiconductor substrate SB is arranged above the insulating film 150.

[0088] The semiconductor substrate SB is, for example, a silicon substrate or the like. The peripheral circuit CBA, which includes a transistor TR, wiring, and the like, is arranged on the surface of the semiconductor substrate SB. Various voltages applied from the contacts CC to the memory cells are controlled by the peripheral circuit CBA, which is electrically connected to the contacts CC. Consequently, the peripheral circuit CBA controls the electrical operation of the memory cell.

[0089] The peripheral circuit CBA is covered with an insulating film 170, and the semiconductor device 10 including the plurality of word lines WL, pillars PL, contacts CC and the like and the peripheral circuit CBA is formed by bonding the insulating film 170 and the insulating film 150 covering the plurality of word lines WL together.

[0090] In manufacturing such a semiconductor device 10, a layered body in which a plurality of silicon nitride layers and a plurality of silicon oxide layers are alternately stacked one upon another is formed via a source line SL on a predetermined substrate.

[0091] Furthermore, stepwise etching is performed on a portion of the layered body to form a step region SR. Furthermore, memory holes for forming pillars PL are formed in the layered body by the same etching, and the memory holes are filled with a memory layer, a semiconductor layer, and the like.

[0092] Next, word lines WL are formed by processing to replace the plurality of silicon nitride layers of the laminated body with conductive layers, which is called replacement processing. Furthermore, a contact CC is formed in the step region SR, and upper-layer wiring or the like is formed in an upper layer of the laminated body.

[0093] Here, for example, while performing etching on the laminated body before the exchange processing, plasma processing is used by the plasma processing device 1 described above. That is, the laminated body before the exchange processing corresponds to the workpiece film 110 described above, and the silicon nitride layers NL and the silicon oxide layers OL of the workpiece film 110 are subjected to plasma processing to form a plurality of storage holes corresponding to the through holes 111 described above.

[0094] The substrate on which the layered body is formed corresponds to the wafer 100 described above. The source line SL is formed, for example, by diffusing impurities on the surface of the wafer 100. Note that even if another layer such as the source line SL is interposed between the wafer 100 and the workpiece film 110, a film thickness of the workpiece film 110 can be measured by the interferometer 3 as described above, as long as the interposed layer is not a light-shielding layer such as the CVD carbon film 120.

[0095] After the laminated body undergoes replacement processing and upper-layer wiring or the like is formed on the laminated body, the semiconductor substrate SB on which the peripheral circuit CBA has been formed is bonded to the substrate on which the laminated body and the like are formed, that is, the wafer 100. Thereafter, the wafer 100 is removed by back grinding or the like, leaving the source line SL. Further, an insulating film 160 with plugs PG, an electrode layer EL, and the like are formed under the source line SL.

[0096] In this way, the semiconductor device 10 according to the first example is manufactured. (Example of plasma processing)

[0097] Next, with reference to Fig. An example is described in which the wafer 100 is processed using the plasma processing apparatus 1 and the interferometer 3 according to the first example.

[0098] Fig. is a flowchart illustrating an example of procedures for plasma processing the wafer 100 according to the first example. The flowchart of Fig. represents procedures from inputting a batch until the input batch of wafers 100 is processed by the plasma processing apparatus 1.

[0099] As in Fig. As shown, wafers 100 for a batch including a predetermined number of wafers 100 are input into the manufacturing process (step S101). Note that in the process of manufacturing the semiconductor device 10, processing is advanced for each batch.

[0100] A workpiece film 110 in which a plurality of insulating layers NL and a plurality of insulating layers OL are alternately stacked one upon another is formed on each of the wafers 100 of a batch (step S102). Further, a CVD carbon layer 120 is formed on the workpiece film 110 (step S103).

[0101] For example, a film thickness of the workpiece film 110 is measured, for example, by performing a measurement with respect to the wafer 100 using the interferometer 3 in a state where the CVD carbon layer 120 is formed (step S104). At this time, as described above with respect to a wafer 100, film thicknesses may be measured at a plurality of locations in the plane of the wafer 100, and an average value or the like of a plurality of acquired pieces of data may be used as the film thickness of the workpiece film 110 in the wafer 100.

[0102] The film thickness of the workpiece film 110 is measured with respect to at least one wafer 100 among the wafers 100 for a batch. Alternatively, the film thickness measurement may be performed with respect to multiple wafers 100, such as a first wafer 100, a middle wafer 100, and a last wafer 100 of the batch. Alternatively, the film thickness measurement may be performed with respect to all wafers 100 of a batch.

[0103] After measuring the film thickness of the workpiece film 110, a silicon oxynitride layer 130 is formed on the CVD carbon layer 120 (step S105), and further, a resist pattern 140p is formed on the silicon oxynitride layer 130 (step S106).

[0104] For each wafer 100, etching is performed on the silicon oxynitride layer 130 using the resist pattern 140p as a mask (step S107), and etching is performed on the CVD carbon layer 120 using the silicon oxynitride layer 130 to which the resist pattern 140p has been transferred as a mask (step S108). As a result, a mask pattern 120p is formed on each wafer 100 by transferring the pattern to the CVD carbon layer 120.

[0105] For each wafer 100, etching is performed on the workpiece film 110 exposed at the mask pattern 120p (step S109). During this process, an etching condition, such as an etching time, is adjusted based on the film thickness of the workpiece film 110 measured by the interferometer 3 so that the workpiece film 110 is properly penetrated.

[0106] In a case where the measurement of the film thickness is performed with respect to a wafer 100, the film thickness of the workpiece film 110 for the wafer 100 is used as a representative value and is applied to all the wafers 100 of a batch.

[0107] In a case where the film thickness measurement is performed with respect to a plurality of wafers 100, an average of a plurality of film thickness values ​​obtained from these wafers 100 may be applied to all wafers 100 of a batch. Alternatively, the wafers 100 of a batch may be divided into groups according to the number of wafers 100 for which the film thickness measurement was performed. For example, a film thickness obtained from a first wafer 100 of the batch may be applied to wafers 100 on the front side, a film thickness obtained from a middle wafer 100 of the batch may be applied to wafers 100 near the center, and a film thickness obtained from a last wafer 100 of the batch may be applied to wafers 100 on the back side.

[0108] In a case where the film thickness measurement is performed with respect to all wafers 100 of a batch, an etching condition based on the corresponding film thickness may be applied to each wafer 100.

[0109] During the etching, the controller 50 determines whether a timing for ending the etching of the workpiece film 110 has been reached under the etching condition corresponding to the film thickness of the workpiece film 110 (step S110).

[0110] The controller 50 continues etching until the time to stop etching the workpiece film 110 is reached (step S110: No) (step S109). When the time to stop etching the workpiece film 110 is reached (step S110: Yes), the controller 50 stops the power supply to the chamber 11.

[0111] This ends the plasma processing on the wafer 100 according to the first example. (Overview)

[0112] In a method for manufacturing a semiconductor device, etching on a workpiece film may be performed using a plasma processing device. The etching on the workpiece film is performed using an etching condition that is appropriately determined in advance.

[0113] However, during the formation of a workpiece film on each wafer, although the film thickness of the workpiece film is controlled, for example, through periodic quality control, the film thickness of the workpiece film may vary for each wafer or for each batch. For example, in a case where the workpiece film has a multilayer structure in which a plurality of different types of layers are stacked, the film thickness variation between batches is approximately ± 10%.

[0114] If etching is performed uniformly on such workpiece films using the same conditions, in a case where an actual film thickness of a workpiece film is thicker than a target film thickness, etching will be completed without achieving a desired etching depth. Furthermore, in a case where an actual film thickness of a workpiece film is thinner than a target film thickness, excessive etching may cause the base film of the workpiece film to be etched away or change the processed shape of the workpiece film, such as expanding in one dimension.

[0115] Therefore, as an example of a countermeasure, a change in the emission wavelength during plasma processing can be monitored, and an end point can be detected in real time. However, in a case where the etching area exposed by the mask pattern, i.e., the mask pattern coverage area, is small under a certain etching condition, or the like, it is not possible to sufficiently detect a change in the wavelength, and accordingly, it is not possible to detect an end point.

[0116] Furthermore, as an example of a countermeasure, it may also be considered to measure a film thickness using an optical film thickness gauge such as an ellipsometer after a workpiece film is formed, and to adjust an etching condition such as an etching time based on the measurement result. However, in a case where the workpiece film has a multi-layer structure in which a plurality of different types of layers are laminated, for example, and the total number of layers exceeds 100, it is difficult to accurately measure the film thickness using the optical film thickness gauge.

[0117] In the method for manufacturing the semiconductor device according to the first example, the back surface of the wafer 100 is irradiated with light, and a thickness of the workpiece film 110 is calculated based on interference light 39sp generated by interference between reflected light 38s reflected by the back surface of the wafer 100 and reflected light 38p transmitted through the wafer 100 and reflected by the bottom surface of the workpiece film 110, and interference light 39sc generated by interference between the reflected light 38s and the reflected light 38c transmitted through the wafer 100 and the workpiece film 110 and reflected by the bottom surface of the CVD carbon layer 120.

[0118] As a result, the film thickness of the workpiece film 110 can be measured with high accuracy. By measuring the film thickness using the interferometer 3 as described above, film thickness information regarding the workpiece film 110 on the wafer 100 can be obtained with high accuracy.

[0119] In the method for manufacturing the semiconductor device according to the first example, etching is performed under an etching condition based on the thickness of the workpiece film 110 calculated from the interference light 39sp and the interference light 39sc, so that the workpiece film 110 exposed by the mask pattern 120p is penetrated.

[0120] As a result, on the workpiece film 110, which varies in film thickness for each wafer 100 or for each batch, processing can be performed under the proper etching condition.

[0121] In the method for manufacturing the semiconductor device according to the first example, during the formation of the mask pattern 120p, a pattern that shields the light emitted onto the wafer 100 is formed on the CVD carbon film 120 as the mask pattern 120p. This can increase the intensity of the reflected light 38sc transmitted through the wafer 100 and the workpiece film 110 and reflected without passing through the upper surface of the workpiece film 110, and can improve the accuracy of measuring the film thickness.

[0122] In the method for manufacturing the semiconductor device according to the first example, the workpiece film 110 is a film in which a plurality of insulating layers NL and a plurality of insulating layers OL are alternately stacked one by one, and the plurality of insulating layers NL included in the workpiece film 110 is 50 or more layers. Therefore, the number of the two types of insulating layers NL and OL included in the workpiece film 110 is 100 or more.

[0123] As described above, by using the interferometer 3, the film thickness of the workpiece film 110 can be measured with high accuracy even in a case where the workpiece film 110 has a multilayer structure and it is difficult to measure a film thickness using an optical film thickness gauge. Furthermore, even in a case where, for example, it is difficult to detect an end point by observing plasma emission, an etching condition such as an etching time can be optimized by measuring a film thickness of the workpiece film 110 using the interferometer 3.

[0124] In the first example described above, after forming the CVD carbon layer 120 on the workpiece film 110, a film thickness of the workpiece film 110 is measured by the interferometer 3. However, the film thickness of the workpiece film 110 may be measured, for example, at a time point after the workpiece film 110 is formed and before the CVD carbon layer 120 is formed.

[0125] At an interface between substances with different refractive indices, light transmission and reflection occur. Therefore, after the workpiece film 110 is formed, even in a state where the upper surface of the workpiece film 110 is in contact with an atmosphere in a measurement environment such as air, the film thickness of the workpiece film 110 can be measured using the interferometer 3.

[0126] The film thickness of the workpiece film 110 may be measured at any time after forming the CVD carbon layer 120, after forming the silicon oxynitride layer 130, after forming the resist pattern 140p, after performing the etching of the silicon oxynitride layer 130, or after performing the etching of the CVD carbon layer 120.

[0127] In this way, the film thickness of the workpiece film 110 can be measured at any time after the workpiece film 110 is formed and before the etching of the workpiece film 110 is started.

[0128] Note that in a case where the measurement of the film thickness is performed after further forming another layer on the workpiece film 110, a layer functioning as a light-shielding layer is preferably formed at least immediately on the workpiece film 110.

[0129] For example, the CVD carbon layer 120 has the above-described properties of a light-shielding layer. Therefore, even if the silicon oxynitride layer 130, the resist pattern 140p, and the like are formed on the CVD carbon layer 120, the amount of light transmitted through these layers is extremely small, and these layers are expected to have little influence on the measurement of the film thickness of the workpiece film 110.

[0130] In addition, the layer acting as a light-shielding layer may be a titanium layer, a tungsten layer, or a nitride layer of a carbon-based material, titanium or tungsten, as well as the carbon-based layer such as the CVD carbon layer 120 described above.

[0131] In the first example described above, the interference light 39sp between the reflected light 38s and the reflected light 38p from the front and back of the wafer 100, the wafer on which the workpiece film 110 and the like are formed, is measured, and the influence of the wafer 100 on the interference light 39sc obtained from the workpiece film 110 is estimated.

[0132] However, for example, an interference spectrum of the wafer 100 alone can be obtained by performing a measurement using the interferometer 3 in a state where the wafer 100 is alone before the workpiece film 110 is formed. A film thickness of the workpiece film 110 can be measured from a result of analyzing the interference spectrum of the wafer 100 alone and the interference spectrum obtained from the wafer 100 on which the workpiece film 110 and the like are formed.

[0133] It is assumed that a silicon wafer or the like used to manufacture a semiconductor device is subject to strict quality control, and there are almost no deviations in various specifications of the silicon wafer, including thickness. However, even in this case, it is assumed that the film thickness of the workpiece film 110 can be measured more reliably and accurately by using not only the interference spectrum of the wafer 100 after the workpiece film 110 is formed, but also the interference spectrum of the wafer 100 alone.

[0134] Measurement in a state where the wafer 100 is alone can be performed for a wafer 100 at a plurality of locations in the plane of the wafer 100, for example, when a batch is input. Furthermore, measurement in a state where the wafer 100 is alone can be performed for one or more wafers 100 included in the batch. All wafers 100 in the batch can be inspected.

[0135] Furthermore, in the first example described above, the etching processing is performed to obtain a desired processed shape, for example, by changing the etching time based on the film thickness of the workpiece film 110 obtained by the interferometer 3. However, the etching conditions include various parameters capable of controlling an etching rate and a processed shape, such as a pressure, a high-frequency power value, a type and flow rate of a processing gas, and a wafer temperature.

[0136] Therefore, when the etching condition is changed based on the film thickness of the workpiece film 110, other parameters may be changed instead of or in addition to the etching condition. [Embodiment]

[0137] An embodiment will be described in detail below with reference to the drawings. This embodiment differs from the first example in that a wafer temperature is measured during plasma processing using interference light. In the drawings mentioned below, the same reference numerals are used for components similar to those in the first example described above, and the description thereof may be omitted. (Example of the configuration of a plasma processing device)

[0138] Fig. 1 is a cross-sectional view schematically showing an example of the configuration of a plasma processing device 2 according to the embodiment. The plasma processing device 2 according to the embodiment includes components corresponding to the respective components of the interferometer 3 according to the first example described above.

[0139] That is, the plasma processing apparatus 2 includes a light source 231, an optical coupler 232, a collimator lens 233, a sensor head 235, a spectroscope 236, and a fiber optic cable 237 as a configuration corresponding to the interferometer 3 according to the first example described above. Furthermore, the plasma processing apparatus 2 includes an electrostatic chuck 220 and a controller 250 instead of the electrostatic chuck 20 and the controller 50 according to the first example described above.

[0140] Similar to the interferometer 3 according to the first example described above, the optical fiber cable 237 connects the light source 231, the optocoupler 232, the collimator lens 233, the sensor head 235, and the spectroscope 236. The sensor head 235 is inserted into a through-hole provided in the electrostatic chuck 220 in the chamber 11 of the plasma processing device 2.

[0141] Thus, the back side of the wafer 200 placed on the electrostatic chuck 220 can be irradiated with light from the light source 231 via the sensor head 235. In addition, interference light is emitted from each part of the wafer 200 to the spectroscope 236 via the sensor head 235 and the collimator lens 233, and the spectroscope 236 outputs an interference spectrum obtained by analyzing the interference light to the controller 250.

[0142] By using the interference spectrum obtained as described above, a temperature of a substance such as the wafer 200 made of a known material and having a known thickness can be calculated.

[0143] The controller 250 of the plasma processing device 2 also functions as an arithmetic device that analyzes the interference spectrum from the spectroscope 236. Therefore, the controller 250 analyzes the interference spectrum of the wafer 200 output from the spectroscope 236 and calculates a temperature of the wafer 200 during plasma processing in the plasma processing device 2. (Example of electrostatic chuck configuration)

[0144] Next, a mechanism for adjusting the temperature of the electrostatic chuck 220 will be described with reference to Fig. described.

[0145] Fig. are schematic views illustrating an example of a mechanism for adjusting the temperature of the electrostatic chuck 220 included in the plasma processing apparatus 2 according to the embodiment. Fig. is a top view of the electrostatic Chuck 220, and Fig. is a schematic view of the temperature readjustment mechanism including a cross-section of the electrostatic chuck 220. In Fig. a through hole into which the sensor head 235 is inserted is not shown.

[0146] As in Fig. As shown, the electrostatic chuck 220 of the plasma processing apparatus 2 includes a main body 21, a chuck portion 22, and a ceramic plate 23. The main body 21 serves as the base of the electrostatic chuck 220. The chuck portion 22 includes the above-described chuck electrode 24 and the like and is arranged on the main body 21. The ceramic plate 23 is arranged on the outermost surface of the electrostatic chuck 220 and serves as a surface for placing the wafer 200.

[0147] Furthermore, the electrostatic chuck 220 includes a coolant flow path 25 and a gas flow path 28, which form part of the temperature adjustment mechanism. In addition to the coolant flow path 25 and the gas flow path 28, the electrostatic chuck 220 is provided with a cooler 82, a gas supply line 81, a mass flow controller (MFC) 83, a valve 84, a tank 85, and temperature sensors 86 and 87 as a temperature adjustment mechanism.

[0148] The cooler 82 is connected to the main body 21 of the electrostatic chuck 220 and is configured to circulate the coolant controlled at a predetermined temperature within the electrostatic chuck 220. That is, the coolant is discharged from an outlet port of the cooler 82 toward the electrostatic chuck 220 and flows into an inlet port of the cooler 82, thereby circulating between the cooler 82 and the electrostatic chuck 220. For example, a fluorinated hydrocarbon such as ethylene glycol, water, or another liquid is used as the coolant, depending on a desired temperature range.

[0149] The coolant flow path 25 is provided at a predetermined depth position within the main body 21 of the electrostatic chuck 220 along the surface of the electrostatic chuck 220, that is, along the ceramic plate 23, which is a surface for placing the wafer 200. The coolant flow path 25 may have any shape, such as meandering within the body 21 or branching into a plurality of paths within the main body 21. The coolant flow path 25 may include a plurality of independent flow paths.

[0150] The temperature sensor 87 is provided on the inlet side of the coolant flow path 25 to the main body 21, and the temperature sensor 86 is provided on the outlet side of the coolant flow path 25. The radiator 82 controls a temperature of the coolant based on the detection results of the temperature sensors 86 and 87.

[0151] The gas flow path 28 is provided so as to penetrate the electrostatic chuck 220 and has a plurality of openings 28g open to the surface of the ceramic plate 23. The plurality of openings 28g are provided in a manner distributed over the entire surface of the ceramic plate 23. In a case where the coolant flow path 25 includes a plurality of independent flow paths, the gas flow path 28 may also include a plurality of independent flow paths.

[0152] A downstream end of the gas supply line 81, which has an upstream end to which the gas supply source CY is connected, is connected to an upstream end of the gas flow path 28. The gas supply source CY stores a gas with high thermal conductivity, such as a He gas or an Ar gas. The gas supply line 81 is provided with an MFC 83, a valve 84, and a tank 85 in this order from the upstream side. The tank 85 is provided with a pressure sensor 85p that measures a pressure in the tank 85.

[0153] By opening the valve 84 of the gas supply line 81, the flow rate of the gas flowing from the gas supply source CY is controlled by the MFC 83, the gas is once stored in the tank 85 and the pressure of the gas is adjusted, and the gas is distributed from the plurality of openings 28g of the ceramic plate 23 between the front side of the ceramic plate 23 and the back side of the wafer 200.

[0154] The controller 250 of the plasma processing device 2 controls the pressure in the tank 85 by changing the gas flow rate through the MFC 83 based on the measurement result of the pressure sensor 85p. As a result, the gas temporarily stored in the tank 85 is supplied to the plurality of openings 28g of the ceramic plate 23 at a predetermined pressure.

[0155] As described above, the gas flow path 28 through which the high thermal conductivity gas flows is arranged near the coolant flow path 25 through which the temperature-controlled coolant flows, on the side closer to the ceramic plate 23, which is a surface for placing the wafer 200, than the coolant flow path 25.

[0156] As a result, heat exchange occurs between the coolant flowing through the coolant flow path 25 and the gas flowing through the gas flow path 28, and the gas is controlled to a predetermined temperature. The gas controlled to the predetermined temperature is distributed to the backside of the wafer 200, allowing the temperature of the wafer 200 to be adjusted.

[0157] In a case where each of the coolant flow path 25 and the gas flow path 28 includes a plurality of independent flow paths as described above, the electrostatic chuck 220 can be divided into a plurality of zones and controlled to different temperatures for the respective zones. (Method for manufacturing semiconductor devices)

[0158] Next, an example of a method for manufacturing a semiconductor device according to the embodiment will be described with reference to FIG. Fig. The method for manufacturing the semiconductor device according to the embodiment includes plasma processing on the wafer 200 in the plasma processing apparatus 2 described above.

[0159] Fig. are cross-sectional views sequentially illustrating some procedures for the method of manufacturing the semiconductor device according to the embodiment. Fig. mainly represent a state from inputting a batch to performing the etching processing by the plasma processing device 2.

[0160] As in Fig. As shown, in the method for manufacturing the semiconductor device according to the embodiment, a plurality of light-shielding layers 210 are formed on the front surface of the wafer 200 after the batch is input.

[0161] That is, as in Fig. As shown, a plurality of recesses 201 are formed on the front side of the wafer 200. The plurality of recesses 201 have substantially equal areas in plan view in a region vertically overlapping the back side of the wafer 200 in a portion to be later irradiated with light via the sensor head 235, and are periodically arranged at predetermined intervals. The spacing between the plurality of recesses 201 is set to be smaller than the wavelength of the light to be later emitted onto the back side of the wafer 200.

[0162] As in Fig. As shown, the plurality of recesses 201 are filled with a CVD carbon layer. Consequently, in the region of the front side of the wafer 200, which corresponds to the back side of the wafer 200 in the portion that will later be irradiated with light, a plurality of light-shielding layers 210 are formed, periodically arranged at predetermined intervals.

[0163] The shape of the plurality of light-shielding layers 210, viewed from above, is, for example, circular, oval, elliptical, polygonal, or the like. The plurality of light-shielding layers 210 can be arranged, for example, in a hexagonal close-packed lattice structure, such that the interval between the plurality of light-shielding layers 210 is smaller than the wavelength of light.

[0164] However, the plurality of recesses 201 and the plurality of light-shielding layers 210 may be formed over the entire surface of the wafer 200.

[0165] As in Fig. As shown, a workpiece film 110 is formed on the wafer 200, in which a plurality of insulating layers NL and OL (see Fig. above) is alternately stacked one at a time. Thus, the plurality of light-shielding layers 210 formed on the front side of the wafer 200 are covered with the workpiece film 110. As described above, for example, the light-shielding layers 210 are formed so as not to cover the entire front side of the wafer 200 and are arranged at predetermined intervals, so that peeling of the workpiece film 110 can be suppressed.

[0166] Further, a CVD carbon layer 120, a silicon oxynitride layer 130, and a resist pattern 140p are formed in this order on the workpiece film 110.

[0167] As in Fig. As shown, the silicon oxynitride layer 130 and the CVD carbon layer 120 are sequentially etched to form a mask pattern 120p of the CVD carbon layer 120 onto which the resist pattern 140p has been transferred.

[0168] As in Fig. As shown, etching is started on the workpiece film 110 using the plasma processing device 2. That is, a wafer 200 is brought into the chamber 11 of the plasma processing device 2 and placed on the electrostatic chuck 220. Further, a plasma P is generated in the chamber 11, while the back side of the wafer 200 is irradiated with light from the light source 231 via the sensor head 235 below the electrostatic chuck 220.

[0169] As a result, etching is started on the workpiece film 110 in portions exposed by the openings of the mask pattern 120p.

[0170] As in Fig. As shown, the etched depth of the workpiece film 110 increases as the plasma processing by the plasma processing device 2 progresses.

[0171] As in Fig. As shown, after a predetermined time has elapsed, the exposed portions of the workpiece film 110 are penetrated, and a plurality of through-holes 111 are formed. The light-shielding layers 210 or the front surface of the wafer 200 are exposed from the bottom surfaces of the through-holes 111.

[0172] Here, the wafer 200 is exposed to a high-temperature plasma during the etching of the workpiece film 110. During plasma processing, the temperature of the wafer 200 is controlled by the electrostatic chuck 220 of the plasma processing device 2 so that the temperature of the wafer 200 is kept constant, but the temperature of the wafer 200 gradually rises due to the heat from the plasma.

[0173] A portion of the light irradiated onto the back surface of the wafer 200 is reflected by the back surface of the wafer 200 and detected by the sensor head 235 as reflected light 238s. Furthermore, another portion of the light irradiated onto the back surface of the wafer 200 is transmitted through the wafer 200, reflected by the back surface of the light-shielding layer 210, and detected by the sensor head 235 as reflected light 238b.

[0174] The above-described spectroscope 236 measures a spectrum of an interference wave obtained by interference between the reflected light 38s and the reflected light 38b. The controller 250 of the plasma processing device 1 performs various calculations based on the interference spectrum measured by the spectroscope 236 to calculate a temperature of the wafer 200 during plasma processing.

[0175] That is, an optical path length of the wafer 200 is obtained from interference light 39sb between the reflected light 38s from the back surface of the wafer 200 and the reflected light 38b from the bottom surface, also referred to as the lower surface, of the light-shielding layer 210. As described above, the optical path length is expressed as the product of a refractive index of a target substance and a distance the light travels in the substance, that is, a thickness of the substance. Furthermore, both the refractive index and the thickness of the substance change depending on the temperature of the substance at that time.

[0176] Therefore, when the temperature of the wafer 200 changes during plasma processing, the optical path length of the wafer 200 also changes. If the refractive index and thickness are known at each temperature, as in the case of the wafer 200 used for manufacturing a semiconductor device, the temperature of the wafer 200 at that time can be obtained from the optical path length of the wafer 200.

[0177] In temperature measurement using such interference light, the interval between the plurality of light-shielding layers 210 is preferably smaller than the wavelength of the light irradiated onto the back surface of the wafer 200 as described above. As a result, in a region where the pattern of the mask pattern 120p is formed and the workpiece film 110 is etched, light is shielded by each of the plurality of light-shielding layers 210, rather than passing between the plurality of light-shielding layers 210, transmitted through the workpiece film 110, and detected by the sensor head 235 as reflected light 238b.

[0178] In a region where the pattern of the mask pattern 120p is formed and the workpiece film 110 is etched, when a part of the light is transmitted through the workpiece film 110, the other part of the light can be reflected by an etched end of the workpiece film 110 and detected by the sensor head 235 as reflected light 238p.

[0179] As in Fig. As shown, the depth reached by the etched end in the workpiece film 110 changes over time. Therefore, the reflected light 238p at the etched end and the interference light between the reflected light 238p and other reflected light from each portion of the wafer 200, such as the reflected light 238s and the reflected light 238b, also change over time and can become interference factors in calculating the temperature of the wafer 200.

[0180] By arranging the plurality of light-shielding layers 210 at intervals smaller than the light wavelength, such interference factors can be eliminated in advance.

[0181] When processing the above-described Fig. when a plurality of light-shielding layers 210 are formed, in a region where the pattern of the mask pattern 120p is formed and the workpiece film 110 is etched, the light-shielding layers 210 having an area slightly larger than the size of the plurality of through-holes 111 may be arranged at positions vertically overlapping the through-holes 111 in plan view.

[0182] As a result, the bottom surfaces of the through-holes 111 fully reach the light-shielding layers 210, which makes it easier for the workpiece film 110 to have uniform etching marks and the through-holes 111 to have a uniform machined shape.

[0183] In a case where the through-holes 111 of the workpiece film 110 are, for example, memory holes or the like for forming the pillars PL of the semiconductor device 10 according to the first example described above, these through-holes 111 are densely arranged, for example, in a staggered manner in plan view. Therefore, in a case where the plurality of light-shielding layers 210 are arranged to correspond to the positions where these through-holes 111 are formed, the interval between the light-shielding layers 210 can be smaller than the light wavelength.

[0184] In addition, in a case where the through holes 111 are memory holes or the like for forming pillars PL, the light-shielding layers 210 exposed from the bottom surfaces of the through holes 111 may be removed by etching or ashing after the through holes 111 are formed.

[0185] Preferred characteristics of the light shielding layers 210 will now be discussed.

[0186] Fig. is a schematic diagram showing a light-shielding layer 210 and components positioned on and below the light-shielding layer 210 according to the embodiment. As shown in Fig. As shown, refractive indices of the wafer 200, the light-shielding layer 210, and the workpiece film 110 are denoted by n0, n1, and n2, respectively, and extinction coefficients of the wafer 200, the light-shielding layer 210, and the workpiece film 110 are k0, k1, and k2.

[0187] Transmittances of light incident from the light source 231 onto the wafer 200, the light-shielding layer 210, and the workpiece film 110, that is, transmittances of light in the air, in the wafer 200, and in the light-shielding layer 210, are denoted by T0, T1, and T2, respectively. Furthermore, reflectances of light at an interface between the wafer 200 and the light-shielding layer 210 and at an interface between the light-shielding layer 210 and the workpiece film 110 are denoted by R0 and R1, respectively.

[0188] In this case, when the transmittance T0 of the light incident on the wafer 200 in the air is 1 (T0=1), the transmittance T1 in the wafer 200 can be expressed by the following formula (1). T1=T0−R0=1−R0

[0189] Furthermore, considering the attenuation of light in the light-shielding layer 210, the transmittance T'1 of the light incident on the light-shielding layer 210 can be expressed by the following formula (2) using a layer thickness d and an absorption coefficient α of the light-shielding layer 210. In formula (2), e is the base of the natural logarithm. T'1=(1−R0)e−αd

[0190] The reflectances R0 and R1 at the interface between the wafer 200 and the light-shielding layer 210 and at the interface between the light-shielding layer 210 and the workpiece film 110 are expressed by the following formulas (3) and (4), respectively: R0=(n1−n0n1+n0)2 R1=T1'⋅(n2−n1n2+n1)2

[0191] From the above, when the absorption coefficient α of the light-shielding layer 210 is α=4πk1 / λ using a wavelength λ of light, the transmittance T2 in the light-shielding layer 210 for the light incident on the workpiece film 110 can be expressed by the following formula (5): T2=T1'−R1={1−(n1−n0n1+n0)2}{1−(n2−n1n2+n1)2}e−4πk1dλ λ: WAVELENGTH d: THICKNESS OF THE LIGHT-SHIELDING LAYER n i : REFRACTORY INDEX OF THE LIGHT-SHIELDING LAYER OR OF THE LAYER LOCATED ON OR UNDER THE LIGHT-SHIELDING LAYER k1: Extinction coefficient of the light-shielding layer

[0192] As described above, the transmittance T2 of light in the light-shielding layer 210 depends on the values ​​of the physical properties of the light-shielding layer 210, such as the absorption coefficient α and the extinction coefficient k1, and the layer thickness. In the configuration according to the embodiment, the light-shielding layer 210 having such physical properties and such a layer thickness that the transmittance T2 in the light-shielding layer 210 is less than 20%, preferably less than 10%, can be used. In this case, the light from the wafer 200 and the workpiece film 110 is incident on the light-shielding layer 210 and returns through the light-shielding layer 210, so that the intensity of the light returning to the sensor head 235 is attenuated to less than 4%. Therefore, it can be said that the light from the workpiece film 110 is sufficiently shielded by such a light-shielding layer 210.

[0193] For example, in a case where the light-shielding layer 210 is a CVD carbon film and the light-shielding layer 210 with a film thickness of 400 nm is irradiated with light having a wavelength of 1,310 nm, the transmittance T2 of the light-shielding layer 210 is 7.0247%. Furthermore, in a case where light having a wavelength of 1,310 nm is irradiated, the light-shielding layer 210 may have a dimension of 100 nm and a pitch of 150 nm in plan view.

[0194] In a state where the light-shielding layer 210 selected as described above shields the influence of light on the workpiece film 110 side, the temperature of the wafer 200 can be calculated by measuring using the interference light during plasma processing. As described above, the optical path length of the wafer 200 is expressed as the product of a refractive index of silicon or the like constituting the wafer 200 and a thickness of the wafer 200, and both the refractive index and the thickness are expressed as a function of the temperature of the wafer 200.

[0195] Fig. are schematic diagrams each showing a state of the wafer 200 during plasma processing according to the embodiment. Fig. shows the wafer 200 in a low temperature state, and Fig. shows the wafer 200 in a high temperature state.

[0196] As in Fig. As shown, the temperature of wafer 200 gradually rises during plasma processing, and wafer 200 expands accordingly. As a result, the thickness of wafer 200 and the distance the light transmitted through wafer 200 and reflected from the front surface of wafer 200 travels within wafer 200 change between the low-temperature state and the high-temperature state.

[0197] When measured using the interference light, such a difference is detected as a difference in the optical path length corresponding to the temperature of the wafer 200. Since the material and the original thickness of the wafer 200 are known, it is possible to detect a temperature change of the wafer 200 during plasma processing based on a change in the optical path length of the wafer 200 by adding a change in the refractive index corresponding to the temperature change to the thermal expansion coefficient of the wafer 200.

[0198] To maintain the temperature of the wafer 200 exposed to the high-temperature plasma during etching of the workpiece film 110, the coolant controlled to a predetermined temperature by the cooler 82 is circulated in the coolant flow path 25 of the electrostatic chuck 220. Furthermore, a high thermal conductivity gas, such as He gas, controlled to a predetermined temperature by heat exchange with the coolant is supplied from the gas supply source CY to the back surface of the wafer 200 placed on the electrostatic chuck 220 via the MFC 83, the tank 85, and the openings 28g of the gas flow path 28. In this way, the temperature of the wafer 200 is controlled to a desired temperature.

[0199] However, as described above, the temperature of wafer 200 gradually rises as plasma processing progresses due to the heat of the plasma. The controller 250 of plasma processing device 2 increases the gas pressure to be supplied to the backside of wafer 200, for example, based on the temperature of wafer 200 measured as described above.

[0200] Specifically, the controller 250 increases the flow rate of the gas flowing into the tank 85 through the MFC 83 to increase the pressure in the tank 85. As a result, the pressure of the gas supplied to the back side of the wafer 200 increases, so that the temperature of the wafer 200 can be lowered.

[0201] By controlling the temperature of the wafer 200 by the electrostatic chuck 220 or the like based on the temperature measurement result as described above, it is easy to suppress an increase in the temperature of the wafer 200 during plasma processing and to keep the temperature of the wafer 200 substantially constant.

[0202] Then, the etching on the workpiece film 110 by the plasma processing apparatus 2 according to the embodiment ends.

[0203] Thereafter, by repeatedly forming various films, etching, and other processing, for example, a semiconductor device similar to that of the first example described above is manufactured. (Example of plasma processing)

[0204] Next, with reference to Fig. An example in which the wafer 200 is processed using the plasma processing apparatus 2 according to the embodiment will be described.

[0205] Fig. is a flowchart illustrating an example of procedures for plasma processing the wafer 200 according to the embodiment. The flowchart of Fig. represents procedures from inputting a batch to processing the input batch of wafers 200 by the plasma processing device 2.

[0206] As in Fig. As shown, wafers 200 for a batch including a predetermined number of wafers 200 are input into the manufacturing process (step S201).

[0207] A plurality of light-shielding layers 210 periodically arranged at predetermined intervals are formed on the front surface of each of the wafers 200 for one batch (step S202).

[0208] Furthermore, a workpiece film 110 is formed on each of the wafers 200, in which a plurality of insulating layers NL and a plurality of insulating layers OL are alternately stacked one on top of the other (step S203). Thus, the plurality of light-shielding layers 210 formed on the front surface of the wafer 200 are covered by the workpiece film 110.

[0209] Further, a CVD carbon layer 120 is formed on the workpiece film 110 (step S204), a silicon oxynitride layer 130 is formed on the CVD carbon layer 120 (step S205), and further, a resist pattern 140p is formed on the silicon oxynitride layer 130 (step S206).

[0210] For each wafer 100, etching is performed on the silicon oxynitride layer 130 using the resist pattern 140p as a mask (step S207), and etching is performed on the CVD carbon layer 120 using the silicon oxynitride layer 130, onto which the resist pattern 140p has been transferred, as a mask (step S208). As a result, a mask pattern 120p is formed by transferring the pattern to the CVD carbon layer 120.

[0211] For each wafer 100, etching is performed on the workpiece film 110 exposed by the mask pattern 120p. During plasma processing, the controller 250 irradiates the backside of the wafer 200 with light, monitors a temperature of the wafer 200 in the plasma (step S209), and determines whether the temperature of the wafer 200 is changing (step S210).

[0212] If the temperature of the wafer 200 has been changed (step S210: Yes), the controller 250 changes, for example, a pressure at which a gas such as He gas is supplied to the electrostatic chuck 220 so that the wafer 200 is maintained at a desired temperature (step S211). If the wafer 200 is maintained at the desired temperature (step S210: No), the control of step S211 is not performed, and the pressure at which the gas is supplied to the electrostatic chuck 220 remains unchanged.

[0213] Furthermore, the controller 250 continues etching (step S209) until a timing to stop etching the workpiece film 110 is reached (step S212: No). When the timing to stop etching is reached (step S212: Yes), the power supply to the chamber 11 is stopped.

[0214] Then, the plasma processing on the wafer 200 according to the embodiment ends. (Overview)

[0215] When etching on the workpiece film using plasma processing equipment, if the wafer temperature changes due to exposure to high-temperature plasma, the etching rate and processed shape of the workpiece film will also change. Therefore, for example, the temperature of the electrostatic chuck is monitored during plasma processing, and the wafer temperature is controlled. However, there is a difference of 10°C or more between the temperature of the electrostatic chuck and the actual wafer temperature, making it difficult to control the temperature with sufficiently high accuracy.

[0216] Therefore, for example, a method for simulating the temperature change of a wafer during plasma processing using a temperature measurement wafer can be applied. When an actual wafer is processed, the wafer temperature is controlled based on a temperature measurement result obtained in advance. However, the temperature measurement wafer is 1.2 mm to 1.4 mm thicker than the actual wafer due to its structure, and the measurement value obtained by the temperature measurement wafer cannot be said to be sufficiently accurate. Furthermore, in recent years, an etching method at a low temperature of less than -10°C can be used, and an existing temperature measurement wafer has the disadvantage that temperature measurement cannot be performed at a low temperature of less than -10°C.

[0217] Therefore, in recent years, a technique for estimating a wafer temperature by observing interference between reflected beams, such as laser beams emitted onto the wafer, has been studied, utilizing a phenomenon in which the wafer's optical path length changes depending on the wafer's temperature. However, in a wafer on which a thick workpiece film having a layered structure is formed, the observation of the wafer's optical path length is affected by a change in the film thickness of the workpiece film. And when etching is performed on such a workpiece film to form a predetermined shape of the workpiece film, the observed wafer's optical path length also varies depending on the machined shape. As described above, even with a measurement method that uses interference light, it may be difficult to accurately estimate a wafer's temperature.

[0218] In the method for manufacturing the semiconductor device according to the embodiment, a back surface of the wafer 200 is irradiated with light while the workpiece film 110 is etched, interference light 239sb is observed, the interference light 239sb being generated by interference between reflected light 238s reflected by the back surface of the wafer 200 and reflected light 238b transmitted through the wafer 200 and reflected by bottom surfaces of the plurality of light-shielding layers 210, and a temperature of the wafer 200 is calculated based on the interference light 239sb during the etching processing.

[0219] By forming the plurality of light-shielding layers 210 that shield light having a predetermined wavelength on the front side of the wafer 200 at predetermined intervals as described above, it is possible to shield the influence of light on the workpiece film 110 side and to precisely measure the temperature of the wafer 200.

[0220] Furthermore, by measuring the temperature using light interference, temperature information regarding the wafer 200 can be obtained with high accuracy. Furthermore, the measurement can be performed at a low temperature, for example, less than -10°C, and thus the temperature of the wafer 200 can be measured without temperature constraints.

[0221] In the method for manufacturing the semiconductor device according to the embodiment, a temperature change of the wafer 200 during plasma processing is monitored based on the interference light 239sb between the light 238s reflected by the back surface of the wafer 200 and the light 238b reflected by the bottom surfaces of the plurality of light-shielding layers 210, and the temperature of the wafer 200 is adjusted so that the wafer 200 is maintained at a predetermined temperature.

[0222] As a result, the temperature of the wafer 200 can be kept substantially constant during plasma processing, a deviation in the etching rate of the workpiece film 110 can be suppressed, and a desired processed shape can be obtained.

[0223] In the method for manufacturing the semiconductor device according to the embodiment, the plurality of light-shielding layers 210 are formed on the front surface of the wafer 200 at intervals smaller than a wavelength of the light with which the wafer 200 is irradiated.

[0224] As described above, the plurality of light-shielding layers 210 are formed, for example, at predetermined intervals instead of covering the entire surface of the wafer 200 to suppress film peeling of the workpiece film 110. In this case, too, light is prevented from passing between the plurality of light-shielding layers 210 by setting the intervals between the plurality of light-shielding layers 210 smaller than the wavelength of the light. Therefore, it is possible to suppress light from the wafer 200 entering the workpiece film 110 and light from the workpiece film 110 entering the wafer 200.

[0225] In the method for manufacturing the semiconductor device according to the embodiment, a transmittance T2 represented by the above formula (5), which is a transmittance of light in the plurality of light-shielding layers 210, is less than 20%, and preferably less than 10%. As a result, the influence of light on the workpiece film 110 side is sufficiently shielded, and the temperature of the wafer 200 can be accurately measured.

[0226] In the above-described embodiment, control is performed to keep the temperature of the wafer 200 constant by changing the gas pressure of the He gas or the like supplied to the electrostatic chuck 220 based on the temperature of the wafer 200 obtained using the interference light. However, the temperature of the wafer 200 may be controlled by another method. For example, the temperature of the wafer 200 may be quickly controlled by using a chiller capable of dispersing the coolant and controlling the distributed coolants to a plurality of set values, for example, a dual chiller such as the chiller 82 described above, and appropriately switching the coolants circulating in the electrostatic chuck to coolants with different temperatures.

[0227] In the embodiment described above, the CVD carbon film is used as the light-shielding layer 210. However, as long as the transmittance T2 represented by the above formula (5) can be suppressed to less than 20%, another material may be used as the light-shielding layer.

[0228] Data on some candidate materials are described below.

[0229] Fig. are diagrams illustrating optical characteristics of materials considered as candidates for the light-shielding layer according to a modification of the embodiment. Fig. is a graph that represents a refractive index of any material, with the horizontal axis representing a wavelength of light. Fig. is a graph depicting an extinction coefficient of any material, where the horizontal axis represents a wavelength of light.

[0230] As in Fig. As shown, with respect to light with a wavelength including a wavelength around (1,300±50) nm, which is a measurement wavelength, titanium, titanium nitride, and tungsten all exhibit higher refractive indices and extinction coefficients than carbon, which is a major component of the CVD carbon film. Regarding tungsten nitride, although there is no data at a wavelength of (1,300±50) nm, it is suspected that tungsten nitride has a refractive index and extinction coefficient higher than those of carbon at a measurement wavelength.

[0231] Fig. is a diagram showing a transmittance of a light-shielding layer according to a modification of the embodiment. In particular, Fig. a transmittance T2 of the light-shielding layer of each candidate material obtained from the above formula (5) in a case where the light-shielding layer is formed on the front surface of the wafer using the above candidate material. Here, similar to the above-described light-shielding layer 210 using the CVD carbon film as discussed above, each light-shielding layer with a film thickness of 400 nm is irradiated with light having a wavelength of 1310 nm.

[0232] As in Fig. As shown, the transmittance T2 of the light-shielding layer using carbon is 7.0247% as described above. In addition, the transmittances T2 of the light-shielding layers using titanium, titanium nitride, tungsten, and tungsten nitride are each 0.0009%, 1.89×10 -6 %, 7.18×10 -5 % and 5.25×10 -5%. However, the transmittance T2 of the light-shielding layer using tungsten nitride remains as a reference value.

[0233] As described above, the light-shielding layers using titanium, titanium nitride, tungsten and tungsten nitride also satisfy the condition T2<20% for transmittance, and it is believed that the light-shielding effect can be sufficiently obtained from them.

[0234] Examples of materials other than those mentioned above that satisfy the transmittance condition T2<20% include metal-based materials that do not transmit infrared light, such as molybdenum, copper, tungsten silicide, aluminum, gold, and silver.

[0235] In addition, in the light-shielding layer using any of the materials described above, it is desirable to remove the light-shielding layers exposed from the bottom surfaces of the through-holes 111 by etching after the through-holes 111 are formed. However, in a case where the light-shielding layers are conductive, the light-shielding layers do not need to be removed. [Additional Notes]

[0236] Supplementary comments on preferred aspects of the present invention are provided below. (Note 1)

[0237] According to a preferred aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method comprising: Preparing a substrate, the substrate including: a workpiece film; and a mask pattern formed on the workpiece film, the mask pattern including a light-shielding layer that shields light; and Etching the workpiece film exposed by the mask structure, wherein the etching of the workpiece film includes: irradiating a back side of the substrate with light in advance; observing first interference light generated by interference between first reflected light reflected by the back surface of the substrate and second reflected light transmitted through the substrate and reflected by a bottom surface of the workpiece film; observing second interference light generated by interference between the first reflected light and the third reflected light transmitted and reflected by the substrate and the workpiece film without being transmitted through a top surface of the workpiece film; Calculating a thickness of the workpiece film based on the first interference light and the second interference light; and Performing the etching under an etching condition based on the thickness of the workpiece film calculated from the first interference light and the second interference light. (Note 2)

[0238] In the method for manufacturing a semiconductor device according to Note 1, wherein the mask structure contains at least one of carbon, titanium, tungsten or nitrides thereof as a main component, and when etching the workpiece film, the thickness of the workpiece film is calculated using the third reflected light, wherein the third reflected light is reflected light transmitted through the substrate and the workpiece film and reflected by a bottom surface of the light-shielding layer. (Note 3)

[0239] In the method for manufacturing a semiconductor device according to Note 1 or Note 2, wherein the workpiece film is a film in which a plurality of first insulating layers and a plurality of second insulating layers are alternately stacked one upon another. (Note 4)

[0240] In the method for manufacturing a semiconductor device according to Note 3, wherein the plurality of first insulating layers included in the workpiece film is 50 or more layers. (Note 5)

[0241] In the method of manufacturing a semiconductor device according to any one of Notes 1 to 4, the method further comprising: Irradiating the back side of the substrate with the light before the workpiece film is formed, and observing third interference light generated by interference between fourth reflected light reflected by the back side of the substrate and fifth reflected light transmitted and reflected by the substrate without being transmitted through a front side of the substrate, wherein, in etching the workpiece film, the thickness of the workpiece film is calculated based on the third interference light in addition to the first interference light and the second interference light. (Note 6)

[0242] According to another preferred aspect of the present invention, there is provided a film thickness measuring method, the method comprising: Preparing a substrate on which a workpiece film is formed; irradiating a back side of the substrate with light; observing first interference light generated by interference between first reflected light reflected by the back surface of the substrate and second reflected light transmitted through the substrate and reflected by a bottom surface of the workpiece film; observing second interference light generated by interference between the first reflected light and the third reflected light transmitted and reflected by the substrate and the workpiece film without being transmitted through a top surface of the workpiece film; and Calculating a thickness of the workpiece film based on the first interference light and the second interference light. (Note 7)

[0243] In the film thickness measuring method according to Note 6, the method further comprising: Forming a structure in a light-shielding layer that shields the light irradiating the substrate, wherein the thickness of the workpiece film is calculated using the third reflected light, the third reflected light being reflected light transmitted through the substrate and the workpiece film and reflected by a bottom surface of the light-shielding layer. (Note 8)

[0244] In the film thickness measurement method according to Note 6 or Note 7, where the workpiece film is a film in which a plurality of first insulating layers and a plurality of second insulating layers are alternately stacked one upon another. (Note 9)

[0245] In the film thickness measurement method according to Note 8, where the plurality of first insulating layers included in the workpiece film is 50 or more layers. (Note 10)

[0246] In the film thickness measuring method according to any one of notes 6 to 9, the method further comprising: Irradiating the back side of the substrate with the light before the workpiece film is formed, and observing third interference light generated by interference between fourth reflected light reflected by the back side of the substrate and fifth reflected light transmitted and reflected by the substrate without being transmitted through a front side of the substrate, wherein the thickness of the workpiece film is calculated based on the third interference light in addition to the first interference light and the second interference light.

[0247] Various embodiments are according to the following numbered clauses.

[0248] Clause 1. A method of manufacturing a semiconductor device, the method comprising: Producing a substrate (200), wherein the substrate (200) includes: a plurality of light-shielding layers (210) arranged at predetermined intervals to shield light having a predetermined wavelength; a workpiece film (110) disposed on the plurality of light-shielding layers (210) and including a plurality of first insulating layers (NL) and a plurality of second insulating layers (OL) alternately stacked one upon another; and a mask structure (120p) located on the workpiece film (110) and having a plurality of openings; and Etching the workpiece film (110) exposed by the plurality of openings, wherein etching the workpiece film (110) includes: irradiating a back side of the substrate (200) with the light during etching of the workpiece film (110); observing interference light (239sb) generated by interference between first reflected light (238s) reflected by the backside of the substrate (200) and second reflected light (238b) transmitted through the substrate (200) and reflected by undersides of the plurality of light-shielding layers (238b); Calculating a temperature of the substrate (200) during the etching process based on the interference light (239sb); and Regulating the temperature of the substrate (200) during the etching process based on the temperature of the substrate (200) calculated from the interference light (239sb).

[0249] Clause 2. A method of manufacturing a semiconductor device according to Clause 1, wherein when etching the workpiece film (110), a temperature change of the substrate (200) during the etching process is monitored on the basis of the interference light (239sb), and the temperature of the substrate (200) is adjusted so that the substrate (200) is kept at a predetermined temperature.

[0250] Clause 3. A method of manufacturing a semiconductor device according to Clause 1 or 2, wherein the plurality of light-shielding layers (210) are formed on a front surface of the substrate (200) at intervals each smaller than the wavelength of the light irradiating the substrate (200).

[0251] Clause 4. A method of manufacturing a semiconductor device according to any one of clauses 1 to 3, wherein a transmittance T of light in the plurality of light-shielding layers (210) is represented by the following formula: T={1−(n1−n0n1+n0)2}{1−(n2−n1n2+n1)2}e−4πk1dλ λ: WAVELENGTH d: THICKNESS OF THE LIGHT-SHIELDING LAYER n i : REFRACTORY INDEX OF THE LIGHT-SHIELDING LAYER OR OF THE LAYER LOCATED ON OR UNDER THE LIGHT-SHIELDING LAYER k1: EXTINCTION COEFFICIENT OF THE LIGHT-SHIELDING LAYER and the transmittance T is less than 20%.

[0252] Clause 5. A method of manufacturing a semiconductor device according to any one of clauses 1 to 4, wherein the plurality of light-shielding layers (210) contains at least one of carbon, titanium, tungsten and nitrides thereof as a main component.

[0253] Clause 6. Temperature measurement method, including: Preparing a substrate (200), wherein a plurality of light-shielding layers (210) that shield light having a predetermined wavelength are formed on a front surface of the substrate (200) at predetermined intervals, wherein a workpiece film (110) is formed by alternately stacking a plurality of first insulating layers (NL) and a plurality of second insulating layers (OL) on the plurality of light-shielding layers (210), and wherein a mask pattern (120p) is formed on the workpiece film (110) and has a plurality of openings; irradiating a back side of the substrate (200) with the light while etching the workpiece film (110) exposed by the plurality of openings; observing interference light (239sb) generated by interference between first reflected light (238s) reflected by the backside of the substrate (200) and second reflected light (238b) transmitted through the substrate (200) and reflected by undersides of the plurality of light-shielding layers (210); and Calculating a temperature of the substrate (200) during the etching process based on the interference light (239sb).

[0254] Clause 7. Temperature measurement method according to Clause 6, where while the measurement of the temperature of the substrate (200) is carried out, a temperature change of the substrate (200) during the etching processing is monitored based on the interference light (239sb), and the substrate (200) is maintained at a predetermined temperature.

[0255] Clause 8. Temperature measurement method according to Clause 6 or 7, where the plurality of light-shielding layers (210) are formed on the front side of the substrate (200) at intervals each smaller than the wavelength of the light irradiating the substrate (200).

[0256] Clause 9. Temperature measurement method according to any of Clauses 6 to 8, where a transmittance T of light in the plurality of light-shielding layers (210) is represented by the following formula: T={1−(n1−n0n1+n0)2}{1−(n2−n1n2+n1)2}e−4πk1dλ λ: WAVELENGTH d: THICKNESS OF THE LIGHT-SHIELDING LAYER n i : REFRACTORY INDEX OF THE LIGHT-SHIELDING LAYER OR OF THE LAYER LOCATED ON OR UNDER THE LIGHT-SHIELDING LAYER k1: EXTINCTION COEFFICIENT OF THE LIGHT-SHIELDING LAYER and the transmittance T is less than 20%.

[0257] Clause 10. Temperature measurement method according to Clause 9, where the plurality of light-shielding layers (210) contains at least one of carbon, titanium, tungsten, or nitrides thereof as a main component.

[0258] Clause 11. Temperature measuring substrate comprising: a substrate (200) having a front surface on which a plurality of light-shielding layers (210) shielding light having a predetermined wavelength are arranged at predetermined intervals; and a workpiece film (110) disposed above the substrate (200) and formed by alternately stacking a plurality of first insulating layers (NL) and a plurality of second insulating layers (OL).

[0259] Clause 12. Temperature measuring substrate according to Clause 11, further comprising: a mask structure (120p) arranged on the workpiece film (110) and having a plurality of openings.

[0260] Clause 13. Temperature measuring substrate according to Clause 11 or 12, where the plurality of light-shielding layers (210) contains at least one of carbon, titanium, tungsten and nitrides thereof as a main component.

Claims

[1] A method of manufacturing a semiconductor device, the method comprising: Producing a substrate (200), wherein the substrate (200) includes: a plurality of light-shielding layers (210) arranged at predetermined intervals to shield light having a predetermined wavelength; a workpiece film (110) disposed on the plurality of light-shielding layers (210) and including a plurality of first insulating layers (NL) and a plurality of second insulating layers (OL) alternately stacked one upon another; and a mask structure (120p) located on the workpiece film (110) and having a plurality of openings; and Etching the workpiece film (110) exposed by the plurality of openings, wherein etching the workpiece film (110) includes: irradiating a back side of the substrate (200) with the light during etching of the workpiece film (110); observing interference light (239sb) generated by interference between first reflected light (238s) reflected by the backside of the substrate (200) and second reflected light (238b) transmitted through the substrate (200) and reflected by undersides of the plurality of light-shielding layers (238b); Calculating a temperature of the substrate (200) during the etching process based on the interference light (239sb); and Regulating the temperature of the substrate (200) during the etching process based on the temperature of the substrate (200) calculated from the interference light (239sb). [2] A method for manufacturing a semiconductor device according to claim 1, wherein, in etching the workpiece film (110), a temperature change of the substrate (200) during the etching process is monitored based on the interference light (239sb), and the temperature of the substrate (200) is adjusted so that the substrate (200) is maintained at a predetermined temperature. [3] A method of manufacturing a semiconductor device according to claim 1 or 2, wherein the plurality of light-shielding layers (210) are formed on a front surface of the substrate (200) at intervals each smaller than the wavelength of the light irradiating the substrate (200). [4] A method of manufacturing a semiconductor device according to any one of the preceding claims, wherein a transmittance T of light in the plurality of light-shielding layers (210) is represented by the following formula: T={1−(n1−n0n1+n0)2}{1−(n2−n1n2+n1)2}e−4πkdλ λ: WAVELENGTH d: THICKNESS OF THE LIGHT-SHIELDING LAYER n i : REFRACTORY INDEX OF THE LIGHT-SHIELDING LAYER OR OF THE LAYER LOCATED ON OR UNDER THE LIGHT-SHIELDING LAYER k1: extinction coefficient of the light-shielding layer and the transmittance T is less than 20%. [5] A method of manufacturing a semiconductor device according to any one of the preceding claims, wherein the plurality of light-shielding layers (210) contains at least one of carbon, titanium, tungsten and nitrides thereof as a main component. [6] Temperature measurement methods, including: Preparing a substrate (200), wherein a plurality of light-shielding layers (210) that shield light having a predetermined wavelength are formed on a front surface of the substrate (200) at predetermined intervals, wherein a workpiece film (110) is formed by alternately stacking a plurality of first insulating layers (NL) and a plurality of second insulating layers (OL) on the plurality of light-shielding layers (210), and wherein a mask pattern (120p) is formed on the workpiece film (110) and has a plurality of openings; irradiating a back side of the substrate (200) with the light while etching the workpiece film (110) exposed by the plurality of openings; observing interference light (239sb) generated by interference between first reflected light (238s) reflected by the backside of the substrate (200) and second reflected light (238b) transmitted through the substrate (200) and reflected by undersides of the plurality of light-shielding layers (210); and Calculating a temperature of the substrate (200) during the etching processing based on the interference light (239sb). [7] The temperature measuring method according to claim 6, wherein while the measurement of the temperature of the substrate (200) is performed, a temperature change of the substrate (200) during the etching processing is monitored based on the interference light (239sb), and the substrate (200) is maintained at a predetermined temperature. [8] The temperature measuring method according to claim 6 or 7, wherein the plurality of light-shielding layers (210) are formed on the front surface of the substrate (200) at intervals each smaller than the wavelength of the light irradiating the substrate (200). [9] A temperature measuring method according to any one of claims 6 to 8, wherein a transmittance T of the light in the plurality of light-shielding layers (210) is represented by the following formula: T={1−(n1−n0n1+n0)2}{1−(n2−n1n2+n1)2}e−4πkdλ λ: WAVELENGTH d: THICKNESS OF THE LIGHT-SHIELDING LAYER n i : REFRACTORY INDEX OF THE LIGHT-SHIELDING LAYER OR OF THE LAYER LOCATED ON OR UNDER THE LIGHT-SHIELDING LAYER k1: extinction coefficient of the light-shielding layer and the transmittance T is less than 20%. [10] The temperature measuring method according to claim 9, wherein the plurality of light-shielding layers (210) contains at least one of carbon, titanium, tungsten, or nitrides thereof as a main component. [11] Temperature measuring substrate, comprising: a substrate (200) having a front surface on which a plurality of light-shielding layers (210) shielding light having a predetermined wavelength are arranged at predetermined intervals; and a workpiece film (110) disposed above the substrate (200) and formed by alternately stacking a plurality of first insulating layers (NL) and a plurality of second insulating layers (OL). [12] The temperature measuring substrate of claim 11, further comprising: a mask structure (120p) arranged on the workpiece film (110) and having a plurality of openings. [13] Temperature measuring substrate according to claim 11 or 12, wherein the plurality of light-shielding layers (210) contains at least one of carbon, titanium, tungsten and nitrides thereof as a main component.

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