ADAPTIVE GATE CURRENT CONTROL

Abstract

A method for driving a transistor is described here. According to one embodiment, the method includes modulating an output voltage by cyclically switching a transistor on and off, wherein a gate current having a first current level is supplied to the transistor in each switching cycle to turn the transistor on. The method further includes determining a characteristic time parameter of the output voltage (e.g., a rise or delay time) and determining an error representing the difference between the determined time parameter and a target time in each switching cycle; adjusting the first current level based on the error; and detecting an oscillation of the error. If an oscillation is detected, the adjustment of the first current level is paused until the magnitude of the error exceeds a threshold in a second number of consecutive switching cycles.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of gate current control for driving metal-oxide-semiconductor (MOS) transistors, which may be used, for example, in motor control applications. BACKGROUND

[0002] In various applications, gate driver circuits are used in conjunction with MOS transistors to switch electrical loads on and off. Gate driver circuits are particularly used to control the switching process of power transistors (e.g., MOS field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs)). For example, the duration of a switching process (e.g., the slew rate (rise and fall times) and delay times) can be controlled by controlling the gate current applied to the gate electrode of a power transistor. In many applications, a defined slew rate is an important design parameter because the slew rate is related to electromagnetic interference (EMI) and is thus relevant to the electromagnetic compatibility (EMC) of an electronic product.Examples of applications where gate driver circuits are used to control the switching process of power transistors include switching power supplies, active power factor correction (PFC) circuits, power converters, motor controllers, etc.

[0003] For example, integrated circuits (ICs) for driving multiple transistor half-bridges used to control the operation of electric motors (e.g., brushless DC motors) are commercially available. Such motor control ICs can implement adaptive algorithms to control the on / off delay times or the rise / fall times (or both) of the connected power transistors. Control loops can be implemented either within the motor control IC or via a microcontroller connected to the motor control IC. Typically, the transistors are cyclically turned on and off according to a specific switching scheme, such as pulse-width modulation (PWM).

[0004] The aforementioned adaptive control algorithms tend to cause oscillations (switching back and forth) between two consecutive control steps, which can increase or worsen the product's EMI and EMC performance. This can be particularly problematic in motor control applications. However, it should be understood that this problem is not limited to motor control applications and can occur in any application where currents are switched through power transistors.

[0005] The inventors have set themselves the goal of improving existing concepts for controlling the switching process of power transistors, particularly with regard to the problem described above. OVERVIEW

[0006] The above-mentioned object is achieved by the method of claims 1 and 8 and the circuit of claim 12. Various embodiments and further developments are covered by the dependent claims. Accordingly, a method for driving a transistor is described herein. In one embodiment, the method includes modulating an output voltage by cyclically switching the transistor on and off. In each switching cycle, a gate current having a first current level is supplied to the transistor to turn the transistor on. The method further includes determining a characteristic time parameter of the output voltage (e.g., a rise time or a delay time), determining an error representing the difference between the determined time parameter and a target time in each switching cycle, and adjusting the first current level based on the determined error.Furthermore, if the error changes sign in a first number of consecutive switching cycles, the method includes pausing the adjustment of the first current level until the error exceeds a threshold in a second number of consecutive switching cycles.

[0007] According to another embodiment, the method includes modulating an output voltage by cyclically switching a transistor on and off, wherein a gate current having a first current level is supplied to the transistor in each switching cycle to turn the transistor on. The method further includes determining a characteristic time parameter of the output voltage (e.g., a rise time or a delay time) and determining an error representing the difference between the determined rise time and a target time in each switching cycle; adjusting the first current level based on the error; and detecting an oscillation of the error. If an oscillation is detected, the adjustment of the first current level is paused until the magnitude of the error exceeds a threshold in a second number of consecutive switching cycles.

[0008] Another embodiment relates to a circuit for driving at least one transistor coupled to an output node. Accordingly, the circuit includes a control circuit configured to modulate an output voltage at the output node by cyclically switching the transistor on and off; a timing circuit configured to measure a characteristic timing parameter of the output voltage (e.g., a rise time or a delay time) in each switching cycle; and a gate driver configured to supply a gate current having a first current level to the transistor in each switching cycle to turn the transistor on, wherein the first current level is adjusted according to a command variable received from the control circuit.The control circuit is further configured to: determine an error in each switching cycle that represents the difference between the determined rise time and a target time; adjust the command variable for the first current level based on the error; and, if the error changes sign in a first number of consecutive switching cycles, pause the adjustment of the command variable until the error exceeds a threshold in a second number of consecutive switching cycles. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The invention can be better understood with reference to the following drawings and descriptions. The components in the figures are not necessarily to scale; instead, the emphasis is placed upon illustrating the principles of the invention. Furthermore, like reference numerals designate corresponding parts throughout the figures. Regarding the drawings: Fig. 1 shows a general example of a circuit for controlling an electric motor. Fig. Figure 2 contains exemplary timing diagrams illustrating the gate current of a high-side transistor of a transistor half-bridge during a turn-on process, the corresponding gate-source voltage, and the corresponding output voltage (phase voltage) of the transistor half-bridge. Fig. 3 shows an exemplary implementation of the circuit of Fig. 1. Fig. 4 is a flowchart showing an example of the control algorithm implemented by the circuit of Fig. 3 can be implemented. Fig. 5 shows an extension / improvement of the procedure of Fig. 4. DETAILED DESCRIPTION

[0010] In the following detailed description, reference is made to the accompanying drawings. The drawings form a part of the description and, for illustrative purposes, show examples of how the embodiments may be used and implemented. It is understood that the features of the various embodiments described herein may be combined with one another unless expressly stated otherwise. Furthermore, it is understood that although the described embodiments relate to the control of electric motors, the embodiments are not limited to motor control applications. The concepts described herein can be easily generalized and used in other applications.

[0011] As mentioned above, integrated circuits for controlling power stages with one or more transistors (or transistor half-bridges) may be prone to oscillations when control loops are used, for example, to control the switching times of the transistors.

[0012] In current motor control systems, switching times can be controlled using digital control loops. Limit cycles can occur, especially when a digital control loop is used. However, limit cycles and other instabilities can also occur in analog solutions. To improve the stability of the overall system, more sophisticated control algorithms can be used, and the resolution can be increased to reduce the LSB current, i.e., the current Δi corresponding to the least significant bit (LSB) of a digital reference value. However, known approaches do not eliminate the aforementioned oscillations and the associated electromagnetic interference.

[0013] Fig. 1 shows a general example of a circuit for controlling an electric motor M. It should be noted that in Fig. 1 only one half-bridge (consisting of the high-side transistor T1 and the low-side transistor T2) is shown to keep the illustration simple. It should be understood that, depending on the motor type, two or more half-bridges may be required to properly operate an electric motor. For example, controlling three-phase brushless DC (BLDC) motors may require three or six transistor half-bridges. In some applications, only one transistor per half-bridge is needed, with the other transistor being replaced by a diode. In other applications, such as a switching converter, only a single transistor or a single transistor half-bridge may be used.

[0014] In the example shown, the high-side transistor T1 is connected between a first supply node, at which the supply voltage V Sis applied, and an output node, while the low-side transistor T2 is connected between the output node and a second supply node, which is at ground potential V during operation GND (or a defined reference voltage). The output node is also called the phase node, and the output voltage Vo at the output node is also called the phase voltage. During operation of the circuit, an electrical load may be connected to the output node. In the example shown, the electrical load is a stator winding of the motor M, and the current supplied to the stator winding is denoted by i M designated.

[0015] In the example shown, transistors T1 and T2 are n-channel MOSFETs. Note that other transistor types can be used. For example, the high-side transistor can also be a p-channel MOSFET. The transistors are turned on and off by charging and discharging their gates, respectively. The gate currents supplied to the gates of transistors T1 and T2 are defined as i G1 or i G2These gate currents are provided by gate drivers 21 and 22, which may include controllable current sources that source or sink the gate currents. If n-channel transistors are used as high-side transistors, a charge pump (or similar circuit) may be required to supply gate driver circuits 21, 22. However, charge pumps and other supply circuits for supplying gate driver circuits are known per se and are therefore not described in detail here and are not shown in the drawings.

[0016] A control circuit 20 generates the input signals for the gate drivers 21 and 22 to adjust the current level of the gate currents and ensure correct timing of the switching processes. The timing of the switching processes can be controlled by a logic signal, which can be modulated to modulate the output voltage according to a specific modulation scheme (e.g., PWM). In the example shown, the control circuit 20 is powered by a supply voltage V DD (e.g. 3.3 V), which differs from the supply voltage V S Furthermore, the control circuit 20 receives the modulated output voltage Vo or a voltage representing the output voltage Vo in order to determine the rise and fall times and / or delay times in each switching cycle.

[0017] In the example of Fig. 1, the control circuit 20 can communicate with a microcontroller via a serial bus 3, such as an SPI (Serial Peripheral Interphase) bus. Furthermore, the microcontroller can output one or more logic signals (such as the enable signal EN) that can be received by the control circuit 20 and that can control one or more functions implemented in the control circuit. The microcontroller 10 can be programmed to configure the control circuit 20 according to the requirements of a particular application, e.g., by sending control parameters to the control circuit 20 via the serial bus 3. These control parameters can include, for example, a PWM switching frequency, target rise / fall / delay times T TARGET the output voltage V OUT , include delay times to prevent cross-conduction in the transistor half-bridge or the like.

[0018] The control circuit 20 may include one or more logic circuits configured to perform the functions described herein. The one or more logic circuits may include hard-wired logic circuits, programmable (e.g., one-time programmable, OTP) logic circuits, a processor configured to execute software (firmware) stored in a memory, or any combination thereof. Furthermore, the control circuit may include an interface circuit that enables the transmission and reception of data via the serial bus 3. Depending on the application, the control circuit 20 may also include a modulator for generating, for example, pulse-width modulated control signals.

[0019] Fig. 2 contains timing diagrams showing exemplary waveforms of the gate current i G1of the high-side transistor T1 during a turn-on process, the corresponding gate-source voltage V GS1 and the corresponding output voltage V O of the transistor half-bridge. The switching process begins at time t0 upon receipt of a switch-on command, e.g., a rising edge of a pulse-width modulated control signal.

[0020] Before time t0, the gate current i G equal to -i HOLD to keep the transistor in an off state. At time t0, the current level of the gate current i G on i PCHG increased, maintaining the current level until time t1. At time t1, the current level is increased to i CHG and maintained at this level until time t2. The period between t0 and t1 is called the pre-charge phase, and the period between t1 and t2 is called the charge phase. At time t2, the current level is reduced to i CHGDVand maintained at this level until time t3. The period between t2 and t3 is called the Miller Plateau phase. At time t3, the current level is reduced (e.g., gradually) to i POSTCHG and maintained at this level until time t4. The period between t3 and t4 is called the recharge phase. At time t4, the current level is increased to i HOLD reduced to keep the transistor on until an off command triggers the turn-off process.

[0021] As in Fig. 2, the level of the precharge current i PCHG and the charging current i CHG the delay time T DEL (between t0 and t2), and the current level i CHGDV in the Miller Plateau phase determines the rise time T RISE (between t2 and t3). The charging phase ends when the output voltage Vo reaches the level V OLand the rise time ends (approximately) when the output voltage Vo reaches the level V OH Accordingly, the rise time T RISE on the length of the Miller plateau phase (which in turn depends on the current level i CHGDV depends).

[0022] One or more of the current levels i PCHG , i CHG , i POSTCHG and i HOLD and the threshold levels V OL and V OH can be configured by the microcontroller 1 via the serial bus 3. In the embodiments described here, the current level i CHGDV be adjusted to achieve a desired rise time, which is called the target rise time T TARGET and is also a parameter that can be set by the microcontroller 1 via the serial bus 3. Similarly, the current level i CHGadjusted to achieve a desired delay time (target time). Generally speaking, one or more specific predetermined current levels (e.g., i CHG , i CHGDV etc.) are adaptively adjusted to one or more characteristic time parameters of the output voltage Vo (e.g. T DEL , T RISE etc.) so that they correspond to the corresponding target time values.

[0023] Fig. 3 shows an exemplary digital implementation of the circuit of Fig. 1 in more detail. As with the example of Fig. 1, a first (high-side) transistor T1 and a second (low-side) transistor T2 are coupled to an output node. It is understood that one of the transistors can be replaced by a diode. In some applications, one of the transistors can be omitted entirely, so that the first transistor T1 forms a simple high-side switch or the second transistor forms a simple low-side switch. In the latter case, the load is connected between the supply nodes at which the supply voltage V S provided, and the output node.

[0024] In the present example, the control circuit 20 is configured to modulate the output voltage Vo at the output node by cyclically switching the first transistor T1 on and off. The modulator can be implemented in the digital core 201 included in the control circuit 20. Furthermore, the circuit of Fig. 3 a time measuring circuit 202 which is designed to measure a characteristic time parameter of the output voltage Vo (e.g. the rise time T RISE in the present example). The timing circuit 202 can be considered as part of the control circuit 20. In the present example, the timing circuit 202 includes a window comparator configured to compare the output voltage Vo with the threshold voltages V OL =V GND +ΔV and V OH =V S -ΔV, where ΔV is an offset that can be fixed or configurable (e.g., by the microcontroller 1 via the serial bus 3). In this example, the window comparator outputs a pulse whose pulse length is the rise time T RISE indicates (see also Fig. 2, T RISE =t3-t2).

[0025] The circuit of Fig. 3 also contains the gate driver 21 for the transistor T1 (as well as the gate driver 22 for the transistor T2). Each gate driver is designed to supply a gate current (i G1 for transistor T1, i G2 for transistor T2) with a first current level (see Fig. 2, current level i CHGDV ) to the respective transistor to turn it on. In the examples described here, the first current is supplied at least for a certain time (within the switching process), which may correspond to the Miller Plateau phase (see Fig. 2, time interval from t2 to t3). The first level can be a reference variable i received from the control circuit 20 SET1 , i SET2 are equivalent to.

[0026] The control circuit 20 (in particular its digital core 201) is further designed to detect an error T in each switching cycle. E , which is the difference between the determined rise time T RISEand a target time T TARGET represents (T E = T RISE - T TARGET ). The control circuit 20 is further configured to (in each cycle) determine the reference variable i SET1 for the first current level i CHGDV to adjust, whereby the reference variable i SET1 is increased if the error T E is positive and is reduced when the error T E is negative. In addition, the control circuit 20 (e.g., its digital core 201) pauses the adjustment of the reference variable i SET1 , if the error changes its sign in a first number q (e.g. q=3) of consecutive switching cycles until the error T E in a second number p (e.g. p=2) of consecutive switching cycles a threshold value T HYST Pausing the cyclic adjustment of the reference variable i SET1 (and similar i SET2) prevents continuous oscillation of the gate current and can thus improve the EMC behavior. Since the cyclic adjustment of the reference variable i SET1 is only paused when the oscillation (limit cycle) has been detected and is continued when the error T E becomes too high, the EMC behavior can be improved without compromising on precision.

[0027] The criterion for detecting an (unwanted) oscillation is the number q of sign changes. The variable q can be fixed or configurable via serial bus 3. In this example, q is set to 3, although higher values ​​of q can be selected depending on the application requirements. The criterion for resuming (ending the pause) the adjustment of the reference variable i SET1 is that the error T E the threshold T HYSTfor p consecutive cycles. The variable p can be fixed or configurable via serial bus 3. In this example, p is set to 2, although higher values ​​of p can be used to prevent the command variable from continuing to adjust due to brief disturbances. p=1 would also be possible; however, this would increase the risk of the command variable adjustment continuing randomly due to disturbances.

[0028] In the example of Fig. 3, the digital core 201 measures the pulse length T RISE at the output of the timing circuit 202 (ie determines T RISE as a digital value stored in a register), calculates the error T E digital and determines the sign and (if the adjustment is not paused) the sign changes in each switching cycle.

[0029] The control circuit 20 (e.g. the one shown in Fig. 3) may be configured to control the current level i G1 =i CHGDV by increasing or decreasing the current level by a fixed current difference Δi. The gate current level can be adjusted in discrete steps of Δi. That is, in the present example, the current level i G1 =i CHGDV equal to k times Δi, where Δi is a constant and k is an integer (i G1 =i CHGDV = k·Δi). The fixed current difference Δi can correspond to the LSB current of a current output DAC (digital-to-analog converter) included in the gate drivers 21 and 22. The integer variable k can correspond to the current command variables i SET1 and i SET2 , which are provided by the digital core 201 and delivered to the gate drivers 21 and 22, respectively. Increasing and decreasing the current level i CHGDV=k·Δi can thus be calculated by incrementing or decrementing k depending on the determined error T E can be achieved in each PWM cycle.

[0030] The examples discussed here aim at tuning the rise time T RISE of the (switched) output voltage Vo. It is understood that this concept can easily be used to determine other characteristic time parameters of the switched output voltage, such as the delay time T DEL (see Fig. 2) that occurs before the rising edge, a fall time, and a delay time that occurs before the falling edge. These times are characteristic timing parameters of the switched output voltage, which are related to corresponding gate current values ​​applied to the transistor during the switching process.

[0031] The embodiments described here will now be explained using the flow chart of Fig. 4, which illustrates an example of a control algorithm that can be implemented, for example, by the circuit in Fig. 3 can be implemented.

[0032] According to Fig. 4 is a transistor (see e.g. Fig. 3, transistor T1) is cyclically switched on and off to modulate an output voltage Vo. The flow diagram of Fig. 4 represents a cycle starting at box S0. In each switching cycle, transistor T1 is supplied with a gate current i G1 with a first current level i CHGDV =k·Δi to switch it on (see Fig. 4, Box S1). As explained above, the first (gate) current level i CHGDV for a certain time during the switching-on process, e.g. during the Miller plateau phase (cf. Fig. 2), maintained. According to Fig. 4, the method includes determining the rise time T RISE the output voltage Vo (see Fig. 4, Box S2) and determining an error T E = T RISE -T TARGET (see Fig. 4, Box S3), which calculates the difference between the determined rise time T RISE and a target time T TARGET represents, in each switching cycle. The further process depends on whether the cyclic adjustment of the first current level i CHGDV =k·Δi was paused, e.g., by locking the variable k (see Fig. 4, Box S4). Assuming that the cyclic adjustment of the first current level i CHGDV is not paused, the process runs with a check whether the error T E is greater than zero, continue (see Fig. 4, Box S5), where the first current level i CHGDV =k·Δi is increased when the error T E is positive (see Fig. 4, Box S7), and is reduced when the error TE is negative (see Fig. 4, Box S6). If the error T E is exactly zero (which is an unlikely case), the initial current level can remain unchanged. Alternatively, a zero error can be treated as a positive error (or a negative error). Generally speaking, the current level is increased or decreased based on the last determined error value.

[0033] If the error changes its sign in q consecutive switching cycles (see Fig. 4, Box S8), the adjustment of the first current level is paused in the subsequent cycles (see Fig. 4, Box S9) until the error T E in p consecutive switching cycles a threshold value T HYST exceeds (see Fig. 4, Box S10).

[0034] In a specific embodiment, q=3 and the digital core 201 of the control circuit 20 may reset a counter to three if no sign change occurs in a cycle and decrement the counter if a sign change occurs in a cycle, that is, if the current value of T E has a different sign than in the previous cycle. If the counter value reaches zero, the result of box S8 is "yes," and further adjustment of the first current level is paused (box S9). If the counter value is not zero, the result of box S8 is "no," and adjustment in the next cycle is not paused.

[0035] If the cyclic adjustment of the first current level i CHGDVhas already been paused in a previous cycle (result of box S4 is "yes"), the increase / decrease of the first current level is skipped and the process continues in boxes S9 and S10. Accordingly, it is checked whether the absolute value (the magnitude) of the error |T E | in p consecutive cycles a given threshold T HSYT exceeds (see Fig. 4, Box S10). In a specific embodiment, p=2 and the digital core 201 of the control circuit 20 may reset a counter to two when |T E | ≤ T HSYT , and decrement the counter if |T E | > T HSYT If the counter reaches zero, the result of box S10 is “yes” and the adjustment of the first current level i CHGDV =k·Δi is continued in the subsequent cycle(s) (see Fig. 4, Box S11). If the counter is not equal to zero, the result of Box S10 is "no" and the adjustment of the first current level remains paused in the subsequent cycle.

[0036] It is understood that the process steps are not necessarily performed in the order shown. This means that the steps can be rearranged to obtain other embodiments. For example, the check performed in box S8 (checking whether the sign of T Ehas changed in q consecutive cycles) before box S5. Depending on the actual implementation, some process steps may be executed concurrently. Pausing the adjustment may also be implemented in different ways. In a simple implementation, the register storing the variable k may be locked so that k cannot be changed. In this example, the increment / decrement operations would have no effect. In another implementation, the register storing the variable k is not explicitly locked, but the increment / decrement operations are skipped. It is understood that one skilled in the art will be able to implement the same function in different (and substantially equivalent) ways within the scope of this disclosure.

[0037] Fig. 5 shows an extension / improvement of the procedure of Fig. 4. Essentially, the additional steps of Fig. 5 the selection of the more suitable value for k (and thus for the first gate current value i G =i CHGDV =k·Δi), where the value k is either left unchanged (i.e., it is the same as in the previous cycle) or set to the second-to-last value of k. The flowchart of Fig. 8 starts at box S8. If the sign of the error T E has changed in q consecutive cycles, adjusting the first current value i CHGDV =k·Δi is paused (e.g., by locking the variable k). Before the actual pause of the adjustment of the first current level, the first current level i CHGDV (which will be used in the next cycle) is set to an average of the first level in the previous cycles, e.g., i CHGDV =(k[n]+k[n-1])·Δi / 2. In the next cycle, k is calculated based on whether the sign of the error T Echanged again, it is set to either k[n] or k[n-1]. Then the variable k is locked until |T E |>T HYST , as explained above. For example, if the sign of the error T E changes again, the previous value of k can be used (i.e. k[n], which means that k is left unchanged), or, if the sign of the error T E does not change again, the second to last value of k (ie k[n-1]) can be used.

[0038] The above with reference to Fig. The concept explained in Figure 5 corresponds to setting the first current level to an average of the first level in the previous cycles before pausing the adjustment of the first current level, and in the subsequent cycle increasing the first current level (i.e. setting k to the higher value max {k[n], k[n-1]}) when the error T Eis positive, and reducing the first current level if the error is negative (i.e., setting k to the lower value min{k[n], k[n-1]}). It should be understood that one skilled in the art will be able to implement the same function in all sorts of different (and substantially equivalent) ways within the scope of this disclosure.

[0039] Although the invention has been illustrated and described with respect to one or more implementations, changes and / or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular, with regard to the various functions performed by the components or structures (units, assemblies, devices, circuits, systems, etc.) described above, the terms (including a reference to a "means") used to describe such components are intended, unless otherwise specified, to correspond to any component or structure that performs the specified function of the described component (i.e., that is functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the function in the exemplary implementations of the invention illustrated herein.

Claims

[1] Method comprising: Modulating an output voltage (Vo) by cyclically switching a transistor (T1) on and off, wherein a gate current (i G1 ) with a first current level (i CHGDV ) to turn on the transistor (T1); Determining a characteristic time parameter (T RISE , T DEL ) of the output voltage (Vo) and determining an error (T E ), which is the difference between the determined time parameter (T RISE ) and a target time, in each switching cycle; Adjusting the first current level based on the error (T E ); and if the error changes its sign in a first number of consecutive switching cycles, pausing the adjustment of the first current level until the magnitude of the error (T E ) a threshold value (T HYST) in a second number of consecutive switching cycles. [2] Method according to claim 1, wherein the characteristic time parameter is a rise time (T RISE ) or a delay time (T DEL ) of the output voltage (Vo). [3] The method of claim 1 or 2, wherein the first current level is for adjusting the first current level based on the error (T E ) is increased if the error (T E ) is positive and is reduced when the error (T E ) is negative. [4] A method according to any one of claims 1 to 3, wherein the first current level is set to an average of the first level in the previous cycles before pausing the adjustment of the first current level. [5] Method according to one of claims 1 to 3, wherein the first current level is set to an average of the first level in the previous cycles before pausing the adjustment of the first current level; and in which in the subsequent cycle the first current level is increased if the error (T E ) is positive, and the first current level is reduced if the error is negative. [6] A method according to any one of claims 1 to 5, wherein adjusting the first current level includes increasing or decreasing the first level by a fixed current difference (Δi). [7] Method according to one of claims 1 to 6, where the first current level is k times Δi, where Δi is a fixed current difference and k is an integer, and in which the increasing and decreasing of the first level is achieved by incrementing and decrementing k, respectively. [8] Method comprising: Modulating an output voltage (Vo) by cyclically switching a transistor (T1) on and off, wherein a gate current (i G1 ) with a first current level (i CHGDV ) to turn on the transistor (T1); Determining a characteristic time parameter (T RISE , T DEL ) of the output voltage (Vo) and determining an error (T E ), which is the difference between the determined time parameter (T RISE , T DEL ) and a target time (T TARGET ), in each switching cycle; Adjusting the first current level based on the error (T E ); Detecting an oscillation of the error (T E ) and, if an oscillation is detected, pausing the adjustment of the first current level until the magnitude of the error (T E ) in a second number of consecutive switching cycles a threshold value (T HYST) exceeds. [9] Method according to claim 8, wherein the characteristic time parameter is a rise time (T RISE ) or a delay time (T DEL ) of the output voltage (Vo). [10] Method according to claim 8 or 9, wherein detecting an oscillation of the error (T E ) the detection that the error (T E ) changes its sign in a first number of consecutive switching cycles. [11] Method according to one of claims 8 to 10, wherein the adjustment of the first current level is continued when the magnitude of the error (T E ) a threshold value (T HYST ) in a second number of consecutive switching cycles. [12] Circuit that has: a first transistor (T1) connected to an output node, a control circuit configured to modulate an output voltage (Vo) at the output node by cyclically switching the transistor (T1) on and off, a time measuring circuit configured to measure a characteristic time parameter (T RISE , T DEL ) of the output voltage (Vo) in each switching cycle; a gate driver configured to supply a gate current (i G1 ) with a first current level (i CHGDV ) to the transistor (T1) to turn on the transistor (T1), wherein the first current level is set according to a command value received from the control circuit; wherein the control circuit is further configured to: in each switching cycle an error (T E ), which is the difference between the determined time parameter (T RISE , T DEL ) and a target time; the reference variable (i SET1 ) for the first current level based on the error (T E ) and adjusting the reference variable (I SET1 ) until the error (T E ) a threshold value (T HYST ) in a second number of consecutive switching cycles when the error changes its sign in a first number of consecutive switching cycles. [13] A circuit according to claim 12, comprising: wherein the control circuit to adjust the reference variable (i SET1 ) for the first current level, is further designed to adjust the reference variable (I SET1 ) if the error (T E ) is positive, and the reference variable (I SET1 ) when the error (T E ) is negative. [14] System that has: an electric motor; The circuit of claim 12, wherein a stator winding of the motor is connected to the output node of the circuit.

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