System for generating a sinusoidal signal

Abstract

System (100) for generating a sinusoidal signal (90), comprising: an input interface (10) designed to receive a periodic input signal; a variable input path (20) with a path input (21) connected to the input interface (10), a path output (22) and an element (29) electrically connected between path input (21) and path output (22) for forming a square wave signal, wherein the variable input path (20) is configured to output a square wave signal at the path output (22) with the periodicity of the input signal applied to the path input (21); a counter module (30) connected to the path output (22) and designed to count edges of the square wave signal and to output a period and / or a frequency of the square wave signal; a digital signal generation module (40) connected to the counter module (30), which is configured to output a plurality of amplitude values ​​(92) of the sinusoidal signal (90) for a plurality of phase values ​​(91) of the sinusoidal signal (90) based on the period and / or the frequency of the square wave signal.

Description

Subject of the invention

[0001] The present invention relates to a system for generating a sinusoidal signal, in particular for generating a high-quality sinusoidal signal with a low DC component based on a variable input signal. The present invention is advantageously applicable by using such a system to operate a resolver, for example, in the automotive sector for measuring an axle position. Technological background

[0002] In many applications, electrical loads exist that require a drive voltage that is as DC-free as possible for trouble-free operation. Examples of such loads include transducers, such as a resolver for converting the angular position of a rotor into an electrical value, as well as capacitive ultrasonic sensors, such as those used for distance measurement in parking assistance systems.

[0003] Transducers such as the one shown schematically in Fig. The resolvers 200 shown in Figure 6 are typically used in the automotive sector to detect the speed and / or position of a motor axis 204. A resolver 200 has two main components: a stationary stator and a rotor rotating with the axis to be measured. The stator has a stationary primary winding 201, and the rotor has two secondary windings 202, 203 rotating with the axis and perpendicular to each other. Due to the spatial arrangement of the secondary windings 202, 203, the signals induced therein by the primary winding 201 always have a phase difference of 90° to each other, which is why one secondary winding is also referred to as a sine winding 202 and the other as a cosine winding 203.

[0004] If a harmonic, for example, sinusoidal, drive voltage is applied to the primary winding, harmonic, for example, sinusoidal or cosinusoidal voltages are also induced in the secondary coils. Depending on the angular position of the rotating axis, the voltages V induced in the sine and cosine windings vary. S and V K in amplitude and phase. By measuring the induced voltages in both secondary windings, the angular position and speed of the rotating axis can be determined by solving the following system of equations: Vs=A∗sin(ωM∗t+φ0)∗sin(ωext∗t) VK=A∗cos(ωM∗t+φ0)∗sin(ωext∗t)

[0005] Here, A denotes the gain factor of the resolver, ω M denotes the rotation speed of the motor axis, t is the time, φ0 is an initial angular position of the motor axis and ω ext is the excitation frequency of the driving voltage at the primary winding.

[0006] Precise position determination using a resolver requires a harmonic drive voltage at the primary winding with low noise and DC components. Such drive voltages are typically generated by amplifying a periodic input signal. Such an input signal is typically generated using a digital microcontroller, pulse-width modulation, and various low-pass filters. Alternatively, such an input signal can be generated using a lookup table in combination with a digital-to-analog converter and a balanced output stage.

[0007] Each of the above implementations has specific disadvantages. An implementation with a digital microcontroller and pulse width modulation, as in Fig. 7A, depends significantly on the quality of the components used for pulse width modulation, which, like the quality of the low-pass filters used, can vary depending on external factors such as temperature, operating and ground voltages, etc. An implementation using a lookup table and digital-to-analog converter, as in Fig. 7B, is less sensitive to external factors, especially with regard to the analog components used. However, a good signal typically requires a large number of entries in the lookup table and thus a lot of memory.

[0008] PLEVRIDIS, JE - Electrical Engineering Vol. 81 (1998), No. 5, pp. 343-349 “An alternative method of precise frequency measurement by the aid of a DDS.” shows a frequency measurement system that includes a frequency comparator and a direct digital synthesizer (DDS) in a feedback loop, where the DDS generates sinusoidal reference signals that act on an input of the frequency comparator.

[0009] WU, Yi Fei - In: Applied Mechanics and Materials, Vol. 373-375 (2013), pp. 838-843. "A Novel Integrated Angel Measurement System" discloses an integrated angle measurement system for a two-channel resolver. VANKKA, Jouko "Direct Digital Synthesizers: Theory, Design and Applications," Report / Helsinki University of Technology, Department of Electrical and Communications Engineering, Electronic Circuit Design Laboratory, Espoo: Helsinki University of Technology, 2000 - ISBN 9789512252329 is a textbook on direct digital synthesis with common embodiments of direct digital synthesizers and thus represents the technological background for the present invention.

[0010] It is an object of the present invention to provide a system for generating a sinusoidal signal which overcomes or at least reduces the disadvantages of the prior art and enables the generation of a noise-free sinusoidal signal with a low DC component, while at the same time reducing a dependence of the signal generation on external factors and requiring less storage space. Description of the invention

[0011] The object of the invention is achieved by the subject matter of the independent patent claim. Preferred developments are the subject matter of the dependent claims.

[0012] A first aspect of the present disclosure relates to a system for generating a sinusoidal signal, in particular a harmonic signal for providing a symmetrical drive voltage. The system comprises an input interface configured to receive a periodic input signal. The input interface is preferably an interface of a mixed-signal circuit configured to receive an input signal, which is designed, for example, as a metallization (pad). Likewise preferably, the input interface is configured to receive a digital input signal, particularly preferably to receive one of a plurality of digital input signals, wherein the plurality of digital input signals comprises signals with different characteristics.

[0013] The system according to the present disclosure further comprises a variable input path with a path input electrically connected to the input interface and a path output. The variable input path electrically connects the path input to the path output and is configured for signal transmission between the path input and path output. The variable input path is configured, in particular, to output a square-wave signal at the path output with the periodicity of the input signal present at the path input. For this purpose, the variable input path comprises an element electrically connected between the path input and path output for forming a square-wave signal (from the periodic input signal present at the input interface).

[0014] The element for shaping a square-wave signal is preferably a component or circuit for shaping a square-wave signal, which particularly preferably comprises a comparator, a two-point regulator (bang-bang amplifier), an RS flip-flop, a Schmitt trigger, or a window comparator. The specific design of the element for shaping a square-wave signal is preferably based on the type of at least one expected input signal, i.e., the person skilled in the art selects the element(s) most suitable for one or more expected input signals.

[0015] Furthermore, the variable input path preferably comprises further components, in particular an element for signal construction and / or an element for removing DC components, which are designed as part of the circuit for forming a square-wave signal or independently thereof and comprise, for example, (digital) band-pass or high-pass filters for removing DC components, (digital) low-pass filters (n-th order, for example, 2-th order) for signal reconstruction. The further components also preferably comprise resistors or resistor networks, for example, for voltage regulation, as well as capacitors, diodes, etc.

[0016] In other words, the variable input path is configured to process at least one of a plurality of periodic input signals of different characteristics applied to the input interface and always output a square-wave signal. The input signals that can be applied to the input interface are periodic signals, for example, sinusoidal periodic signals. The periodic input signals also preferably include pulse-width-modulated signals, sawtooth signals, CLK signals, rectangular signals (square-wave voltages, rectangular pulses), needle pulses, triangular signals, trapezoidal voltages, staircase voltages, half-cycle signals (half-wave rectified or full-wave rectified signals), etc.The variable input path is designed to output a square-wave signal, particularly preferably a square-wave voltage, with the periodicity of the input signal (in particular the same time interval between local extrema, for example zero crossings or edges) at the path output.

[0017] The variable input path thus advantageously always provides subsequent system components with a similar signal for further processing, which at the same time has the characteristic property of the input signal for further processing, namely its periodicity.

[0018] The system according to the present disclosure further comprises a counter module connected to the path output, which is configured to count edges of the square-wave signal. The counter module is preferably configured to count consecutive and / or positive edges of the square-wave signal. The counter module is further configured to determine a period and / or a frequency of the square-wave signal based on the counted edges. For this purpose, the counter module preferably further comprises an input for at least one time signal (for example, an internal CLK signal or a start and stop signal of a measurement, a gate signal, etc.). Particularly preferably, the counter module is configured as a frequency counter (counting frequency meter). In this case, the frequency is preferably determined directly, or the period is first determined and then the frequency is determined as the reciprocal of the determined period.The counter module is further configured to output the determined period and / or frequency of the square-wave signal received from the path output of the variable input path. The counter module preferably outputs the determined period / frequency of the square-wave signal as a digital signal. The counter module is further configured to form a moving average of the square-wave signal in order to avoid fluctuations in the determined period and / or frequency, for example, due to fluctuations (jitter) in the square-wave signal.

[0019] The system according to the present disclosure further comprises a digital signal generation module connected to the counter module, which is configured to output a plurality of amplitude values ​​of the sinusoidal signal for a plurality of phase values ​​of the sinusoidal signal based on the period and / or frequency of the square-wave signal obtained from the counter module. In other words, an input signal of the digital signal generation module is the period or frequency of the input signal applied to the input interface, and an output signal of the digital signal generation module is a digital harmonic signal, in particular a sampled digital harmonic signal, particularly preferably in the time domain. The digital signal generation module is therefore preferably configured as a numerically controlled oscillator.Various implementations of numerically controlled oscillators are known to those skilled in the art; an advantageous implementation is described below.

[0020] The disclosed system advantageously enables the generation of a symmetrical digital signal based on a variety of input signals, which are always converted into a square-wave signal with the periodicity of the input signal by the variable input path. Because both the input interface and the variable input path are preferably designed to receive and process digital signals, respectively, the generation of the symmetrical digital signal is advantageously independent or only slightly dependent on external influences, such as temperature, ground voltage, etc.

[0021] In a preferred embodiment, the system according to the present disclosure further comprises a digital-to-analog converter connected to the digital signal generation module, which is configured to convert the plurality of amplitude values ​​of the sinusoidal signal output by the digital signal generation module into an analog sinusoidal signal. A person skilled in the art will be aware of a variety of possible configurations for a digital-to-analog converter. According to this embodiment, the system is advantageously configured as a system for direct digital synthesis. Furthermore, the system according to the present disclosure preferably comprises an output stage configured to amplify the analog sinusoidal signal output by the digital-to-analog converter.The amplified analog sinusoidal signal can be advantageously used to drive a load, for example, a load that requires a symmetrical drive voltage. The amplified analog sinusoidal signal can be particularly advantageously used to drive a resolver and can be applied to the primary winding of the resolver.

[0022] The variable input path according to a preferred embodiment preferably has a first input path electrically connected between the input interface and the path output, and a second input path electrically connected between the input interface and the path output. The first input path has the element for forming a square-wave signal, and the first input path is configured to process a pulse-width-modulated signal. The second input path is configured to process a square-wave signal and preferably represents a direct electrical connection between the input interface and the path output.

[0023] Thus, the at least two signal inputs of the multiplexer are connected via a respective input path to the path input and, via this, to the input interface, and the signal output of the multiplexer is connected to the path output and, via this, to the counter module. The multiplexer preferably has a control input and is configured to connect the signal present at one of the signal inputs to the signal output based on a control signal present at the control input.

[0024] Particularly preferably, the variable input path of the system according to the present embodiment has a multiplexer that is electrically connected between the path input and the path output. The first input path is then electrically connected between the input interface and the multiplexer, and the second input path is then electrically connected between the input interface and the multiplexer. Thus, the at least two signal inputs of the multiplexer are connected via a respective input path to the path input and via this to the input interface, and the signal output of the multiplexer is connected to the path output and via this to the counter module. The multiplexer further preferably has a control input and is then designed to connect the signal present at one of the signal inputs to the signal output based on a control signal present at the control input.

[0025] The first input path particularly preferably comprises a (digital) second-order low-pass filter for signal reconstruction. Likewise preferably, the first input path further comprises at least one (digital) high-pass or band-pass filter, which is particularly preferably designed to remove DC components from the pre-filtered signal. According to this embodiment, a variable input path is advantageously provided, which, with rectangular signals and pulse-width-modulated signals, can process the most common input signals for the digital generation of sinusoidal (symmetrical) signals as described above.The variable input path preferably also has additional input paths, for example, a third input path configured for processing triangular signals, a fourth input path configured for processing trapezoidal voltages, or the like, wherein each of these additional input paths also has an element for forming a square-wave signal from the periodic input signal. However, in a particularly simple, structurally simple, and inexpensive embodiment, the variable input path advantageously consists of the first and second input paths.

[0026] In a further preferred embodiment of the system according to the present disclosure, the digital signal generation module comprises a phase accumulator configured to determine the plurality of phase values. The use of phase accumulators for recursively generating the phase values ​​of a sinusoidal signal to be synthesized by repeatedly adding a phase difference advantageously enables different sampling rates of the signal to be synthesized while simultaneously maintaining a low memory requirement of the digital signal generation module.

[0027] Furthermore, the module for digital signal generation according to this embodiment preferably has an amplitude accumulator designed to determine the plurality of amplitude values. In other words, the module for digital signal generation is designed to also recursively generate the amplitude values ​​of the signal to be synthesized, in particular by adding amplitude increments to previously determined amplitude values. If a sinusoidal signal is generated with the system according to the invention at a sampling rate that guarantees an alias-free sinusoidal signal, the maximum change in the amplitude values, i.e., the maximum amplitude increment, is significantly smaller than the maximum amplitude value. This advantageously further reduces the memory requirements of the module; particularly advantageously, a word length for storing the amplitude increment is more than half less than the word length for storing an amplitude value.

[0028] In a further preferred embodiment of the system according to the present disclosure, the module for digital signal generation, in particular the phase accumulator, has a step size module designed to determine a step size based on the period and / or the frequency of the square-wave signal. The period / frequency of the sinusoidal signal to be generated should correspond to the previously determined period / frequency of the square-wave signal. By determining the step size of the sampling of the signal to be generated, preferably based on the period / frequency of the square-wave voltage, the direct digital synthesis of the sinusoidal signal can advantageously be carried out with a fixed number of support values. Particularly preferably, the step size is determined as the quotient of the determined period of the square-wave signal and the fixed number of support values ​​of the direct digital synthesis of the sinusoidal signal.

[0029] Furthermore, the module for digital signal generation, in particular the phase accumulator, preferably further comprises a step size counter. The phase accumulator is preferably further configured to accumulate the plurality of phase values ​​with the step size determined by the step size module. The step size counter is preferably configured to count the number of accumulated step sizes and to make the thus determined number available to further processes of the digital signal generation, for example, the amplitude accumulation or an adder (overflow) of the phase accumulation and / or an adder (overflow) of the amplitude accumulation. The step size counter preferably also receives a clock signal as a reference signal for the count.Furthermore, the phase accumulator preferably has an adder for recursively adding the (phase) step sizes and a phase register for storing and holding the current result of the adder's addition. Furthermore, the phase accumulator preferably has feedback from the phase register to the adder, and / or the adder receives a signal from the step size counter, for example, to implement a period overflow.

[0030] According to this preferred embodiment, the amplitude accumulator preferably further comprises a lookup table for determining an amplitude value of the sinusoidal signal for a phase value of the sinusoidal signal. In other words, the lookup table determines an amplitude value of the sinusoidal signal as an output value using a phase value of the sinusoidal signal as an input value. Instead of absolute amplitude values, the lookup table of the amplitude accumulator stores only amplitude increments between two consecutive phase values ​​of the signal. If a sinusoidal signal is generated with the system according to the invention at a sampling rate that guarantees an alias-free sinusoidal signal, the maximum change in the amplitude values, i.e., the maximum amplitude increment, is significantly smaller than the maximum amplitude value.Thus, the memory requirement of the lookup table is advantageously significantly smaller than the memory requirement of a lookup table for amplitude values.

[0031] According to this preferred embodiment, the step size module is further configured to determine the step size based on the period and / or the frequency of the square-wave signal and on the number of amplitude increments stored in the lookup table. Particularly preferably, the step size module is configured to determine the step size as the quotient of the determined period of the square-wave signal and the number of amplitude increments stored in the lookup table. Advantageously, the direct digital synthesis of the sinusoidal signal can thus be carried out using the amplitude accumulator, since determining the step size of the sampling of the signal to be generated based on the determined period of the square-wave signal and the fixed number of amplitude increments advantageously enables the storage of fixed amplitude increments.In other words, by appropriately selecting the step size based on the determined period of the square wave and the fixed number of amplitude increments, the same amplitude increments can always be used for the direct digital synthesis of sinusoidal signals of various frequencies. This reduces the number of values ​​to be stored and the required memory space.

[0032] In a particularly preferred embodiment of the system according to the present disclosure, the values ​​stored in the lookup table consist of the amplitude increments between consecutive phase values ​​of a quarter period of the sinusoidal signal. In other words, only values ​​corresponding to a quarter period of the sinusoidal signal are stored in the lookup table. According to this embodiment, the amplitude accumulator is advantageously configured to determine the amplitude values ​​of a first quarter period of the sinusoidal signal by adding the amplitude increments and to determine the amplitude values ​​of the remaining period duration by accumulating the amplitude increments with a suitably manipulated sign and / or suitably manipulated order. If the amplitude values ​​of the first quarter period were determined by recursively adding N amplitude increments in the order i = 1,..., N-1, N, the amplitude values ​​of the second quarter period can be determined by recursively adding the negative values ​​of the N inversely ordered amplitude increments of the order i = N, N-1, ..., 1, the amplitude values ​​of the third quarter period can be determined by recursively adding the negative values ​​of the N regularly ordered amplitude increments of the order i = 1,..., N-1, N and the amplitude values ​​of the fourth quarter period can be determined by recursively adding the values ​​of the N inversely ordered amplitude increments of the order i = N, N-1, ..., 1. The amplitude accumulator is particularly preferably designed to carry out the aforementioned operations, whereby further memory space can advantageously be saved.

[0033] In a further preferred embodiment, a number of amplitude increments is stored in the lookup table, which, when determining the step size as the quotient of the period of the square wave and the number of stored amplitude increments, result in an undersampling of the sinusoidal signal to be generated for the determined period. Therefore, the number of stored amplitude increments is preferably smaller than the number of steps that would result from the quotient of the determined period of the square wave and a regular step size that satisfies the Nyquist-Shannon sampling theorem (regular step size = determined period of the square wave / number of amplitude increments, taking the Nyquist-Shannon sampling theorem into account).Particularly preferably, the number of stored amplitude increments corresponds to less than 90%, further preferably less than 80%, and particularly preferably less than 70% of the number determined as described above. The waveform of a sinusoidal signal is well known, and moreover, the sinusoidal signal is band-limited, which is why such undersampling advantageously does not violate the Nyquist-Shannon sampling theorem. Such undersampling can advantageously save additional storage space in the lookup table. The combination of the aforementioned measures (storing amplitude increments for a quarter period of the signal and corresponding phase values ​​with a subsampling step size) advantageously reduces the storage space required for the lookup table by up to 87.5% compared to conventional solutions (storing the amplitude values ​​for one period and without undersampling).

[0034] In a further preferred embodiment of the system according to the present disclosure, the amplitude accumulator further comprises an adder for adding the amplitude increments. The adder particularly preferably comprises an adder for recursively adding the amplitude increments and an amplitude register for storing and holding the current result of the adder's addition. Furthermore, the adder preferably comprises feedback from the amplitude register to the adder. Likewise, the adder preferably receives a signal from the step size counter of the phase accumulator, for example, to manipulate the sign and / or the order of the added amplitude increments. Furthermore, the amplitude accumulator preferably comprises a digital low-pass filter.This is preferably configured to receive the amplitude values ​​generated by the adder, filter them, and output the filtered amplitude values ​​to a digital-to-analog converter. According to this embodiment, the system according to the present disclosure preferably comprises the digital-to-analog converter and / or an output stage, as described above.

[0035] In a particularly preferred embodiment of the system according to the present disclosure, it comprises a symmetrical output stage for driving a load, for example the primary winding of a resolver. The symmetrical output stage comprises a first amplifier path that electrically connects a first class A amplifier, the load, and a first low-impedance switch. The symmetrical output stage further comprises a second amplifier path that electrically connects a second class A amplifier, the load, and a second low-impedance switch. The symmetrical output stage comprises a control unit configured to selectively connect the digital-to-analog converter to the first amplifier path or the second amplifier path and to switch the first low-impedance switch and the second low-impedance switch.

[0036] The first and / or second amplifier path electrically connect the respective class A amplifier, the load and the respective low-impedance switch to one another, in particular in series. The load is preferably electrically arranged between the first class A amplifier and the first low-impedance switch and between the second class A amplifier and the second low-impedance switch. The load is electrically connected between a first node and a second node such that an electrical current from the first node flows through the load in a first direction and an electrical current from the second node to the first node flows through the load in a second direction. The first node is electrically connected between the output of the first class A amplifier and the second low-impedance switch and the second node is electrically connected between the output of the second class A amplifier and the first low-impedance switch.Accordingly, when the control unit connects the digital-to-analog converter of the system according to the present disclosure to the first amplifier path, a current flows from the output of the first class A amplifier via the first node through the load and is diverted from there through the second node and through the first low-impedance switch to ground. Likewise, when the control unit connects the digital-to-analog converter of the system according to the present disclosure to the second amplifier path, a current flows from the output of the second class A amplifier via the second node through the load and is diverted from there through the first node and through the second low-impedance switch to ground. Accordingly, the polarity of an electrical current flowing through the load advantageously changes when the amplifier path connected to the voltage source changes.

[0037] The control unit is preferably designed to control an additional component, for example a multiplexer, or the class A amplifier directly for the exclusive connection of the first or second amplifier path to the digital-to-analog converter. In other words, an amplifier path can be disconnected from the voltage source by not applying a signal to the input of the respective class A amplifier or by controlling the respective class A amplifier such that it does not generate an output signal (despite the input signal). The control unit is further designed to switch the first low-impedance switch and the second low-impedance switch, i.e. to make them either electrically conductive or electrically non-conductive. Particularly preferably, the control unit is designed for mutually exclusive switching of the low-impedance switches, i.e. always switches one switch electrically conductive and the other switch electrically non-conductive.Likewise, the control unit is preferably configured to perform the alternating switching of the low-resistance switches and the selective connection of one of the two amplifier paths to the voltage source essentially simultaneously. The control unit is further preferably configured to control further components of the system according to the present disclosure, as described above.

[0038] The symmetrical output stage according to the present disclosure advantageously enables the generation of an interference-free symmetrical output signal with a low DC component and is simple and cost-effective to implement. At the same time, the symmetrical output stage according to the present disclosure enables the generation of an amplified signal with high linearity and a wide bandwidth while simultaneously exhibiting a low level of harmonic interference. Furthermore, the output stage according to the present disclosure can advantageously be operated with a digitally generated voltage reference.

[0039] A further aspect of the present disclosure relates to the use of a system according to the present disclosure as described above for operating a load, in particular a load requiring a DC-free, symmetrical drive voltage. The load is preferably a primary winding of a resolver.

[0040] The electronic or electrical devices and / or other relevant devices or components according to the embodiments of the present invention described herein may be implemented using any suitable hardware, firmware (e.g., an application-specific integrated circuit), software, or a combination of software, firmware, and hardware. The various components of these devices may, for example, be packaged on an integrated circuit (IC) or on separate IC chips. Furthermore, the various components of these devices may be realized on a flexible printed circuit board, a tape carrier package (TCP), a printed circuit board (PCB), or on a substrate. The electrical connections or interconnections described herein may be realized by wires or conductive elements, e.g., on a printed circuit board or other circuit carrier.The conductive elements may include metallizations, e.g., surface metallizations and / or pins, and / or conductive polymers or ceramics. Additional electrical energy may be transmitted via wireless connections, e.g., through electromagnetic radiation and / or light.

[0041] Furthermore, the various components of these devices may be a process or thread running on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in memory, which may be implemented in a computing device using standard memory, such as random access memory (RAM). The computer program instructions may also be stored in other non-transferable, computer-readable media, such as a CD, flash drive, or the like.

[0042] It will also be apparent to those skilled in the art that the functionalities of multiple computers (data processing devices, control units, control devices) can be combined or combined in a single device, or that the functionality of a specific data processing device can be distributed across a plurality of devices in order to implement the functionalities according to the present disclosure. The devices can be arranged centrally or decentrally at different locations. In the case of a decentralized arrangement, suitable communication means are set up between the devices in order to transmit data between these devices that is required for carrying out the respective steps or for providing the respective functions of the individual devices.

[0043] Further aspects of the present invention are disclosed in the dependent claims or in the following description of the drawings. Short description of the characters

[0044] The invention is explained below in exemplary embodiments with reference to the accompanying drawings. They show: Fig. 1 is a schematic diagram of a system according to an embodiment; Fig. 2 (A)-(C) schematic representations of a section of a system according to an embodiment, in particular variable input paths; Fig. 3 schematic representations of a further section of a system according to an embodiment, in particular a module for digital signal generation; Fig. 4 is a schematic diagram of a system according to another embodiment; Fig. 5 is a schematic representation of a portion of a sinusoidal signal to be generated; Fig. 6 is a schematic diagram of a resolver according to the prior art; and Fig. 7 schematic representations of systems for signal generation for a primary winding of a resolver according to the prior art; Detailed description of the characters

[0045] Detailed embodiments will now be described, illustrated by way of example in the accompanying drawings. The effects and features of these embodiments will be described with reference to the accompanying drawings. In the drawings, like reference numerals designate like elements, and redundant descriptions are omitted. The present disclosure may be embodied in various forms and should not be construed as limited only to the embodiments shown herein. Rather, these embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art.

[0046] Therefore, methods, elements, and techniques that are not necessary for a person skilled in the art to fully understand the aspects and features of the present disclosure may not be described. In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity.

[0047] As used herein, the term "and / or" includes all combinations of one or more of the listed elements. Furthermore, the use of "may" in describing embodiments of the present disclosure refers to "one or more embodiments of the present disclosure." In the following description of embodiments, the singular terms may also include the plural, unless the context clearly indicates otherwise.

[0048] Although the terms "first" and "second" are used to describe different elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another.

[0049] For example, a first element may be referred to as a second element, and a second element may be referred to as a first element without departing from the scope of the present disclosure. Expressions such as "at least one of," when preceded by a list of elements, modify the entire list, not just the individual elements of the list.

[0050] Terms such as "substantially," "approximately," and similar terms are used as approximations rather than degrees, and are intended to account for inherent variations in measured or calculated values ​​that will be recognized by those skilled in the art. When the term "substantially" is used in connection with a characteristic that can be expressed by a numerical value, the term "substantially" means a range of at least + / - 5% of the value centered on the value.

[0051] Fig. 1 shows a schematic representation of a system 100 for generating a sinusoidal signal 90 according to one embodiment. The system 100 has an input interface 10 configured to receive a periodic input signal. The input interface 10 is connected to a signal source 1, which provides a periodic input signal. This can be at least one of a plurality of different input signals (square-wave signal, PWM signal, sawtooth signal, etc.). The input interface 10 is electrically connected to a path input 21 of a variable input path 20, which further has a path output 22. The variable input path 20 is configured to output a square-wave signal at the path output 22 with the periodicity of the input signal present at the path input 21.

[0052] The system 100 further comprises a counter module 30 connected to the path output 22 and configured to count edges of the square-wave signal output by means of the path output 22. The counter module 30 is further configured to determine and output a period and / or a frequency of the square-wave signal output by means of the path output 22, wherein the determination is based on the counted edges of the square-wave signal. The system 100 further comprises a digital signal generation module 40 connected to the counter module 30, which is configured to output a plurality of amplitude values ​​92 of the sinusoidal signal 90 for a plurality of phase values ​​91 of the sinusoidal signal 90 based on the period and / or the frequency of the square-wave signal, i.e., as a numerically controlled oscillator. The aforementioned components represent a minimal configuration of the system 100.

[0053] An output of the digital signal generation module 40 is electrically connected to the input of a digital-to-analog converter 50, and an output of the digital-to-analog converter 50 is connected to an output stage 60. The digital-to-analog converter 50 is designed to convert the plurality of amplitude values ​​92 of the sinusoidal signal 90 into an analog signal and to output the analog signal to the output stage 60. The output stage 60 is designed to amplify the signal received by the digital-to-analog converter 50 and to supply it, for example, to the primary winding 201 of a resolver, as shown by way of example in Fig. 6. According to a preferred embodiment, the digital-to-analog converter 50 and the output stage 60 are part of the signal generation system 100.

[0054] Fig. 2(A) to 2(C) show schematic representations of a section of a system 100 according to various embodiments, in particular variable input paths 20. The variable input path 20 is, as already described with reference to Fig. 1, electrically connected between an input interface 10 and a counter module 30. The Fig. The variable input paths 20 shown in Figures 2(A) to 2(C) each comprise a multiplexer 23 and a first input path 24 electrically connected between the input interface 21 and the multiplexer 23. The first input path 24 is designed to process a pulse-width-modulated signal, in particular a periodic and possibly sinusoidal PWM signal, received from the signal source 1 via the input interface 10, and for this purpose each comprise a combination of an element for signal construction 26, for example a second-order digital low-pass filter 26, an element for removing DC components 27, for example a digital band- or high-pass filter 27, and an element 29 for forming a square-wave signal from the periodic PWM input signal. The element 29 for forming a square-wave signal is Fig. 2(B) is a comparator 29.1, such as a window comparator or a Schmitt trigger (comparator with feedback of the output to a non-inverting input), and in Fig. 2(C) is a differently constructed two-point controller 29.2, for example, using RS flip-flops or the like. The first input path 24 is thus designed to convert the pulse-width-modulated input signal received from the input interface 10 into a square-wave signal, wherein the periodicity of the input signal is maintained. The variable input path 20 further has a second input path 25 electrically connected between the input interface 21 and the multiplexer 23. The second input path 25 is designed to process a square-wave signal received from the signal source 1 via the input interface 10 and, for this purpose, is preferably designed as a direct electrical connection between the input interface 21 and the multiplexer 23.The multiplexer 23 is further configured to connect either the first input path 24 or the second input path 25 to the output of the multiplexer 23 as path output 22 of the variable input path 20, depending on a control signal 28 output by a control unit 68 and present at a signal input of the multiplexer 23. The variable input path 20 preferably has means (not shown) connected to the control unit 68 for detecting / determining a type of input signal present at the input interface 10. The control unit 68 is preferably configured to generate the control signal 28 depending on the detected / determined type of input signal.Preferably, the control unit 68 is configured to output a control signal 28 upon application of a pulse-width-modulated signal to the input interface 10, which control signal controls the multiplexer 23 to connect the first input path 24 to the path output 22, and to output a control signal 28 upon application of a square-wave signal to the input interface 10, which control signal controls the multiplexer 23 to connect the second input path 25 to the path output 22. Thus, a square-wave signal with the periodicity of the input signal applied to the input interface 10 is always present at the path output 22 to the counter module 30.

[0055] Fig. 3 shows schematic representations of a further section of a system 100 according to an embodiment, in particular a module for digital signal generation 40. Fig. 3A shows a schematic representation of the module for digital signal generation 40 with a phase accumulator 70 configured to determine the plurality of phase values ​​91 and with an amplitude accumulator 80 configured to determine the plurality of amplitude values ​​92. The phase accumulator 70 is connected to the counter module 30, in particular electrically connected between the counter module 30 and the amplitude accumulator 80, and receives from it a signal for the determined period and / or frequency of the square-wave signal output by the variable input path 20 and determines a plurality of phase values ​​for a sinusoidal signal to be generated with the determined period and / or frequency.The amplitude accumulator 80 is electrically connected between the phase accumulator 70 and the digital-to-analog converter 50 and is configured to receive the plurality of phase values ​​from the phase accumulator 70, determine the plurality of amplitude values ​​for the plurality of received phase values, and output the plurality of amplitude values ​​to the digital-to-analog converter 50.

[0056] Fig. 3B further shows a structure of the phase accumulator 70 and the amplitude accumulator 80. In particular, the phase accumulator 70 has a step size module 71 and a step size counter 72. According to the illustrated embodiment, the step size module 71 is connected to the input interface 30. The step size module 71 is configured to determine a step size 95 (of a sample of the sinusoidal signal 90 to be generated) based on the period and / or frequency of the square wave signal output by the variable input path 20, as determined by the counter module 30. In the illustrated embodiment, the step size counter 72 is electrically connected between the step size module 71 and the amplitude accumulator 80 and is configured to count a number of step sizes 95, for example, a number of step sizes 95 accumulated in a phase register, and to provide this information to other modules of the system 100.

[0057] The amplitude accumulator 80 has in the embodiment of the Fig. 3B, a lookup table 81 is configured to determine an amplitude value 92 of the sinusoidal signal 90 based on a phase value 91 of the sinusoidal signal 90 to be determined. The lookup table 81 stores, in particular, amplitude increments 93, 94 between two consecutive phase values ​​91, i.e., the difference between the amplitude values ​​92 corresponding to these consecutive phase values ​​91. According to the Fig. In the embodiment illustrated in Figure 3B, the step size module 71 is particularly configured to determine the step size 95 based on the period and / or frequency of the square wave signal output by the variable input path 20, as determined by the counter module 30, and based on the number of amplitude increments 93, 94 stored in the lookup table 81. The amplitude accumulator 80 further comprises an adder with an adder 82 connected to the lookup table 81 and configured to add amplitude increments 93, 94. The amplitude accumulator 80 further comprises an amplitude register 83 connected to the adder 82 and configured to store / hold an output of the adder 82. The amplitude register 83 is designed to output a currently stored signal to the digital-to-analog converter 50, directly or via at least one filter (not shown).

[0058] Fig. Figure 4 shows a schematic representation of a system 100 according to another embodiment. This embodiment combines components of the system 100 described with reference to Fig. 2 and Fig. 3 explained sections of the system 100. In particular, the system 100 of the Fig. 4 the one relating to Fig. 2 explained variable input path 20 as well as components of the related to Fig. 3 explained module for digital signal generation 40, in particular components of phase accumulator 70 and amplitude accumulator 80. As in the Fig. 4, the control unit 68 is configured to output a first switching signal SWT 1 to the multiplexer 23 in order to selectively connect the first input path 24 or the second input path 25 to the path output 22. The control unit 68 is further configured to output a clock signal CLK to the step size counter 72. The step size counter 72 is configured to determine a number of step sizes 95 of the sinusoidal signal 90 to be generated based on the step size 95 received from the step size module 71 and the clock signal CLK, and to output this number as the step number SCNT to further components of the system 100.

[0059] The step size counter 72 outputs the step number SCNT, among other things, to the adder 73 of the phase accumulator 70. The adder 73 is designed to determine a current phase value 91 of the sinusoidal signal 90 to be generated based on the step number SCNT and the clock signal CLK and to output it to a phase register 74. The adder 73 uses CLK and SCNT to account for an overflow when a full period of the sinusoidal signal 90 to be generated is reached. The phase register 74 is designed to store a last output value of the adder 73 and hold it at an output of the phase register 74. The output is connected to the input of the adder 73 via a feedback loop, ensuring recursive phase accumulation until a full period of the sinusoidal signal 90 to be generated is reached. The output of the phase register 74 is further connected to a lookup table 81.The phase values ​​91 held at the output of the phase register 74 during a full period of the sinusoidal signal 90 to be generated comprise the phase values ​​91 contained in the . Fig. 5, wherein a distance between the phase values ​​φ1, φ2, φ3 corresponds to the step size 95 determined by the step size module 71, which the step size counter 72 receives from the step size module 71.

[0060] The amplitude accumulator 80 has the lookup table 81, which stores amplitude increments 93, 94 corresponding to the phase values ​​91 of the sinusoidal signal 90 to be determined. The lookup table 81 is configured to output the amplitude increment corresponding to the phase value 91 received from the phase register 74 to the adder 82 of the amplitude accumulator 80. For example, the lookup table 81 is configured to determine the amplitude increment 93 in response to receiving the phase value φ1 and output it to the adder 82. At a time uniquely determined by the clock signal CLK, at which the lookup table 81 receives the phase value φ1, the amplitude register 83 outputs the amplitude value 92 corresponding to the phase value φ1.The output of the amplitude register 83 is connected to the input of the adder 82 via a feedback loop of the amplitude accumulator 80, so that the adder 82 receives the amplitude value 92 corresponding to the phase value φ1 and the amplitude increment 93 corresponding to the phase value φ1. The adder 82 thus determines a sum of the obtained values, whereby the amplitude value 92 corresponding to the phase value φ2 is obtained and output to the amplitude register 83, where it is held. At a next time, uniquely determined by the clock signal CLK, at which the lookup table 81 receives the phase value φ2, the amplitude register 83 now outputs the amplitude value 92 just determined and corresponding to the phase value φ2.The output of the amplitude register 83 is connected to the input of the adder 82 via the feedback loop of the amplitude accumulator 80, so that the adder 82 receives the amplitude value 92 corresponding to the phase value φ2 and the amplitude increment 94 corresponding to the phase value φ2. Thus, the adder 82 calculates a sum of the obtained values, whereby the amplitude value 92 corresponding to the phase value φ3 is obtained and output to the amplitude register 83, where it is held. When performing the accumulation of the amplitude values ​​92, the adder 82 takes into account both the step size SCNT and the clock signal CLK, for example with regard to a sign of the amplitude increments 93, 94. In addition, the lookup table 81 also takes into account the step size SCNT and the clock signal CLK when performing the accumulation of the amplitude values ​​92, for example with regard to a sequence of the amplitude increments 93, 94.Thus, based on the amplitude increments 93, 94 stored in the lookup table 81, all amplitude values ​​92 of a full period of the sinusoidal signal 90 to be generated are successively generated based on the phase values ​​91 of a full period of the sinusoidal signal 90 to be generated and output by the amplitude register 83. It is sufficient if the lookup table 81 contains only amplitude increments 93, 94 between successive phase values ​​φ1, φ2, φ3 of a quarter period of the sinusoidal signal 90 and also contains amplitude increments 93, 94 only for a number of phase values ​​91 of the band-limited signal 90 that correspond to a subsampling of the sinusoidal signal 90.

[0061] The amplitude values ​​92 digitally output by the amplitude register 83 are interpolated via a digital low-pass filter 84 and output to the digital-to-analog converter 50, which converts the digital amplitude values ​​92 into an analog sinusoidal signal. The digital-to-analog converter 50 outputs the analog signal to a symmetrical output stage 60.

[0062] The symmetrical output stage 60 is designed to drive a load 69, which may be, for example, the primary winding 201 of a resolver, as shown in Fig. 6. The symmetrical output stage 60 comprises a control unit 68 and a first amplifier path 61, which electrically connects a first class A amplifier 62, the load 69 and a first low-impedance switch 63 and in Fig. 4 is limited by a dashed line. The symmetrical output stage 60 further comprises a second amplifier path 64, which electrically connects a second class A amplifier 65, the load 69 and a second low-impedance switch 66 and in Fig. 4 is also bordered by a dashed line.

[0063] In the Fig. In the embodiment of the symmetrical output stage 60 shown in Figure 4, the digital-to-analog converter 50 can be selectively connected to the first amplifier path 61 and the second amplifier path 64 by means of a multiplexer 67, wherein the multiplexer 67 is controlled by the control unit 68. In particular, the multiplexer 67 has a signal input to which the analog sinusoidal signal generated by the digital-to-analog converter 50 is applied. In addition, the multiplexer 67 has a first signal output, a second signal output, and a control input. The control unit 68 applies a control signal SWT4 to the control input, and the multiplexer 67 connects either the first signal output or the second signal output to the signal input depending on the control signal SWT4.By connecting the first signal output to the first amplifier path 61 and the second signal output to the second amplifier path 64, the digital-to-analog converter 50 can be selectively connected to one of the two amplifier paths 61, 64.

[0064] The control unit 68 is further configured to switch the first low-resistance switch 63 by means of a switching signal SWT2 and the second low-resistance switch 66 by means of a switching signal SWT3, i.e., in particular, to set it either conductive or non-conductive. In particular, the control unit 68 is configured to always set one of the two switches 63, 66 conductive and the other of the two switches 63, 66 non-conductive, so that only one of the two switches 63, 66 is always conductive. As shown in Fig. As further shown in Figure 4, the load 69 is electrically connected between a first node and a second node. The first node is electrically connected between the output of the first class A amplifier 62 and the second low-impedance switch 66, and the second node is electrically connected between the output of the second class A amplifier 65 and the first low-impedance switch 63.

[0065] The control unit 68 controls the multiplexer 67 and the switches 63, 66 such that, during a first time period, the sinusoidal signal output by the digital-to-analog converter 50 is applied to the input of the first class A amplifier 62, and the first low-impedance switch 63 is turned on and the second low-impedance switch 66 is turned off. An amplified driver voltage generated by the first class A amplifier 62 based on the sinusoidal signal is thus applied to the load 69, so that a current of the first polarity flows through the load 69 and is diverted to ground via the first low-impedance switch 63.The control unit 68 further controls the multiplexer 67 and the switches 63, 66 such that, during a second time period, the sinusoidal signal output by the digital-to-analog converter 50 is applied to the input of the second class A amplifier 65 via the second signal output, and the second low-impedance switch 66 is turned on and the first low-impedance switch 63 is turned off. An amplified driver voltage generated by the second class A amplifier 65 based on the sinusoidal signal is thus applied to the load 69, so that a current of second polarity, opposite to the first polarity, flows through the load 69 and is diverted to ground via the second low-impedance switch 66. A symmetrical alternating voltage is thus applied to the load 69, or a symmetrical alternating current flows through the load 69 as the driver current.

[0066] Fig. Figure 5 shows a schematic representation of a section, in particular a half period (π), of a sinusoidal signal 90 to be generated. As described above with reference to Fig. 4, the sinusoidal signal 90 is generated with the system 100 by generating amplitude values ​​92 for defined phase values ​​91, wherein the phase values ​​91 are generated by means of phase accumulation and the amplitude values ​​92 are generated by amplitude accumulation using amplitude increments 93, 94.

[0067] Fig. Figure 6 shows a schematic representation of a resolver 200 according to the prior art. The illustrated resolver 200 is designed to detect a speed and / or a position of a motor axis 204 and, for this purpose, has a stationary stator and a rotor rotating with the axis to be measured. The stator has a stationary primary winding 201, and the rotor has two secondary windings 202, 203 rotating with the axis and perpendicular to each other. Due to the spatial arrangement of the secondary windings 202, 203, the signals induced therein by the primary winding 201 always have a phase difference of 90° to each other, which is why one secondary winding is also referred to as a sine winding 202 and the other as a cosine winding 203.By knowing the sinusoidal signal applied to the primary winding 201 and measuring the signals induced in the secondary windings 202, 203, the speed and / or position of the motor axis 204 can be determined mathematically. The use of a system 100 as described above for generating a noise-free and DC-free drive voltage for the primary winding 201 advantageously enables the speed and / or position of the motor axis 204 to be determined with particularly high accuracy.

[0068] Fig. Figure 7 shows schematic representations of systems 300, 400 for signal generation according to the prior art. Fig. 7A shows an implementation 300 with a digital microcontroller 301, 304 for outputting pulse-width modulated signals, wherein a positive half-cycle of the pulse-width modulated signal at the output 301 of the microcontroller is connected to the primary winding 201 via a first low-pass filter 302 and a first amplifier 303, and wherein a negative half-cycle of the pulse-width modulated signal at the output 304 of the microcontroller is connected to the primary winding 201 via a second low-pass filter 305 and a second amplifier 306. The voltage applied to the primary winding 201 is adversely dependent on the quality of the components 301, 304 and the low-pass filters 302, 305 used for pulse width modulation, whereby the quality of 301, 304 of these components and the low-pass filters 302, 305 can vary greatly depending on external factors such as temperature, operating and ground voltages, etc. Fig.7B shows an implementation 400 using edge detection 402, a lookup table 403, a digital-to-analog converter 404, and an asymmetric output stage comprising a first amplifier 405, an inverter 406, and a second amplifier 407. In known solutions, the lookup table 403 contains a large number of entries and requires a lot of memory space to generate a signal with a certain quality. List of reference symbols 100 System for generating a sinusoidal signal 10 Input interface 20 variable input path 21 Path entrance 22 Path Exit 23 multiplexers 24 first entrance path 25 second entrance path 26 Element for signal reconstruction 27 Element for removing DC components 28 Control signal 29 Element for forming a square wave signal 29.1 Comparator 29.2 Two-point controller 30 counter module 40 module for digital signal generation 50 digital-to-analog converters 60 power amplifier 61 first amplifier path 62 first class A amplifiers 63 first low-resistance switch 64 second amplifier path 65 second class A amplifier 66 second low-resistance switch 67 multiplexers 68 Control unit 69 Last 70 phase accumulator 71 Step size module 72 step counters 73 adders 74 phase registers 80 amplitude accumulator 81 Lookup table 82 adders 83 amplitude registers 84 low-pass filters 90 sinusoidal signal 91 Phase value 92 amplitude value 93 Amplitude increment 94 Amplitude increment 95 step size 200 resolvers 201 Primary winding 202 sine winding 203 cosine winding 204 Motor axle 300 PWM-based signal generation system 301 positive PWM signal source 302 first low-pass filter 303 first amplifier 304 negative PWM signal source 305 second low-pass filter 306 second amplifier 400 LUT-DAC-based signal generation system 401 Square wave signal source 402 Edge detection 403 Lookup Table 404 Digital-to-analog converter 405 first amplifier 406 Inverter 407 second amplifier SWT1 first switching signal SWT3 second switching signal SWT3 third switching signal SWT4 fourth switching signal CLK clock signal SCNT step count

Claims

[1] System (100) for generating a sinusoidal signal (90), comprising: an input interface (10) configured to receive a periodic input signal; a variable input path (20) having a path input (21) connected to the input interface (10), a path output (22) and an element (29) electrically connected between the path input (21) and the path output (22) for forming a square-wave signal, wherein the variable input path (20) is designed to output a square-wave signal at the path output (22) with the periodicity of the input signal present at the path input (21); a counter module (30) connected to the path output (22) and designed to count edges of the square-wave signal and to output a period and / or a frequency of the square-wave signal; a digital signal generation module (40) connected to the counter module (30) and designed to output a plurality of amplitude values ​​(92) of the sinusoidal signal (90) for a plurality of phase values ​​(91) of the sinusoidal signal (90) based on the period and / or the frequency of the square-wave signal. [2] The system (100) of claim 1, further comprising a digital-to-analog converter (50) connected to the digital signal generation module (40) and an output stage (60), wherein the digital-to-analog converter (50) is configured to convert the plurality of amplitude values ​​(92) of the sinusoidal signal (90) into an analog signal and output the analog signal to the output stage (60). [3] System (100) according to claim 2, wherein the output stage (60) is a symmetrical output stage for driving a load (69), comprising: a first amplifier path (61) electrically connecting a first class A amplifier (62), the load (69) and a first low-impedance switch (63); a second amplifier path (64) electrically connecting a second class A amplifier (65), the load (69) and a second low-impedance switch (66); a control unit (68) configured to selectively connect the digital-to-analog converter (50) to the first amplifier path (61) or the second amplifier path (64) and to switch the first low-impedance switch (63) and the second low-impedance switch (66). [4] System (100) according to one of the preceding claims, wherein the variable input path (20) has a first input path (24) electrically connected between the input interface (21) and the path output (22) and a second input path (25) electrically connected between the input interface (21) and the path output (22), wherein the first input path (24) is designed to process a pulse-width modulated signal and has the element (29) for forming a square-wave signal, and wherein the second input path (25) is designed to process a square-wave signal and preferably represents a direct electrical connection between the input interface (21) and the path output (22). [5] System (100) according to one of the preceding claims, wherein the element (29) for forming a square wave signal comprises a comparator (29.1), a two-point controller (29.2), an RS flip-flop, a Schmitt trigger or a window comparator. [6] System (100) according to one of the preceding claims, wherein the module for digital signal generation (40) has a phase accumulator (70) designed to determine the plurality of phase values ​​(91) and an amplitude accumulator (80) designed to determine the plurality of amplitude values ​​(92), wherein the phase accumulator (70) preferably has a step size module (71) designed to determine a step size (95) based on the period and / or the frequency of the square-wave signal and a step size counter (72) and is further preferably designed to accumulate the plurality of phase values ​​(91) with the determined step size (95). [7] The system (100) of claim 6, wherein the amplitude accumulator (80) comprises a lookup table (81) for determining an amplitude value (92) of the sinusoidal signal (90) for a phase value (91) of the sinusoidal signal (90), the lookup table (81) storing amplitude increments (93, 94) between two consecutive phase values ​​(91). [8] System (100) according to claim 7, wherein the step size module (71) is designed to determine the step size (95) based on the period and / or the frequency of the square wave signal and on a number of amplitude increments (93, 94) stored in the lookup table (81). [9] System (100) according to claim 7 or 8, wherein the values ​​stored in the lookup table (81) consist of the amplitude increments (93, 94) between successive phase values ​​(91) of a quarter period of the sinusoidal signal (90). [10] The system (100) of any one of claims 6 to 9, wherein the amplitude accumulator (80) further comprises an adder (82, 83) for adding the amplitude increments and / or a digital low-pass filter (84) for outputting the plurality of amplitude values ​​to the digital-to-analog converter (50) of claim 2.

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