Housing architectures with vertically stacked voltage regulators

Abstract

Embodiments of a microelectronic assembly may include a first integrated circuit (IC) with a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, wherein the first IC die contains conductive traces parallel to the first and second surfaces and exposed at the third surface; a second IC die with a fourth surface containing a voltage regulator circuit; and a third IC die with a fifth surface, wherein the third surface of the first IC die is electrically coupled to the fifth surface of the third IC die by first interconnects, the fourth surface of the second IC die is electrically coupled to the fifth surface of the third IC die by second interconnects, and the first IC die is electrically coupled to the second IC die by conductive paths in the third IC die.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to techniques, methods, and apparatus related to vertically stacked die package architectures. BACKGROUND

[0002] Electronic circuits, typically manufactured on a wafer of semiconductor material, such as silicon, are called integrated circuits (ICs). The wafer containing such ICs is typically divided into numerous individual dies. The dies can be packaged in an IC package, which contains one or more dies along with other electronic components such as resistors, capacitors, and inductors. The IC package can be integrated into an electronic system, such as a consumer electronics system, or into a server, such as a mainframe computer. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The embodiments will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. The embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings. Fig. 1A-1D are schematic cross-sectional views of an exemplary IC die according to some embodiments of the present disclosure. Fig. 2A is a schematic perspective view of the exemplary IC die of Fig. 1A according to some embodiments of the present disclosure. Fig. 2B is a schematic perspective view of the exemplary IC die of Fig. 1B according to some embodiments of the present disclosure. Fig. 2C is a schematic perspective view of the exemplary IC die of Fig. 1C according to some embodiments of the present disclosure. Fig. 2D is a schematic perspective view of the exemplary IC die of Fig. 1D according to some embodiments of the present disclosure. Fig. 3A is a schematic cross-sectional view of an exemplary microelectronic assembly according to some embodiments of the present disclosure. Fig. Figure 3B is a schematic cross-sectional view of a portion of the microelectronic assembly of Fig. 3A. Fig. 3C is a schematic cross-sectional view of a portion of the exemplary microelectronic assembly of Fig. 3A according to some embodiments of the present disclosure. Fig. 3D is a schematic cross-sectional view of a portion of the exemplary microelectronic assembly of Fig. 3A according to some embodiments of the present disclosure. Fig. 4A is a schematic perspective view of an exemplary microelectronic assembly incorporating the exemplary IC die of Fig. 2A according to some embodiments of the present disclosure. Fig. 4B is a schematic perspective view of an exemplary microelectronic assembly incorporating the exemplary IC die of Fig. 2B according to some embodiments of the present disclosure. Fig. 5A-5C are schematic cross-sectional views of microelectronic assemblies according to some embodiments of the present disclosure. Fig. 6 is a simplified flowchart illustrating example operations that may be associated with embodiments of an example microelectronic assembly. Fig. 7 is a simplified flowchart illustrating example operations that may be associated with embodiments of an example microelectronic assembly. Fig. 8 is a simplified flow diagram illustrating example operations that may be associated with embodiments of an example microelectronic assembly. Fig. 9 is a cross-sectional view of a device package containing one or more microelectronic assemblies according to one of the embodiments disclosed herein. Fig. 10 is a side cross-sectional view of a device assembly including one or more microelectronic assemblies according to one of the embodiments disclosed herein. Fig. 11 is a block diagram of an exemplary computing device including one or more microelectronic assemblies according to any embodiment disclosed herein. DETAILED DESCRIPTIONOverview

[0004] To illustrate the IC packages described herein, it is important to understand the phenomena that can occur during IC assembly and packaging. The following basic information can be considered a basis upon which the present disclosure can be properly explained. This information is provided for illustrative purposes only and should therefore not be construed in any way to limit the broad scope of the present disclosure and its potential applications.

[0005] The trend in the computer industry is toward using multiple processors in large servers, with the multiple processors packaged in a single package, such as a multi-chip module (MCM). The multiple processors, along with other IC dies containing memory circuitry (e.g., cache memory circuitry, high-bandwidth memory circuitry, etc.), are interconnected by high-speed data buses in the MCM's package substrate, allowing the entire assembly of processors to interoperate. However, current technology for such MCMs is inherently limited in its ability to meet the bandwidth and distance requirements of next-generation servers, which could have signal speeds exceeding 10 GHz and / or data speeds of 3-10 terabytes per second.The limitations mainly concern bandwidth reduction, signal delay, signal loss, and signal distortion for various reasons, one of which is the configuration in which the multiple processors are interconnected within the chassis.

[0006] Current packaging architecture, whether 2D, 2.5D, or 3D, uses multiple IC dies aligned parallel to each other and connected by various types of interconnects such as copper microbumps, solder balls, etc. In general, a typical IC die consists of a substrate, an active area in the substrate containing transistors and other active circuitry, and a metallization stack above the substrate that shares a contact area with the active area. The metallization stack is the area of ​​the IC die where the individual components (e.g., transistors, capacitors, resistors, etc.) are connected to each other with traces and vias. Copper and aluminum are commonly used as metals for the traces and vias. The metallization stack typically includes contact pads, insulating layers (e.g.,Intermediate layer dielectrics (ILDs) such as silicon oxide, conductive layers containing the traces and bond pads for chip-to-chip or chip-to-package connections. Modern IC dies can contain more than 10 conductive layers in the metallization stack.

[0007] Conventionally, multiple such IC dies can be stacked in a package in several ways: (1) back-to-back, where the substrate of one IC die is in direct contact with the substrate of another IC die; (2) back-to-front, where the substrate of one IC die is in direct contact with the metallization stack of the other IC die; and (3) front-to-front, where the metallization stacks of the two IC dies are in direct contact. In all these configurations, the IC dies are arranged parallel to each other, with the active circuits lying in planes parallel to the contact pads of neighboring IC dies. Such an architecture suffers from certain inherent limitations. For example, compute IC dies with high-performance computing circuits that generate a lot of heat must be placed at the top of such a stack so that the heat can be properly dissipated.Such placement limits the number of high-performance ICs that can be accommodated in a package with limited (or restricted) footprint.

[0008] Memory IC packages typically require 2 to 3 watts of power, so there is usually not much voltage drop, whereas computer systems typically require 100 watts of power. For such computing systems, a highly efficient power supply is a significant challenge and critical to achieving the desired performance per watt. An IC package may include a voltage regulator (VR) to control the power supply to an IC die. Integrating VRs into IC packages with vertically stacked IC dies can be difficult due to the limited space within an IC package. Various microelectronic assemblies disclosed herein can exhibit improved power delivery and signal speed while reducing package complexity compared to conventional approaches.

[0009] The microelectronic assemblies disclosed herein may include IC dies that are vertically stacked and electrically connected at a lateral edge (e.g., stacked back-to-back, back-to-front, or front-to-front and rotated 90 degrees) to a surface of a base IC die. In particular, a microelectronic assembly disclosed herein may include an IC die coupled to a base IC die by interconnects on a first surface of the IC die and a second surface of the base IC die such that the first surface is in contact with the second surface, and the IC die may include a substrate attached to a metallization stack along an interface orthogonal to the first surface. The metallization stack of the IC die may include multiple layers of conductive traces in a dielectric material, and the interconnects may be connected to the conductive traces exposed on the first surface.The IC die may also be electrically coupled to a VR circuit, which may be a VR chip coupled to the surface of the base IC die or integrated into the base IC die. In some embodiments, the interconnects may include oxide-oxide bonds and metal-metal bonds, wherein the metal-metal bonds include first bond pads in the first IC die and second bond pads in the second IC die, wherein the first bond pads comprise portions of the conductive traces exposed on the first surface.

[0010] Accordingly, microelectronic assemblies, associated devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including conductive traces parallel to the first and second surfaces, and the conductive traces exposed at the third surface; a second IC die having a fourth surface, the second IC die including a voltage regulator circuit;and a third IC die having a fifth surface, wherein the third surface of the first IC die is electrically coupled to the fifth surface of the third IC die by first interconnects, the fourth surface of the second IC die is electrically coupled to the fifth surface of the third IC die by second interconnects, and the first IC die is electrically coupled to the second IC die by conduction paths in the third IC die;

[0011] Each of the structures, assemblies, packages, methods, devices, and systems of the present disclosure may incorporate several innovative aspects, none of which is solely responsible for all of the desirable features disclosed herein. Details of one or more embodiments of the subject matter described in this specification are set forth in the following description and the accompanying drawings.

[0012] In the following detailed description, various aspects of the illustrative implementations are described using terms commonly used by those skilled in the art to convey the substance of their work to others skilled in the art.

[0013] The terms "circuit" and "circuitry" refer to one or more passive and / or active electrical and / or electronic components arranged to interact with each other to perform a desired function. These terms also refer to analog circuits, digital circuits, hard-wired circuits, programmable circuits, microcontroller circuits, and / or any other type of physical electrical and / or electronic hardware components.

[0014] The term “integrated circuit” refers to a circuit that is integrated into a monolithic semiconductor or analog material.

[0015] In some embodiments, the IC dies disclosed herein may contain substantially monocrystalline semiconductors such as silicon or germanium as the base material (e.g., substrate, body) on which integrated circuits are fabricated using conventional semiconductor processing methods. The semiconductor base material may, for example, include N-type pr-type materials. The chips may, for example, be a crystalline base material consisting of silicon (or another semiconductor material) or a silicon-on-insulator (SOI) structure. In some other embodiments, the base material of one or more IC dies may include alternative materials that may or may not be combined with silicon, such as germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of Group III-N, Group III-V, Group II-VI, or Group IV materials.In yet other embodiments, the base material may contain compound semiconductors, e.g., having a first sublattice of at least one element from Group III of the Periodic Table (e.g., Al, Ga, In) and a second sublattice of at least one element from Group V of the Periodic Table (e.g., P, As, Sb). In other embodiments, the base material may contain an intrinsic IV- or III-V-type semiconductor material or alloy that is not intentionally doped with electrically active impurities; in other embodiments, nominal impurity dopant amounts may be present. In yet other embodiments, the base material may contain a non-crystalline material, such as polymers; for example, the base material may contain silicon dioxide-filled epoxy.In other embodiments, the base material may include a high mobility oxide semiconductor material such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide.In general, the base material may contain one or more of the following materials: tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N- or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, and black phosphorus, each of which may be doped with one or more of the elements gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. Although only a few examples of the material for dies are described here, any material or structure that can be used as a basis (e.g.base material) on which IC circuits and structures as described herein can be built, falls within the scope of the present disclosure.

[0016] Unless otherwise described, the IC dies described herein include one or more IC structures (or simply "ICs") that implement (i.e., are configured to execute) a particular functionality. In one such example, the term "memory die" may be used to describe a die that includes one or more ICs that implement memory circuitry (e.g., ICs that implement one or more of the following: memory devices, memory arrays, control logic for controlling the memory devices and arrays, etc.). In another example, the term "compute die" may be used to describe a die that includes one or more ICs that implement logic / compute circuitry (e.g., ICs that implement one or more I / O functions, arithmetic operations, data pipelining, etc.).

[0017] In another example, the terms "package" and "IC package" are synonymous, as are the terms "chip" and "IC die." The terms "chip," "die," and "IC die" are used interchangeably here.

[0018] The term "optical structure" encompasses arrays of shapes fabricated in integrated circuits to receive, transform, and / or transmit optical signals as described herein. These may include optical conductors such as waveguides, electromagnetic radiation sources such as lasers and light-emitting diodes (LEDs), and electro-optical devices such as photodetectors.

[0019] In various embodiments, each photonic integrated circuit (PIC) described herein may include a semiconductor material, such as N- or P-type materials. For example, the PIC may include a crystalline base material consisting of silicon (or another semiconductor material) or an SOI structure (or generally a semiconductor-on-insulator structure). In some embodiments, the PIC may be formed using alternative materials that may or may not be combined with silicon, including, but not limited to, lithium niobite, indium phosphide, silicon dioxide, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum gallium arsenide, aluminum arsenide, indium aluminum arsenide, aluminum indium antimonide, indium gallium arsenide, gallium nitride, indium gallium nitride, aluminum indium nitride, or gallium antimonide, or other combinations of Group III-N or Group IV materials.In some embodiments, the PIC may include a non-crystalline material, such as polymers. In some embodiments, the PIC may be formed on a printed circuit board (PCB). In some embodiments, the PIC may be inhomogeneous and include a carrier material (such as glass or silicon carbide) as the base material with a thin semiconductor layer overlying an active side containing transistors and similar components. Although some examples of the material for the PIC are described here, any material or structure that can serve as the basis for the PIC is within the scope of the present disclosure.

[0020] The term "insulating" means "electrically insulating," and the term "conductive" means "electrically conductive," unless otherwise specified. With respect to optical signals and / or devices, components, and elements that operate with optical signals, the term "conductive" may also mean "optically conductive."

[0021] The terms “oxide,” “carbide,” “nitride,” etc., refer to compounds containing oxygen, carbon, nitrogen, etc.

[0022] The term “high-k dielectric” refers to a material with a higher dielectric constant than silicon oxide, while the term “low-k dielectric” refers to a material with a lower dielectric constant than silicon oxide.

[0023] The term "insulating material" or "insulator" (also referred to herein as "dielectric material" or "dielectric") refers to solid materials (and / or liquid materials that solidify after processing as described herein) that are substantially electrically non-conductive. Examples and not limitations include organic polymers and plastics, as well as inorganic materials such as ionic crystals, porcelain, glass, silicon, silicon oxide, silicon carbide, silicon carbonitride, silicon nitride, and aluminum oxide, or a combination thereof. These may include dielectric materials, materials with high polarizability, and / or piezoelectric materials. They may be transparent or opaque without departing from the scope of the present disclosure. Other examples of insulating materials include underfills and molds or mold-like materials used in packaging applications, e.g.,Materials used in organic interlayers, packaging substrates and other such components.

[0024] In various embodiments, elements comprising an IC may include, for example, transistors, diodes, current sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. In various embodiments, elements comprising an IC may be elements that are monolithically integrated into an IC, mounted on an IC, or connected to an IC. The ICs described herein may be either analog or digital and may be used in a variety of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on which components are connected to the IC. The ICs described herein may be used in a single IC die or as part of a chipset to perform one or more related functions in a computer.

[0025] In various embodiments of the present disclosure, the transistors described herein may be field-effect transistors (FETs), e.g., MOSFETs. In many embodiments, a FET is a four-terminal device. In a silicon-on-insulator, nanoribbon, or gate-all-around (GAA) FET, the FET is a three-terminal device that includes source, drain, and gate terminals and uses an electric field to control the current flowing through the device. A FET typically includes a channel material, a source region, and a drain region provided in and / or above the channel material, a gate stack including a gate electrode material, alternatively referred to as a "work function" material, provided over a portion of the channel material (the "channel portion") between the source and drain regions, and optionally also a gate dielectric between the gate electrode material and the channel material.

[0026] In a general sense, an "interconnect" refers to any element that creates a physical connection between two other elements. For example, an electrical interconnect creates an electrical connection between two electrical components and facilitates the communication of electrical signals between them; an optical interconnect creates an optical connection between two optical components and facilitates the communication of optical signals between them. In this document, both electrical and optical interconnects are referred to collectively as "interconnect." The type of interconnect described is understood here by reference to the associated signal carrier. With reference to an electronic device, e.g.For example, in the case of an IC that operates with electrical signals, the term "interconnect" describes any element made of an electrically conductive material to establish an electrical connection to one or more elements connected to the IC and / or between different such elements. In such cases, the term "interconnect" can refer to both conductive traces (sometimes called "lines", "wires", "metal lines", or "trenchments") and conductive vias (sometimes called "vias" or "metal vias"). Occasionally, electrically conductive traces and vias are also referred to as "conducting traces" and "conductive vias" respectively, to emphasize that these elements contain electrically conductive materials such as metals. Likewise, the term "interconnect" can be used when used in reference to a component that also operates with optical signals, such as a camera.A PIC can describe any element made of an optically conductive material to provide an optical connection to one or more elements connected to the PIC. In such cases, the term "interconnect" can refer to optical fibers, including optical fibers, optical splitters, optical combiners, optical couplers, and optical transit points.

[0027] The term "waveguide" refers to any structure designed to guide the propagation of light from one location to another, typically through a substrate material such as silicon or glass. In various examples, waveguides can be formed from silicon, doped silicon, silicon nitride, glasses such as silicon dioxide (e.g., silicon dioxide or SiO2), borosilicate (e.g., 70-80 wt% SiO2, 7-13 wt% B2O3, 4-8 wt% Na2O or K2O, and 2-8 wt% Al2O3), and so on. Waveguides can be formed using various techniques, including, but not limited to, in-situ waveguide formation. In some embodiments, for example, the waveguides can be fabricated in-situ in glass by low-temperature glass-to-glass bonding or by laser direct writing. Formed-in-situ waveguides can have lower losses.

[0028] The term "conducting trace" can be used to describe an electrically conductive element insulated by an insulating material. In IC dies, such an insulating material includes a low-k dielectric present within the IC die. In package substrates and printed circuit boards, this insulating material includes organic materials such as Ajinomoto Buildup Film (ABF), polyimide, or epoxy resin. Such conductive traces are typically arranged in multiple levels or layers of metallization stacks.

[0029] The term "conductive via" can be used to describe an electrically conductive element that connects two or more conductive lines at different levels of a metallization stack. For this purpose, a via can be provided substantially perpendicular to the plane of an IC die or a support structure on which an IC structure is mounted, and can connect two conductive lines in adjacent levels or two conductive lines in non-adjacent levels.

[0030] The term "packaging substrate" can be used to describe any substrate material that facilitates the assembly of any collection of semiconductor chips and / or other electrical components, such as passive electrical components. A packaging substrate can be made of any material, including, but not limited to, insulating materials such as resin-impregnated glass fibers (e.g., printed circuit boards or printed circuit boards), glass, ceramic, silicon, silicon carbide, etc. Furthermore, as used herein, a packaging substrate can refer to a substrate containing build-up layers (e.g., ABF layers).

[0031] The term “metallization stack” can refer to a stack of one or more interconnects that connect to various circuit components of an IC die and / or a package substrate.

[0032] As used here, the term “pitch” of interconnects refers to the center-to-center distance between adjacent interconnects.

[0033] It is recognized that an additional level of underfill (e.g., organic polymer material such as benzotriazole, imidazole, polyimide, or epoxy) may be present in an IC package described herein and need not be labeled to avoid cluttering the drawings. In various embodiments, the underfill levels may include the same or different insulating materials. In some embodiments, the underfill levels may include thermosetting epoxies with silicon oxide particles; in other embodiments, the underfill levels may include any suitable material capable of performing underfill functions, such as supporting the die and reducing thermal stress on the interconnects. In some embodiments, the choice of underfill material may be based on design considerations, such as form factor, size, loading, operating conditions, etc.In other embodiments, the choice of underfill material may be based on material properties and processing conditions, such as curing temperature, glass transition temperature, viscosity, and chemical resistance, among other factors. In some embodiments, the choice of underfill material may be based on both design and processing considerations.

[0034] In some embodiments, one or more levels of solder resists (e.g., liquid epoxy, liquid photoimageable polymers, photoimageable dry film polymers, acrylate, solvent) may be present in an IC package described herein, which are not labeled or shown to avoid cluttering the drawings. The solder resist may be a liquid or dry film material, including photoimageable polymers. In some embodiments, the solder resist may not be photoimageable.

[0035] The terms "substantially," "close," "approximately," "near," and "approximately" generally refer to being within + / - 20% of a target value (e.g., within + / - 5% or 10% of a target value) based on the context of a particular value as described herein or as known in the art.

[0036] Terms indicating the orientation of various elements, such as "coplanar," "perpendicular," "orthogonal," "parallel," or any other angle between the elements, generally refer to being within + / - 5% to 20% of a target value based on the context of a particular value described herein or known in the art.

[0037] The term "connected" means a direct connection (which may be one or more mechanical, electrical and / or thermal connections) between the things that are connected, without any intermediate devices, while the term "coupled" means either a direct connection between the things that are connected or an indirect connection through one or more passive or active intermediate devices.

[0038] Throughout the description, the terms "in one embodiment" or "in embodiments" are used, each of which may refer to one or more identical or different embodiments.

[0039] Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.

[0040] The disclosure may use perspective descriptions such as "above," "below," "top," "bottom," and "side"; such descriptions are for convenience of discussion and are not intended to limit the application of the disclosed embodiments.

[0041] As used herein, the terms "over," "under," "between," and "on" refer to the relative position of a material layer or component with respect to other layers or components. For example, a layer disposed over or under another layer may be in direct contact with the other layer or may have one or more intervening layers. Furthermore, a layer disposed between two layers may be in direct contact with one or both of the two layers or may have one or more intervening layers. In contrast, a first layer described as being "on" a second layer refers to a layer that is in direct contact with that second layer. Likewise, unless expressly stated otherwise, a feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.

[0042] The term “arrange” as used here refers to the position, location, placement and / or arrangement and not to a specific method of formation.

[0043] The term “between,” when used in reference to measurement ranges, includes the ends of the measurement ranges.

[0044] For the purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). As used herein, the notation "A / B / C" means (A), (B), and / or (C).

[0045] Although certain elements are referred to herein in the singular, these elements may include multiple subelements. For example, the term "electrically conductive material" may include one or more electrically conductive materials. In another example, "a dielectric material" may include one or more dielectric materials.

[0046] Unless otherwise indicated, the use of the ordinal adjectives "first", "second", "third", etc., to describe a common object merely means that different instances of similar objects are meant, and is not intended to imply that the objects so described must be in any particular order, whether temporal, spatial, rank, or otherwise.

[0047] In the following detailed description, reference is made to the accompanying drawings, which form a part of this document, and in which is shown by way of illustration embodiments that may be practiced. It should be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the present disclosure. The following detailed description, therefore, is not to be considered limiting.

[0048] The attached drawings are not necessarily to scale.

[0049] Throughout the drawings, like reference numbers refer to like or similar elements / materials. Therefore, unless otherwise stated, explanations given in connection with one of the drawings regarding an element / material with a particular reference number apply to other drawings in which elements / materials with the same reference numbers may be shown. Furthermore, the singular and plural forms of the designations with reference numbers may be used to designate a single or multiple instances of the same or a similar type, kind, or class of elements, respectively.

[0050] In addition, some schematic representations of example structures of various devices and assemblies described herein may be shown in the drawings, with precise right angles and straight lines. However, it should be understood that such schematic representations may not reflect real-world process limitations, which may result in features that do not appear as "ideal" when any of the structures described herein are examined, for example, with images from suitable characterization tools such as scanning electron microscopy (SEM) images, transmission electron microscope (TEM) images, or non-contact profilometers. Such images of real structures may also reveal possible processing and / or surface defects, such as:Surface roughness, curvature or profile deviation, pits or scratches, imperfectly straight edges of materials, tapered through-holes or other openings, unintentional rounding of corners or thickness variations between different material layers, occasional screw, edge, or combination dislocations within the crystalline region(s), and / or occasional dislocation defects of individual atoms or atom clusters. There may be other defects not listed here that are common in the manufacturing and / or packaging of products.

[0051] Note that in the figures, various components (e.g., interconnects) are shown aligned (e.g., at their respective interfaces) for illustrative purposes only; in reality, some or all of them may be misaligned. Furthermore, the assembly may contain other components such as bond pads, landing pads, metallization, etc., which are not shown in the figures to avoid clutter. Furthermore, the figures are intended to show the relative arrangement of components within their assemblies, and in general, such assemblies may contain other components not shown (e.g., various interface layers or various other components related to optical functionality, electrical connectivity, or thermal mitigation).In some further embodiments, the assembly shown in the figures may, for example, include multiple dies along with other electrical components. Although some components of the assemblies are depicted in the figures as planar rectangles or rectangular bodies, this is for illustrative purposes only, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped, as dictated and sometimes unavoidable by the manufacturing processes used to fabricate the various components.

[0052] In the drawings, a particular number and arrangement of structures and components are shown for illustrative purposes, and any desired number or arrangement of such structures and components may be present in various embodiments.

[0053] Unless otherwise stated, the structures shown in the figures may take any suitable form depending on material properties, manufacturing processes and operating conditions.

[0054] For the sake of simplicity, a collection of drawings labeled with different letters, e.g. Fig. 1A-1D, such a collection may be referred to here without the letters, e.g. as “ Fig. 1". If a collection of reference numbers with different letters exists (e.g., 108A, 108B), such a collection may be referred to here without the letters (e.g., as "108").

[0055] Various operations may be described sequentially as multiple discrete actions or operations in a manner most useful for understanding the claimed subject matter. However, the order of description should not be understood to necessarily dictate the order of these operations. In particular, these operations may not be performed in the order of presentation. The described operations may be performed in a different order than in the described embodiment. Various additional operations may be performed, and / or the described operations may be omitted from further embodiments. Exemplary embodiments

[0056] Fig. 1A is a schematic cross-sectional view of an exemplary IC die 100 according to some embodiments of the present disclosure. In the illustrated embodiment, the IC die 100 includes a metallization stack 102 with a surface 104 that is orthogonal to another surface 106. In various embodiments, the surfaces 104 and 106 may be planarized. Generally, an IC die different from IC die 100 will not have planar edges along the thickness; for example, the vertical surfaces corresponding to surface 104 would be rough because they underwent a dicing process when the IC die was singulated from a wafer. In contrast, the surface 104 of the IC die 100 may be flat and planar, with a surface roughness of less than 10 angstroms and a total thickness variation (TTV) across the surface 104 of less than 3 microns.

[0057] The metallization stack 102 may be located on a substrate 110 (e.g., at an interface 108). The interface 108 may be orthogonal to the surface 104 and parallel to the surface 106 (e.g., in the xy plane). It should be understood that the interface 108 may be in the xy plane but not exactly planar. The substrate 110 may also include an active region 112. In some embodiments, the active region 112 may include transistors, diodes, and other active circuitry and may be located near the interface 108. In some other embodiments, the active region 112 may be absent, or transistors, diodes, and other active circuitry may not be present in the active region 112. The substrate 110 may have a surface 114 that may be coplanar with the surface 104. In some embodiments, the substrate 110 may include a semiconductor material as listed in the previous subsection.In other embodiments, the substrate 110 may be made of glass, ceramic, or other materials suitable for fabricating functional elements of an IC.

[0058] In various embodiments, the metallization stack 102 may include a dielectric material or a plurality of layers of dielectric material and conductive traces 120 through the dielectric material. The conductive traces 120 may run parallel to the surface 106 such that the conductive traces 120 run orthogonal to the surface 104. In some embodiments, a dielectric material of the metallization stack 102 may include silicon oxide; in other embodiments, the dielectric material of the metallization stack 102 may include any suitable dielectric material used as an interlayer dielectric (ILD) in a typical semiconductor integrated circuit die and as described above in the previous subsection. The conductive traces 120 may, in many embodiments, include a conductive metal, such as copper.In some embodiments, between 2 and 6 layers of conductive traces 120 may be present in the plurality of layers of dielectric material. Conductive vias 122 through the dielectric material may conductively connect the conductive traces 120 to the active circuitry in the active area 112. Conductive vias 122 are orthogonal to the conductive traces 120. The conductive traces 120 may extend to the surface 104 such that portions of the conductive traces 120 are exposed on the surface 104; these exposed portions may form bonding portions 124. In various embodiments, multiple conductive traces 120 may be present between the interface 108 and the surface 106. One or more of the conductive traces 120 may be exposed on the surface 104 as bonding portions 124. In some embodiments, a linear dimension (e.g., length, width, or diagonal) of the largest bond portion 124 may be less than 5 micrometers.In some embodiments, the bonding portions 124 may be spaced apart by less than 9 micrometers. In some embodiments, a bonding pad (e.g., similar to the conductive bonding pad 308 shown in FIG. Fig. 3) on a bonding portion 124 on the surface 104.

[0059] Fig. 1B is a schematic cross-sectional view of another exemplary IC die 100 according to some other embodiments of the present disclosure. In some embodiments, the IC die 100 may include metallization stacks 102A and 102B on both sides of the substrate 110. The metallization stack 102A may share the interface 108A with the substrate 110, and the metallization stack 102B may share the interface 108B with the substrate 110. In some embodiments, as shown in Fig. 1B, the active area 112 may be located near the interface 108A; in other embodiments, the active area 112 may be located near the interface 108B. Conductive lines 120A and conductive vias 122A may be located in the metallization stack 102A. Conductive lines 120B and conductive vias 122B may be located in the metallization stack 102B. In some embodiments, the conductive lines 120A may be configured to conduct signals, while the conductive lines 120B may be configured to conduct power and ground to the active area 112. In such embodiments, the conductive lines 120B may be thicker than the conductive lines 120A (i.e., the conductive lines 120A may be thinner than the conductive lines 120B). In other embodiments, traces 120A and traces 120B may be configured to carry signals, power, and ground without distinction between them.In such embodiments, traces 120A and 120B may have a similar thickness. TSVs 202 through substrate 110 may enable conduction paths between traces 120A and 120B and / or active area 112 and traces 120B. In some embodiments, TSVs 202 may extend through active area 112 (e.g., as shown in FIG. Fig. 1C).

[0060] Fig. 1C is a schematic cross-sectional view of another exemplary IC die 100 according to some embodiments of the present disclosure. Fig. The IC die 100 shown in Figure 1C is an assembly comprising a first IC die 100A and a second IC die 100B. In the illustrated embodiment, a first IC die 100A is connected in a front-to-front configuration to a second IC die 100B by interconnects 305. The first IC die 100A and the second IC die 100B may be formed from the Fig. 1A. The first IC die 100A may include a metallization stack 102A having a surface 104A orthogonal to another surface 106A. The metallization stack 102A may be connected along an interface 108A to a substrate 110A having an active area 112A. The substrate 110A may have a surface 114A that may be coplanar with the surface 104A. The metallization stack 102A may include a dielectric material and conductive traces 120A through the dielectric material. The conductive traces 120A may be parallel to the surface 106A such that the conductive traces 120A are orthogonal to the surface 104A. Conductive vias 122A through the dielectric material may connect conductive traces 120A to active circuitry in the active area 112A, and one or more conductive vias 122A may extend further through the active area 112A, as shown.Conductive vias 122A are orthogonal to the conductive traces 120A. The conductive traces 120A may extend to the surface 104A such that portions of the conductive traces 120A are exposed on the surface 104A; these exposed portions may form bonding sections 124A.

[0061] The second IC die 100B may include a metallization stack 102B having a surface 104B orthogonal to another surface 106B. The metallization stack 102B may be attached to a substrate 110B having an active area 112B along an interface 108B. The substrate 110B may have a surface 114B that may be coplanar with the surface 104B and the surfaces 104A, 114A. The metallization stack 102B may include a dielectric material and conductive traces 120B through the dielectric material. The conductive traces 120B may run parallel to the surface 106B, such that the conductive traces 120B run orthogonal to the surface 104B. Conductive vias 122B through the dielectric material may connect conductive traces 120B to active circuitry in the active area 112B, and one or more conductive vias 122B may extend further through the active area 112B, as shown. Conductive vias 122B are orthogonal to the conductive traces 120B.The conductive traces 120B may extend to the surface 104B such that portions of the conductive traces 120B are exposed on the surface 104B; these exposed portions may form bonding portions 124B. Conductive vias 122A of the first IC die 100A may be connected to conductive vias 122B of the second IC die 100B by interconnects 305. The interconnects 305 may include any suitable interconnects, such as hybrid interconnects (e.g., bond pads in a dielectric material 115 forming oxide-oxide bonds and metal-metal bonds), as described below with reference to the interconnects 304 in FIG. Fig. 3 described.

[0062] Fig. 1D is a schematic cross-sectional view of another exemplary IC die 100 according to some other embodiments of the present disclosure. The IC die 100 may include a substrate 110 and more than one metallization stack 102. The metallization stack 102A has mutually orthogonal surfaces 104 and 106, as shown in Fig. 1A. The metallization stack 102A is located on the substrate 110 along the interface 108A, which is orthogonal to the surface 104 and parallel to the surface 106. The metallization stack 102A may comprise a dielectric material (e.g., the material described in Fig. 3B) and a plurality of layers of conductive traces 120A in the dielectric material, each layer of conductive traces 120A being parallel to the surface 106 (and to the interface 108A) such that the conductive traces 120A are orthogonal to the surface 104. The metallization stack 102A may also include conductive vias 122A through the dielectric material, the conductive vias 122A being orthogonal to the conductive traces 120A. As in the embodiment of Fig. 1A, bonding portions 124 are arranged on the surface 104, which bonding portions comprise portions of the conductive traces 120A exposed on the surface 104. In various embodiments, the substrate 110 may include a semiconductor material, as described with respect to Fig. 1A and discussed in the previous subsection. In various embodiments, the active region 112A may be disposed in the substrate 110 on a side of the substrate 110 remote from the interface 108A.

[0063] In many embodiments, the IC die 100 may include another metallization stack 102B on the substrate 110 along another interface 108B. In many embodiments, the active area 112A may be located near the interface 108B. The metallization stack 102B may include conductive lines 120B and conductive vias (not labeled to avoid cluttering the drawings) in dielectric material. The metallization stack 102B may be located on another metallization stack 102C along another interface 108C. The metallization stack 102C may include conductive lines 120C and conductive vias (not labeled to avoid cluttering the drawings). The conductive lines 120C may be conductively connected to the conductive lines 120B at the interface 108C by interconnects 128. The interconnects 128 may comprise any suitable interconnect technology for connecting traces / vias in the stack 102B to traces / vias in the stack 102C.For example, in some implementations, the interconnects 128 may include hybrid bond interfaces such that some traces or vias in the stack 102B are directly connected to some traces or vias in the stack 102C.

[0064] The metallization stack 102C may be substantially similar to the metallization stack 102B, except that it may additionally include optical structures 130 of a photonic IC. The metallization stack 102C may, for example, include optical waveguides. The metallization stack 102C may be connected to another active region 112B along another interface 108D by interconnects 305. The interconnects 305 may include any suitable interconnects, such as hybrid bonds (e.g., bond pads in a dielectric material 115 forming oxide-oxide bonds and metal-metal bonds), as described below with reference to the interconnects 304 in Fig. 3. The interfaces 108A-108D may be parallel to each other and orthogonal to the surface 104. The active region 112B may include other optical structures 130 of the photonic circuits, e.g., electromagnetic radiation sources such as lasers and LEDs, and electromagnetic radiation detectors such as electro-optical photodetectors optically coupled to optical waveguides in the metallization stack 102C. The active region 112B may also include electronic circuits that may be connected to the conductive lines 120C in the metallization stack 102C. In many cases, the photonic circuits and the electronic circuits may be made of a suitable material, e.g., as described in the previous subsection with reference to materials suitable for photonic ICs. In various embodiments, at least some optical structures 130 (e.g.,optical fiber) between the active region 112A and the active region 112B.

[0065] The optical structures 130 may include one or more electromagnetic radiation sources that enable the generation of optical signals, e.g., lasers with wavelengths between approximately 0.8 and 1.7 micrometers or oscillators that generate electromagnetic radiation with wavelengths in the millimeter range, or a combination of lasers and oscillators that generate electromagnetic energy with wavelengths between 0.8 micrometers and a few millimeters or centimeters. Other optical structures 130, such as electro-optical devices, may enable the reception, conversion, and transmission of optical signals. In some embodiments, the electro-optical devices may be any devices or components configured to encode information into / onto the electromagnetic signals, such as modulators, polarizers, phase shifters, and photodetectors.

[0066] The optical structures 130 may include waveguides that guide optical signals and can also couple, switch, split, multiplex, and demultiplex optical signals. In some embodiments, the waveguides may include any component configured to inject or launch the electromagnetic signal into the propagation medium, such as an optical fiber. In some embodiments, the waveguides may also be configured as optical multiplexers and / or demultiplexers, for example, to perform frequency division multiplexing (FDM) or wavelength division multiplexing (WDM). In some embodiments, the waveguides may include a demultiplexer, such as an arrayed waveguide grating (AWG) demultiplexer, an echelle grating, a single-mode waveguide, or a thin film filter (TFF) demultiplexer.

[0067] The waveguides may include planar and non-planar waveguides of any type. In one example, the waveguides may include a silicon photonic waveguide based on a silicon-on-insulator (SOI) platform and configured to guide electromagnetic radiation of any wavelength range from about 0.8 micrometers to about 5 centimeters. In another example, the waveguide may support wavelengths from about 1.2 micrometers to about 1.7 micrometers in the near-infrared and infrared ranges for use in data communications and telecommunications. In another example, the waveguides may support wavelengths from about 1 millimeter to about 10 millimeters (extremely high frequency (EHF) band of radio / microwaves), and in particular, wavelengths of about 2 millimeters may be used for radar and wireless radio frequency (RF) communications.

[0068] In general, the light supplied to the optical structures 130 may contain any electromagnetic signals with information encoded therein (or, in other words, any electromagnetic signals modulated to contain information). Often, the electromagnetic signals are signals associated with optical amplitudes, phases, and wavelengths, which is why the descriptions herein refer to "optical" signals (or light) and "optical" components. However, the optical structures 130 described herein are not limited to working with electromagnetic signals of the optical spectrum, and the descriptions given herein with reference to optical signals and / or optical components are equally applicable to electromagnetic signals of any suitable wavelength, such aselectromagnetic signals in the near-infrared (NIR) and / or infrared (IR) band, as well as electromagnetic signals in the RF and / or microwave band.

[0069] In various embodiments, exposed surfaces of one or more optical structures 130 (e.g., optical waveguides) in the metallization stack 102C on a side of the IC die 100 opposite the surface 104 may be configured to be coupled to an optical fiber. In many embodiments, the substrate 110 may also include vias (TSVs) 202 that connect traces 120A in the metallization stack 102A to traces 120B in the metallization stack 102B and / or in the active region 112A. In some embodiments, the optical structures 130 may provide optical connections for signal propagation between circuits in the active region 112A (i.e., intra-die connections). In other embodiments, the optical structures 130 may provide an optical connection for signal propagation between IC dies 100, e.g.,by optical fibers (not shown) connected to the optical structures 130.

[0070] Fig. Figure 2A is a simplified perspective view of an IC die 100. Fig. 2A shows the IC Die 100 of Fig. 1A, which has been rotated 90 degrees so that surfaces 114 and 104 are at the bottom and surface 106 is at the side. The IC die 100 may include a substrate 110, an active area 112, and a metallization stack 102. The IC die 100 may have any suitable dimensions. In various embodiments, the IC die 100 may have a thickness (e.g., z-dimension) between 10 microns and 800 microns (e.g., between 10 microns and 100 microns), a width (e.g., y-dimension) between 1 millimeter and 6 millimeters, and a length (e.g., x-dimension) between 10 millimeters and 33 millimeters. The substrate 110 of the IC die 100 may be thinned to give the IC die 100 the desired thickness.

[0071] Fig. Figure 2B is a simplified perspective view of an IC die 100. Fig. 2B shows the IC die 100 from Fig. 1B, which has been rotated 90 degrees so that the surfaces 114, 104A and 104B are arranged at the bottom and the surfaces 106A, 106B are arranged at the sides. The IC die 100 may include a substrate 110, an active area 112 and metallization stacks 102A, 102B. The IC die 100 may have any suitable dimensions, including those described above with reference to Fig. 2A. The substrate 110 may have any thickness (e.g., the z-dimension). For example, the substrate 110 may have a thickness between less than 1 micrometer and 50 micrometers (e.g., between 0.25 micrometers and 5 micrometers or between 20 micrometers and 50 micrometers). In some embodiments, the substrate 110 may be almost completely removed, so that the TSVs 202 may be very thin (e.g., with a thickness of less than 1 micron) and may make direct contact with a transistor source / drain in the active area 112.

[0072] Fig. Figure 2C is a simplified perspective view of an IC die 100. Fig. 2C shows the IC die 100 from Fig. 1C, which has been rotated 90 degrees so that surfaces 114A, 114B, 104A, and 104B are at the bottom and surfaces 106A, 106B are at the side. The IC die 100 may include substrates 110A, 110B, active areas 112A, 112B, metallization stacks 102A, 102B, and a dielectric 115 with interconnects 305. In various embodiments, the IC die 100 may have a thickness (e.g., z-dimension) between 20 micrometers and 1,600 micrometers (e.g., between 20 micrometers and 200 micrometers), a width (e.g., y-dimension) between 1 millimeter and 6 millimeters, and a length (e.g., x-dimension) between 10 millimeters and 33 millimeters.

[0073] Fig. 2D is a simplified perspective view of an IC die 100. Fig. 2D shows the IC die 100 from Fig. 1D, which has been rotated 90 degrees so that the surfaces 114, 104A, 104B, and 104C are at the bottom and the surfaces 106A, 106B are at the side. The IC die 100 may include a substrate 110, active areas 112A, 112B, and metallization stacks 102A, 102B, 102C. The IC die 100 may have any suitable dimensions, including those described above with reference to Fig. Dimensions described in Figure 2A.

[0074] Fig. 3A-3D show simplified schematic cross-sections of various configurations of a microelectronic assembly 300 according to embodiments of the present disclosure. Fig. 3A shows a microelectronic assembly 300 comprising a plurality of IC dies 100, e.g., 100(1), 100(2), and 100(3), coupled to another IC die 302 by interconnects 304 such that the surface 104 of any one IC die 100 is in direct contact with a surface 306 of the IC die 302. As shown in the Fig. 1-2, the surface 104 is orthogonal to the interface 108 between the active area 112 and the metallization stack 102 of any IC die 100. In some embodiments, the IC dies 100 may include active circuitry (e.g., transistors, diodes) in the active area 112. In other embodiments, one or more IC dies 100 may not include active circuitry in the active area 112; in such embodiments, the active area 112 may be fused to the substrate 110 (e.g., absent).

[0075] In various embodiments, IC die 302 may include an interposer with conductive traces to enable conductive connection of IC die 100 to other IC dies and / or package substrates, and IC die 302 may not include any active circuitry. In other embodiments, IC die 302 may include active circuitry. In many embodiments, IC dies 100 may be conductively connected by conductive paths within IC die 302. For example, IC die 302 may include an on-chip network that interconnects the computational circuitry of IC dies 100. In various embodiments, IC die 100 may be conductively connected to IC die 302 by interconnects 304, which may also include hybrid bonds. In such a configuration, the surface 114 of the substrate 110 of the IC dies 100 may be in direct contact with the surface 306 of the IC dies 302.

[0076] Fig. 3B is a schematic cross-sectional view of a detail of a particular interconnect 304 in the microelectronic assembly 300. Although only the interconnect 304 is depicted, the same structure and description may apply to other such interconnects with hybrid bonds in the microelectronic assembly 300. In general, the interconnect 304 at an interface between the surface 104 of the IC die 100 and the surface 306 of the IC die 302 may include metal-to-metal bonds between the bond portions 124 of the IC die 100 and the bond pads 308 of the IC die 302, as well as dielectric-to-dielectric bonds (e.g., oxide-to-oxide bonds) in the dielectric materials 116 and 310 of the IC dies 100 and 302, respectively. The bonding portions 124 belonging to the IC die 100 can connect to the bonding pads 308 of the IC die 302. As described in the description of Fig. 1, the bonding portions 124 may include a portion of the conductive traces 120 exposed on the surface 104; the bonding pads 308 may include conventional conductive structures electroplated on the surface 306. The dielectric material 116 (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.) in the IC die 100 may bond to a dielectric material 310 in the IC die 302. In some embodiments, the dielectric material 310 of the IC die 302 is the same as the dielectric material 116 of the IC die 100. In various embodiments, the dielectric material 310 includes silicon oxide, silicon nitride, silicon carbonitride, and other such inorganic materials commonly used to fabricate semiconductor IC dies.The interconnected metallic and dielectric materials form a hybrid interconnect 304 that enables electrical and mechanical coupling between the IC die 100 and the IC die 302. In various embodiments, the interconnects 304 may have a linear dimension of less than 5 micrometers and a pitch of less than 10 micrometers between adjacent interconnects.

[0077] Back to Fig. 3A: The IC dies 100 may be coupled to the IC die 302 such that the metallization stack 102 of one of the IC dies 100, e.g., 100(1), may be in direct contact with the substrate 110 of the adjacent IC die 100, e.g., 100(2). In some embodiments, the IC dies 100(1) and 100(2) may be bonded to each other at least by oxide-oxide bonds. In some embodiments, interconnects 304 comprising metal-metal bonds and oxide-oxide bonds may be present at the planar contact interface between the IC dies 100(1) and 100(2), as described with reference to Fig. 3B. In some such embodiments, the conductive contact between the active area 112 of the IC die 100(1) and 100(2) may be achieved by conductive lines 120 in the IC die 100(1), by interconnects 304 at the interface between the IC dies 100(1) and 100(2), and by TSVs 202 in the IC die 100(2); in such embodiments, the TSVs 202 are in conductive contact with the interconnects 304 between the IC dies 100(1) and 100(2). In other embodiments (not shown), the metallization stack 102 of the IC dies 100(1) and 100(2) may be in contact in a front-to-front configuration. In other embodiments (not shown), the substrates 110 of the IC dies 100(1) and 100(2) may be in contact in a back-to-back configuration.

[0078] In various embodiments, the IC dies 100 may be arranged in parallel rows such that a gap 312 exists between adjacent IC dies 100. In some embodiments, the gap 312 may be uniform throughout the microelectronic assembly 300 and on the order of a few millimeters (e.g., less than 5 millimeters); in other embodiments, the gap 312 may be uneven, with some IC dies 100 being closer together than others. In some of these embodiments, the IC dies 100 may include circuitry that consumes electrical power and generates heat during operation. For example, the IC dies 100 may include computing circuitry of a microprocessor. The gap 312 may be configured to allow a cooling fluid to flow therethrough. The cooling fluid (not shown) may be air in some embodiments; in other embodiments, the cooling fluid may be a liquid coolant.

[0079] In some embodiments, IC dies 100 may include computing circuitry, and IC die 302 may include an on-chip network that conductively connects the array of IC dies 100. In some other embodiments, some IC dies 100 may include graphics processing circuitry and other IC dies may include computer circuitry, and IC dies 302 may include memory circuitry. Any suitable circuit configuration may be provided in microelectronic assembly 300 between IC dies 100 and IC dies 302 as desired and based on particular requirements.

[0080] Fig. 3C is a schematic cross-sectional view of a portion 313 of the microelectronic assembly 300 of Fig. 3A according to some embodiments of the present disclosure. The IC die 302 may include a metallization stack 314 attached to a substrate 316 having an active area 318. The substrate 316 is connected to the metallization stack 314 along another interface 320 that is parallel to the surface 306. In some embodiments, the active area 318 includes active circuits (not shown), including transistors and diodes. The active area 318 may be located near the interface 320 in such embodiments. In some embodiments, the active area 318 may not be present. The metallization stack 314 may also include conductive paths (e.g., traces 322 and conductive vias 324) in a dielectric material. In some embodiments, the dielectric material of the metallization stack 314 is the dielectric material 310 in Fig. 3B. The conductive traces 322 can be connected to the bond pads 308 via conductive vias 324.

[0081] Fig. 3D is a schematic cross-sectional view of part 313 of the microelectronic assembly 300 of Fig. 3A according to some embodiments of the present disclosure. The IC die 302 may be substantially similar to the embodiment of Fig. 3C, except that it is flipped (e.g., upside down) so that the substrate 316 is proximate the surface 104 of the IC die 100. In such embodiments, the IC die 302 may include an interface layer 326 (e.g., a bonding layer) on a side of the substrate 316 opposite the metallization stack 314. The interface layer 326 includes bond pads 308 with a dielectric material between the bond pads 308 (e.g., surrounding the bond pads 308), such that the interconnects 304 are formed from metal-to-metal bonds of the bond portions 124 and the bond pads 308 and oxide-to-oxide bonds of the dielectric materials of the substrate 110 of the IC die 100(3) and the interface layer 326 of the IC die 302. In some embodiments, the dielectric material of the interface layer 326 is the same material as the dielectric material 310 in Fig. 3B. In some embodiments, the dielectric material of the interface layer 326 is the same material as the dielectric material 116 of the IC die 100 in Fig. 3B. In various embodiments, the dielectric material of the interface layer 326 may include silicon oxide, silicon nitride, silicon carbonitride, or other inorganic materials commonly used to fabricate semiconductor IC dies. In such embodiments, the IC die 302 may further include TSVs 330 in the substrate 316 between the interface layer 326 and the metallization stack 314. TSVs 330 may enable electrical connection between the interconnects 304 and the active area 318 and / or the conductive lines 322 in the IC die 302.

[0082] Fig. 4A is a simplified perspective view of an exemplary microelectronic assembly 300 incorporating the IC dies 100 of Fig. 2A. For clarity, and to avoid cluttering the drawings, the figures are not drawn to scale, and no detailed features are shown. A plurality of IC dies 100 (e.g., IC dies 100(1), 100(2), and 100(3)) may be coupled to the surface 306 of the IC die 302 at corresponding surfaces 104 (e.g., surfaces 104(1), 104(2), and 104(3)). The plurality of IC dies 100 may be coupled to the IC die 302 by suitable interconnects, e.g., by the interconnects 304 in Fig. 3. In many embodiments, the IC die 302 may be large, for example, as large as a conventional photomask, which may have a footprint of about 850 square millimeters. Although Fig. 4A shows the IC dies 100 with metallization stacks 102(1), 102(2), 102(3) facing away from each other, in some embodiments one or more of the IC dies 100 may have metallization stacks 102 facing each other.

[0083] Fig. 4B is a simplified perspective view of an exemplary microelectronic assembly 300 incorporating the IC dies 100 of Fig. 2B. For clarity, and to avoid cluttering the drawings, the figures are not drawn to scale, and no detailed features are shown. A plurality of IC dies 100 (e.g., IC dies 100(1), 100(2), 100(3), and 100(4)) may be bonded to surface 306 of IC die 302 at respective surfaces 104A, 104B. IC dies 100 may be stacked vertically and bonded together, for example, by oxide-oxide bonds or inorganic dielectric-inorganic dielectric bonds. The stacked and bonded IC dies 100 may be rotated 90 degrees and electrically bonded to IC die 302. The plurality of IC dies 100 may be coupled to the IC die 302 by suitable interconnects, e.g., by the interconnects 304 in Fig. 3. Stacking and bonding the IC dies 100 before coupling them with the IC die 302 can facilitate handling of the IC dies 100 during assembly operations. Any number of IC dies 100 can be stacked and bonded together, for example, between 2 and 100 IC dies. Although Fig. 4B shows the IC dies 100 in a particular stacking arrangement (e.g., all facing in the same direction), in some embodiments, one or more IC dies 100 may have a different stacking arrangement (e.g., one or more IC dies 100 may be reversed to face in an opposite direction). Although Fig. 4B the IC dies 100 from Fig. 1B, a stack of IC dies 100 can contain all IC dies 100 of the Fig. 1A-1D included.

[0084] Fig. Figure 5A is a schematic cross-sectional view of the microelectronic assembly 300 according to some embodiments of the present disclosure. The embodiment shown in the figure is substantially similar to that of Fig. 3A, except that the IC dies 100 are not connected to each other (e.g., at a surface 106) and are separated by gaps 312(1) and 312(2), and the microelectronic assembly 300 further includes voltage regulator (VR) dies 350 (e.g., VR dies 350(1), 350(2), 350(3)) and a package substrate 404. Individual IC dies 100 are coupled to individual VR dies 350 such that each IC die 100 is coupled to a respective VR die 350 and the respective VR die 350 provides regulated power to the respective IC die 100 in a range between 0.2 volts (V) and 2 V.

[0085] The VR die 350 may include electronic components and circuitry for maintaining a constant voltage. For example, the VR die 350 may include a voltage input, a voltage output, an input capacitor, an output capacitor, an inductor, a switching transistor, and / or a diode, as well as a control circuit comprising a plurality of transistors for voltage regulation and for controlling the switching transistor and / or diode. The VR die 350 may be a separate IC die, as shown in Fig. 5A, or it may be integrated into a base die, such as the IC die 302, as shown in Fig. 5B and Fig. 5C. The microelectronic assembly 300 may include a plurality of IC dies 100 and a plurality of VR dies 350, where each VR die 350 regulates the power supply of a corresponding IC die 100 at the same or a different voltage / frequency. In various embodiments, the VR die 350 may include different voltage rails configured to supply power at correspondingly different voltages. The VR die 350 may be manufactured using processes particularly suited for voltage regulator circuits, such as a specialized silicon process or processes that utilize III-V devices, such as gallium nitride or silicon carbide, to support improved power conversion. The VR die 350 may have an active surface (e.g., a first surface) and a back surface (e.g.,an opposite second surface), wherein the active surface comprises a metallization stack and the back surface comprises a substrate.

[0086] The active surface of the VR die 350 may be electrically connected to the IC die 302 by interconnects 304 at a surface 306. The interconnects 304 may include, for example, metal-to-metal interconnects and dielectric-to-dielectric interconnects, as shown in Fig. 3B. In some embodiments, the VR die 350 may be electrically coupled to the IC die 100 by conductive paths 323 through the IC die 302 and interconnects 304 at surface 104 (e.g., as shown for VR 350(1) and 350(2)). In some embodiments, the VR die 350 may be electrically coupled to the IC die by the interconnect 304 at surface 106 (e.g., as shown for VR 350(1) and 350(3)). The side surface of the VR die 350 with the interconnect 304 may also be planarized. The VR dies 350 may be electrically connected to one or more current sources 325 in the package substrate 404 via conduction paths 323 and TSVs 202 through IC die 302 and via interconnects 352. The one or more current sources 325 in the package substrate 404 may be configured to provide unregulated current at 5 V or 2 V.

[0087] The package substrate 404 may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and one or more conductive paths to conduct power, ground, and signals through the dielectric material (e.g., including conductive traces and / or conductive vias, as shown). In some embodiments, the insulating material of the package substrate 404 may be a dielectric material, such as an organic dielectric material, a Class 4 fire-retardant (FR-4) material, BT resin, polyimide materials, glass-reinforced epoxy matrix materials, organic dielectrics with inorganic fillers, or low-k and ultra-low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymeric dielectrics).In particular, if the package substrate 404 is formed using standard printed circuit board (PCB) processes, the package substrate 404 may include FR-4, and the conductive paths in the package substrate 404 may be formed by patterned copper sheets separated by build-up layers of the FR-4. The conductive paths in the package substrate 404 may be enclosed by liner materials, such as adhesive and / or barrier liners, as appropriate. In some embodiments, the package substrate 404 may be manufactured using a lithographically defined via packaging process. In some embodiments, the package substrate 404 may be manufactured using standard organic package manufacturing processes, and thus the package substrate 404 may take the form of an organic package.In some embodiments, the package substrate 404 may be a set of redistribution layers formed on a plate carrier by laminating or spin-coating a dielectric material, with conductive vias and lines created by laser drilling and plating. In some embodiments, the package substrate 404 may be formed on a removable carrier using any suitable technique, such as a redistribution layer technique. Any method known in the art may be used to fabricate the package substrate 404, and for brevity, such methods will not be discussed further here.

[0088] The IC die 302 may be connected to the package substrate 404 via interconnects 352. The interconnects 352 disclosed herein may take any suitable form. When interconnects are described herein, a surface of a first die may include a first set of conductive contacts, and a surface of a second die or package substrate may include a second set of conductive contacts. One or more conductive contacts of the first set may then be electrically and mechanically coupled to some of the conductive contacts of the second set through the interconnects. In some embodiments, a set of interconnects 352 may include solder (e.g., solder pads or balls that undergo thermal reflow to form the interconnects 352).The interconnects 352 containing solder may include any suitable solder material, such as lead / tin, tin / bismuth, eutectic tin / silver, ternary tin / silver / copper, eutectic tin / copper, tin / nickel / copper, tin / bismuth / copper, tin / indium / copper, tin / zinc / indium / bismuth, or other alloys. In some embodiments, a set of interconnects 352 may include an anisotropic conductive material, such as an anisotropic conductive foil or an anisotropic conductive paste. An anisotropic conductive material may include conductive materials dispersed in a non-conductive material. In some embodiments, an anisotropic conductive material may include microscopic conductive particles embedded in a binder or thermosetting adhesive film (e.g., a biphenyl-type thermosetting epoxy resin or an acrylic-based material).In some embodiments, the conductive particles may include a polymer and / or one or more metals (e.g., nickel or gold). For example, the conductive particles may include nickel-coated gold or silver-coated copper coated with a polymer. In another example, the conductive particles may include nickel. If an anisotropic conductive material is not compressed, there may be no conductive path from one side of the material to the other. However, if the anisotropic conductive material is appropriately compressed (e.g., by conductive contacts on both sides of the anisotropic conductive material), the conductive materials may touch each other near the compression region, creating a conductive path from one side of the film to the other in the compression region.

[0089] In some embodiments, some of the interconnects in a microelectronic assembly or IC package, as described herein, may be metal-to-metal interconnects (e.g., copper-to-copper interconnects or plated interconnects). In such embodiments, the conductive contacts on both sides of the interconnect may be bonded together (e.g., under elevated pressure and / or temperature) without the use of intervening solder or an anisotropic conductive material. In some metal-to-metal interconnects, a dielectric material (e.g., silicon oxide, silicon nitride, silicon carbide) may be present between the bonded metals (e.g., between copper pads or posts that form the respective conductive contacts). In some embodiments, one side of an interconnect may have a metal column (e.g., a copper column) and the other side of the bond may have a metal contact (e.g.,a copper contact) embedded in a dielectric. In some embodiments, a metal-to-metal interconnect (e.g., a copper-to-copper interconnect) may include a noble metal (e.g., gold) or a metal whose oxides are conductive (e.g., silver). In some embodiments, a metal-to-metal interconnect may include metal nanostructures (e.g., nanorods), which may have a lower melting point. Metal-to-metal interconnects can reliably conduct higher current than other types of interconnects. For example, some solder joints may form brittle intermetallics when current flows, and the maximum current flowing through such interconnects may be limited to avoid mechanical failure.

[0090] In some embodiments, a thin cap of solder may be used in a metal-to-metal interconnect to accommodate planarity, and this solder may become an intermetallic compound during processing. In some embodiments, the solder used in some of the interconnects may have a higher melting point than the solder in other interconnects. For example, if the interconnects in an IC package are fabricated before other interconnects, a higher temperature solder (e.g., with a melting point above 200 degrees Celsius) may be used for the first-fabricated solder-based interconnects, while a lower temperature solder (e.g., with a melting point below 200 degrees Celsius) may be used for the second-fabricated interconnects. In some embodiments, a high-temperature solder may include tin, tin and gold, or tin, silver, and copper (e.g.,96.5% tin, 3% silver, and 0.5% copper). In some embodiments, a low-temperature solder may contain tin and bismuth (e.g., tin-bismuth eutectic), tin, silver, bismuth, indium, indium and tin, or gallium.

[0091] In some embodiments, the microelectronic assembly 300 may also include an underfill material 127. In some embodiments, the underfill material 127 may extend between the bottom surface of the IC die 302 and the top surface of the package substrate 404 around the associated interconnects 352. The underfill material 127 may be an insulating material, such as a suitable epoxy material. In some embodiments, the underfill material 127 may comprise a capillary underfill, a non-conductive foil (NCF), or a molded underfill. In some embodiments, the underfill material 127 may include an epoxy flux that assists in soldering the IC die 302 to the package substrate 404 as the interconnects 352 are formed, and then polymerizes and encapsulates the interconnects 352.The underfill material 127 may be selected to have a coefficient of thermal expansion (CTE) that mitigates or minimizes the stresses between the IC die 302 and the package substrate 404 that arise from uneven thermal expansion in the microelectronic assembly 300.

[0092] In some embodiments, the microelectronic assembly 300 may also include a circuit board (not shown). The package substrate 404 may be connected to the circuit board by interconnects (not shown) on the underside of the package substrate 404. The interconnects may be any suitable interconnects, including solder balls for a ball grid array, pins in a pin grid array, or lands in a land grid array. The circuit board may be, for example, a motherboard to which other components may be attached. The circuit board may include conductive paths and other conductive contacts to carry power, ground, and signals through the circuit board, as known in the art.In some embodiments, the interconnects may not connect the package substrate 404 to a circuit board, but may instead connect the package substrate 404 to another IC package, an interposer, or other suitable component.

[0093] Fig. Figure 5B is a schematic cross-sectional view of the microelectronic assembly 300 according to some embodiments of the present disclosure. The embodiment shown in the figure is substantially similar to that of Fig. 5A, except that the VR die 350 (e.g., VR dies 350(1), 350(2), 350(3)) is integrated into the IC die 302. The VR die 350 is electrically coupled to the respective IC die 100 by interconnects 304 (e.g., at the interface of surface 104 of the IC die 100 and surface 306 of the IC die 302). The conductive paths 323 in the IC die 302 are not shown to avoid cluttering the drawing.

[0094] Fig. Figure 5C is a schematic cross-sectional view of another microelectronic assembly 300 according to some embodiments of the present disclosure. The embodiment shown in the figure is similar to that of Fig. 5B, except that the IC dies 100 are made of at least Fig. 1B shown embodiments are selected and as in Fig. 4B, and that the microelectronic assembly 300 also includes further stacked IC dies. As shown in Fig. 5C, the IC die 302 may be connected to a stack of other IC dies 402 (e.g., 402(1), 402(2), etc.) such that the IC die 302 is the topmost of the stack of IC dies 402. The bottommost IC die 402 may be connected to the package substrate 404 through interconnects 352. The stack of IC dies 402, including the IC die 302, may include HBM (high-bandwidth memory) circuitry, and the vertically stacked IC dies 100 on the IC die 302 may include compute circuitry that may be directly connected to the HBM circuitry via the interconnects 354 and the TSVs 202 in the IC die 302 and IC die 402. Interconnects 354 may include any suitable interconnects, such as interconnects 304 or interconnects 352, among others. Various other circuit configurations also fall within the broad scope of the embodiments disclosed herein.

[0095] In various embodiments, each of the features described with reference to one of the Fig. 1-5 may be combined with other features to form a package with one or more IC die(s) as described herein, e.g., to form a modified IC die 100 or a modified microelectronic assembly 300. Some such combinations are described above, but further combinations and modifications are possible in various embodiments. Various embodiments described in different figures may be suitably combined depending on the particular requirements within the broad scope of the embodiments. Exemplary procedures

[0096] Fig. 6 is a simplified flowchart illustrating example operations that may be associated with the fabrication of certain embodiments of the microelectronic assembly 300. At 602, IC dies 100 having planarized surfaces 104 and 106 (among other surfaces) may be fabricated. Fabrication of such IC dies 100 may include semiconductor manufacturing techniques known in the art. For example, providing a wafer containing portions of IC dies 100, the portions including a substrate 110 with TSVs 202, coupling the metallization stack 102A to the substrate 110 along the interface 108A, and coupling the metallization stack 102B to the substrate 110 along the interface 108B.

[0097] Accordingly, in some embodiments, such as in Fig. 1B, the conductive lines 120B in the metallization stack 102B may be thicker than the conductive lines 120A in the metallization stack 102A. In some other embodiments (e.g., as shown in Fig. 1D), the metallization stack 102B may additionally include the metallization stack 102C and the active area 112B with optical structures 130. Example operations further include stacking a plurality of wafers, dicing the plurality of wafers into stacks of IC dies 100, planarizing the surfaces 104 orthogonal to the interfaces 108A and 108B, and separating individual IC dies 100 from each stack.

[0098] At 604, the IC die 100 (e.g., a first IC die) may be electrically coupled to the surface 306 of the IC die 302 (e.g., a second IC die) along the respective lateral surface 104 (e.g., a planarized surface orthogonal to surface 106) of the IC die 100 with interconnects 304 comprising metal-to-metal bonds and dielectric-to-dielectric bonds. In various embodiments, the IC die 302 may include an "interposer" IC die that provides conduction paths between the IC die 100 and a package substrate 404 or other component. As shown in Fig. 3, the IC die 302 may include a corresponding substrate 316 attached to a corresponding metallization stack 314 along an interface 320 that is orthogonal to the interfaces 108A and 108B. The IC die 100 may be one of a plurality of IC dies 100 that may be electrically coupled to the surface 306 of the IC die 302.

[0099] At 606, the VR die 350 may be electrically coupled to the surface 306 of the IC die 302 (e.g., the second die) with interconnects 304 including metal-to-metal bonds and dielectric-to-dielectric bonds. In various embodiments, the VR die 350 may include VR circuitry and other components for voltage regulation. In various embodiments, the IC die 302 may provide conduction paths between the IC die 100 and the VR die 350. The VR die 350 may be one of a plurality of VR dies 350 that may be electrically coupled to the surface 306 of the IC die 302. Individual ones of the plurality of IC dies 100 may be electrically coupled to individual ones of the plurality of VR dies 350 through conduction paths in the IC die 302.

[0100] At 608, the VR die 350 may be electrically connected to a power source. For example, a package substrate 404 having a power source or a connection to a power source may be electrically coupled to the IC die 302.

[0101] Fig. 7 is a simplified flowchart illustrating exemplary operations that may be associated with the fabrication of certain embodiments of the microelectronic assembly 300. At 702, IC dies 100 (e.g., first IC dies) having planarized surfaces 104 and 106 (among other surfaces) may be fabricated. The fabrication of such IC dies 100 may be performed using the methods described above with reference to Fig. 6. The IC die 100 may have a first surface, an opposite second surface 106, and a third surface 104 orthogonal to the first and second surfaces. The IC die 100 may further include conductive traces parallel to the first and second surfaces, and the conductive traces are exposed at the third surface 104 (e.g., the side surface) as conductive bond portions 124. The third surface 104 may include conductive bond portions, and the second surface 106 may include first conductive bond pads.

[0102] At 704, a VR die 350 may be fabricated having a fourth surface (e.g., the active surface) with second conductive bond pads and a fifth surface (e.g., a side surface) orthogonal to the fourth surface with third conductive bond pads. The fourth surface and the fifth surface of the VR die 350 may be planarized. The VR die 350 may be connected to the surface 104 of the IC die 100 through interconnects 304, including metal-to-metal bonds and dielectric-to-dielectric bonds. In particular, third conductive bond pads on the fifth surface (e.g., the side surface) of the VR die 350 may be electrically coupled to first conductive bond pads on the second surface 106 of the IC die 100. In various embodiments, the interconnects 304 formed between the IC die 100 and the VR die 350 may provide direct communication paths between the IC die 100 and the VR die 350.The IC die 100 and the VR die 350 may each be one of a plurality of IC dies 100 and VR dies 350. Individual ones of the plurality of IC dies 100 may be electrically coupled to individual ones of the plurality of VR dies 350 by interconnects 304 between third conductive bond pads on the fifth surface of the VR die 350 and first conductive bond pads on the surface 106 of the IC die 100.

[0103] At 706, conductive bond portions on the third surface 104 of the IC die 100 (e.g., first IC die) may be electrically coupled to some of the fourth conductive bond pads on a sixth surface (e.g., surface 306) of the IC die 302 (e.g., second IC die), forming interconnects 304, and second conductive bond pads on the fourth surface (e.g., the active surface) of the VR die 350 may be electrically coupled to some of the fourth conductive bond pads on the sixth surface (e.g., surface 306) of the IC die 302, forming interconnects 304. The interconnects 304 may include metal-to-metal bonds and dielectric-to-dielectric bonds. Individual ones of a plurality of IC dies 100 may be coupled to individual ones of a plurality of VR dies 350, and the plurality of IC dies 100 and the plurality of VR dies 350 may be electrically connected to the surface 306 of the IC die 302.

[0104] At 708, the VR die 350 may be electrically connected to a power source. For example, a package substrate 404 having a power source or a connection to a power source may be electrically coupled to the IC die 302.

[0105] Fig. 8 is a simplified flowchart illustrating exemplary operations that may be associated with the fabrication of certain embodiments of the microelectronic assembly 300. At 802, IC dies 100 (e.g., first IC dies) having planarized surfaces 104 and 106 (among other surfaces) may be fabricated. The fabrication of such IC dies 100 may be performed using the methods described above with reference to Fig. 6. The IC die 100 may have a first surface, an opposite second surface 106, and a third surface 104 orthogonal to the first and second surfaces. The IC die 100 may further include conductive traces parallel to the first and second surfaces and exposed at the third surface 104 (e.g., the side surface) as conductive bond portions 124. The third surface 104 may include conductive bond portions.

[0106] At 804, the IC dies 100 are stacked on the first and second surfaces, and the stacked IC dies 100 are glued together. In some embodiments, the IC dies 100 may be stacked on a carrier, glued together, and then removed from the carrier. The side surface 104 of the IC dies 100 may be planarized before stacking and gluing or planarized after stacking and gluing. In some embodiments, wafers with IC dies 100 may be stacked, glued together, then singulated and planarized.

[0107] At 806, conductive bond portions on the third surfaces 104 of IC dies 100 (e.g., first IC dies) may be electrically coupled to second conductive bond pads on a fourth surface (e.g., surface 306) of IC die 302 (e.g., second IC die), forming interconnects 304. Interconnects 304 may include metal-to-metal bonds and dielectric-to-dielectric bonds. IC die 302 may include a plurality of VR circuits 350, and individual ones of the plurality of IC dies 100 may be electrically coupled to individual ones of the plurality of VR circuits 350.

[0108] At 808, the VR circuit 350 in the IC die 302 may be electrically connected to a power source. For example, a package substrate 404 having a power source or a connection to a power source may be electrically coupled to the IC die 302.

[0109] Although in the Fig. 6 to 8 various processes are shown in a particular order, this is for illustrative purposes only, and the processes described herein may be rearranged and / or repeated as desired. Furthermore, other methods not shown may be performed without departing from the scope of the present disclosure. Furthermore, various of the methods described herein with respect to the Fig. 6-8 may be modified in accordance with the present disclosure to fabricate other microelectronic packages 300 disclosed herein. Although various operations are illustrated once each, they may be repeated any number of times. For example, one or more operations may be performed in parallel to fabricate and test multiple microelectronic packages substantially simultaneously. In another example, the operations may be performed in a different order to reflect the structure of a particular microelectronic package in which one or more substrates or other components described herein may be included.

[0110] In addition, the Fig. 6-8 may be combined or contain more details than described. For example, the processes may be appropriately modified without departing from the scope of the disclosure for IC dies 100 that do not have a semiconductor substrate, but are fabricated on other materials, such as glass or ceramic. Furthermore, the various processes shown and described may also include other manufacturing processes related to the fabrication of other components of the microelectronic assemblies described herein or any devices that include the microelectronic assemblies described herein. The processes described in the Fig. 6 to 8 may include, for example, various cleaning operations, additional surface planarization operations, surface roughening operations, operations for inserting barrier and / or adhesion layers as desired, and / or operations for incorporating the microelectronic packages described herein into or with an IC component, a computing device, or any structure or device. Examples of components and elements

[0111] The housings disclosed here, for example one of the ones in the Fig. 1-5 or other embodiments described herein may be incorporated into any suitable electronic component. Fig. Figures 9 through 11 show various examples of packages, assemblies, and components that may be used with or include the IC packages described herein.

[0112] Fig. Figure 9 is a side cross-sectional view of an exemplary IC package 2200 that may include IC packages in accordance with any of the embodiments disclosed herein. In some embodiments, the IC package 2200 may be a SiP.

[0113] As shown in the figure, the package substrate 2252 may be made of an insulator (e.g., a ceramic, a build-up foil, an epoxy foil with filler particles therein, etc.) and may have conductive paths extending through the insulator between the first surface 2272 and the second surface 2274, or between various locations on the first surface 2272 and / or between various locations on the second surface 2274. These conductive paths may take the form of any interconnect structure including leads and / or vias.

[0114] The package substrate 2252 may include conductive contacts 2263 coupled to the conduction path 2262 via the package substrate 2252 so that the circuits within the die 2256 and / or the interposer 2257 may be electrically connected to various conductive contacts 2264 (or to other devices included in the package substrate 2252, not shown).

[0115] The IC package 2200 may include an interposer 2257 connected to the package substrate 2252 via conductive contacts 2261 of the interposer 2257, first-level interconnects 2265, and conductive contacts 2263 of the package substrate 2252. The first-level interconnects 2265 shown in the figure are solder pads, but any suitable first-level interconnects 2265 may be used, such as solder pads, solder posts, or bond wires.

[0116] The IC package 2200 may include one or more dies 2256 connected to the interposer 2257 via conductive contacts 2254 of the dies 2256, first-level interconnects 2258, and conductive contacts 2260 of the interposer 2257. The conductive contacts 2260 may be coupled to conductive paths (not shown) via the interposer 2257 so that the circuits in the dies 2256 may be electrically connected to various conductive contacts 2261 (or to other devices in the interposer 2257, not shown). The first-level interconnects 2258 shown in the figure are solder pads, but any suitable first-level interconnects 2258 may be used, such as solder pads, solder posts, or bond wires. As used herein, a “conductive contact” may refer to a section of electrically conductive material (e.g.metal) that serves as an interface between different components; conductive contacts can be recessed into, flush with, or extend from a surface of a component and can take any suitable form (e.g., a conductive pad or a socket).

[0117] In some embodiments, the underfill material 2266 may be disposed between the package substrate 2252 and the interposer 2257 around the first-level interconnects 2265, and the mold 2268 may be disposed around the dies 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the mold 2268. Examples of materials that may be used for the underfill material 2266 and the mold 2268 include suitable epoxies. The second-level interconnects 2270 may be connected to the conductive contacts 2264. The second level interconnects 2270 shown in the figure are solder balls (e.g., for a ball grid array (BGA)), but any suitable second level interconnects 2270 may be used (e.g., pins in a pin grid array or pads in a land grid array).Second level interconnects 2270 may be used to connect the IC package 2200 to another component, such as a printed circuit board (e.g., a motherboard), an interposer, or another IC package, as known in the art and as described below with reference to FIG. Fig. 10 discussed.

[0118] In various embodiments, each of the dies 2256 may be a microelectronic assembly 300 as described herein. In embodiments where the IC package 2200 includes multiple dies 2256, the IC package 2200 may be referred to as a multi-chip package (MCP). The dies 2256 may include circuitry that performs any desired function. For example, in addition to the microelectronic assembly 300 described herein, one or more of the dies 2256 may be logic chips (e.g., silicon-based), one or more of the dies 2256 may be memory chips (e.g., HBM), etc. In some embodiments, each of the dies 2256 may be implemented as described with reference to any of the preceding figures. In some embodiments, at least some of the dies 2256 may not include any of the implementations described herein.

[0119] Although the IC package 2200 shown in the figure is a flip-chip package, other package architectures may also be used. For example, the IC package 2200 may be a BGA package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 2200 may be a wafer-level chip scale (WLCSP) package or a panel fan-out (FO) package. Although two 2256 dies are depicted in the IC package 2200, the IC package 2200 may contain any number of 2256 dies. The IC package 2200 may include additional passive components, such as surface-mount resistors, capacitors, and inductors, disposed on the first side 2272 or the second side 2274 of the package substrate 2252 or on either side of the interposer 2257. More generally, the IC package 2200 may include any other active or passive components known in the art.

[0120] In some embodiments, the IC package 2200 may not include an interposer 2257; instead, the dies 2256 may be directly connected to the conductive contacts 2263 on the first surface 2272 through the first level interconnects 2265.

[0121] Fig. 10 is a side cross-sectional view of an IC package 2300 that may include components having one or more microelectronic assemblies 300 in accordance with any of the embodiments disclosed herein. The IC package 2300 includes a number of components disposed on a circuit board 2302 (e.g., a motherboard). The IC package 2300 includes components disposed on a first surface 2340 of the circuit board 2302 and an opposite second surface 2342 of the circuit board 2302; generally, the components may be disposed on one or both surfaces 2340 and 2342. In particular, any suitable one of the components of the IC package 2300 may include any of the one or more microelectronic assemblies 300 in accordance with any of the embodiments disclosed herein; e.g., For example, any of the IC packages discussed below with reference to IC package 2300 may take the form of any of the IC packages discussed above with reference to Fig. 9 discussed embodiments of the IC package 2200.

[0122] In some embodiments, circuit board 2302 may be a printed circuit board with multiple metal layers separated by insulating layers and connected by electrically conductive vias. One or more of the metal layers may be formed in a desired circuit pattern to conduct electrical signals (optionally in conjunction with other metal layers) between components coupled to circuit board 2302. In other embodiments, circuit board 2302 may be a non-PCB package substrate.

[0123] As shown in the figure, in some embodiments, the IC assembly 2300 may include a package-on-interposer structure 2336 connected to the first surface 2340 of the circuit board 2302 via coupling components 2316. Coupling components 2316 may electrically and mechanically couple the package-on-interposer structure 2336 to the circuit board 2302 and may include solder balls (as shown), male and female portions of a socket, an adhesive, an underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0124] The package-on-interposer structure 2336 may include an IC package 2320 connected to the interposer 2304 via coupling components 2318. The coupling components 2318 may take any suitable form depending on the desired functions, such as the forms described above with reference to the coupling components 2316. In some embodiments, the IC package 2320 may be or include the IC package 2200, e.g., as described above with reference to Fig. 9. In some embodiments, IC package 2320 may include at least one microelectronic assembly 300 as described herein. Microelectronic assembly 300 is not specifically illustrated in the figure to avoid cluttering the drawing.

[0125] Although a single IC package 2320 is shown in the figure, multiple IC packages may be coupled to the interposer 2304; additional interposers may also be coupled to the interposer 2304. The interposer 2304 may represent an intermediate package substrate that serves as a bridge between the circuit board 2302 and the IC package 2320. In general, the interposer 2304 may redistribute a connection to a greater distance or redirect a connection to a different connection. For example, the interposer 2304 may couple the IC package 2320 to a BGA of coupling components 2316 to connect it to the circuit board 2302.

[0126] In the embodiment shown in the figure, the IC package 2320 and the circuit board 2302 are mounted on opposite sides of the interposer 2304. In other embodiments, the IC package 2320 and the circuit board 2302 may be mounted on the same side of the interposer 2304. In some embodiments, three or more components may be interconnected using the interposer 2304.

[0127] The interposer 2304 may be formed from an epoxy resin, a glass-fiber-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer 2304 may be formed from alternative rigid or flexible materials, which may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other Group III-V and Group IV materials. The interposer 2304 may include metallic interconnects 2308 and vias 2310, including, but not limited to, TSVs 2306. The interposer 2304 may also include embedded components 2314, including both passive and active components. These components include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD components, and memory components.More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) may also be formed on the interposer 2304. The package-on-interposer structure 2336 may take the form of any of the package-on-interposer structures known in the art.

[0128] In some embodiments, the IC assembly 2300 may include an IC package 2324 coupled to the first surface 2340 of the circuit board 2302 by coupling components 2322. The coupling components 2322 may take the form of any of the embodiments described above with reference to the coupling components 2316, and the IC package 2324 may take the form of any of the embodiments described above with reference to the IC package 2320.

[0129] In some embodiments, the IC assembly 2300 may include a package-on-package structure 2334 connected to the second surface 2342 of the circuit board 2302 via coupling components 2328. The package-on-package structure 2334 may include an IC package 2326 and an IC package 2332 connected together by coupling components 2330 such that the IC package 2326 is disposed between the circuit board 2302 and the IC package 2332. The coupling components 2328 and 2330 may take the form of one of the above-described embodiments of the coupling components 2316, and the IC packages 2326 and / or 2332 may take the form of one of the above-described embodiments of the IC package 2320. The package-on-package structure 2334 may be configured in accordance with any of the package-on-package structures known in the art.

[0130] Fig. 11 is a block diagram of an exemplary computing device 2400 that may include one or more components having one or more IC packages according to any of the embodiments disclosed herein. For example, any suitable components of computing device 2400 may include a microelectronic assembly (e.g., 100) in accordance with any of the embodiments disclosed herein. In another example, one or more of the components of computing device 2400 may include any embodiments of IC package 2200 (e.g., as shown in Fig. 9). In another example, one or more of the components of the computing device 2400 may include an IC device package 2300 (e.g., as shown in Fig. 10 shown).

[0131] The figure illustrates a number of components included in computing device 2400, but one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in computing device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single system-on-chip (SOC) die.

[0132] Furthermore, in various embodiments, computing device 1000 may not include one or more of the components illustrated in the figure, but computing device 1000 may include interface circuitry for coupling to one or more components. For example, computing device 2400 may not include a display device 2406, but may include interface circuitry for the display device (e.g., a connector and driver circuitry) to which display device 2406 may be connected. In another set of examples, computing device 2400 may not include an audio input device 1824 or an audio output device 1808, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 1824 or an audio output device 1808 may be coupled.

[0133] Computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to a device or portion of a device that processes electronic data from registers and / or memories to convert that electronic data into other electronic data that can be stored in registers and / or memories. Processing device 2402 may include one or more DSPs, ASICs, CPUs, GPUs, cryptoprocessors (special-purpose processors that execute cryptographic algorithms in hardware), server processors, or other suitable processing devices. Computing device 2400 may include a memory 2404, which in turn may include one or more storage devices such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g.,Read-only memory (ROM), flash memory, solid-state memory, and / or a hard disk. In some embodiments, memory 2404 includes memory that shares a die with processing device 2402. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0134] In some embodiments, computing device 2400 may include a communications chip 2412 (e.g., one or more communications chips). For example, communications chip 2412 may be configured to manage wireless communication for transmitting data to and from computing device 2400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data through a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated devices do not include wires, although in some embodiments, they may include wires.

[0135] The 2412 communications chip can implement any number of wireless standards or protocols, including, but not limited to, Institute for Electrical and Electronic Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with all amendments, updates, and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16-compliant Broadband Wireless Access (BWA) networks are commonly referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, a certification mark for products that pass conformance and interoperability testing to the IEEE 802.16 standards.The communication chip 2412 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2412 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as other wireless protocols referred to as 3G, 4G, 5G, and beyond. The communication chip 2412 may also operate with other wireless protocols in other embodiments.Computing device 2400 may include an antenna 2422 to enable wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0136] In some embodiments, the communication chip 2412 may manage wired communication, such as electrical, optical, or other suitable communication protocols (e.g., Ethernet). As previously mentioned, the communication chip 2412 may include multiple communication chips. For example, a first communication chip 2412 may be dedicated to shorter-range wireless communication such as Wi-Fi or Bluetooth, and a second communication chip 2412 may be dedicated to longer-range wireless communication such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2412 may be dedicated to wireless communication and a second communication chip 2412 may be dedicated to wired communication.

[0137] Computing device 2400 may include a battery / power supply circuit 2414. Battery / power supply circuit 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of computing device 2400 to a power source (e.g., AC power) separate from computing device 2400.

[0138] Computing device 2400 may include a display device 2406 (or corresponding interface circuitry, as described above). Display device 2406 may include any suitable visual indicator, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0139] Computing device 2400 may include an audio output device 2408 (or corresponding interface circuitry, as described above). Audio output device 2408 may be any device that generates an acoustic signal, such as speakers, headphones, or earphones.

[0140] Computing device 2400 may include an audio input device 2418 (or corresponding interface circuitry, as described above). Audio input device 2418 may include any device that generates a signal representative of sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments with a MIDI output).

[0141] Computing device 2400 may include a GPS device 2416 (or corresponding interface circuitry, as described above). GPS device 2416 may communicate with a satellite-based system and receive the location of computing device 2400, as is known in the art.

[0142] Computing device 2400 may include another output device 2410 (or corresponding interface circuitry, as described above). Examples of other output devices 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0143] Computing device 2400 may include another input device 2420 (or corresponding interface circuitry, as described above). Examples of other input devices 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a Quick Response (QR) code reader, any sensor, or a Radio Frequency Identification (RFID) reader.

[0144] Computing device 2400 may have any desired form factor, such as a portable or mobile computing device (e.g., a cellular phone, a smartphone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computer, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment controller, a vehicle controller, a digital camera, a digital video recorder, or a portable computing device. In some embodiments, computing device 2400 may be any other electronic device that processes data.

[0145] The description of the illustrated embodiments of the disclosure, including what is described in the abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations and examples of the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as will be appreciated by those skilled in the art.

[0146] The following sections describe various examples of the embodiments disclosed herein.

[0147] Example 1 is a microelectronic assembly comprising a first IC die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die having conductive traces parallel to the first and second surfaces, the conductive traces being exposed at the third surface; a second IC die having a fourth surface, the second IC die having voltage regulator circuitry; and a third IC die having a fifth surface, the third surface of the first IC die being electrically coupled to the fifth surface of the third IC die by first interconnects, the fourth surface of the second IC die being electrically coupled to the fifth surface of the third IC die by second interconnects, and the first IC die being electrically coupled to the second IC die by conductive paths in the third IC die.

[0148] Example 2 may include the subject matter of Example 1 and further specify that the first IC die is one of a plurality of first IC dies, the second IC die is one of a plurality of second IC dies, and individual ones of the plurality of second IC dies are electrically coupled to individual ones of the third IC dies by conduction paths in the third IC die.

[0149] Example 3 may include the subject matter of Example 2 and may further specify that the plurality of first IC dies are spaced apart from each other by a gap.

[0150] Example 4 may include the subject matter of any of Examples 1 to 3, wherein the first interconnects and the second interconnects may include metal-to-metal bonds and dielectric-to-dielectric bonds.

[0151] Example 5 may include the subject matter of any of Examples 1-4 and further state that the fifth surface of the third IC die includes conductive contacts and the first interconnects are formed by electrically coupling individual ones of the conductive contacts on the fifth surface of the third IC die to individual ones of the conductive traces exposed on the third surface of the first IC die.

[0152] Example 6 may include the subject matter of any of Examples 1 to 5 and further specify that the second IC die further comprises a sixth surface orthogonal to the second surface, and wherein the sixth surface of the second IC die is electrically coupled to the second surface of the first IC die by third interconnects.

[0153] Example 7 may include the subject matter of Example 6 and further specify that the third interconnects include metal-to-metal bonds and dielectric-to-dielectric bonds.

[0154] Example 8 may include the subject matter of any of Examples 1 to 7 and further specify that the first IC die includes a substrate and a metallization stack having an interface parallel to the first and second surfaces.

[0155] Example 9 may include the subject matter of any of Examples 1 to 8 and further state that the first IC die further includes a substrate and two metallization stacks on each side of the substrate along respective interfaces parallel to the first and second surfaces.

[0156] Example 10 may include the subject matter of Example 9 and further specify that one of the two metallization stacks additionally includes optical structures.

[0157] Example 11 is a microelectronic assembly comprising a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die having a conductive trace parallel to the first and second surfaces, the conductive trace being exposed at the third surface; and a second IC die having a fourth surface with a conductive contact, the second IC die including voltage regulator circuitry, the third surface of the first IC die being electrically coupled to the fourth surface of the second IC die by an interconnect, and the first IC die being electrically coupled to the voltage regulator circuitry in the second IC die.

[0158] Example 12 may include the subject matter of Example 11 and further specify that the first IC die is one of a plurality of first IC dies, that the voltage regulator circuit is one of a plurality of voltage regulator circuits, and that individual ones of the first IC dies are electrically coupled to individual ones of the plurality of voltage regulator circuits.

[0159] Example 13 may include the subject matter of Example 12 and further specify that the plurality of first IC dies are spaced apart from each other by a gap.

[0160] Example 14 may include the subject matter of Example 12 and further specify that the plurality of first IC dies are bonded together at the respective first and second surfaces.

[0161] Example 15 may include the subject matter of any of Examples 11 to 14 and further specify that the interconnect includes a metal-to-metal bond and a dielectric-to-dielectric bond.

[0162] Example 16 may include the subject matter of any of Examples 11 to 15 and further specify that the second IC die further includes a fifth surface opposite the fourth surface, and the microelectronic assembly may further include a package substrate electrically connected to the fifth surface of the second IC die, the package substrate including a power source.

[0163] Example 17 may include the subject matter of any of Examples 11 to 16 and may further specify that the first IC die includes a substrate and a metallization stack having an interface parallel to the first and second surfaces.

[0164] Example 18 may include the subject matter of any of Examples 11 to 16 and further state that the first IC die further includes a substrate and two metallization stacks on each side of the substrate along respective interfaces that are parallel to the first and second surfaces.

[0165] Example 19 is a microelectronic assembly comprising a first IC die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die comprising a substrate and a metallization stack having an interface parallel to the first and second surfaces; a second IC die having a fourth surface and a voltage regulator circuit; and a third IC die having a fifth surface and including conductive paths, the third surface of the first IC die being electrically coupled to the fifth surface of the third IC die by first interconnects, the fourth surface of the second IC die being electrically coupled to the fifth surface of the third IC die by second interconnects, and the first IC die being electrically coupled to the second IC die by the conductive paths in the third IC die.

[0166] Example 20 may include the subject matter of Example 19 and further state that the first IC die is one of a plurality of first IC dies, the second IC die is one of a plurality of second IC dies, and individual ones of the plurality of first IC dies are electrically coupled to individual ones of the second IC dies through the conduction paths in the third IC die.

[0167] Example 21 may include the subject matter of Example 20 and further specify that the plurality of first IC dies are spaced apart from each other by a gap.

[0168] Example 22 may include the subject matter of any of Examples 19 to 21 and further specify that the first interconnects or the second interconnects include metal-to-metal bonds and dielectric-to-dielectric bonds.

[0169] Example 23 may include the subject matter of any of Examples 19 to 22 and further state that the first IC die further includes conductive traces parallel to the first and second surfaces, and that the conductive traces are exposed at the third surface.

[0170] Example 24 may include the subject matter of any of Examples 19-23 and further specify that the second IC die further comprises a sixth surface orthogonal to the fourth surface, and the sixth surface of the second IC die is electrically coupled to the second surface of the first IC die by third interconnects.

[0171] Example 25 may include the subject matter of Example 23 and further state that the first interconnects are formed by electrically coupling individual ones of the conductive traces exposed on the third surface of the first IC die to individual ones of the conductive bond pads on the fifth surface of the third IC die.

Claims

[1] Microelectronic assembly comprising: a first integrated circuit (IC) having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including conductive traces parallel to the first and second surfaces, the conductive traces being exposed at the third surface; a second IC die having a fourth surface, the second IC die including a voltage regulator circuit; and a third IC die having a fifth surface, wherein the third surface of the first IC die is electrically coupled to the fifth surface of the third IC die by first interconnects, the fourth surface of the second IC die is electrically coupled to the fifth surface of the third IC die by second interconnects, and the first IC die is electrically coupled to the second IC die by conduction paths in the third IC die. [2] The microelectronic assembly of claim 1, wherein the first IC die is one of a plurality of first IC dies, the second IC die is one of a plurality of second IC dies, and individual ones of the plurality of second IC dies are electrically coupled to individual ones of the third IC dies by conduction paths in the third IC die. [3] The microelectronic assembly of claim 2, wherein the plurality of first IC dies are spaced apart from each other by a gap. [4] The microelectronic assembly of any one of claims 1 to 3, wherein the first interconnects and the second interconnects comprise metal-to-metal bonds and dielectric-to-dielectric bonds. [5] The microelectronic assembly of any one of claims 1 to 4, wherein the fifth surface of the third IC die comprises conductive contacts and the first interconnects are formed by electrically coupling individual ones of the conductive contacts on the fifth surface of the third IC die to individual ones of the conductive traces exposed on the third surface of the first IC die. [6] The microelectronic assembly of any one of claims 1 to 5, wherein the second IC die further comprises a sixth surface orthogonal to the second surface, and wherein the sixth surface of the second IC die is electrically connected to the second surface of the first IC die by third interconnects. [7] The microelectronic assembly of claim 6, wherein the third interconnects comprise metal-to-metal bonds and dielectric-to-dielectric bonds. [8] The microelectronic assembly of any one of claims 1 to 7, wherein the first IC die further comprises a substrate and a metallization stack having an interface parallel to the first and second surfaces. [9] The microelectronic assembly of any one of claims 1 to 8, wherein the first IC die further includes a substrate and two metallization stacks on each side of the substrate along respective interfaces parallel to the first and second surfaces. [10] The microelectronic assembly of claim 9, wherein one of the two metallization stacks further includes optical structures. [11] Computing device comprising: a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die having a conductive trace parallel to the first and second surfaces, the conductive trace being exposed at the third surface; and a second IC die having a fourth surface with a conductive contact, the second IC die including a voltage regulator circuit, the third surface of the first IC die being electrically coupled to the fourth surface of the second IC die by an interconnect, and the first IC die being electrically coupled to the voltage regulator circuit in the second IC die. [12] The computing device of claim 11, wherein the first IC die is one of a plurality of first IC dies, the voltage regulator circuit is one of a plurality of voltage regulator circuits, and individual ones of the first IC dies are electrically coupled to individual ones of the plurality of voltage regulator circuits. [13] The computing device of claim 12, wherein the plurality of first IC dies are spaced apart by a gap. [14] The computing device of claim 12, wherein the plurality of first IC dies are interconnected at a first and second surface, respectively. [15] The computing device of any of claims 11-14, wherein the interconnect comprises a metal-to-metal bond and a dielectric-to-dielectric bond. [16] The computing device of any of claims 11-15, wherein the second IC die further comprises a fifth surface opposite the fourth surface, and the computing device further comprises: a package substrate electrically connected to the fifth surface of the second IC die, the package substrate containing a power source. [17] The computing device of any of claims 11 to 16, wherein the first IC die further comprises a substrate and a metallization stack having an interface parallel to the first and second surfaces. [18] The computing device of any of claims 11-16, wherein the first IC die further includes a substrate and two metallization stacks on each side of the substrate along respective interfaces parallel to the first and second surfaces. [19] Package for an integrated circuit (IC), comprising: a first IC die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die comprising a substrate and a metallization stack having an interface parallel to the first and second surfaces; a second IC die having a fourth surface and a voltage regulator circuit; and a third IC die having a fifth surface and including conductive paths, wherein the third surface of the first IC die is electrically coupled to the fifth surface of the third IC die by first interconnects, the fourth surface of the second IC die is electrically coupled to the fifth surface of the third IC die by second interconnects, and the first IC die is electrically coupled to the second IC die by the conductive paths in the third IC die. [20] The IC package of claim 19, wherein the first IC die is one of a plurality of first IC dies, the second IC die is one of a plurality of IC dies, and individual ones of the plurality of first IC dies are electrically connected to individual ones of the second IC dies via the conductive paths in the third IC die. [21] The IC package of claim 20, wherein the plurality of first IC dies are spaced apart from each other by a gap. [22] The IC package of any one of claims 19 to 21, wherein the first interconnects or the second interconnects comprise metal-to-metal bonds and dielectric-to-dielectric bonds. [23] The IC package of any of claims 19-22, wherein the first IC die further includes conductive traces parallel to the first and second surfaces, and the conductive traces are exposed at the third surface. [24] The IC package of any of claims 19-23, wherein the second IC die further comprises a sixth surface orthogonal to the fourth surface, and the sixth surface of the second IC die is electrically connected to the second surface of the first IC die by third interconnects. [25] The IC package of claim 23, wherein the first interconnects are formed by electrically coupling individual ones of the conductive traces exposed on the third surface of the first IC die to individual ones of the conductive bond pads on the fifth surface of the third IC die.

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