Reinforcement learning for a traffic simulation

Abstract

In various examples, a traffic model containing one or more traffic scenarios can be generated and / or updated based on the use of human feedback. Human feedback can indicate a preference for different traffic scenarios to identify which scenarios are more realistic in a model. A reward model can capture this preference information and rank the realism of one or more traffic scenarios.

Description

TECHNICAL AREA

[0001] At least one embodiment relates to processing resources used to generate and update one or more traffic models based on human feedback, which are connected to an autonomous machine. For example, at least one embodiment relates to using human preference information for one or more traffic scenarios to generate a traffic model that can be used by an autonomous vehicle to navigate in an environment. BACKGROUND

[0002] The costs and risks of conducting real-world tests for autonomous machines are considerable. Developers of autonomous machines often rely on simulations to test the reliability of various systems within an autonomous machine. For example, testing and / or controlling an autonomous vehicle may involve simulating various traffic conditions the autonomous vehicle might encounter. Accurately and effectively simulating realistic traffic models is challenging, as it requires striking a balance between the realism of the simulation and the diversity of situations represented. Creating realistic traffic models is essential to ensure that insights gained from simulation tests can be seamlessly applied to real-world scenarios.

[0003] Conventional methods for generating realistic traffic models have limited capabilities when it comes to capturing human preferences for realistic scenarios in traffic simulations. These methods rely on predefined rules or statistical models that are unable to capture the wide range of human preferences and subjective perceptions of realistic traffic scenarios. Furthermore, conventional methods make it difficult to create consistent and diverse traffic simulation models, as traffic simulation encompasses a multitude of models, each with its own specific characteristics, limitations, underlying assumptions, data requirements, and / or algorithms, making it challenging to effectively incorporate human preferences. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 shows an example of a traffic simulation system according to at least one embodiment; Fig. 2 shows an example of training a traffic model in accordance with at least one embodiment; Fig. Figure 3 shows an example of generated traffic scenarios in accordance with at least one embodiment; Fig. 4 shows an example of capturing feedback for a scenario according to at least one embodiment; Fig. Figure 5 shows an example of a method for updating a reward model in accordance with at least one embodiment; Fig. Figure 6 shows an example of a method for generating a traffic model according to at least one embodiment; Fig. Figure 7 shows an example of a processor according to at least one embodiment; Fig. 8A illustrates a logic according to at least one embodiment; Fig. 8B illustrates a logic according to at least one embodiment; Fig. Figure 9 illustrates the training and use of a neural network according to at least one embodiment; Fig. Figure 10 shows an example of a data center system according to at least one embodiment; Fig. Figure 11A shows an example of an autonomous vehicle according to at least one embodiment; Fig. Figure 11B shows an example of camera positions and fields of view for the autonomous vehicle of Fig. 11A according to at least one embodiment; Fig. Figure 11C is a block diagram illustrating an example system architecture for the autonomous vehicle of Fig. 11A illustrated according to at least one embodiment; Fig. 11D is a diagram that represents a system for communication between one or more cloud-based servers and the autonomous vehicle. Fig. 11A represents at least one embodiment; Fig. 12 is a block diagram illustrating a computer system according to at least one embodiment; Fig. 13 is a block diagram illustrating a computer system according to at least one embodiment; Fig. 14 illustrates a computer system according to at least one embodiment; Fig. 15 illustrates a computer system according to at least one embodiment; Fig. 16A illustrates a computer system according to at least one embodiment; Fig. 16B shows a computer system according to at least one embodiment; Fig. 16C illustrates a computer system according to at least one embodiment; Fig. Figure 16D shows a computer system according to at least one embodiment; Fig. 16E and Fig. Figure 16F illustrates a common programming model according to at least one embodiment; Fig. Figure 17 shows exemplary integrated circuits and associated graphics processors according to at least one embodiment; Fig. Figures 18A-18B illustrate exemplary integrated circuits and associated graphics processors according to at least one embodiment; Fig. Figures 19A-19B illustrate an additional exemplary graphics processor logic according to at least one embodiment; Fig. 20 illustrates a computer system according to at least one embodiment; Fig. 21A illustrates a parallel processor according to at least one embodiment; Fig. 21B illustrates a partition unit according to at least one embodiment; Fig. 21C illustrates a processing cluster according to at least one embodiment; Fig. 21D illustrates a graphics multiprocessor according to at least one embodiment; Fig. Figure 22 illustrates a system of a multi-graphics processing unit (GPU) according to at least one embodiment; Fig. 23 illustrates a graphics processor according to at least one embodiment; Fig. 24 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment; Fig. Figure 25 illustrates a processor for deep learning applications according to at least one embodiment; Fig. Figure 26 is a block diagram illustrating an exemplary neuromorphic processor according to at least one embodiment; Fig. 27 illustrates at least sections of a graphics processor according to one or more embodiments; Fig. 28 illustrates at least sections of a graphics processor according to one or more embodiments; Fig. 29 illustrates at least sections of a graphics processor according to one or more embodiments; Fig. 30 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment; Fig. 31 is a block diagram of at least portions of a graphics processor core according to at least one embodiment; Fig. Figures 32A-32B show, according to at least one embodiment, a thread execution logic comprising an arrangement of processing elements of a graphics processor core; Fig. 33 illustrates a parallel processing unit (“PPU”) according to at least one embodiment; Fig. Figure 34 illustrates a general processing cluster (“GPC”) according to at least one embodiment; Fig. Figure 35 illustrates a storage partition unit of a parallel processing unit (“PPU”) according to at least one embodiment; Fig. Figure 36 illustrates a streaming multiprocessor according to at least one embodiment; Fig. Figure 37 is an example of a data flow diagram for an advanced data processing pipeline according to at least one embodiment; Fig. Figure 38 is a system diagram for an exemplary system for training, adapting, instantiating and deploying machine learning models in an advanced data processing pipeline according to at least one embodiment; Fig. 39 shows an exemplary representation of an advanced data processing pipeline 3810A for processing image data according to at least one embodiment; Fig. 40A, according to at least one embodiment, includes an exemplary data flow diagram of a virtual instrument supporting an ultrasound device; Fig. According to at least one embodiment, 40B includes an exemplary data flow diagram of a virtual instrument that supports a CT scanner; Fig. Figure 41A shows a data flow diagram for a method for training a machine learning model according to at least one embodiment; and Fig. According to at least one embodiment, 41B is an exemplary representation of a client-server architecture for improving commenting tools with pre-trained commenting models. DETAILED DESCRIPTION

[0004] Embodiments of the present disclosure relate to reinforcement learning for traffic simulations. Systems and methods are disclosed that employ reinforcement learning with human preference (RLHF) to improve the realism of existing traffic models. Models using RLHF are intended to capture the nuances of human preferences regarding realism and to unify different traffic models in order to provide traffic models that are well-suited to human preferences regarding realism.

[0005] Unlike conventional systems, this revelation offers a three-stage framework that leverages human feedback to improve traffic models for the generation of realistic scenarios. The framework enables realistic traffic simulation using reinforcement learning with human feedback (RLHF) and an autoregressive backbone model. The presented methods can utilize human feedback to capture human preferences regarding the realism of traffic models based on language models, such as large language models (LLMs), or to refine a wide range of traffic models. A variety of different traffic simulation models can be unified via a universal interface for inputting reward models.For example, an autoregressive backbone model with a preferred roll-out length is revealed to optimize the simulation of near-future events in order to generate realistic trajectories that correspond to human preferences. In this way, traffic models can be created that reduce unrealistic collisions or off-road driving. The presented approaches determine the realism in traffic models using one or more reward models that quantify realism in accordance with human preferences, effectively improving the realism of a wide range of existing traffic models. Traffic models can be trained to enable one or more autonomous machines (e.g., autonomous vehicles) to navigate an environment, using a traffic model to provide one or more control inputs to the autonomous machine (e.g., steering, steering, etc.).for the vehicle 1100 in the . Fig. 11A-D).

[0006] Referring to Fig. 1 is Fig. Figure 1 is an example of a traffic simulation system 100 (“System 100”) corresponding to some embodiments of the present disclosure. It is clear that this and other arrangements described herein are presented only as examples. Other arrangements and elements (e.g., machines, interfaces, functions, arrays, functional groups, etc.) may be used in addition to or instead of those shown, and some elements may be omitted entirely. Furthermore, many of the elements described herein are functional units that may be implemented as single or distributed components, or in conjunction with other components, in any suitable combination and at any suitable location. Various functions described herein, which are performed by units, may be executed by hardware, firmware, and / or software.For example, different functions can be performed by a processor that executes instructions stored in memory.

[0007] The system 100 can comprise a traffic simulation device 102 (“device 102”) and / or a network 108. The device 102 can comprise one or more feedback collectors 106, one or more models 110, a reward modeler 112, a fine-tuning module 114, a processor 140, a storage device 142, and / or a communication manager 122. In at least one embodiment, the system 100 is configured to capture one or more traffic scenes of a traffic model, to capture preference data indicating the realism of the one or more traffic scenes, to capture a reward value, at least partially based on the preference data, to compute the traffic model using the reward value, and / or to move an autonomous vehicle based on the update of the traffic model.

[0008] In at least one embodiment, a module comprises any combination of any type of logic (e.g., software, hardware, firmware) and / or circuits configured to perform a function as described. In at least one embodiment, a module comprises one or more circuits that are part of a larger system (e.g., an integrated circuit (IC), a system-on-a-chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), etc.). In at least one embodiment, a control unit comprises any combination of any type of logic (e.g., software, hardware, firmware) and / or circuits configured to perform a function as described. In at least one embodiment, the software comprises software packages, code, programming languages, drivers, instructions, instruction sets, or a combination thereof.In at least one embodiment, the hardware comprises hard-wired circuits, programmable circuits, state machine circuits, fixed-function circuits, execution units, firmware with stored instructions that are executed by programmable circuits, or a combination thereof.

[0009] In at least one embodiment, a logic unit comprises firmware logic, hardware logic, or a combination thereof, configured to provide any function as described herein. In at least one embodiment, a logic unit comprises circuitry that is part of a larger system (e.g., IC, SoC, CPU, GPU, DPU). In at least one embodiment, a logic unit comprises logic circuitry for implementing firmware and / or hardware.

[0010] In at least one embodiment, a machine comprises a module and / or a logic unit as further described herein. In at least one embodiment, a component comprises a module and / or a logic unit as further described herein. In at least one embodiment, a machine comprises software logic, firmware logic, hardware logic, or a combination thereof, configured to provide any function as further described herein. In at least one embodiment, a component comprises software logic, firmware logic, hardware logic, or a combination thereof, configured to provide any function as described herein.In at least one embodiment, operations performed by the hardware and / or firmware can alternatively be implemented via a software module, which may be designed as a software package, code, and / or instruction set. In at least one embodiment, a logic unit can also use a portion of the software to implement its function.

[0011] In at least one embodiment, terms such as "module" and nominalized verbs (e.g., feedback collector 106, reward modeler 112, fine-tuning module 114, communication manager 122, processor 140 and / or other terms), as used in each implementation described herein, refer to any combination of software logic, firmware logic, hardware logic and / or circuitry designed to provide the functionality described herein, unless otherwise indicated by the context or expressly stated.In at least one embodiment, software can be structured as a software package, code, and / or instruction set or instructions, and "hardware" as used in each implementation described herein can include, for example, individually or in any combination, hardwired circuits, programmable circuits, state machine circuits, fixed-function circuits, execution units, and / or firmware that stores instructions executed by programmable circuits. In at least one embodiment, modules can be implemented collectively or individually as circuits that are part of a larger system, such as an integrated circuit (IC), a system-on-chip (SoC), and so on.

[0012] In at least one embodiment, the device 102, the feedback collector 106, the reward modeler 112, the model(s) 110, the fine-tuning module 114, the communication manager 122, and the processor 140 communicate with each other via a connection (not shown), for example, a bus. In at least one embodiment, the processor 140 is implemented, for example, by a central processing unit (“CPU”), one or more microprocessors, one or more microcontrollers, one or more graphics processing units (“GPU(s)”), one or more data processing units (“DPU(s)”), and / or other components. In at least one embodiment, the storage device 142 comprises a memory (e.g.,one or more non-volatile, processor-readable media) in which processor-executable instructions are stored which, when executed by the processor 140 of the device 102, implement the feedback collector 106. In at least one embodiment, the storage device 142 comprises a memory (e.g., one or more non-volatile, processor-readable media) that stores processor-executable instructions which, when executed by the processor 140, access one or more traffic scenes of a traffic model, access preference data specifying a realism of the one or more traffic scenes, calculate a reward value at least partially based on the preference data, update the traffic model using the reward value, and / or move an autonomous vehicle based on the update of the traffic model.

[0013] In at least one embodiment, further non-restrictive examples include the implementation of memory (e.g., one or more non-volatile media readable by a processor), for example, using volatile memory (e.g., dynamic random access memory (“DRAM”)) and / or non-volatile memory (e.g., a hard disk, a solid-state device (“SSD”), and / or another component).

[0014] In at least one embodiment, the communication manager 122 can include one or more components and functions for communication over one or more networks, such as network 108. In at least one embodiment, the communication manager 122 is configured to communicate over any number of the networks described herein.

[0015] In at least one embodiment, the communication manager 122 is configured to manage communications received by its respective system (e.g., requests, queries, data, etc.) and / or provided by a respective system (e.g., requests, queries, data, etc.), such as between any device 102 and / or other components that may be included in the system 100. In at least one embodiment, the communication manager 122 can manage communication within a respective system.

[0016] In at least one embodiment, the system 100 comprises one or more processors, such as the processor 140. In at least one embodiment, the system 100 comprises a different number of processors (e.g., more than one processor 140) and / or one or more other suitable components (e.g., one or more user interface components and / or one or more other components), which are not shown for clarity. In at least one embodiment, the processor 140 is a processor as described below.

[0017] In at least one embodiment, the components of the system 100 communicate via one or more networks, such as the network 108 and / or other network types described herein. The network 108 comprises one or more networks of any number of network types. In some examples, the network 108 comprises a cellular network and / or the Internet.

[0018] As in Fig. As shown in Figure 1, these components involve data acquisition, which includes gathering information about human preferences regarding realism using a mix of real traffic scenes and those generated by traffic models; reward model training, which involves training a model capable of evaluating the realism of a traffic scenario based on human preferences; and fine-tuning, in which the model is harmonized with the reward model trained in the previous stage. In this way, a wide range of traffic models can generate more authentic traffic scenarios. Formulation of a traffic simulation

[0019] The model(s) 110 can comprise one or more models containing data that represent one or more traffic scenes and / or traffic scenarios. A traffic scenario describes the position and movement of one or more vehicles and / or objects in an environment. A traffic scenario can be represented by a traffic simulation that specifies how vehicles and / or objects move within an environment. A traffic simulation problem can be formulated in various ways. For example, in a scenario with M vehicles, the vehicles can be in a state (which includes, for example, a position x, y, a velocity, and a direction) at time step t, which is known as st=[st1,…,stM], can be represented, whereby sti=(xti,yti,zti,θti) applies, and an action (i.e., control) is considered at=[at1,…,atM] exhibiting, whereby ati=(v˙t,θt) (Acceleration and rate of change of direction) applies. In such an example, c = (I, s t-Thist:t+1 ) a decision-relevant context that provides semantic maps for all agents I = I 1 , ..., I M as well as their current and T hist previous states s t-Thist:t+1 = s t-Thist , ...s t includes. In some examples, the state s t+1 derived at time t + 1 from a transition function f, which s t+1 = f(s t , α t ) taking into account the previous state s t and the control α t , which follows a unicycle dynamic, is calculated. Collection of human feedback

[0020] The feedback collector 106 has one or more components designed to collect or otherwise capture feedback information associated with the model(s) 110. The system 100 compares human preferences with generated traffic scenarios under identical initial conditions. Since all trajectories in the simulation are collected using existing traffic models (e.g., from model(s) 110), a considerable amount of data can be generated and iteratively improved. For example, any person with driving experience can act as an identifier after a brief introduction to the user interface, so no specialized expertise is required. To obtain human feedback, pairs of traffic scenarios (S1, S2) are generated from the same context c. Each scenario Si=[St−Thist:t+Tfut]i,i=1,2 represents collected sequences of states of length T futHuman commentators or markers are shown videos of these paired traffic scenarios, with maps and vehicles appropriately marked. The commentators are then asked to indicate which scenario appears more realistic. In at least one embodiment, human commentators (e.g., markers) can be tasked with creating a ranking or order of one or more traffic scenarios based on perceived realism and / or other suitable criteria of the traffic scenarios.

[0021] In a traffic model such as model(s) 110, the total number of generated traffic scenarios can be increased to improve the probability of generating at least one realistic scenario. The feedback collector 106 generates N traffic scenarios S1, ···, S Nand asks human commentators to select the most realistic scenario from the set. This procedure results in N - 1 scenario pairs with preference relationships (S). i > S j ), where S i the scenario chosen by the human commentator is and S j any other scenario. In cases where the traffic model cannot generate realistic scenarios, commentators have the option to state that none of the presented scenarios appear realistic. If this option is selected, the Ground Truth scenario will be used. gt used as the preferred scenario, which is referred to as (S gt > S j ) is referred to. Reward modeling

[0022] The reward modeler 112 comprises one or more components configured to generate and update a reward model for the model(s) 110. For example, the reward modeler 112 can maintain a reward model used to calculate a reward value. In at least one embodiment, a reward model r HF (.; ϕ) is applied to two traffic scenarios generated under the same initial conditions and compared to calculate a loss used to train the reward model. In some examples, the following loss is calculated by the reward modeler 112: lRM=ES1,S2∼D[−logσ(rHF(S1;ϕ)−rHF(S2;ϕ))],S1≻S2 where r HF( S1; ϕ) represents the reward model. The training dataset can be compiled using human preferences in conjunction with one or more traffic scenarios generated with one or more traffic models (e.g., without any enhancements). In some examples, the reward model r HF In one or more other examples, the reward model may be an autoregressive model, while in one or more other examples, it may be an encoder-decoder model that uses a fixed-length sequence. In at least one embodiment, the reward model is an autoregressive model that can take any sequence length as input. To calculate the reward, an average of the reward values ​​over a sequence S is used. i calculated.

[0023] The Reward Modeler 112 can manage one or more reward models parameterized with a CTG encoder and fully connected neural networks for the output layer. This selection of inputs for a reward model can serve as a universal module applicable to any traffic scenario. The choice of the exemplary reward model is not limited, and other models and / or variations can also be implemented.

[0024] A reward model can be evaluated by the reward modeler 112 using the collected human preference data (e.g., generated by the feedback collector 106). This evaluation involves comparing the reward values ​​with the human preferences. For example, the collected human preferences can be divided into a training and a validation subset, comprising 400 and 100 units, respectively. In at least one embodiment, the accuracy of the reward model converges with increasing sample size. Fine-tuning of the traffic model

[0025] The fine-tuning module 114 has one or more components configured to adapt the model(s) 110. In at least one embodiment, the fine-tuning module 114 is configured to achieve a target: r̃ = r + α · r HF(S), optimized, where r is the initial loss for training the provided traffic model and α is a scaling term. For RLHF to train large language models (LLMs), the majority of the model parameters can be frozen for computational reasons.

[0026] The model(s) 110 can be trained using one or more training datasets. A dataset can comprise a comprehensive compilation of real-world driving data and recorded vehicle trajectories from two unique settings, encompassing a wide variety of driving scenarios, including high-traffic situations. A training portion of a dataset can be used for data acquisition, reward model training, and traffic model fine-tuning. The traffic model's performance can be evaluated using a randomly selected subset of 100 scenes from the validation portion of one or more training datasets.

[0027] The stability (i.e., the avoidance of collisions and off-road driving) and realism of the trajectories generated by each model can be assessed by specifying the failure rate, measured as the average percentage of agents (e.g., vehicles) that experience a critical failure (i.e., a collision or off-road driving) in a traffic scenario. In some embodiments, realism is assessed by comparing data statistics between the generated traffic simulations and the actual trajectories from the dataset by calculating the Wasserstein distance between their normalized histograms of driving profiles. Realism can be measured using the realism deviation, which is the average of the realism values ​​for three properties: magnitude of longitudinal acceleration, magnitude of lateral acceleration, and jerk.The reward model naturally captures human preference, which is measured using the reward value (reward) with the help of the reward modeler 112.

[0028] Fig. Figure 2 is an example of training a traffic model (“Training 200”) in accordance with at least one embodiment. The Training 200 may include one or more feedback collections 202, reward modeling 204, and / or model fine-tuning 206. Furthermore, Fig. 2. Examples relating to System 100 of Fig. 1 described. In at least one embodiment, one or more traffic scenes 208 can contain one or more traffic scenarios. In the feedback collection 202, the traffic scenes 208 are grouped into one or more sets of scenario pairs 210. The scenario pairs 210 can be used to generate one or more feedback relationships 212. For example, one or more traffic scenarios can be indicated as more realistic based on human preference data, which represent feedback relationships 212 between the scenarios in each pairing. The feedback relationships 212 can be used by the reward modeling 204 to update a reward model 214 by calculating one or more reward values. During model fine-tuning 206, one or more traffic scenarios 218 can be selected from the traffic model 216 and applied to the reward model 214.In some examples, the reward model 214 is first trained by the reward model 204. The reward model 214 can be used to calculate reward values ​​220, which are used by training targets 222 to evaluate the realism of the traffic scenarios 218. The traffic model 216 can be updated using the reward values ​​220 to improve the realism of the traffic scenarios 218.

[0029] Fig. Figure 3 shows an example of generated traffic scenarios 300 in accordance with at least one embodiment. The generated traffic scenarios 300 may include a simulated roadway 302. The simulated roadway 302 may represent one or more road configurations, such as an intersection, a highway, an on / off ramp, a motorway junction, a merging lane, an entrance, a parking area, and / or another environment suitable for use by human, biological (e.g., animals and / or other organisms), and / or vehicle traffic (e.g., bicycles, autonomous vehicles, semi-autonomous, and / or non-autonomous vehicles). The simulated roadway 302 may correspond to metadata specifying one or more features associated with the simulated roadway 302, such as:Road type, region, geographical information, speed information, historical traffic information, intersection control scheme and / or other features suitable for describing a roadway.

[0030] The simulated roadway 302 may contain one or more representations of one or more objects that navigate in conjunction with or are otherwise located on the simulated roadway 302. For example, the simulated roadway 302 may contain representations of one or more vehicles, such as vehicle 304A, vehicle 304B, vehicle 304C, vehicle 304D, and / or vehicle 304E (referred to here individually and / or collectively as "Vehicles 304"). In some examples, the objects represented in conjunction with the simulated roadway 302 may also include one or more pedestrians, structures, and / or other obstacles.

[0031] Objects represented in the generated traffic scenarios 300 can have one or more associated trajectories (e.g., trajectory paths) by which an object can navigate or otherwise move on the simulated roadway 302. For example, the vehicle 304A can have one or more trajectories, such as trajectory 306A and / or trajectory 306B, each representing a possible scenario for the navigation of the vehicle 304A on the simulated roadway 302. In at least one embodiment, one or more scenarios of a vehicle navigating on the simulated roadway 302 can be generated or otherwise retrieved and made available to one or more human commentators (e.g., using the feedback collector 106 of Fig. 1) These human commentators can select the most realistic scenario from a set of one or more scenarios. In some examples, the human commentators can rank or otherwise order one or more scenarios from a set of scenarios based at least partially on the perceived realism of the one or more scenarios by the human commentators. For example, a first traffic scenario associated with trajectory 306A and a second traffic scenario associated with trajectory 306B may be provided to a commentator who selects the scenario corresponding to trajectory 306A as more realistic than the scenario corresponding to trajectory 306B because trajectory 306B leaves the roadway (which, while not an impossible scenario, may be perceived as less realistic by a human commentator).One or more scenarios selected by human commentators can be (e.g., using the reward modeler 112 and / or the fine-tuning module 114 from . Fig. 1) can be used to implement one or more traffic models, such as model(s) 110 from Fig. 1, to update.

[0032] Fig. Figure 4 is an example of a collection of 400 scenario feedbacks in accordance with at least one embodiment. The collection of scenario feedbacks is exemplified using System 100. Fig. 1 described. The scenario feedback collection 400 can include a feedback collection 404 that accesses one or more traffic scenarios, such as a scenario 402A, a scenario 402B, and / or a scenario 402C (here individually and / or collectively referred to as "Scenarios 402"). In at least one embodiment, the Scenarios 402 can represent one or more traffic scenarios. For example, each of the Scenarios 402 can represent one or more trajectories that one or more objects (e.g., vehicles) can use to navigate in an environment, such as a roadway. The Scenarios 402 can be made available to the feedback collection 404 as a scenario set 410.

[0033] Scenario set 410 can be made available to one or more commentators. In at least one embodiment, one or more commentators can select a scenario from scenario set 410 that they determine to be the most realistic scenario in the set. In at least one embodiment, one or more commentators can also select a ranking of one or more scenarios from scenario set 410 based on determining a level of realism for the scenarios. This selection and / or ranking of the scenarios in scenario set 410 is used to determine one or more feedback relationships 412 between the scenarios in scenario set 410. The feedback relationships 412 can be used to determine the most realistic scenario 420 based on the provided commentator feedback.For example, based on feedback from one or more commentators (e.g., using the feedback collection 404), scenario 402B can be identified as the most realistic scenario 420, since it may be perceived as more realistic than scenario 402A or scenario 402C. The feedback relationships 412 can be used to update a reward model (e.g., using the reward modeler 112). Fig. 1) and / or a traffic model (e.g. to update model(s) 110 using the fine-tuning module 114 from Fig. 1) be used.

[0034] Referring to Fig. Each block of the Method 500 described herein comprises a computational process that can be performed using any combination of hardware, firmware, and / or software. For example, various functions can be performed by a processor executing instructions stored in memory. The methods can also be stored as computer-usable instructions on computer storage media. The methods can be provided by a standalone application, a service, a hosted service (standalone or in combination with another hosted service), or a plug-in for another product, to name just a few. Furthermore, Method 500 is exemplified using the traffic simulation system of Fig. 1 described. However, these procedures can additionally or alternatively be performed by any system or any combination of systems, including, but not limited to, the systems described here.

[0035] Fig. Figure 5 is a flowchart showing a method 500 for updating a reward model in accordance with some embodiments of the present disclosure. Method 500 includes, in block B502, the detection of one or more traffic scenes. For example, one or more traffic scenes and one or more traffic scenarios can be accessed by the model(s) 110 of Fig. 1 can be accessed.

[0036] Procedure 500, in block B504, includes receiving a selection of one or more traffic scenarios associated with the traffic scenes. For example, using feedback collector 106, human feedback from one or more commentators can be used to select one or more traffic scenarios. In some examples, feedback collector 106 is used to identify one or more traffic scenarios that are selected as more realistic and / or likely than one or more other traffic scenarios.

[0037] Procedure 500, in block B506, involves updating a reward model using the selection of one or more traffic scenarios. For example, the reward modeler 112 can use the selection of one or more traffic scenarios identified by the feedback collector 106 to update one or more reward models as defined in the model(s) 110 of Fig. It may contain 1. After block B506, procedure 500 can be terminated.

[0038] Referring to Fig. 6. Each block of the procedure 600 described herein comprises a computational process that can be performed using any combination of hardware, firmware, and / or software. For example, various functions can be performed by a processor executing instructions stored in memory. The procedures can also be stored as computer-usable instructions on computer storage media. The procedures can be provided by a standalone application, a service, a hosted service (standalone or in combination with another hosted service), or a plug-in for another product, to name just a few. Furthermore, the procedure 600 is exemplified by the traffic simulation system of Fig. 1 described. However, these procedures can additionally or alternatively be performed by any system or any combination of systems, including, but not limited to, the systems described here.

[0039] Fig. Figure 6 is a flowchart showing a method 600 for generating a traffic model in accordance with some embodiments of the present disclosure. Method 600 comprises, in block B602, the acquisition of one or more traffic scenes. For example, one or more traffic scenes can be accessed from one or more traffic models of model(s) 110. Fig. 1 can be accessed.

[0040] Procedure 600 includes, in block B604, the collection of preference data. This preference data can be based, for example, on feedback information generated by one or more human commentators selecting one or more traffic scenarios, via the feedback collector 106.

[0041] Procedure 600, in block B606, includes the calculation of reward values ​​based on preference data. For example, a reward model generated by reward model 112 can be used to calculate reward values ​​based on feedback information generated by feedback collector 106.

[0042] Procedure 600 includes, in block B608, updating a traffic model using the reward values. For example, the fine-tuning module 114 can use the calculated reward values ​​to update one or more traffic models of model(s) 110. After block B608, procedure 600 can be terminated.

[0043] Fig. Figure 7 shows an example 700 of a processor according to at least one embodiment. In at least one embodiment, a processor 702 performs one or more methods as described with reference to the Fig. 1 to 6 are described to cause one or more traffic scenes of a traffic model to be captured, preference data indicating a realism of the one or more traffic scenes to be captured, reward values ​​to be calculated at least partially on the basis of the preference data, the traffic model to be updated using the reward values ​​and / or an autonomous machine to be caused to navigate in an environment based on the updated traffic model.In at least one embodiment, the processor 702 performs operations to cause one or more traffic scenes of a traffic model to be captured, preference data indicating a realism of the one or more traffic scenes to be captured, reward values ​​to be calculated at least partially based on the preference data, the traffic model to be updated using the reward values, and / or an autonomous machine to be caused to navigate in an environment based on the updated traffic model.

[0044] In at least one embodiment, the processor 702 comprises one or more processors such as those used in conjunction with the Fig. 17-29. In at least one embodiment, the processor 702 is any suitable processing unit or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, or PPUs. In at least one embodiment, the processor 702 comprises one or more feedback modules 704, a reward module 706, and / or a fine-tuning module 708. In at least one embodiment, the feedback module 704, the reward module 706, and / or the fine-tuning module 708 are part of the processor 702, e.g., as described in Fig. 7 is shown, or part of one or more other processors. In at least one embodiment, the feedback module 704, the reward module 706 and / or the fine-tuning module 708 are distributed across multiple processors that communicate via a bus, a network, by writing to a shared memory, or any suitable communication method, such as those described in the Fig. described on pages 17-29.

[0045] In at least one embodiment, the feedback module 704 comprises circuits that cause one or more feedback information items associated with one or more traffic scenarios to be generated and / or collected, e.g., as described in the Fig. 1-6 is shown.

[0046] In at least one embodiment, the reward module 706 comprises circuits that cause an update of one or more reward models associated with one or more traffic models, e.g., as described in the Fig. 1-6 is shown.

[0047] In at least one embodiment, the fine-tuning module 708 comprises circuits that cause one or more traffic models to be updated based on a reward model and one or more traffic scenarios, e.g., as described in the Fig. 1-6 is shown. LOGIC

[0048] Fig. Figure 8A illustrates the logic 815, which, as described elsewhere herein, can be used in one or more settings to perform operations as described herein according to at least one embodiment. In at least one embodiment, the logic 815 is used to perform inferencing and / or training operations associated with one or more embodiments. In at least one embodiment, the logic 815 is inference and / or training logic. Details of the logic 815 are given below in conjunction with the Fig. 8A and / or 8B described. In at least one embodiment, the logic refers to any combination of software logic, hardware logic and / or firmware logic to provide the functions or operations described herein, wherein the logic, in whole or in part, may be designed as a circuit that is part of a larger system, e.g., an integrated circuit (IC), a system-on-chip (SoC), or one or more processors (e.g., CPU, GPU).

[0049] In at least one embodiment, the logic 815 may, without limitation, comprise a code and / or data memory 801 for storing forward and / or output weights and / or input / output data and / or other parameters for configuring neurons or layers of a neural network that is trained in aspects of one or more embodiments and / or used for inference. In at least one embodiment, the logic 815 may comprise or be coupled to a code and / or data memory 801 for storing graph code or other software that controls the timing and / or order in which information about weights and / or other parameters is loaded to configure the logic, including integer and / or floating-point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, code, such as...Graph code, based on an architecture of a neural network to which the code corresponds, weights or other parameter information in processor ALUs. In at least one embodiment, the code and / or data memory 801 stores weight parameters and / or input / output data of each layer of a neural network that is trained during the forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments, or used in conjunction with one or more embodiments. In at least one embodiment, each part of the code and / or data memory 801 may be encompassed by another on-chip or off-chip data memory, including the L1, L2, or L3 cache of a processor or system memory.

[0050] In at least one embodiment, each part of the code and / or data memory 801 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or code and / or data memory 801 can be a cache memory, a dynamic randomly addressable memory (“DRAM”), a static randomly addressable memory (“SRAM”), a non-volatile memory (e.g., flash memory), or another type of memory.In at least one embodiment, the decision as to whether the code and / or code and / or data memory 801 is internal or external to a processor, or comprises DRAM, SRAM, Flash or another type of memory, may depend on whether memory is available on or off the chip, on the latency requirements of the training and / or inference functions being performed, on the size of the data stacks used in inferencing and / or training a neural network, or on a combination of these factors.

[0051] In at least one embodiment, the logic 815 can, without limitation, comprise a code and / or data store 805 for storing backward and / or output weighting and / or input / output data corresponding to neurons or layers of a neural network that is trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, the code and / or data store 805 stores weighting parameters and / or input / output data of each layer of a neural network that is trained or used in conjunction with one or more embodiments during backward propagation of input / output data and / or weighting parameters during training and / or inference using aspects of one or more embodiments.In at least one embodiment, the logic 815 may include or be coupled to a code and / or data memory 805 to store a graph code or other software that controls the timing and / or order in which information about weights and / or other parameters is loaded to configure the logic, including integer and / or floating-point units (collectively referred to as arithmetic logic units (ALUs)).

[0052] In at least one embodiment, a code, such as a graph code, based on a neural network architecture to which the code corresponds, causes weight or other parameter information to be loaded into processor ALUs. In at least one embodiment, any part of the code and / or data memory 805 may include another on-chip or off-chip data memory, including the L1, L2, or L3 cache or system memory of a processor. In at least one embodiment, any part of the code and / or data memory 805 may be located internally or externally in one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data memory 805 may be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory.In at least one embodiment, the choice of whether the code and / or data storage 805 is internal or external to a processor, or whether it includes, for example, DRAM, SRAM, Flash or another type of memory, may depend on the available memory on or off the chip, on the latency requirements of the training and / or inference functions being performed, on the batch size of the data used in inferencing and / or training a neural network, or on a combination of these factors.

[0053] In at least one embodiment, the code and / or data memory 801 and the code and / or data memory 805 can be separate memory structures. In at least one embodiment, the code and / or data memory 801 and the code and / or data memory 805 can be a combined memory structure. In at least one embodiment, the code and / or data memory 801 and the code and / or data memory 805 can be partially combined and partially separate. In at least one embodiment, each part of the code and / or data memory 801 and the code and / or data memory 805 can be encompassed by another on-chip or off-chip data memory, including the L1, L2, or L3 cache of a processor or system memory.

[0054] In at least one embodiment, the logic 815 can, without limitation, comprise one or more arithmetic logic unit(s) (“ALU(s)”) 810, including integer and / or floating-point units, to perform logical and / or mathematical operations that can be performed at least partially on a training and / or inference code (e.g., graph code), the result of which can generate activations (e.g., output values ​​of layers or neurons within a neural network) stored in an activation memory 820, which are functions of input / output and / or weighting parameter data stored in code and / or data memory 801 and / or code and / or data memory 805.In at least one embodiment, activations stored in an activation memory 820 are generated according to linear algebraic and / or matrix-based mathematics, which are executed by ALU(s) 810 in response to execution instructions or other code, wherein weight values ​​stored in code and / or data memory 805 and / or data memory 801 are used as operands together with other values, such as default values, gradient information, pulse values ​​or other parameters or hyperparameters, any or all of which may be stored in code and / or data memory 805 or code and / or data memory 801 or in another memory on or off the chip.

[0055] In at least one embodiment, ALU(s) 810 are contained within one or more processors or other hardware logic devices or circuits, while in another embodiment, ALU(s) 810 may be external to a processor or other hardware logic device or circuit that uses them (e.g., a coprocessor). In at least one embodiment, the ALU(s) 810 may be contained within the execution units of a processor or otherwise in a group of ALUs that the execution units of a processor can access, either within the same processor or distributed across different processors of different types (e.g., central processing units, graphics processing units, fixed functional units, etc.).In at least one embodiment, the code and / or data memory 801, the code and / or data memory 805, and the activation memory 820 can share a processor or other hardware logic device or circuit, while in another embodiment they can be located in different processors or other hardware logic devices or circuits, or in a combination of identical and different processors or other hardware logic devices or circuits. In at least one embodiment, any part of the activation memory 820 can be contained in another on-chip or off-chip data memory, including the L1, L2, or L3 cache or system memory of a processor.Furthermore, the code for inference and / or training can be stored together with other code that a processor or other hardware logic or circuitry can access and that is fetched and / or processed using the fetch, decode, scheduling, execution, elimination, and / or other logic circuitry of a processor.

[0056] In at least one embodiment, the activation memory 820 can be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or another type of memory. In at least one embodiment, the activation memory 820 can be located wholly or partially inside or outside one or more processors or other logic circuits. In at least one embodiment, the decision as to whether the activation memory 820 is located, for example, inside or outside a processor, or whether it comprises DRAM, SRAM, flash memory, or another type of memory, can depend on the available on-chip or off-chip memory, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in inferencing and / or training a neural network, or a combination of these factors.

[0057] In at least one embodiment, the in Fig. The logic 815 shown in Figure 8A can be used in conjunction with an application-specific integrated circuit (“ASIC”), such as Google’s TensorFlow® Processing Unit, a Graphcore™ Inference Processing Unit (IPU), or an Intel Corp. Nervana® processor (e.g., “Lake Crest”). In at least one embodiment, the logic shown in Figure 8A can be used in conjunction with an application-specific integrated circuit (“ASIC”), such as Google’s TensorFlow® Processing Unit, a Graphcore™ Inference Processing Unit (IPU), or an Intel Corp. Nervana® Processor (e.g., “Lake Crest”). Fig. 8A shows that the 815 logic can be used in conjunction with hardware of the central processing unit (“CPU”), the graphics processing unit (“GPU”) or other hardware, such as field-programmable gate arrays (“FPGAs”).

[0058] In at least one embodiment, at least one in Fig. 8A The component shown or described is used to implement procedures and / or functions that are associated with the Fig. 1-7 are described. In at least one embodiment, at least one component of Fig. 8A is used to initiate the generation and / or updating of a traffic model, to access one or more traffic scenes of the traffic model, to generate preference data of the one or more traffic scenes, to calculate a reward value, and / or to control an autonomous machine. In at least one embodiment, at least one component of Fig. 8A selects at least one aspect relating to the feedback collector 106, the model(s) 110, the reward modeler 112, the fine-tuning module 114, the processor 140 and / or the communication manager 120 of Fig. 1, the feedback collection 202, the reward modeling 204 and / or the model fine-tuning 206 of Fig. 2, the generated traffic scenarios 300 of Fig. 3, the collection of 400 scenario feedbacks from Fig. 4, the procedure 500 of Fig. 5, the procedure 600 of Fig. 6 and / or the 700 processor from Fig. 7 is described.

[0059] Fig. Figure 8B shows the logic 815 according to at least one embodiment. In at least one embodiment, the logic is an inference and training logic. In at least one embodiment, the logic 815 can, without limitation, comprise hardware logic in which computing resources are dedicated or otherwise used exclusively in conjunction with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, the logic 815 can be further defined by the following: Fig. The logic 815 shown in Figure 8B can be used in conjunction with an application-specific integrated circuit (ASIC), such as Google's TensorFlow® Processing Unit, a Graphcore™ Inference Processing Unit (IPU), or an Intel Corp. Nervana® processor (e.g., "Lake Crest"). In at least one embodiment, the logic shown in Figure 8B can be used in conjunction with an application-specific integrated circuit (ASIC), such as Google's TensorFlow® Processing Unit, a Graphcore™ Inference Processing Unit (IPU), or an Intel Corp. Nervana® Processor ... Fig. The logic 815 shown in Figure 8B is used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware, such as field-programmable gate arrays (FPGAs). In at least one embodiment, the logic 815 comprises, without limitation, a code and / or data memory 801 and a code and / or data memory 805, which can be used to store code (e.g., graph code), weight values, and / or other information, including default values, gradient information, pulse values, and / or other parameter or hyperparameter information. In at least one embodiment, the logic 815 is further described in Figure 8B. Fig. As shown in Figure 8B, each code and / or data store 801 and each code and / or data store 805 is associated with a dedicated computing resource, such as computing hardware 802 and computing hardware 806, respectively. In at least one embodiment, each of the computing hardware 802 and computing hardware 806 comprises one or more ALUs that execute mathematical functions, such as linear algebraic functions, only on information stored in the code and / or data store 801 and in the code and / or data store 805, respectively, with the result being stored in the activation memory 820.

[0060] In at least one embodiment, each of the code and / or data stores 801 and 805 and the corresponding computing hardware 802 and 806, respectively, corresponds to different layers of a neural network, such that the resulting activation from a "memory / computing pair 801 / 802" consisting of code and / or data store 801 and computing hardware 802 is provided as input for a next "memory / computing pair 805 / 806" consisting of code and / or data store 805 and computing hardware 806, in order to reflect a conceptual organization of a neural network. In at least one embodiment, each of the memory / computing pairs 801 / 802 and 805 / 806 can correspond to more than one layer of the neural network. In at least one embodiment, additional memory / computing pairs (not shown) can be included sequentially or in parallel with the memory / computing pairs 801 / 802 and 805 / 806 in the logic 815.

[0061] In at least one embodiment, at least one in Fig. 8B component shown or described is used to implement procedures and / or functions that are associated with the Fig. 1-7 are described. In at least one embodiment, at least one component of Fig. 8B is used to initiate the generation and / or updating of a traffic model, to access one or more traffic scenes of the traffic model, to generate preference data of the one or more traffic scenes, to calculate a reward value, and / or to control an autonomous machine. In at least one embodiment, at least one component of Fig. 8B selects at least one aspect relating to the feedback collector 106, the model(s) 110, the reward modeler 112, the fine-tuning module 114, the processor 140 and / or the communication manager 120 of Fig. 1, the feedback collection 202, the reward modeling 204 and / or the model fine-tuning 206 of Fig. 2, the generated traffic scenarios 300 of Fig. 3, the collection of 400 scenario feedbacks from Fig. 4, the procedure 500 of Fig. 5, the procedure 600 of Fig. 6 and / or the 700 processor from Fig. 7 is described. Training and deployment of a neural network

[0062] Fig. 9 illustrates the training and deployment of a deep neural network, according to at least one embodiment. In at least one embodiment, the untrained neural network 906 is trained using a training dataset 902. In at least one embodiment, the training framework 904 is a PyTorch framework, while in other embodiments, the training framework 904 is a TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training framework. In at least one embodiment, the training framework 904 trains an untrained neural network 906 and enables it to be trained using the processing resources described herein to generate a trained neural network 908.In at least one embodiment, the weights can be selected randomly or by pre-training using a deep belief network. In at least one embodiment, the training can be supervised, partially supervised, or unsupervised.

[0063] In at least one embodiment, an untrained neural network 906 is trained using supervised learning, wherein the training dataset 902 comprises an input paired with a desired output for that input, or wherein the training dataset 902 comprises an input paired with a known output, and an output of the neural network 906 is manually evaluated. In at least one embodiment, the untrained neural network 906 is trained in a supervised manner and processes inputs from the training dataset 902 and compares the resulting outputs with a set of expected or desired outputs. In at least one embodiment, the errors are then propagated back by the untrained neural network 906. In at least one embodiment, the training framework 904 adjusts the weights that control the untrained neural network 906.In at least one embodiment, the training framework 904 includes tools to monitor how well the untrained neural network 906 converges to a model, such as the trained neural network 908, that is capable of generating correct answers based on input data, such as a new dataset 912, as shown in the result 914. In at least one embodiment, the training framework 904 repeatedly trains the untrained neural network 906 while adjusting the weights to refine an output of the untrained neural network 906 using a loss function and an adjustment algorithm, such as stochastic gradient descent. In at least one embodiment, the training framework 904 trains the untrained neural network 906 until the untrained neural network 906 achieves a desired accuracy.In at least one embodiment, the trained neural network 908 may then be used to implement any number of machine learning operations.

[0064] In at least one embodiment, the untrained neural network 906 is trained using unsupervised learning, wherein the untrained neural network 906 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised training dataset 902 comprises input data without associated execution data or "ground truth" data. In at least one embodiment, the untrained neural network 906 can learn groupings within the training dataset 902 and determine how individual inputs relate to the untrained dataset 902. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in a trained neural network 908, which is capable of performing operations useful in reducing the dimensionality of a new dataset 912.In at least one embodiment, unsupervised training may also be used to perform anomaly detection, which allows for identifying data points in a new data set 912 that deviate from normal patterns of the new data set 912.

[0065] In at least one embodiment, semi-supervised learning can be used, which is a method in which the training dataset 902 comprises a mixture of labeled and unlabeled data. In at least one embodiment, the training framework 904 can be used to perform incremental learning, for example, by transferred learning methods. In at least one embodiment, the incremental learning enables a trained neural network 908 to adapt to a new dataset 912 without forgetting the knowledge imparted to the trained neural network during the initial training.

[0066] In at least one embodiment, the 904 training framework is a framework processed in conjunction with a software development toolkit such as an OpenVINO (Open Visual Inference and Neural Network Optimization) toolkit. In at least one embodiment, the OpenVINO toolkit is a toolkit such as that developed by Intel Corporation in Santa Clara, CA. In at least one embodiment, OpenVINO includes or uses Logic 815 to perform operations described herein. In at least one embodiment, a system-on-a-chip (SoC), integrated circuit, or processor uses OpenVINO to perform operations described herein.

[0067] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications, particularly neural network applications, for various tasks and operations, such as human vision emulation, speech recognition, natural language processing, recommendation systems, and / or variations thereof. In at least one embodiment, OpenVINO supports neural networks such as convolutional neural networks (CNNs), feedback and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries such as OpenCV, OpenCL, and / or variants thereof.

[0068] In at least one embodiment, OpenVINO supports neural network models for various tasks and operations, such as classification, segmentation, object recognition, face recognition, speech recognition, pose estimation (e.g., of people and / or objects), monocular depth estimation, image inpainting, style transfer, action recognition, coloring, and / or variations thereof.

[0069] In at least one embodiment, OpenVINO comprises one or more software tools and / or modules for model optimization, also referred to as a model optimizer. In at least one embodiment, a model optimizer is a command-line tool that facilitates the transitions between training and deploying neural network models. In at least one embodiment, a model optimizer optimizes neural network models for execution on various devices and / or processing units, such as a GPU, CPU, PPU, GPGPU, and / or variants thereof. In at least one embodiment, a model optimizer creates an internal representation of a model and optimizes the model to generate an intermediate representation. In at least one embodiment, a model optimizer reduces the number of layers in a model.In at least one embodiment, a model optimizer removes the layers of a model that are used for training. In at least one embodiment, a model optimizer performs various operations on neural networks, such as changing the inputs to a model (e.g., changing the size of the inputs to a model), changing the size of the inputs to a model (e.g., changing the stack size of a model), changing a model structure (e.g., modifying layers of a model), normalization, standardization, quantization (e.g., converting weights of a model from a first representation, such as floating point, to a second representation, such as integer), and / or variations thereof.

[0070] In at least one embodiment, OpenVINO comprises one or more software libraries for inferencing, also referred to as an inference engine. In at least one embodiment, the inference engine is a C++ library or another suitable library in a programming language. In at least one embodiment, an inference engine is used to derive input data. In at least one embodiment, an inference engine implements various classes to derive input data and generate one or more results. In at least one embodiment, an inference engine implements one or more API functions to process an intermediate representation, specify input and / or output formats, and / or execute a model on one or more devices.

[0071] In at least one embodiment, OpenVINO offers various options for the heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computing processes and / or systems that use one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions for executing a program on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute a program and / or sections of a program on different devices. In at least one embodiment, OpenVINO provides various software functions to, for example, execute a first section of the code on a CPU and a second section of the code on a GPU and / or FPGA.In at least one embodiment, OpenVINO provides various software functions to run one or more layers of a neural network on one or more devices (e.g., a first set of layers on a first device, such as a GPU, and a second set of layers on a second device, such as a CPU).

[0072] In at least one embodiment, OpenVINO exhibits various functionalities similar to those of a CUDA programming model, such as various model operations for neural networks associated with frameworks like TensorFlow, PyTorch, and / or variants thereof. In at least one embodiment, one or more CUDA programming model operations are performed using OpenVINO. In at least one embodiment, various systems, methods, and / or techniques described herein are implemented using OpenVINO.

[0073] In at least one embodiment, at least one in Fig. 9. The component shown or described is used to implement procedures and / or functions that are associated with the Fig. 1-7 are described. In at least one embodiment, at least one component of Fig. 9 is used to initiate the generation and / or updating of a traffic model, to access one or more traffic scenes of the traffic model, to generate preference data of the one or more traffic scenes, to calculate a reward value, and / or to control an autonomous machine. In at least one embodiment, at least one component of Fig. 9 select at least one aspect relating to the feedback collector 106, the model(s) 110, the reward modeler 112, the fine-tuning module 114, the processor 140 and / or the communication manager 120 of Fig. 1, the feedback collection 202, the reward modeling 204 and / or the model fine-tuning 206 of Fig. 2, the generated traffic scenarios 300 of Fig. 3, the collection of 400 scenario feedbacks from Fig. 4, the procedure 500 of Fig. 5, the procedure 600 of Fig. 6 and / or the 700 processor from Fig. 7 is described. DATA CENTER

[0074] Fig. Figure 10 shows an example of a data center 1000 in which at least one embodiment can be used. In at least one embodiment, the data center 1000 has a data center infrastructure layer 1010, a framework layer 1020, a software layer 1030, and an application layer 1040.

[0075] In at least one embodiment, as described in Fig. As shown in Figure 10, the data center infrastructure layer 1010 can have a resource orchestrator 1012, clustered compute resources 1014 and node compute resources (“node CRs”) 1016(1)-1016(N), where “N” is a positive integer (which may be a different positive integer “N” than the one used in other figures). In at least one embodiment, the node CRs 1016(1)-1016(N) can include any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processing units, etc.), storage devices 1018(1)-1018(N) (e.g., dynamic read-only memory, solid-state or hard disk drives), network input / output devices (“NW 1 / 0”), network switches, virtual machines (“VMs”), power supply modules, and cooling modules, etc. In at least one embodiment, one or more node CRs can be among the node CRss 1016(1)-1016(N) refers to a server that has one or more of the computing resources mentioned above.

[0076] In at least one embodiment, the grouped compute resources 1014 can comprise separate groupings of node CRs housed in one or more racks (not shown), or many racks housed in data centers at different geographic locations (also not shown). In at least one embodiment, separate groupings of node CRs within the grouped compute resources 1014 can comprise grouped compute, network, storage, or memory resources that can be configured or allocated to support one or more workloads. In at least one embodiment, multiple node CRs comprising CPUs or processors can be grouped in one or more racks to provide compute resources to support one or more workloads.In at least one embodiment, one or more racks can also include any number of power supply modules, cooling modules, and network switches in any combination.

[0077] In at least one embodiment, the resource orchestrator 1012 can configure or otherwise control one or more nodes CRs 1016(1)-1016(N) and / or grouped computing resources 1014. In at least one embodiment, the resource orchestrator 1012 can include a software design infrastructure (“SDI”) management unit for the data center 1000. In at least one embodiment, the resource orchestrator can include hardware, software, or a combination thereof.

[0078] In at least one embodiment, as described in Fig. As shown in Figure 10, the framework layer 1020 includes a job scheduler 1032, a configuration manager 1034, a resource manager 1036, and a distributed file system 1038. In at least one embodiment, the framework layer 1020 can include a frame or framework to support the software 1032 of the software layer 1030 and / or one or more applications 1042 of the application layer 1040. In at least one embodiment, the software 1032 or the application(s) 1042 can each be web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 1020 may be a type of free and open-source software web application framework such as Apache SparkTM (hereinafter referred to as "Spark"), which can use a distributed file system 1038 for processing large amounts of data (e.g., "Big Data").In at least one embodiment, the job scheduler 1032 can include a Spark driver to facilitate the scheduling of workloads supported by different layers of the data center 1000. In at least one embodiment, the configuration manager 1034 can be able to configure different layers, such as the software layer 1030 and the framework layer 1020, which includes Spark and the distributed file system 1038, to support the processing of large amounts of data. In at least one embodiment, the resource manager 1036 can be able to manage clustered or grouped computing resources allocated or assigned to support the distributed file system 1038 and the job scheduler 1032. In at least one embodiment, clustered or grouped computing resources 1014 can be located in the infrastructure layer 1010 of the data center.In at least one embodiment, the resource manager 1036 can be coordinated with the resource orchestrator 1012 to manage these allocated or assigned computer resources.

[0079] In at least one embodiment, the software contained in software layer 1030 may comprise software 1032 that is used by at least sections of the node CRs 1016(1)-1016(N), the grouped computing resources 1014, and / or the distributed file system 1038 of framework layer 1020. In at least one embodiment, one or more types of software may comprise, but are not limited to, internet search software, email virus scanning software, database software, and streaming video content software.

[0080] In at least one embodiment, the application(s) 1042 contained in the application layer 1040 may comprise one or more types of applications used by at least sections of the nodes CRs 1016(1)-1016(N), grouped compute resources 1014, and / or the distributed file system 1038 of the framework layer 1020. In at least one embodiment, one or more types of applications may comprise any number of genome applications, cognitive computations, and machine learning applications, including, but not limited to, training or inferencing software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0081] In at least one embodiment, each of the configuration manager 1034, resource manager 1036, and resource orchestrator 1012 can implement any number and type of self-modifying actions based on any amount and type of data collected in any technically feasible way. In at least one embodiment, self-modifying actions can relieve a data center operator of data center 1000 of potentially making poor configuration decisions and potentially avoiding underutilized and / or poorly functioning sections of a data center.

[0082] In at least one embodiment, the data center 1000 may include tools, services, software, or other resources for training one or more machine learning models or for predicting or deriving information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weighting parameters according to a neural network architecture using software and computing resources described above in relation to the data center 1000.In at least one embodiment, trained machine learning models corresponding to one or more neural networks can be used to derive or predict information, utilizing the resources described above in relation to the data center 1000 by using weighting parameters calculated by one or more training techniques described here.

[0083] In at least one embodiment, the data center can use CPUs, application-specific integrated circuits (ASICs), GPUs, FPGAs, or other hardware to perform training and / or inferencing using the resources described above. Furthermore, one or more of the software and / or hardware resources described above can be provided as a service to allow users to train information or perform inferencing, such as image recognition, speech recognition, or other artificial intelligence services.

[0084] Logic 815 is used to perform inferencing and / or training operations in conjunction with one or more embodiments. Details of Logic 815 are given here in conjunction with the Fig. 8A and / or 8B described. In at least one embodiment, the logic 815 in the data center 1000 can be used for inferencing or prediction operations that are at least partially based on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0085] In at least one embodiment, at least one in Fig. 10. The component shown or described is used to implement procedures and / or functions that are associated with the Fig. 1-7 are described. In at least one embodiment, at least one component of Fig. 10 is used to initiate the generation and / or updating of a traffic model, to access one or more traffic scenes of the traffic model, to generate preference data of the one or more traffic scenes, to calculate a reward value, and / or to control an autonomous machine. In at least one embodiment, at least one component of Fig. 10 select at least one aspect relating to the feedback collector 106, the model(s) 110, the reward modeler 112, the fine-tuning module 114, the processor 140 and / or the communication manager 120 of Fig. 1, the feedback collection 202, the reward modeling 204 and / or the model fine-tuning 206 of Fig. 2, the generated traffic scenarios 300 of Fig. 3, the collection of 400 scenario feedbacks from Fig. 4, the procedure 500 of Fig. 5, the procedure 600 of Fig. 6 and / or the 700 processor from Fig. 7 is described. Autonomous vehicle

[0086] Fig. Figure 11A shows an example of an autonomous vehicle 1100 according to at least one embodiment. In at least one embodiment, the autonomous vehicle 1100 (here alternatively referred to as "vehicle 1100") can be, without restriction, a passenger vehicle, such as a car, a truck, a bus, and / or another type of vehicle that carries one or more passengers. In at least one embodiment, the vehicle 1100 can be a semi-trailer truck used for transporting goods. In at least one embodiment, the vehicle 1100 can be an aircraft, a robotic vehicle, or another type of vehicle.

[0087] Autonomous vehicles can be described in terms of automation levels defined by the National Highway Traffic Safety Administration (“NHTSA”), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers (“SAE”) in the “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-141806, published June 15, 2018, Standard No. J3016-201609, published September 30, 2016, and earlier and future versions of this standard). In at least one embodiment, the vehicle 1100 may be capable of performing functionality corresponding to one or more of Levels 1 through 5 of autonomous driving. For example, in at least one embodiment, the vehicle 1100 may be capable of driving conditionally automated (Level 3), highly automated (Level 4), and / or fully automated (Level 5), depending on the embodiment.

[0088] In at least one embodiment, the vehicle 1100 can, without restriction, comprise components such as a chassis, a vehicle body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, the vehicle 1100 can, without restriction, comprise a drive system 1150, such as an internal combustion engine, a hybrid-electric drive, a pure electric motor, and / or another type of drive system. In at least one embodiment, the drive system 1150 can be connected to a drivetrain of the vehicle 1100, which may include, among other things, a transmission to enable the propulsion of the vehicle 1100. In at least one embodiment, the drive system 1150 can be controlled in response to the reception of signals from a throttle valve / accelerator pedal (or multiple accelerator pedals) 1152.

[0089] In at least one embodiment, a steering system 1154, which may include a steering wheel without restriction, is used to steer the vehicle 1100 (e.g., along a desired path or route) when a drive system 1150 is in operation (e.g., when the vehicle is in motion). In at least one embodiment, the steering system 1154 can receive signals from one or more steering actuators 1156. In at least one embodiment, a steering wheel can optionally be used for full automation (Level 5). In at least one embodiment, a brake sensor system 1146 can be used to actuate the vehicle brakes in response to receiving signals from one or more brake actuators 1148 and / or brake sensors.

[0090] In at least one embodiment, the controller(s) 1136, which without restriction include one or more system-on-chips (“SoCs”) (in Fig. 11A not shown) and / or graphics processing units (“GPUs”), send signals (e.g., representative of commands) to one or more components and / or systems of the vehicle 1100. In at least one embodiment, the controller(s) 1136 may, for example, send signals to actuate the vehicle brakes via the brake actuator(s) 1148, to actuate the steering system 1154 via the steering actuator(s) 1156, and to actuate the drive system 1150 via a throttle valve / accelerator pedal(s) 1152. In at least one embodiment, the controller(s) 1136 may include one or more in-vehicle (e.g., integrated) computing units that process sensor signals and output operating commands (e.g., signals representing commands) to enable autonomous driving and / or to assist a human driver in operating the vehicle 1100.In at least one embodiment, the controller(s) 1136 may comprise a first controller 1136 for autonomous driving functions, a second controller 1136 for functional safety functions, a third controller 1136 for artificial intelligence functions (e.g., computer vision), a fourth controller 1136 for infotainment functions, a fifth controller 1136 for emergency redundancy, and / or other controllers. In at least one embodiment, a single controller 1136 may perform two or more of the aforementioned functions, two or more controllers 1136 may perform a single function, and / or any combination thereof.

[0091] In at least one embodiment, the controller(s) 1136 provide signals for controlling one or more components and / or systems of the vehicle 1100 in response to sensor data received from one or more sensors (e.g. sensor inputs). In at least one embodiment, sensor data can be obtained, for example, and without limitation, from a Global Navigation Satellite System (“GNSS”) sensor(s) 1158 (e.g., Global Positioning System sensor(s)), radar sensor(s) 1160, ultrasonic sensor(s) 1162, lidar sensor(s) 1164, inertial measurement unit (“IMU”) sensor(s) 1166 (e.g., accelerometer(s), gyroscope(s), a magnetic compass or compasses, magnetometer, etc.), microphone(s) 1196, stereo camera(s) 1168, wide-angle camera(s) 1170 (e.g., fisheye cameras), infrared camera(s) 1172, surround camera(s) 1174 (e.g., 360-degree cameras), remote cameras (not in Fig. 11A), mid-range camera(s) (not shown in Fig. 11A shown), speed sensor(s) 1144 (e.g. to measure the speed of the vehicle 1100), vibration sensor(s) 1142, steering sensor(s) 1140, brake sensor(s) (e.g. as part of the brake sensor system 1146) and / or other sensor types are received.

[0092] In at least one embodiment, one or more of the controllers 1136 can receive inputs (e.g., in the form of input data) from an instrument cluster 1132 of the vehicle 1100 and provide outputs (e.g., in the form of output data, display data, etc.) via a human-machine interface (“HMI”) display 1134, an acoustic alarm, a loudspeaker, and / or via other components of the vehicle 1100. In at least one embodiment, the outputs can include information such as vehicle speed, engine speed, time, map data (e.g., a high-resolution map (in Fig. 11A not shown)), position data (e.g., the position of vehicle 1100, as shown on a map), direction, position of other vehicles (e.g., an occupancy grid), information about objects and the status of objects as perceived by the controller(s) 1136, etc. In at least one embodiment, the HMI display 1134 can, for example, show information about the presence of one or more objects (e.g., a road sign, a warning sign, a changing traffic light, etc.) and / or information about driving maneuvers that the vehicle has performed, is currently performing, or will perform (e.g., lane change now, exit 34B in two miles, etc.).

[0093] In at least one embodiment, the vehicle 1100 further comprises a network interface 1124 which can use radio antenna(s) 1126 and / or modem(s) for communication via one or more networks. For example, in at least one embodiment, the network interface 1124 may be capable of communicating via Long-Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communication (“GSM”), IMT-CDMA Multi-Carrier (“CDMA1800”) networks, etc. In at least one embodiment, the radio antenna(s) 1126 can also enable communication between objects in the environment (e.g. vehicles, mobile equipment, etc.) using local area networks such as Bluetooth, Bluetooth Low Energy (“LE”), Z-Wave, ZigBee, etc., and / or low-power wide area networks (“LPWANs”) such as LoRaWAN, SigFox, etc. protocols.

[0094] Logic 815 is used to perform inferencing and / or training operations in conjunction with one or more embodiments. Details of Logic 815 are given here in conjunction with the Fig. 8A and / or 8B described. In at least one embodiment, the logic 815 in the vehicle 1100 can be used for inferencing or prediction operations that are at least partially based on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0095] In at least one embodiment, at least one in Fig. 11A Component shown or described is used to implement procedures and / or functions that are associated with the Fig. 1-7 are described. In at least one embodiment, at least one component of Fig. 11A is used to initiate the generation and / or updating of a traffic model, to access one or more traffic scenes of the traffic model, to generate preference data of the one or more traffic scenes, to calculate a reward value, and / or to control an autonomous machine. In at least one embodiment, at least one component of Fig. 11A selects at least one aspect relating to the feedback collector 106, the model(s) 110, the reward modeler 112, the fine-tuning module 114, the processor 140 and / or the communication manager 120 of Fig. 1, the feedback collection 202, the reward modeling 204 and / or the model fine-tuning 206 of Fig. 2, the generated traffic scenarios 300 of Fig. 3, the collection of 400 scenario feedbacks from Fig. 4, the procedure 500 of Fig. 5, the procedure 600 of Fig. 6 and / or the 700 processor from Fig. 7 is described.

[0096] Fig. Figure 11B shows an example of camera positions and fields of view for the autonomous vehicle 1100. Fig. 11A, according to at least one embodiment. In at least one embodiment, the cameras and their respective fields of view represent an exemplary embodiment and are not to be considered limiting. For example, in at least one embodiment, additional and / or alternative cameras may be present and / or the cameras may be arranged at other locations on the vehicle 1100.

[0097] In at least one embodiment, the camera types may be digital cameras, which may be adapted for use with components and / or systems of the vehicle 1100, but are not limited to this. In at least one embodiment, the camera(s) may operate at Automotive Safety Integrity Level (ASIL) B and / or at another ASIL. In at least one embodiment, the camera types may achieve any frame rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the cameras may use a rolling shutter, a global shutter, another shutter type, or a combination thereof.In at least one embodiment, the color filter arrangement can comprise a red-clear-clear-clear color filter arrangement (“RCCC”), a red-clear-clear-blue color filter arrangement (“RCCB”), a red-blue-green clear color filter arrangement (“RBGC”), a Foveon X3 color filter arrangement, a Bayer sensor color filter arrangement (“RGGB”), a monochrome sensor color filter arrangement, and / or another type of color filter arrangement. In at least one embodiment, clear-pixel cameras, such as cameras with an RCCC, an RCCB, and / or an RBGC color filter arrangement, can be used to increase light sensitivity.

[0098] In at least one embodiment, one or more cameras can be used to implement advanced driver assistance systems (ADAS) (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function monocular camera can be installed, providing functions such as lane keeping assist, traffic sign recognition, and intelligent headlight control. In at least one embodiment, one or more of the cameras (e.g., all cameras) can simultaneously record and provide image data (e.g., video).

[0099] In at least one embodiment, one or more cameras can be mounted in a mounting arrangement, such as a custom-designed (three-dimensional ("3D") printed) arrangement, to eliminate stray light and reflections from the vehicle 1100 (e.g., reflections from the dashboard reflected in the windshield mirrors) that could impair the camera's ability to capture image data. In at least one embodiment, the assemblies for the exterior mirrors can be individually 3D printed, so that a camera mounting plate corresponds to the shape of an exterior mirror. In at least one embodiment, the camera(s) can be integrated into the exterior mirrors. In at least one embodiment, for side cameras, the camera(s) can also be integrated into four pillars at each corner of a passenger compartment.

[0100] In at least one embodiment, cameras with a field of view that includes sections of the environment in front of the vehicle 1100 (e.g., forward-facing cameras) can be used for all-around vision to assist in the detection of forward-facing paths and obstacles, and, with the aid of one or more controllers 1136 and / or control SoCs, to provide information that is crucial for generating an occupancy grid and / or determining preferred vehicle paths. In at least one embodiment, forward-facing cameras can be used to perform many of the same ADAS functions as LIDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance.In at least one embodiment, forward-facing cameras can also be used for ADAS functions and systems, including but not limited to lane departure warning (“LDW”), adaptive cruise control (“ACC”) and / or other functions such as traffic sign recognition.

[0101] In at least one embodiment, a plurality of cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform comprising a CMOS color image sensor (complementary metal oxide semiconductor). In at least one embodiment, the wide-angle camera 1170 can be used to detect objects approaching from the periphery (e.g., pedestrians, crossing traffic, or bicycles). Although in Fig. While only one wide-angle camera 1170 is shown in Figure 11B, other embodiments may include any number (including zero) of wide-angle cameras on the vehicle 1100. In at least one embodiment, any number of wide-angle camera(s) 1198 (e.g., a pair of wide-angle stereo cameras) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, the wide-angle camera(s) 1198 may also be used for object detection and classification, as well as for basic object tracking.

[0102] In at least one embodiment, any number of stereo camera(s) 1168 can also be arranged in a forward-facing configuration. In at least one embodiment, one or more of the stereo camera(s) 1168 can have an integrated control unit comprising a scalable processing unit that can provide programmable logic (“FPGA”) and a multi-core microprocessor with an integrated controller area network (“CAN”) or Ethernet interface on a single chip. In at least one embodiment, such a unit can be used to create a 3D map of the vehicle 1100's surroundings, which includes a distance estimate for all points in the image.In at least one embodiment, one or more of the stereo camera(s) 1168 can, without limitation, comprise compact stereo vision sensor(s) which can, without limitation, include two camera lenses (one on the left and one on the right) and an image processing chip that can measure the distance between the vehicle 1100 and the target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1168 can also be used in addition to or as an alternative to those described herein.

[0103] In at least one embodiment, cameras with a field of view that includes sections of the environment to the sides of the vehicle 1100 (e.g., side cameras) can be used for the surround view and provide information that is used to create and update an occupancy grid and to generate side impact warnings. In at least one embodiment, the surround camera(s) 1174 (e.g., four surround cameras 1174, as described in Fig. (as shown in Figure 11B) is positioned on the vehicle 1100. In at least one embodiment, the surround camera(s) 1174 can, without limitation, comprise any number and combination of wide-angle camera(s), fisheye camera(s), 360-degree camera(s), and / or similar cameras. For example, in at least one embodiment, four fisheye cameras can be positioned at the front, rear, and sides of the vehicle 1100. In at least one embodiment, the vehicle 1100 can use three surround camera(s) 1174 (e.g., left, right, and rear) and one or more other cameras (e.g., a forward-facing camera) as a fourth surround-view camera.

[0104] In at least one embodiment, cameras with a field of view that includes sections of the environment behind the vehicle 1100 (e.g., reversing cameras) can be used for parking assistance, surround view, rear collision warnings, and the creation and updating of the occupancy grid. In at least one embodiment, a plurality of cameras can be used, including, but not limited to, cameras that are also suitable as forward-facing cameras (e.g., wide-area cameras 1198 and / or mid-range cameras 1176, stereo cameras 1168, infrared cameras 1172, etc.), as described herein.

[0105] In at least one embodiment, at least one in Fig. 11B component shown or described is used to implement procedures and / or functions that are associated with the Fig. 1-7 are described. In at least one embodiment, at least one component of Fig. 11B is used to initiate the generation and / or updating of a traffic model, to access one or more traffic scenes of the traffic model, to generate preference data of the one or more traffic scenes, to calculate a reward value, and / or to control an autonomous machine. In at least one embodiment, at least one component of Fig. 11B selects at least one aspect relating to the feedback collector 106, the model(s) 110, the reward modeler 112, the fine-tuning module 114, the processor 140 and / or the communication manager 120 of Fig. 1, the feedback collection 202, the reward modeling 204 and / or the model fine-tuning 206 of Fig. 2, the generated traffic scenarios 300 of Fig. 3, the collection of 400 scenario feedbacks from Fig. 4, the procedure 500 of Fig. 5, the procedure 600 of Fig. 6 and / or the 700 processor from Fig. 7 is described.

[0106] Fig. 11C is a block diagram illustrating an example system architecture for the autonomous vehicle 1100 of Fig. 11A according to at least one embodiment. In at least one embodiment, each component, feature and system of the vehicle 1100 is shown. Fig. 11C is shown as connected via a bus 1102. In at least one embodiment, the bus 1102 can have a CAN data interface (here alternatively referred to as a "CAN bus") without restriction. In at least one embodiment, a CAN can be a network within the vehicle 1100, used to support the control of various features and functions of the vehicle 1100, such as actuation of the brakes, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, the bus 1102 can be configured to have dozens or even hundreds of nodes, each of which has its own unique identifier (e.g., a CAN ID). In at least one embodiment, the bus 1102 can be read to determine the steering wheel angle, vehicle speed, engine revolutions per minute ("RPMs"), button positions, and / or other vehicle status indicators.In at least one embodiment, the bus 1102 can be a CAN bus that is ASIL B compliant.

[0107] In at least one embodiment, FlexRay and / or Ethernet protocols can be used in addition to or as an alternative to CAN. In at least one embodiment, any number of buses can be used to form Bus 1102, which can, without restriction, include zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses with other protocols. In at least one embodiment, two or more Bus 1102s can be used to perform different functions and / or they can be used for redundancy. For example, a first bus can be used for collision avoidance functionality and a second bus for actuation control. In at least one embodiment, each bus of Bus 1102 can communicate with any component of the vehicle 1100, and two or more buses of Bus 1102s can communicate with corresponding components.In at least one embodiment, any number of system(s) on (one) chip(s) (“SoC(s)”) 1104 (such as SoC 1104(A) and SoC 1104(B)), any controller 1136 and / or any computer in the vehicle can have access to the same input data (e.g. inputs from sensors of the vehicle 1100) and be connected to a common bus, such as the CAN bus.

[0108] In at least one embodiment, the vehicle 1100 can have one or more control units 1136, as described here in relation to Fig. 11A is described. In at least one embodiment, the controller(s) 1136 can be used for a variety of functions. In at least one embodiment, the controller(s) 1136 can be coupled with various other components and systems of the vehicle 1100 and used for controlling the vehicle 1100, for the artificial intelligence of the vehicle 1100, for infotainment for the vehicle 1100 and / or other functions.

[0109] In at least one embodiment, the vehicle 1100 can have any number of SoCs 1104. In at least one embodiment, each of the SoCs 1104 can, without limitation, have central processing units (“CPU(s)”) 1106, graphics processing units (“GPU(s)”) 1108, processor(s) 1110, cache(s) 1112, accelerators 1114, data storage 1116, and / or other components and features not shown. In at least one embodiment, the SoC(s) 1104 can be used to control the vehicle 1100 in a variety of platforms and systems. In at least one embodiment, the SoC(s) 1104 can, for example, be combined in a system (e.g., the system of the vehicle 1100) with a high-definition (“HD”) card 1122, which is accessed via a network interface 1124 by one or more servers (in Fig. 11C not shown) can receive map refreshes and / or updates.

[0110] In at least one embodiment, the CPU(s) 1106 may comprise a CPU cluster or CPU complex (here alternatively referred to as "CCPLEX"). In at least one embodiment, the CPU(s) 1106 may comprise multiple cores and / or Level Two ("L2") caches. In at least one embodiment, the CPU(s) 1106 may, for example, comprise eight cores in a coherent multiprocessor configuration. In at least one embodiment, the CPU(s) 1106 may comprise four dual-core clusters, each cluster having a dedicated L2 cache (e.g., a 2 megabyte (MB) L2 cache). In at least one embodiment, the CPU(s) 1106 (e.g., CCPLEX) may be configured to support concurrent cluster operations, so that any combination of clusters of the CPU(s) 1106 can be active at any given time.

[0111] In at least one embodiment, one or more of the CPU(s) 1106 can implement power management functions that, without limitation, have one or more of the following features: individual hardware blocks can be automatically clocked when idle to save dynamic power; each core can be clocked when the core is not actively executing instructions due to the execution of Wait for Interrupt (“WFI”) / Wait for Event (“WFE”) instructions; each core can be independently power-controlled; each core cluster can be independently clock-controlled when all cores are clock-controlled or power-controlled; and / or each core cluster can be independently power-controlled when all cores are power-controlled.In at least one embodiment, the CPU(s) 1106 can further implement an extended power state management algorithm in which permissible power states and expected wake-up times are defined, and the hardware / microcode determines the best power state to adopt for the core, cluster, and CCPLEX. In at least one embodiment, the processor cores can support simplified sequences for inputting the power state into software, with the work offloaded to the microcode.

[0112] In at least one embodiment, the GPU(s) 1108 may include an integrated GPU (here alternatively referred to as an "iGPU"). In at least one embodiment, the GPU(s) 1108 may be programmable and efficient for parallel workloads. In at least one embodiment, the GPU(s) 1108 may use an extended Tensor instruction set. In at least one embodiment, the GPU(s) 1108 may include one or more streaming microprocessors, each streaming microprocessor having an L1 cache (e.g., an L1 cache with a memory capacity of at least 96 KB), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with a memory capacity of 512 KB). In at least one embodiment, the GPU(s) 1108 may include at least eight streaming microprocessors.In at least one embodiment, the GPU(s) 1108 can use one or more application programming interfaces (APIs) for computations. In at least one embodiment, the GPU(s) 1108 can use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0113] In at least one embodiment, one or more of the GPU(s) 1108 can be energy-optimized for best performance in automotive and embedded applications. In one embodiment, the GPU(s) 1108 can, for example, be manufactured using a Fin field-effect transistor (FinFET) circuit. In at least one embodiment, each streaming microprocessor can contain a number of mixed-precision processing cores divided into multiple blocks. For example, 64 PF32 cores and 32 PF64 cores can be divided into four processing blocks. In at least one embodiment, each processing block can be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two NVIDIA mixed-precision Tensor cores for deep learning matrix arithmetic, a level zero instruction cache (“L0”), a scheduler (e.g., a warp scheduler) or control unit, a dispatch unit, and / or a 64 KB register file.In at least one embodiment, streaming microprocessors can have independent parallel integer and floating-point data paths to enable efficient execution of workloads with a mix of computations and addressing calculations. In at least one embodiment, streaming microprocessors can have an independent thread scheduling function to enable finer-grained synchronization and collaboration between parallel threads. In at least one embodiment, streaming microprocessors can have a combined L1 data cache and a shared memory unit to improve performance while simplifying programming.

[0114] In at least one embodiment, one or more of the GPU(s) 1108 may incorporate high-bandwidth memory (“HBM”) and / or a 16 GB HBM2 memory subsystem to provide a peak memory bandwidth of approximately 1200 GB / second in some examples. In at least one embodiment, synchronous graphics random-access memory (“SGRAM”), such as type 5 synchronous graphics dual-data-rate random-access memory (“GDDR5”), may be used in addition to or as an alternative to the HBM memory.

[0115] In at least one embodiment, the GPU(s) 1108 can incorporate unified memory technology. In at least one embodiment, support for address translation services (“ATS”) can be used so that the GPU(s) 1108 can directly access the page tables of the CPU(s) 1106. In at least one embodiment, an address translation request can be sent to the CPU(s) 1106 when the memory management unit (“MMU”) of the GPU(s) 1108 detects an error. In response, two CPUs of the CPU(s) 1106 can search their page tables for a virtual-physical mapping of the address and, in at least one embodiment, transmit the translation back to the GPU(s) 1108.In at least one embodiment, the Unified Memory technology can enable a single, unified virtual address space for the memory of both the CPU(s) 1106 and the GPU(s) 1108, thereby simplifying the programming of the GPU(s) 1108 and the connection of applications to the GPU(s) 1108.

[0116] In at least one embodiment, the GPU(s) 1108 can have any number of access counters that can track the frequency of GPU(s) 1108 accessing the memory of other processors. In at least one embodiment, access counters can help move memory pages into the physical memory of the processor that accesses pages most frequently, thereby improving the efficiency of memory areas shared by processors.

[0117] In at least one embodiment, one or more of the SoC(s) 1104 can have any number of cache(s) 1112, including those described herein. In at least one embodiment, the cache(s) 1112 can, for example, have a Level 3 cache (“L3”) available to both the CPU(s) 1106 and the GPU(s) 1108 (e.g., connected to both the CPU(s) 1106 and the GPU(s) 1108). In at least one embodiment, the cache(s) 1112 can have a write-back cache capable of tracking the states of the rows, for example, by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, an L3 cache can have 4 MB of memory or more, depending on the embodiment, although smaller cache sizes can also be used.

[0118] In at least one embodiment, one or more of the SoC(s) 1104 can include one or more accelerators 1114 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, the SoC(s) 1104 can include a hardware acceleration cluster, which may include optimized hardware accelerators and / or a large on-chip memory. In at least one embodiment, a large on-chip memory (e.g., 4 MB SRAM) enables the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster can be used to complement the GPU(s) 1108 and to offload some tasks of the GPU(s) 1108 (e.g., to free up more GPU cycles for other tasks).In at least one embodiment, the accelerator(s) 1114 can be used for targeted workloads (e.g., perception, convolutional neural networks (“CNNs”), regenerative neural networks (“RNNs”), etc.) that are stable enough to be suitable for acceleration. In at least one embodiment, a CNN can include a region-based or regional convolutional neural network (“RCNNs”) and a fast RCNN (e.g., as used for object recognition) or another type of CNN.

[0119] In at least one embodiment, the accelerator(s) 1114 (e.g., hardware acceleration cluster) may include one or more deep learning accelerators (“DLA”). In at least one embodiment, a DLA may, without restriction, include one or more tensor processing units (“TPUs”), which may be configured to provide an additional ten trillion operations per second for deep learning applications and inferencing. In at least one embodiment, the TPUs may be accelerators designed and optimized for performing image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, the DLA may also be optimized for a specific set of neural network types and floating-point operations, as well as for inferencing.In at least one embodiment, the design of the DLA(s) can provide more performance per millimeter than a typical general-purpose GPU and generally far surpasses the performance of a CPU. In at least one embodiment, the TPU(s) can perform multiple functions, including a single-instance convolution function that supports, for example, INT8, INT16, and FP16 data types for both features and weights, as well as post-processor functions.In at least one embodiment, DLA(s) can quickly and efficiently execute neural networks, in particular CNNs, on processed or unprocessed data for a variety of functions, including, for example and without limitation: a CNN for object identification and recognition using data from camera sensors; a CNN for distance estimation using data from camera sensors; a CNN for the detection and identification of emergency vehicles and recognition using data from microphones; a CNN for facial recognition and the identification of vehicle owners using data from camera sensors; and / or a CNN for safety-related and / or security-related events.

[0120] In at least one embodiment, the DLA(s) can perform any function of the GPU(s) 1108, and by using an inference accelerator, a developer can, for example, allocate either the DLA(s) or the GPU(s) 1108 for any given function. In at least one embodiment, a developer can, for example, concentrate the processing of CNNs and floating-point operations on the DLA(s) and leave other functions to the GPU(s) 1108 and / or the accelerator(s) 1114.

[0121] In at least one embodiment, the accelerator(s) 1114 may comprise the programmable image processing accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA(s) may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1138, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, the PVA(s) may offer a balance between performance and flexibility. In at least one embodiment, each PVA may, for example, without limitation, comprise any number of reduced instruction set (“RISC”), direct memory access (“DMA”), and / or vector processors.

[0122] In at least one embodiment, the RISC cores can interact with image sensors (e.g., image sensors of one of the cameras described herein), image signal processors, etc. In at least one embodiment, each RISC core can have any amount of memory. In at least one embodiment, the RISC cores can use one of several protocols, depending on the embodiment. In at least one embodiment, RISC cores can run a real-time operating system (RTOS). In at least one embodiment, RISC cores can be implemented with one or more integrated circuit devices, application-specific integrated circuits (ASICs), and / or memory devices. In at least one embodiment, RISC cores can, for example, include an instruction cache and / or tightly coupled RAM.

[0123] In at least one embodiment, a DMA can enable components of the PVA(s) to access system memory independently of the CPU(s) 1106. In at least one embodiment, a DMA can support any number of features used to optimize a PVA, including, but not limited to, support for multidimensional addressing and / or circular addressing. In at least one embodiment, a DMA can support up to six or more dimensions of addressing, which can, without limitation, include block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0124] In at least one embodiment, vector processors can be programmable processors designed for efficient and flexible execution of computer vision algorithm programming and providing signal processing capabilities. In at least one embodiment, a PVA can comprise a PVA core and two vector processing subsystem partitions. In at least one embodiment, a PVA core can comprise a processor subsystem, DMA engine(s) (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, a vector processing subsystem can function as a primary processing unit of a PVA and comprise a vector processing unit (“VPU”), an instruction cache, and / or a vector memory (e.g., “VMEM”). In at least one embodiment, the VPU core can comprise a digital signal processor, such as…A digital signal processor with multiple data points per instruction (“SIMD”) and very long instruction words (“VLIW”). In at least one embodiment, a combination of SIMD and VLIW can increase throughput and speed.

[0125] In at least one embodiment, each vector processor can have an instruction cache and be connected to dedicated memory. Consequently, in at least one embodiment, each vector processor can be configured to operate independently of other vector processors. In at least one embodiment, vector processors contained in a given PVA can be configured to use data parallelism. For example, in at least one embodiment, multiple vector processors contained in a single PVA can execute a general computer vision algorithm, but for different image regions. In at least one embodiment, vector processors contained in a given PVA can simultaneously execute different image processing algorithms for a single image, or even different algorithms for successive images or sections of an image.In at least one embodiment, an arbitrary number of PVAs can be present in a hardware acceleration cluster, and an arbitrary number of vector processors can be present in each PVA. In at least one embodiment, the PVA(s) can include an additional error correction code (ECC) memory to increase overall system safety.

[0126] In at least one embodiment, the accelerator(s) 1114 may include an on-chip computer vision network and a static random-access memory (“SRAM”) to provide a high-bandwidth, low-latency SRAM for the accelerator(s). In at least one embodiment, the on-chip memory may include at least 4 MB of SRAM, comprising, for example, and without limitation, eight field-configurable memory blocks accessible by both a PVA and a DLA. In at least one embodiment, each pair of memory blocks may include an extended peripheral bus interface (“APB”), configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any desired memory type may be used.In at least one embodiment, a PVA and a DLA can access the memory via a backbone, enabling high-speed access to the memory for both the PVA and the DLA. In at least one embodiment, the backbone can include an on-chip computer vision network that connects the PVA and the DLA to the memory (e.g., using an APB).

[0127] In at least one embodiment, a computer vision network on the chip can have an interface that, prior to the transmission of control signals / addresses / data, determines that both a PVA and a DLA are providing available and valid signals. In at least one embodiment, an interface can provide separate phases and separate channels for the transmission of control signals / addresses / data, as well as burst communication for continuous data transmission. In at least one embodiment, an interface can conform to the standards of the International Organization for Standardization (ISO) 26262 or the International Electrotechnical Commission (IEC) 61508, although other standards and protocols can also be used.

[0128] In at least one embodiment, one or more of the SoC(s) 1104 can include a real-time ray tracing hardware accelerator. In at least one embodiment, the real-time ray tracing hardware accelerator can be used to quickly and efficiently determine the positions and dimensions of objects (e.g., within a world model), to generate real-time visualization simulations, for radar signal interpretation, for sound propagation synthesis and / or analysis, for the simulation of SONAR systems, for general wave propagation simulation, for comparison with lidar data for localization purposes, and / or for other functions and / or purposes.

[0129] In at least one embodiment, the accelerator(s) 1114 can have a wide range of applications for autonomous driving. In at least one embodiment, a PVA can be used for key processing steps in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of a PVA are well suited for algorithmic domains that require predictable processing with low power consumption and low latency. In other words, a PVA is well suited for semi-dense or dense regular computations, even with small datasets, that require predictable runtimes with low latency and low power consumption. In at least one embodiment, such as in the vehicle 1100, PVAs can be designed to execute classical computer vision algorithms, as they can efficiently perform object recognition and integer mathematical procedures.

[0130] For example, in at least one embodiment of a technology, a PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm can be used in some examples, although this is not intended as a limitation. In at least one embodiment, motion estimation / stereo matching is used in-motion applications for Level 3-5 autonomous driving (e.g., structure of motion, pedestrian detection, lane detection, etc.). In at least one embodiment, a PVA can perform computer stereo vision functions on input from two monocular cameras.

[0131] In at least one embodiment, a PVA can be used to perform a dense optical flow. For example, in at least one embodiment, a PVA can process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to deliver processed RADAR data. In at least one embodiment, a PVA is used for time-of-flight depth processing by processing raw time-of-flight data to, for example, provide processed time-of-flight data.

[0132] In at least one embodiment, a DLA can be used to operate any type of network to improve control and driving safety, including, for example, but not limited to, a neural network that outputs a confidence measure for each object detection. In at least one embodiment, the confidence can be represented or interpreted as a probability, or as a relative "weighting" of each detection compared to other detections. In at least one embodiment, a confidence measure further enables the system to make decisions about which detections should be considered true positives and which should be considered false positives. In at least one embodiment, a system can set a confidence threshold and consider only detections that exceed the threshold as true positives.In an embodiment where an automatic emergency braking system (“AEB”) is used, false positive detections would cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, highly reliable detections can be considered triggers for AEB. In at least one embodiment, a DLA can employ a neural network for regression of the confidence level. In at least one embodiment, the neural network can take as input at least a subset of parameters, such as the dimensions of the boundary frame, the estimated base area (obtained, for example, from another subsystem), the output of the IMU sensor(s) 1166, which correlates with the orientation of the vehicle 1100, the distance, the estimates of the 3D position of the object obtained from the neural network and / or other sensors (e.g., LIDAR sensor(s) 1164 or RADAR sensor(s) 1160), and others.

[0133] In at least one embodiment, one or more SoC(s) 1104 can include one or more data storage devices 1116 (e.g., a memory). In at least one embodiment, the data storage device 1116 can be an on-chip memory of the SoC(s) 1104 that can store neural networks to be executed on GPU(s) 1108 and / or a DLA. In at least one embodiment, the capacity of the data storage device(s) 1116 can be large enough to store multiple instances of neural networks for redundancy and security. In at least one embodiment, the data storage device(s) 1112 can include L2 or L3 cache(s).

[0134] In at least one embodiment, one or more of the SoC(s) 1104 can include any number of processors 1110 (e.g., embedded processors). In at least one embodiment, the processor(s) 1110 can include a boot and power management processor, which can be a dedicated processor and a dedicated subsystem for handling the boot power and management functions and the associated security enforcement. In at least one embodiment, the boot and power management processor can be part of the boot sequence of the SoC(s) 1104 and provide runtime power management services.In at least one embodiment, a processor can provide clock and voltage programming, low-power system transition support, SoC(s) 1104 temperature and temperature sensor management, and / or SoC(s) 1104 power supply state management for boot power supply and management. In at least one embodiment, each temperature sensor can be implemented as a ring oscillator whose output frequency is proportional to the temperature, and (one) SoC(s) 1104 can use ring oscillators to sense temperatures of CPU(s) 1106, GPU(s) 1108, and / or accelerator(s) 1114.In at least one embodiment, when it is detected that the temperatures exceed a threshold, a boot and power management processor can enter a temperature fault routine and put the SoC(s) 1104 into a lower power state and / or put the vehicle 1100 into a chauffeur-assured-stop mode (e.g., bring the vehicle 1100 to a safe stop).

[0135] In at least one embodiment, the processor(s) 1110 may further comprise a set of embedded processors that can serve as an audio processing machine, which may be an audio subsystem that enables full hardware support for multi-channel audio across multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing machine is a dedicated processor core with a digital signal processor and dedicated RAM.

[0136] In at least one embodiment, the processor(s) 1110 may further comprise an "always on" processor machine that can provide the necessary hardware functions to support low-power sensor management and wake-up use cases. In at least one embodiment, an "always on" processor machine may, without restriction, comprise a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0137] In at least one embodiment, the processor(s) 1110 can further comprise a safety cluster machine which, without limitation, includes a dedicated processor subsystem for handling safety management for automotive applications. In at least one embodiment, a safety cluster machine can, without limitation, comprise two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt control, etc.), and / or routing logic. In a safety mode, in at least one embodiment, two or more cores can operate in a lockstep mode and function as a single core with comparison logic to detect any differences between their operations.In at least one embodiment, the processor(s) 1110 may further comprise a real-time camera machine, which may, without limitation, include a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, the processor(s) 1110 may further comprise a high dynamic range signal processor, which may, without limitation, include an image signal processor that is a hardware machine that is part of a camera processing pipeline.

[0138] In at least one embodiment, the processor(s) 1110 may include a video image compositor, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by a video playback application to generate a final image for a player window. In at least one embodiment, a video image compositor may perform lens distortion correction on the wide-angle camera(s) 1170, the surround camera(s) 1174, and / or on the sensor(s) of the surveillance camera(s) in the cabin. In at least one embodiment, the sensor(s) of the surveillance camera(s) in the cabin are preferably monitored by a neural network running on another instance of the SoC 1104 and configured to detect events in the cabin and react accordingly.In at least one embodiment, a system inside the vehicle can perform lip-reading without restriction to activate the mobile phone service and make a call, dictate emails, change the destination, activate or change the infotainment system and vehicle settings, or enable voice-controlled internet browsing. In at least one embodiment, certain functions are available to a driver when a vehicle is operating in autonomous mode and are otherwise deactivated.

[0139] In at least one embodiment, the video image compositor can feature improved temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, when motion occurs in a video, the noise reduction appropriately weights the spatial information and reduces the weight of information provided by adjacent frames. In at least one embodiment where a frame or a portion of a frame does not exhibit motion, the temporal noise reduction performed by the video image compositor can use information from a previous frame to reduce the noise in the current frame.

[0140] In at least one embodiment, a video image compositor can also be configured to perform stereo rectification on input stereo lens frames. Furthermore, in at least one embodiment, a video image compositor can be used for user interface design when the operating system desktop is in use and the GPU(s) 1108 are not required for continuously rendering new surfaces. In at least one embodiment, when the GPU(s) 1108 are powered on and actively performing 3D rendering, a video image compositor can be used to offload the GPU(s) 1108, thereby improving performance and responsiveness.

[0141] In at least one embodiment, one or more of the SoC(s) 1104 may additionally include a serial (Mobile Industry Processor Interface ("MIPI") camera interface for receiving video and camera inputs, a high-speed interface, and / or a video input block that can be used for a camera and related pixel input functions. In at least one embodiment, one or more of the SoC(s) 1104 may additionally include one or more software-controlled input / output controllers that can be used to receive I / O signals that are not assigned to a specific role.

[0142] In at least one embodiment, one or more of the SoC(s) 1104 may also have a wide range of peripheral interfaces to enable communication with peripheral devices, audio encoders / decoders (“codecs”), power management, and / or other devices. In at least one embodiment, the SoC(s) 1104 may be used to process data from cameras (e.g., connected via Gigabit Multimedia Serial Link and Ethernet channels), sensors (e.g., LiDAR sensor(s) 1164, radar sensor(s) 1160, etc., which may be connected via Ethernet channels), data from bus 1102 (e.g., vehicle speed 1100, steering wheel position, etc.), data from GNSS sensor(s) 1158 (e.g., connected via an Ethernet bus or a CAN bus), etc.In at least one embodiment, one or more of the SoC(s) 1104 may also have dedicated high-performance mass storage controllers, which may have their own DMA machines and which may be used to relieve the CPU(s) 1106 of routine data management tasks.

[0143] In at least one embodiment, the SoC(s) 1104 can be an end-to-end platform with a flexible architecture that encompasses automation levels 3 to 5, thereby providing a comprehensive functional safety architecture that utilizes computer vision and ADAS techniques for diversity and redundancy, and provides a platform for a flexible, reliable driving software stack along with deep learning tools. In at least one embodiment, the SoC(s) 1104 can be faster, more reliable, and even more energy- and space-efficient than conventional systems. For example, in at least one embodiment, the accelerator(s) 1114, in combination with the CPU(s) 1106, the GPU(s) 1108, and the data storage(s) 1116, can form a fast, efficient platform for autonomous vehicles of levels 3-5.

[0144] In at least one embodiment, computer vision algorithms can be executed on CPUs, which may be designed using high-level programming languages ​​such as C to perform a variety of processing algorithms on a variety of visual data. However, in at least one embodiment, CPUs are often unable to meet the performance requirements of many image processing applications, such as execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object recognition algorithms in real time, as used in in-vehicle ADAS applications and in practical Level 3-5 autonomous vehicles.

[0145] Embodiments such as those described here enable the simultaneous and / or sequential execution of multiple neural networks and the combination of the results to enable Level 3-5 autonomous driving functions. For example, in at least one embodiment, a CNN running on a DLA or a discrete GPU (e.g., GPU(s) 1120) can include text and word recognition that enables the reading and understanding of traffic signs, including signs for which the neural network has not been specifically trained. In at least one embodiment, a DLA can also include a neural network capable of identifying, interpreting, and semantically understanding a traffic sign and passing this semantic understanding to the path planning modules running on a CPU complex.

[0146] In at least one embodiment, multiple neural networks can be executed simultaneously, as in Level 3, 4, or 5 driving. For example, in at least one embodiment, a warning sign stating "Caution: Flashing lights indicate icing" can be interpreted independently or jointly by multiple neural networks, along with an electric light. In at least one embodiment, such a warning sign itself can be identified as a traffic sign by a first neural network (e.g., a trained neural network), and the text "Flashing lights indicate black ice" can be interpreted by a second neural network, which informs the vehicle's path planning software (preferably running on a CPU complex) that black ice is present when flashing lights are detected.In at least one embodiment, the flashing light can be identified by operating a third neural network across multiple images, which informs the vehicle's path planning software about the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example, within a DLA and / or on GPU(s) 1108.

[0147] In at least one embodiment, a CNN for facial recognition and vehicle owner identification can use data from camera sensors to identify the presence of an authorized driver and / or owner of the vehicle 1100. In at least one embodiment, an always-on sensor processing machine can be used to unlock a vehicle when an owner approaches a driver's door and turns on the lights, and, in security mode, to disable the vehicle when the owner leaves the vehicle. In this way, the SoC(s) 1104 provide security against theft and / or carjacking.

[0148] In at least one embodiment, a CNN for the detection and identification of emergency vehicles can use data from microphones 1196 to detect and identify the sirens of emergency vehicles. In at least one embodiment, the SoC(s) 1104 use a CNN for classifying environmental and urban noise as well as for classifying visual data. In at least one embodiment, a CNN running on a DLA is trained to detect the relative approach speed of emergency vehicles (e.g., using the Doppler effect). In at least one embodiment, a CNN can also be trained to identify emergency vehicles specific to the local area in which the vehicle is traveling, as identified by GNSS sensor(s) 1158.In at least one embodiment, a CNN will attempt to detect European sirens when deployed in Europe, and a CNN will attempt to identify only North American sirens when deployed in North America. In at least one embodiment, once an emergency vehicle is detected, a control program can be used to execute an emergency vehicle safety routine, slowing the vehicle down, pulling over to the side of the road, parking the vehicle, and / or letting the vehicle idle, using the ultrasonic sensor(s) 1162, until the emergency vehicle(s) pass by.

[0149] In at least one embodiment, the vehicle 1100 may have one or more CPU(s) 1118 (e.g., discrete CPU(s) or dCPU(s)) which may be connected to the SoC(s) 1104 via a high-speed connection (e.g., PCIe). In at least one embodiment, the CPU(s) 1118 may, for example, be an x86 processor. A CPU(s) 1118 may be used to perform a variety of functions, including mediating potentially inconsistent results between ADAS sensors and the SoC(s) 1104 and / or monitoring the status and state of the controller(s) 1136 and / or an infotainment system on a single chip (“infotainment SoC”) 1130, for example. In at least one embodiment, the SoC(s) 1104 has one or more connections, one of which may be a Peripheral Component Interconnect Express (PCIe).

[0150] In at least one embodiment, the vehicle 1100 can have GPU(s) 1120 (e.g., discrete GPU(s) or dGPU(s)) that can be coupled to the SoC(s) 1104 via a high-speed connection (e.g., NVIDIA's NVLINK channel). In at least one embodiment, GPU(s) 1120 can provide additional artificial intelligence functionality, for example, by running redundant and / or different neural networks, and can be used to train and / or update neural networks, based at least partially on inputs (e.g., sensor data) from sensors of the vehicle 1100.

[0151] In at least one embodiment, the vehicle 1100 can also have a network interface 1124, which can, without restriction, include one or more radio antennas 1126 (e.g., one or more radio antennas 1126 for different communication protocols, such as a mobile communication antenna, a Bluetooth antenna, etc.). In at least one embodiment, the network interface 1124 can be used to enable a wireless connection to internet cloud services (e.g., with one or more servers and / or other network equipment), with other vehicles, and / or with computing equipment (e.g., passenger client devices). In at least one embodiment, a direct connection between the vehicle 80 and another vehicle and / or an indirect connection (e.g., via networks and the internet) can be established for communication with other vehicles.In at least one embodiment, direct connections can be established via a vehicle-to-vehicle communication link. In at least one embodiment, the vehicle-to-vehicle communication link can provide the vehicle 1100 with information about vehicles in its vicinity (e.g., vehicles in front of, beside, and / or behind the vehicle 1100). In at least one embodiment, the aforementioned functionality can be part of a cooperative adaptive cruise control function of the vehicle 1100.

[0152] In at least one embodiment, the network interface 1124 can include a SoC that provides modulation and demodulation functions and enables the controller(s) 1136 to communicate via wireless networks. In at least one embodiment, the network interface 1124 can include a high-frequency front end for up-conversion from a baseband to a high frequency and down-conversion from a high frequency to a baseband. In at least one embodiment, the frequency conversions can be performed in any technically feasible way. For example, frequency conversions can be performed by known methods and / or using superheterodyne methods. In at least one embodiment, the high-frequency front-end functionality can be provided by a separate chip.In at least one embodiment, the network interfaces can have wireless functionality for communication via LTE, WCDMA, UMTS, GSM, CDMA1400, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN and / or other wireless protocols.

[0153] In at least one embodiment, the vehicle 1100 may furthermore include one or more data storage devices 1128, which may, without restriction, include off-chip memory (e.g., off-SoC(s) 1104). In at least one embodiment, the data storage device(s) 1128 may, without restriction, include one or more memory elements, including RAM, SRAM, dynamic random-access memory (“DRAM”), video random-access memory (“VRAM”), flash memory, hard disks, and / or other components and / or devices capable of storing at least one bit of data.

[0154] In at least one embodiment, the vehicle 1100 may additionally include GNSS sensor(s) 1158 (e.g., GPS and / or GPS-enabled sensors) to assist in mapping, perception, grid generation, and / or path planning. In at least one embodiment, any number of GNSS sensor(s) 1158 may be used, including, for example, and without limitation, a GPS unit that uses a USB port with an Ethernet-to-serial bridge (e.g., RS-232).

[0155] In at least one embodiment, the vehicle 1100 may also include RADAR sensor(s) 1160. In at least one embodiment, the RADAR sensor(s) 1160 of a vehicle 1100 may be used for vehicle detection over long distances, even in darkness and / or adverse weather conditions. In at least one embodiment, the RADAR functional safety levels may be ASIL B. In at least one embodiment, the RADAR sensor(s) 1160 may use a CAN bus and / or the bus 1102 (e.g., for transmitting the data generated by the RADAR sensor(s) 1160) for control and access to object tracking data, with some examples providing access to raw data via Ethernet channels. In at least one embodiment, a wide range of RADAR sensor types may be used.For example, and without limitation, RADAR sensor(s) 1160 can be suitable for use with front, rear, and side radar. In at least one embodiment, one or more of the RADAR sensors 1160 are pulse-Doppler radar sensors.

[0156] In at least one embodiment, the RADAR sensor(s) 1160 can have different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, side coverage with short-range, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control. In at least one embodiment, long-range RADAR systems can provide a wide field of view, which is achieved by two or more independent scans, for example, within a range of 250 m (meters). In at least one embodiment, the RADAR sensor(s) 1160 can help to distinguish between stationary and moving objects and can be used by the ADAS system 1138 for emergency braking assistance and forward collision warning.In at least one embodiment, the sensor(s) 1160, which is / are included in a long-range radar system, can, without restriction, comprise a monostatic multimodal radar with multiple (e.g., six or more) fixed radar antennas and a high-speed CAN and FlexRay interface. In at least one embodiment with six antennas, four antennas in the center can generate a focused beam pattern for detecting the vehicle's surroundings at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, the other two antennas can extend the field of view so that vehicles entering or leaving a lane of the vehicle 1100 can be detected quickly.

[0157] In at least one embodiment, medium-range RADAR systems can, for example, have a range of up to 160 m (front) or 80 m (rear) and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, short-range RADAR systems can, without limitation, include any number of RADAR sensors 1160, which can be installed at both ends of the rear bumper. In at least one embodiment, a RADAR sensor system, when installed at both ends of the rear bumper, can generate two beams that continuously monitor the blind spots in the direction behind and beside the vehicle. In at least one embodiment, short-range RADAR systems can be used in the ADAS system 1138 for blind spot detection and / or lane-change assistance.

[0158] In at least one embodiment, the vehicle 1100 may also have ultrasonic sensor(s) 1162. In at least one embodiment, the ultrasonic sensor(s) 1162, which may be arranged on the front, rear, and / or sides of the vehicle 1100, may be used for parking assistance and / or for creating and updating an occupancy grid. In at least one embodiment, a plurality of ultrasonic sensors 1162 may be used, and different ultrasonic sensors 1162 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensor(s) 1162 may operate at functional safety levels of ASIL B.

[0159] In at least one embodiment, the vehicle can have 1100 LIDAR sensor(s) 1164. In at least one embodiment, the LIDAR sensor(s) 1164 can be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the LIDAR sensor(s) 1164 can operate at functional safety level ASIL B. In at least one embodiment, the vehicle can have multiple LIDAR sensors 1164 (e.g., two, four, six, etc.) that can use an Ethernet channel (e.g., to deliver data to a Gigabit Ethernet switch).

[0160] In at least one embodiment, the LIDAR sensor(s) 1164 may be able to provide a list of objects and their distances for a 360-degree field of view. In at least one embodiment, the commercially available LIDAR sensor(s) 1164 may have a displayed range of approximately 100 m, with an accuracy of 2 cm to 3 cm, and with support for a 100 Mbps Ethernet connection, for example. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, the LIDAR sensor(s) 1164 may have a small device that can be embedded in the front, rear, a side, and / or a corner area of ​​the vehicle 1100.In at least one embodiment, the LIDAR sensor(s) 1164 can provide a horizontal field of view of up to 120 degrees and a vertical field of view of up to 35 degrees with a range of 200 m, even for objects with low reflectivity. In at least one embodiment, the front-mounted LIDAR sensor(s) 1164 can be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0161] In at least one embodiment, LIDAR technologies, such as 3D Flash LIDAR, can also be used. In at least one embodiment, a 3D Flash LIDAR uses a laser pulse as a transmission source to illuminate the area around the vehicle 1100 up to a distance of approximately 200 m. In at least one embodiment, a Flash LIDAR unit without limitation includes a receptor that records the time of flight of the laser pulse and the reflected light on each pixel, which in turn corresponds to the distance of the vehicle 1100 to objects. In at least one embodiment, the Flash LIDAR can enable the generation of highly accurate and distortion-free images of the environment with each laser pulse. In at least one embodiment, four Flash LIDAR sensors can be used, one on each side of the vehicle 1100.In at least one embodiment, 3D flash LIDAR systems without restriction include a solid-state 3D star array LIDAR camera that has no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use a 5-nanosecond Class I (eye-safe) laser pulse per image and capture the reflected laser light as a 3D distance point cloud and co-registered intensity data.

[0162] In at least one embodiment, the vehicle may also have one or more IMU sensors 1166. In at least one embodiment, the IMU sensor(s) 1166 may be located in the center of the rear axle of the vehicle 1100. In at least one embodiment, the IMU sensor(s) 1166 may, for example, without limitation, include one or more accelerometers, magnetometers, gyroscopes, a magnetic compass, magnetic compasses, and / or other sensor types. In at least one embodiment, such as in six-axis applications, the IMU sensor(s) 1166 may, without limitation, include accelerometers and gyroscopes. In at least one embodiment, such as in nine-axis applications, the IMU sensor(s) 1166 may, without limitation, include accelerometers, gyroscopes, and magnetometers.

[0163] In at least one embodiment, the IMU sensor(s) 1166 can be implemented as a miniaturized, high-performance GPS-based inertial navigation system (“GPS / INS”) that combines microelectromechanical systems (“MEMS”) inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filter algorithms to provide estimates of position, speed, and orientation. In at least one embodiment, the IMU sensor(s) 1166 can enable the vehicle 1100 to estimate its course without requiring input from a magnetic sensor by directly observing and correlating changes in speed from the GPS with the IMU sensor(s) 1166. In at least one embodiment, the IMU sensor(s) 1166 and GNSS sensor(s) 1158 can be combined in a single integrated unit.

[0164] In at least one embodiment, the vehicle 1100 can have one or more microphones 1196 arranged in and / or around the vehicle 1100. In at least one embodiment, the microphone(s) 1196 can be used, among other things, for the detection and identification of emergency vehicles.

[0165] In at least one embodiment, the vehicle 1100 can also have any number of camera types, including stereo camera(s) 1168, wide-angle camera(s) 1170, infrared camera(s) 1172, surround camera(s) 1174, wide-area camera(s) 1198, medium-area camera(s) 1176, and / or other camera types. In at least one embodiment, cameras can be used to capture image data around the entire perimeter of the vehicle 1100. In at least one embodiment, the types of cameras used depend on the vehicle 1100. In at least one embodiment, any combination of camera types can be used to ensure the required coverage around the vehicle 1100. In at least one embodiment, the number of cameras can vary depending on the embodiment.In at least one embodiment, the vehicle 1100 can, for example, have six, seven, ten, twelve, or any other number of cameras. In at least one embodiment, the cameras can, for example, and without limitation, support Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet communication. In at least one embodiment, each camera can be one of those previously described here with reference to… Fig. 11A and Fig. 11B is described in more detail.

[0166] In at least one embodiment, the vehicle 1100 may also have one or more vibration sensors 1142. In at least one embodiment, the vibration sensor(s) 1142 may measure vibrations of components of the vehicle 1100, such as the axle(s). For example, in at least one embodiment, changes in the vibrations may indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 1142 are used, differences between the vibrations may be used to determine the friction or slip of the road surface (e.g., when the difference in vibrations is between a driven axle and a freely rotating axle).

[0167] In at least one embodiment, the vehicle 1100 may include an ADAS system 1138. In at least one embodiment, the ADAS system 1138 may, in some examples without restriction, include a system of control (SoC). In at least one embodiment, the ADAS system 1138 may, without restriction, include any number and combination of an autonomous / adaptive / automatic cruise control system (“ACC”), a cooperative adaptive cruise control system (“CACC”), a forward collision warning system (“FCW”), an automatic emergency braking system (“AEB”), a lane departure warning system (“LDW”), a lane keeping assist system (“LKA”), a blind spot warning system (“BSW”), a rear cross traffic warning system (“RCTW”), a collision warning system (“CW”), a lane centering system (“LC”), and / or other systems, features, and / or functions.

[0168] In at least one embodiment, the ACC system can use radar sensor(s) 1160, lidar sensor(s) 1164, and / or any number of cameras. In at least one embodiment, the ACC system can include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, a longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of the vehicle 1100 and automatically adjusts the speed of the vehicle 1100 to maintain a safe distance from vehicles ahead. In at least one embodiment, the lateral ACC system maintains the distance and advises the vehicle 1100 to change lanes if necessary. In at least one embodiment, the lateral ACC system is connected to other ADAS applications such as LC and CW.

[0169] In at least one embodiment, the CACC system uses information from other vehicles, which can be received via the network interface 1124 and / or the radio antenna(s) 1126 from other vehicles via a wireless connection or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, direct connections can be provided by a vehicle-to-vehicle communication link (“V2V”), while indirect connections can be provided by an infrastructure-to-vehicle communication link (“I2V”). In general, V2V communication provides information about vehicles immediately ahead (e.g., vehicles that are directly in front of and in the same lane as vehicle 1100), while I2V communication provides information about traffic further ahead.In at least one embodiment, a CACC system can have either one or both I2V and V2V information sources. In at least one embodiment, a CACC system can be more reliable given the information about vehicles ahead of vehicle 1100 and has the potential to improve traffic flow and reduce congestion on the road.

[0170] In at least one embodiment, an FCW system is designed to warn the driver of a hazard so that the driver can take corrective action. In at least one embodiment, an FCW system uses a forward-facing camera and / or radar sensor(s) 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide feedback to the driver, e.g., via a display, a speaker, and / or a vibrating component. In at least one embodiment, an FCW system can provide a warning, e.g., in the form of a sound, a visual warning, a vibration, and / or a rapid braking pulse.

[0171] In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or object and can automatically apply the brakes if the driver does not take corrective action within a specific time or distance parameter. In at least one embodiment, the AEB system can use forward-facing camera(s) and / or radar sensor(s) coupled with a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver so that they can take corrective action to avoid a collision. If the driver fails to take corrective action, the AEB system can automatically apply the brakes to prevent or at least mitigate the effects of the predicted collision.In at least one embodiment, the AEB system may incorporate techniques such as dynamic brake support and / or crash imminent braking or braking in the event of an impending collision.

[0172] In at least one embodiment, an LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to warn the driver if the vehicle crosses the lane markings. In at least one embodiment, the LDW system is not activated if the driver indicates an intentional lane departure, for example, by using a turn signal. In at least one embodiment, the LDW system can use forward-facing cameras coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide feedback to the driver, for example, via a display, a speaker, and / or a vibrating component. In at least one embodiment, an LKA system is a variant of an LDW system.In at least one embodiment, an LKA system provides steering intervention or braking to correct vehicle 1100 when vehicle 1100 begins to leave its lane.

[0173] In at least one embodiment, a BSW system detects and warns the driver of vehicles in the vehicle's blind spot. In at least one embodiment, a BSW system can issue a visual, audible, and / or tactile warning to indicate that merging or changing lanes is unsafe. In at least one embodiment, a BSW system can issue an additional warning when the driver activates a turn signal. In at least one embodiment, the BSW system can use a rear-facing camera and / or radar sensor 1160 coupled with a dedicated processor, DSP, FPGA, and / or ASIC, which is / are electrically coupled to driver feedback, such as a display, a speaker, and / or a vibrating component.

[0174] In at least one embodiment, an RCTW system can provide a visual, audible, and / or tactile notification when an object is detected outside the range of the reversing camera while the vehicle is reversing. In at least one embodiment, an RCTW system includes an AEB system to ensure that the vehicle brakes are applied to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing radar sensors coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide feedback to the driver, such as a display, a speaker, and / or a vibrating component.

[0175] In at least one embodiment, conventional ADAS systems can be prone to false positives, which can be annoying and distracting for the driver, but are typically not catastrophic because conventional ADAS systems warn the driver and give them the opportunity to decide whether a safety condition actually exists and to act accordingly. In at least one embodiment, the vehicle 1100 decides for itself, in the event of conflicting results, whether to follow the result of a primary computer or a secondary computer (e.g., a first controller 1136 or a second controller of the controllers 1136). In at least one embodiment, the ADAS system 1138 can, for example, be a backup and / or secondary computer that provides perceptual information to a rationality module of the backup computer.In at least one embodiment, a rationality monitor of the backup computer can execute redundant, diverse software on hardware components to detect errors in perception and dynamic driving tasks. In at least one embodiment, the outputs of the ADAS system 1138 can be forwarded to a higher-level MCU. In at least one embodiment, a monitoring MCU determines how conflicts can be resolved between outputs from a primary computer and outputs from a secondary computer to ensure safe operation.

[0176] In at least one embodiment, a primary computer can be configured to provide the higher-level MCU with a confidence value indicating the primary computer's confidence in the selected result. In at least one embodiment, the supervising MCU can follow the primary computer's instruction if the confidence value exceeds a threshold, regardless of whether the secondary computer delivers a contradictory or inconsistent result. In at least one embodiment where the confidence value does not reach the threshold and the primary and secondary computers display different results (e.g., a conflict), the supervising MCU can mediate between the computers to determine the appropriate result.

[0177] In at least one embodiment, the monitoring MCU can be configured to execute a neural network(s) trained and configured to determine, at least partially, based on outputs from a primary computer and outputs from a secondary computer, the conditions under which the secondary computer triggers false alarms. In at least one embodiment, the neural network(s) in the monitoring MCU can learn when the output of the secondary computer can be trusted and when it cannot. For example, in at least one embodiment, if the secondary computer is a radar-based FCW system, a neural network in the monitoring MCU can learn when the FCW system identifies metallic objects that are not actually hazards, such as a drain grate or manhole cover, triggering an alarm.In at least one embodiment, where the secondary computer is a camera-based LDW system, a neural network in the monitoring MCU can learn to override the LDW system when cyclists or pedestrians are present and leaving the lane is indeed the safest maneuver. In at least one embodiment, a monitoring MCU can include a DLA or a GPU suitable for running neural networks with associated memory. In at least one embodiment, the monitoring MCU can include and / or be contained within a component of the SoC(s) 1104.

[0178] In at least one embodiment, the ADAS system 1138 can include a secondary computer that executes the ADAS functionality using conventional computer vision rules. In at least one embodiment, the secondary computer can use classic computer vision rules (if-then), and the presence of a neural network (or neural networks) in the higher-level MCU can improve reliability, safety, and performance. In at least one embodiment, the overall system becomes more fault-tolerant due to the different implementation and intentional non-identity, particularly with respect to errors caused by software functions (or software-hardware interfaces).For example, in at least one embodiment, if there is a software bug or error in the software running on the primary computer, and if non-identical software code running on the secondary computer produces a consistent overall result, then the monitoring MCU can have greater confidence that an overall result is correct and that a bug in the software or hardware on the primary computer is not causing a material error.

[0179] In at least one embodiment, an output from the ADAS system 1138 can be fed into the perception block and / or the dynamic driving task block of the primary computer. For example, if, in at least one embodiment, the ADAS system 1138 displays a forward crash warning due to an object immediately ahead, the perception block can use this information in object identification. In at least one embodiment, the secondary computer can have its own trained neural network, thus reducing the risk of false alarms, as described herein.

[0180] In at least one embodiment, the vehicle 1100 may additionally include an infotainment SoC 1130 (e.g., an onboard infotainment system (IVI)). Although depicted and described as an SoC, in at least one embodiment the infotainment SoC 1130 may not be an SoC and may, without limitation, comprise two or more discrete components. In at least one embodiment, the infotainment SoC 1130 may, without limitation, comprise a combination of hardware and software that can be used to provide audio (e.g., music, a personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g.,Navigation systems, rear parking assistance, a radio data system, vehicle-related information such as fuel level, total distance traveled, brake fluid level, oil level, door open / close status, air filter information, etc.) for the vehicle 1100. The infotainment SoC 1130 can, for example, include radios, record players, navigation systems, video players, USB and Bluetooth connectivity, car computers, in-car entertainment, WiFi, audio controls on the steering wheel, a hands-free system, a heads-up display (“HUD”), an HMI display 1134, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, functions, and / or systems), and / or other components. In at least one embodiment, the infotainment SoC 1130 can also be used to provide information (e.g., visual and / or audible) to the user(s) of the vehicle 1100, such as...Information from the ADAS system 1138, information on autonomous driving, such as planned vehicle maneuvers, trajectories, environmental information (e.g. intersection information, vehicle information, road information, etc.), and / or other information.

[0181] In at least one embodiment, the infotainment SoC 1130 can have any quantity and type of GPU functionality. In at least one embodiment, the infotainment SoC 1130 can communicate with other devices, systems, and / or components of the vehicle 1100 via bus 1102. In at least one embodiment, the infotainment SoC 1130 can be coupled with a monitoring MCU so that a GPU of the infotainment system can perform some self-driving functions if the primary controller(s) 1136 (e.g., the primary and / or backup computer of the vehicle 1100) fails. In at least one embodiment, the infotainment SoC 1130 can put the vehicle 1100 into a chauffeur-to-safe-stop mode, as described herein.

[0182] In at least one embodiment, the vehicle 1100 may also include a combination instrument 1132 (e.g., a digital dashboard, an electronic combination instrument, a digital instrument panel, etc.). In at least one embodiment, the combination instrument 1132 may, without limitation, include a controller and / or a supercomputer (e.g., a discrete controller or a supercomputer). In at least one embodiment, the combination instrument 1132 may, without limitation, include any number and combination of instruments, such as a speedometer, fuel level indicator, oil pressure indicator, tachometer, odometer, turn signals, gear position indicator, seat belt warning light(s), parking brake warning light(s), engine malfunction light(s), information about additional restraint systems (e.g., airbags), lighting controls, safety system controls, navigation information, etc.In some examples, the information can be displayed and / or shared between the infotainment SoC 1130 and the instrument cluster 1132. In at least one embodiment, the instrument cluster 1132 can incorporate part of the infotainment SoC 1130, or vice versa.

[0183] In at least one embodiment, at least one in Fig. 11C component shown or described is used to implement procedures and / or functions that are associated with the Fig. 1-7 are described. In at least one embodiment, at least one component of Fig. 11C is used to initiate the generation and / or updating of a traffic model, to access one or more traffic scenes of the traffic model, to generate preference data of the one or more traffic scenes, to calculate a reward value, and / or to control an autonomous machine. In at least one embodiment, at least one component of Fig. 11C selects at least one aspect relating to the feedback collector 106, the model(s) 110, the reward modeler 112, the fine-tuning module 114, the processor 140 and / or the communication manager 120 of Fig. 1, the feedback collection 202, the reward modeling 204 and / or the model fine-tuning 206 of Fig. 2, the generated traffic scenarios 300 of Fig. 3, the collection of 400 scenario feedbacks from Fig. 4, the procedure 500 of Fig. 5, the procedure 600 of Fig. 6 and / or the 700 processor from Fig. 7 is described.

[0184] Fig. 11D is a diagram of a system 1176 for communication between the cloud-based server(s) and the autonomous vehicle 1100. Fig. 11A, according to at least one embodiment. In at least one embodiment, the system 1176 can, without limitation, comprise the server(s) 1178, the network(s) 1190, and any number and type of vehicles, including the vehicle 1100. In at least one embodiment, the server(s) 1178 can, without limitation, comprise a plurality of GPUs 1184(A)-1184(H) (hereinafter collectively referred to as GPUs 1184), PCIe switches 1182(A)-1182(H) (hereinafter collectively referred to as PCIe switches 1182), and / or CPUs 1180(A)-1180(B) (hereinafter collectively referred to as CPUs 1180). In at least one embodiment, GPUs 1184, CPUs 1180 and PCIe switches 1182 can be interconnected via high-speed links, such as, and without limitation, the NVIDIA-developed NVLink interfaces 1188 and / or PCIe links 1186.In at least one embodiment, the GPUs 1184 are connected via an NVLink and / or NVSwitch SoC, and the GPUs 1184 and PCIe switches 1182 are connected via PCIe links. Although eight GPUs 1184, two CPUs 1180, and four PCIe switches 1182 are shown, this is not to be understood as a limitation. In at least one embodiment, each of the servers 1178 can, without limitation, have any number of GPUs 1184, CPUs 1180, and / or PCIe switches 1182 in any combination. For example, in at least one embodiment, the server(s) 1178 can each have eight, sixteen, thirty-two, and / or more GPUs 1184.

[0185] In at least one embodiment, the server(s) 1178 can receive image data from vehicles via the network(s) 1190. This data is representative of images showing unexpected or altered road conditions, such as recently commenced roadworks. In at least one embodiment, the server(s) 1178 can transmit neural networks 1192, updated neural networks 1192, and / or map information 1194 to vehicles via the network(s) 1190. This map information includes, without limitation, information about traffic and road conditions. In at least one embodiment, the map information updates 1194 can include, without limitation, updates to the HD map 1122, such as information about construction sites, potholes, detours, floods, and / or other obstacles.In at least one embodiment, neural networks 1192 and / or map information 1194 can result from new training and / or experience represented in data received from any number of vehicles in the environment, and / or be based at least partially on training performed in a data center (e.g. using server(s) 1178 and / or other servers).

[0186] In at least one embodiment, the server(s) 1178 can be used to train machine learning models (e.g., neural networks) at least partially based on training data. In at least one embodiment, the training data can be generated from vehicles and / or in a simulation (e.g., using a game machine). In at least one embodiment, any amount of training data is tagged (e.g., if the associated neural network benefits from supervised learning) and / or subjected to other preprocessing. In at least one embodiment, any amount of training data is not tagged and / or preprocessed (e.g., if the associated neural network does not require supervised learning). In at least one embodiment, once machine learning models are trained, vehicle machine learning models can be used (e.g.,Transmission to vehicles via network(s) 1190, and / or machine learning models can be used by server(s) 1178 for remote monitoring of vehicles.

[0187] In at least one embodiment, the server(s) 1178 can receive data from vehicles and apply that data to current real-time neural networks for intelligent inferencing in real time. In at least one embodiment, the server(s) 1178 can include deep learning supercomputers and / or dedicated AI computers powered by GPU(s) 1184, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, the server(s) 1178 can include a deep learning infrastructure that uses CPU-powered data centers.

[0188] In at least one embodiment, the deep learning infrastructure of server(s) 1178 can be capable of fast, real-time inference and use this capability to evaluate and verify the state of processors, software, and / or associated hardware in the vehicle 1100. In at least one embodiment, the deep learning infrastructure can, for example, receive periodic updates from the vehicle 1100, such as an image sequence and / or objects that the vehicle 1100 has located in this image sequence (e.g., via computer vision and / or other machine object classification techniques).In at least one embodiment, the deep learning infrastructure can run its own neural network to identify objects and compare them with the objects identified by the vehicle 1100, and if the results do not match and the deep learning infrastructure concludes that the AI ​​in the vehicle 1100 is malfunctioning, the server(s) 1178 can send a signal to the vehicle 1100 instructing a fail-safe computer of the vehicle 1100 to take over control, notify the passengers and perform a safe parking maneuver.

[0189] In at least one embodiment, the server(s) may include GPU(s) 1184 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3). In at least one embodiment, the combination of GPU-driven servers and inference acceleration may enable real-time responsiveness. In at least one embodiment, e.g., where performance is less critical, servers with CPUs, FPGAs, and other processors may also be used for inferencing. In at least one embodiment, the hardware structure(s) 1015 is / are used to implement one or more embodiments. Details of the hardware structure(s) 1015 are provided in conjunction with the Fig. 8A and / or 8B described.

[0190] In at least one embodiment, at least one in Fig. The component shown or described in Figure 11D is used to implement procedures and / or functions related to the Fig. 1-7 are described. In at least one embodiment, at least one component of Fig. 11D is used to initiate the generation and / or updating of a traffic model, to access one or more traffic scenes of the traffic model, to generate preference data of the one or more traffic scenes, to calculate a reward value, and / or to control an autonomous machine. In at least one embodiment, at least one component of Fig. 11D selects at least one aspect relating to the feedback collector 106, the model(s) 110, the reward modeler 112, the fine-tuning module 114, the processor 140 and / or the communication manager 120 of Fig. 1, the feedback collection 202, the reward modeling 204 and / or the model fine-tuning 206 of Fig. 2, the generated traffic scenarios 300 of Fig. 3, the collection of 400 scenario feedbacks from Fig. 4, the procedure 500 of Fig. 5, the procedure 600 of Fig. 6 and / or the 700 processor from Fig. 7 is described. COMPUTER SYSTEMS

[0191] Fig. Figure 12 is a block diagram illustrating an exemplary computer system, which may be a system with interconnected facilities and components, a system-on-a-chip (SoC), or a combination thereof, 1200, which, according to at least one embodiment, includes a processor containing execution units for executing an instruction. In at least one embodiment, the computer system 1200 may, without limitation, include a component, such as a processor 1202, to employ execution units, including logic, for performing algorithms for processing data according to the present disclosure, as in the embodiment described herein. In at least one embodiment, the computer system 1200 may include processors, such as...The PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™ or Intel® Nervana™ microprocessors available from Intel Corporation in Santa Clara, California, although other systems (including PCs with other microprocessors, technical workstations, set-top boxes, and the like) may also be used. In at least one embodiment, the Computer System 1200 may run a version of the WINDOWS operating system available from Microsoft Corporation in Redmond, Washington, although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0192] These embodiments can also be used in other embodiments, such as handheld devices and embedded applications. Some examples of portable devices include mobile phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, embedded applications can include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip, network computers (“NetPCs”), set-top boxes, network hubs, wide-area network switches (“WAN”), or any other system capable of executing one or more instructions according to at least one embodiment.

[0193] In at least one embodiment, the computer system 1200 can, without limitation, comprise a processor 1202, which can, without limitation, include one or more execution units 1208 for training a machine learning and / or inferencing model according to the techniques described herein. In at least one embodiment, the computer system 1200 is a single-processor desktop or server system, but in another embodiment, the computer system 1200 can be a multiprocessor system. In at least one embodiment, the processor 1202 can, without limitation, comprise a CISC (Complex Instruction Set Computer) microprocessor, a RISC (Reduced Instruction Set Computing) microprocessor, a VLIW (Very Long Instruction Word) microprocessor, a processor implementing a combination of instruction sets, or any other device, such as a digital signal processor.In at least one embodiment, the processor 1202 can be connected to a processor bus 1210, which can transmit data signals between the processor 1202 and other components in the computer system 1200.

[0194] In at least one embodiment, the processor 1202 can, without limitation, have an internal Level 1 ("L1") cache memory ("cache") 1204. In at least one embodiment, the processor 1202 can have a single internal cache or multiple levels of an internal cache. In at least one embodiment, the cache memory can be located outside the processor 1202. Other embodiments can also have a combination of internal and external caches, depending on the specific implementation and requirements. In at least one embodiment, the register file 1206 can store different data types in different registers, including, without limitation, integer registers, floating-point registers, status registers, and instruction pointer registers.

[0195] In at least one embodiment, the execution unit 1208, which includes unrestricted logic for performing integer and floating-point operations, is also located in the processor 1202. In at least one embodiment, the processor 1202 may also include a read-only memory ("ROM") for microcode ("ucode") that stores microcode for specific macro instructions. In at least one embodiment, the execution unit 1208 may include logic for handling a packed instruction set 1209. In at least one embodiment, by including a packed instruction set 1209 in the instruction set of a general-purpose processor 1202, together with associated instruction execution circuitry, the operations used by many multimedia applications using packed data can be performed in a general-purpose processor 1202.In at least one embodiment, many multimedia applications can be accelerated and run more efficiently by utilizing the full width of a processor's data bus to perform operations on packed data, thereby eliminating the need to transfer smaller data units across the processor's data bus to perform one or more operations on one data element at a time.

[0196] In at least one embodiment, the execution unit 1208 can also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, the computer system 1200 can, without restriction, include a memory 1220. In at least one embodiment, the memory 1220 can be a dynamic random-access memory (“DRAM”) device, a static random-access memory (“SRAM”) device, a flash memory device, or another type of memory device. In at least one embodiment, the memory 1220 can store instructions 1219 and / or data 1221, represented by data signals that can be executed by the processor 1202.

[0197] In at least one embodiment, the system logic chip can be connected to the processor bus 1210 and the memory 1220. In at least one embodiment, the system logic chip can, without restriction, include a memory control hub (“MCH”) 1216, and the processor 1202 can communicate with the MCH 1216 via the processor bus 1210. In at least one embodiment, the MCH 1216 can provide a high-bandwidth memory path 1218 to the memory 1220 for instruction and data storage, as well as for storing graphics instructions, data, and textures. In at least one embodiment, the MCH 1216 can route data signals between the processor 1202, the memory 1220, and other components in the computer system 1200, and bridge data signals between the processor bus 1210, the memory 1220, and a system I / O interface 1222.In at least one embodiment, the system logic chip can provide a graphics port for connection to a graphics controller. In at least one embodiment, the MCH 1216 can be coupled to the memory 1220 via a high-bandwidth memory path 1218, and the graphics / video card 1212 can be coupled to the MCH 1216 via an AGP connection 1214.

[0198] In at least one embodiment, the computer system 1200 can use the system I / O interface 1222 as a proprietary hub interface bus to couple the MCH 1216 to an I / O controller hub (“ICH”) 1230. In at least one embodiment, the ICH 1230 can provide direct connections to some I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus can, without restriction, include a high-speed I / O bus for connecting peripheral devices to the memory 1220, the chipset, and the processor 1202. Examples include an audio controller 1229, a firmware hub (“Flash BIOS”) 1228, a wireless transceiver 1226, a data storage device 1224, a legacy I / O controller 1223 with user input and keyboard interfaces, a serial expansion port 1227, such as a Universal Serial Bus (“USB”) port, and a network controller 1234.In at least one embodiment, the data storage device 1224 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device or another mass storage device.

[0199] In at least one embodiment, it shows Fig. 12 a system comprising interconnected hardware devices or “chips”, whereas in other embodiments Fig. 12 can show an exemplary SoC. In at least one embodiment, the in Fig. The 12 illustrated devices are interconnected via proprietary connections, standardized connections (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components of the computer system 1200 are interconnected via Compute Express Link (CXL) connections.

[0200] Logic 815 is used to perform inferencing and / or training operations in conjunction with one or more embodiments. Details of Logic 815 are given here in conjunction with the Fig. 8A and / or 8B described. In at least one embodiment, the logic 815 in the computer system 1200 can be used for inferencing or prediction operations that are at least partially based on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0201] In at least one embodiment, at least one in Fig. 12. The component shown or described is used to implement procedures and / or functions that are associated with the Fig. 1-7 are described. In at least one embodiment, at least one component of Fig. 12 is used to initiate the generation and / or updating of a traffic model, to access one or more traffic scenes of the traffic model, to generate preference data of the one or more traffic scenes, to calculate a reward value, and / or to control an autonomous machine. In at least one embodiment, at least one component of Fig. 12 select at least one aspect relating to the feedback collector 106, the model(s) 110, the reward modeler 112, the fine-tuning module 114, the processor 140 and / or the communication manager 120 of Fig. 1, the feedback collection 202, the reward modeling 204 and / or the model fine-tuning 206 of Fig. 2, the generated traffic scenarios 300 of Fig. 3, the collection of 400 scenario feedbacks from Fig. 4, the procedure 500 of Fig. 5, the procedure 600 of Fig. 6 and / or the 700 processor from Fig. 7 is described.

[0202] Fig. Figure 13 is a block diagram showing an electronic device 1300 for using a processor 1310 according to at least one embodiment. In at least one embodiment, the electronic device 1300 can be, for example, and without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop computer, a tablet, a mobile device, a telephone, an embedded computer, or any other suitable electronic device.

[0203] In at least one embodiment, the electronic device 1300 can, without restriction, include a processor 1310 that is communicatively connected to any number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1310 is coupled via a bus or interface, such as an I2C bus, a system management bus (“SMBus”), a low-pin-count bus (LPC), a serial peripheral interface (“SPI”), a high-definition audio bus (“HDA”), a serial advance technology attachment bus (“SATA”), a universal serial bus (“USB”) (versions 1, 2, 3, etc.), or a universal asynchronous receiver / transmitter bus (“UART”). In at least one embodiment, Fig. 13 a system comprising interconnected hardware devices or “chips”, whereas in other embodiments Fig. 13 can show an exemplary system on a chip (“SoC”). In at least one embodiment, the features described in Fig. The 13 illustrated devices are connected to each other by proprietary connections, standardized connections (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components of Fig. 13 are interconnected via Compute Express Link (CXL) connections.

[0204] In at least one embodiment, Fig. 13 a display 1324, a touchscreen 1325, a touchpad 1330, a Near Field Communications (“NFC”) unit 1345, a sensor hub 1340, a thermal sensor 1346, an Express chipset (“EC”) 1335, a Trusted Platform Module (“TPM”) 1338, BIOS / Firmware / Flash memory (“BIOS, FW Flash”) 1322, a DSP 1360, a drive 1320 such as a solid state disk (“SSD”) or a hard disk drive (“HDD”), a wireless local area network (“WLAN”) unit 1350, a Bluetooth unit 1352, a wireless wide area network (“WWAN”) unit 1356, a global positioning system (GPS) unit 1355, a camera (“USB 3.0 camera”) 1354, such as… B. a USB 3.0 camera, and / or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) 1315, which is implemented, for example, in the LPDDR3 standard. These components can be implemented in any suitable way.

[0205] In at least one embodiment, other components can be communicatively connected to the processor 1310 via the components described herein. In at least one embodiment, an accelerometer 1341, an ambient light sensor (“ALS”) 1342, a compass 1343, and a gyroscope 1344 can be communicatively connected to the sensor hub 1340. In at least one embodiment, a thermal sensor 1339, a fan 1337, a keyboard 1346, and a touchpad 1330 can be communicatively connected to the EC 1335. In at least one embodiment, loudspeakers 1363, headphones 1364, and a microphone (“mic”) 1365 can be communicatively coupled to an audio unit (“audio codec and class D amp”) 1364, which in turn can be communicatively coupled to the DSP 1360. In at least one embodiment, the audio unit 1364 can, for example and without restriction, include an audio encoder / decoder (“codec”) and a class D amplifier.In at least one embodiment, the SIM card (“SIM”) 1357 can be communicatively coupled with the WWAN unit 1356. In at least one embodiment, components such as the WLAN unit 1350 and the Bluetooth unit 1352, as well as the WWAN unit 1356, can be implemented in a Next Generation Form Factor (“NGFF”).

[0206] Logic 815 is used to perform inferencing and / or training operations in conjunction with one or more embodiments. Details of Logic 815 are given here in conjunction with the Fig. 8A and / or 8B described. In at least one embodiment, the logic 815 in the electronic device 1300 can be used for inferencing or prediction operations that are at least partially based on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0207] In at least one embodiment, at least one in Fig. 13. The component shown or described is used to implement procedures and / or functions that are associated with the Fig. 1-7 are described. In at least one embodiment, at least one component of Fig. 13 is used to initiate the generation and / or updating of a traffic model, to access one or more traffic scenes of the traffic model, to generate preference data of the one or more traffic scenes, to calculate a reward value, and / or to control an autonomous machine. In at least one embodiment, at least one component of Fig. 13 select at least one aspect relating to the feedback collector 106, the model(s) 110, the reward modeler 112, the fine-tuning module 114, the processor 140 and / or the communication manager 120 of Fig. 1, the feedback collection 202, the reward modeling 204 and / or the model fine-tuning 206 of Fig. 2, the generated traffic scenarios 300 of Fig. 3, the collection of 400 scenario feedbacks from Fig. 4, the procedure 500 of Fig. 5, the procedure 600 of Fig. 6 and / or the 700 processor from Fig. 7 is described.

[0208] Fig. Figure 14 illustrates a computer system 1400 according to at least one embodiment. In at least one embodiment, the computer system 1400 is configured to implement various processes and procedures described in this disclosure.

[0209] In at least one embodiment, the computer system 1400 comprises, without limitation, at least one central processing unit (“CPU”) 1402 connected to a communication bus 1410 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), Peripheral Component Interconnect Express (“PCI Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or another bus or point-to-point communication protocol. In at least one embodiment, the computer system 1400 comprises, without limitation, main memory 1404 and control logic (e.g., implemented as hardware, software, or a combination thereof), and the data is stored in the main memory 1404, which may be in the form of random-access memory (“RAM”).In at least one embodiment, a network interface subsystem (“network interface”) 1422 provides an interface to other computing devices and networks to receive data with the computer system 1400 and to transmit data to other systems.

[0210] In at least one embodiment, the computer system 1400 comprises, without limitation, input devices 1408, a parallel processing system 1412, and display devices 1406, which may be implemented using a conventional cathode ray tube (“CRT”), a liquid crystal display (“LCD”), a light-emitting diode (“LED”), a plasma display, or other suitable display technologies. In at least one embodiment, user input is received from input devices 1408, such as a keyboard, mouse, touchpad, microphone, etc. In at least one embodiment, each module described herein may be arranged on a single semiconductor platform to form a processing system.

[0211] Logic 815 is used to perform inferencing and / or training operations in conjunction with one or more embodiments. Details of Logic 815 are given here in conjunction with the Fig. 8A and / or 8B described. In at least one embodiment, the logic 815 in the computer system 1400 can be used for inferencing or prediction operations that are based at least partially on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0212] In at least one embodiment, at least one in Fig. 14. The component shown or described is used to implement procedures and / or functions that are associated with the Fig. 1-7 are described. In at least one embodiment, at least one component of Fig.14 is used to initiate the generation and / or updating of a traffic model, to access one or more traffic scenes of the traffic model, to generate preference data of the one or more traffic scenes, to calculate a reward value, and / or to control an autonomous machine. In at least one embodiment, at least one component of Fig. 14 select at least one aspect relating to the feedback collector 106, the model(s) 110, the reward modeler 112, the fine-tuning module 114, the processor 140 and / or the communication manager 120 of Fig. 1, the feedback collection 202, the reward modeling 204 and / or the model fine-tuning 206 of Fig. 2, the generated traffic scenarios 300 of Fig. 3, the collection of 400 scenario feedbacks from Fig. 4, the procedure 500 of Fig. 5, the procedure 600 of Fig. 6 and / or the 700 processor from Fig.7 is described.

[0213] Fig. Figure 15 illustrates a computer system 1500 according to at least one embodiment. In at least one embodiment, the computer system 1500 comprises, without limitation, a computer 1510 and a USB stick 1520. In at least one embodiment, the computer 1510 can comprise, without limitation, any number and type of processor(s) (not shown) and memory (not shown). In at least one embodiment, the computer 1510 comprises, without limitation, a server, a cloud instance, a laptop, and a desktop computer.

[0214] In at least one embodiment, the USB stick 1520 comprises, without limitation, a processing unit 1530, a USB interface 1540, and USB interface logic 1550. In at least one embodiment, the processing unit 1530 can be any instruction execution system, device, or facility capable of executing instructions. In at least one embodiment, the processing unit 1530 can comprise, without limitation, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1530 comprises an application-specific integrated circuit (“ASIC”) optimized for performing any number and type of machine learning operations.In at least one embodiment, the processing unit 1530 is, for example, a Tensor Processing Unit (“TPC”) optimized for performing machine learning inference operations. In at least one embodiment, the processing unit 1530 is an image processing unit (“VPU”) optimized for performing image processing and machine learning operations.

[0215] In at least one embodiment, the USB interface 1540 can be any type of USB plug or USB socket. In at least one embodiment, for example, the USB interface 1540 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, the USB interface 1540 is a USB 3.0 Type-A plug. In at least one embodiment, the USB interface logic 1550 can comprise any amount and type of logic that enables the processing unit 1530 to connect to a device (e.g., a computer 1510) via the USB port 1540.

[0216] Logic 815 is used to perform inferencing and / or training operations in conjunction with one or more embodiments. Details of Logic 815 are given here in conjunction with the Fig.8A and / or 8B described. In at least one embodiment, the logic 815 in the computer system 1500 can be used for inferencing or prediction operations that are based at least partially on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0217] In at least one embodiment, at least one in Fig. 15. The component shown or described is used to implement procedures and / or functions that are associated with the Fig. 1-7 are described. In at least one embodiment, at least one component of Fig.15 is used to initiate the generation and / or updating of a traffic model, to access one or more traffic scenes of the traffic model, to generate preference data of the one or more traffic scenes, to calculate a reward value, and / or to control an autonomous machine. In at least one embodiment, at least one component of Fig. 15 select at least one aspect relating to the feedback collector 106, the model(s) 110, the reward modeler 112, the fine-tuning module 114, the processor 140 and / or the communication manager 120 of Fig. 1, the feedback collection 202, the reward modeling 204 and / or the model fine-tuning 206 of Fig. 2, the generated traffic scenarios 300 of Fig. 3, the collection of 400 scenario feedbacks from Fig. 4, the procedure 500 of Fig. 5, the procedure 600 of Fig. 6 and / or the 700 processor from Fig.7 is described.

[0218] Fig.Figure 16A shows an exemplary architecture in which a plurality of GPUs 1610(1) - 1610(N) are communicatively coupled to a plurality of multi-core processors 1605(1) - 1605(M) via high-speed links 1640(1) - 1640(N) (e.g., buses, point-to-point links, etc.). In at least one embodiment, the high-speed links 1640(1) - 1640(N) support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or more. In at least one embodiment, various link protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In various figures, “N” and “M” represent positive integers, which may differ from figure to figure. In at least one embodiment, one or more GPUs in a plurality of GPUs 1610(1)-1610(N) have one or more graphics cores (also simply referred to as "cores") 1900, as shown in the Fig. 19A and Fig. Disclosed in at least one embodiment, one or more graphics cores 1900 can be designated as streaming multiprocessors (“SMs”), stream processors (“SPs”), stream processing units (“SPUs”), compute units (“CUs”), execution units (“EUs”) and / or slices, wherein a slice in this context can refer to a section of the processing resources in a processing unit (e.g. 16 cores, a ray tracing unit, a thread director or scheduler).

[0219] Additionally, and in at least one embodiment, two or more GPUs 1610 are interconnected via high-speed links 1629(1)-1629(2), which may be implemented with similar or different protocols / links than those used for high-speed links 1640(1)-1640(N). Similarly, two or more multi-core processors 1605 may be interconnected via a high-speed link 1628, which may be a symmetric multiprocessor bus (SMP) operating at 20 GB / s, 30 GB / s, 120 GB / s or more. Alternatively, all communication between the various in Fig. System components shown in 16A are connected via similar protocols / lines (e.g., via a common connection structure).

[0220] In one embodiment, each multi-core processor 1605 is communicatively connected to a processor memory 1601(1) - 1601(M) via memory links 1626(1) - 1626(M), and each GPU 1610(1) - 1610(N) is communicatively connected to the GPU memory 1620(1) - 1620(N) via GPU memory links 1650(1) - 1650(N). In at least one embodiment, the memory links 1626 and 1650 can use similar or different memory access technologies. For example, the processor memories 1601(1) - 1601(M) and the GPU memories 1620 can be volatile memories such as dynamic random access memories (DRAMs) (including stacked DRAMs), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or non-volatile memories such as 3D XPoint or Nano-RAM. In at least one embodiment, one section of the processor memories 1601 can be volatile memory and another section can be non-volatile memory (e.g.,using a two-level memory hierarchy (2LM).

[0221] As described here, different multi-core processors 1605 and GPUs 1610 can be physically connected to specific memory 1601 and 1620, respectively, and / or a unified memory architecture can be implemented where a virtual system address space (also called "effective address space") is distributed across different physical memory locations. For example, the processor memory locations 1601(1) - 1601(M) can each comprise 64 GB of system address space, and the GPU memory locations 1620(1) - 1620(N) can each comprise 32 GB of system address space, resulting in a total addressable memory of 256 GB in this example if M=2 and N=4. Other values ​​for N and M are possible.

[0222] In at least one embodiment, at least one in Fig.16A component shown or described is used to implement procedures and / or functions that are associated with the Fig. 1-7 are described. In at least one embodiment, at least one component of Fig. 16A is used to initiate the generation and / or updating of a traffic model, to access one or more traffic scenes of the traffic model, to generate preference data of the one or more traffic scenes, to calculate a reward value, and / or to control an autonomous machine. In at least one embodiment, at least one component of Fig. 16A selects at least one aspect relating to the feedback collector 106, the model(s) 110, the reward modeler 112, the fine-tuning module 114, the processor 140 and / or the communication manager 120 of Fig. 1, the feedback collection 202, the reward modeling 204 and / or the model fine-tuning 206 of Fig.2, the generated traffic scenarios 300 of Fig. 3, the collection of 400 scenario feedbacks from Fig. 4, the procedure 500 of Fig. 5, the procedure 600 of Fig. 6 and / or the 700 processor from Fig. 7 is described.

[0223] Fig. Figure 16B shows additional details for a connection between a multi-core processor 1607 and a graphics acceleration module 1646 according to an exemplary embodiment. In at least one embodiment, the graphics acceleration module 1646 can comprise one or more GPU chips integrated on a line card connected to the processor 1607 via a high-speed connection 1640 (e.g., a PCIe bus, NVLink, etc.). Alternatively, in at least one embodiment, the graphics acceleration module 1646 can be integrated on a package or chip with the processor 1607.

[0224] In at least one embodiment, the processor 1607 comprises a plurality of cores 1660A-1660D (which may be referred to as "execution units"), each with a translation lookaside buffer ("TLB") 1661A-1661D and one or more caches 1662A-1662D. In at least one embodiment, the cores 1660A-1660D may include various other components for instruction execution and data processing, which are not shown. In at least one embodiment, the caches 1662A-1662D may include Level 1 (L1) and Level 2 (L2) caches. Additionally, one or more shared caches 1656 may be present within the caches 1662A-1662D, which are shared by groups of cores 1660A-1660D. For example, one embodiment of the 1607 processor has 24 cores, each with its own L1 cache, twelve shared L2 caches and twelve shared L3 caches.In this embodiment, one or more L2 and L3 caches are shared by two adjacent cores. In at least one embodiment, the processor 1607 and the graphics acceleration module 1646 are connected to the system memory 1614, which shares the processor memories 1601(1) - 1601(M) of . Fig. can have 16A.

[0225] In at least one embodiment, the coherence of data and instructions stored in various caches 1662A-1662D, 1656, and system memory 1614 is maintained by communication between the cores via a coherence bus 1664. In at least one embodiment, for example, each cache can have cache coherence logic / circuitry connected to it to communicate via the coherence bus 1664 in response to detected read or write operations in specific cache rows. In at least one embodiment, a cache snooping protocol is implemented over the coherence bus 1664 to monitor cache accesses.

[0226] In at least one embodiment, a proxy circuit 1625 communicatively couples the graphics acceleration module 1646 to the coherence bus 1664, so that the graphics acceleration module 1646 can participate in a cache coherence protocol as a peer of the cores 1660A-1660D. In at least one embodiment, an interface 1635 provides connectivity with the proxy circuit 1625 via the high-speed connection 1640, and an interface 1637 connects the graphics acceleration module 1646 to the high-speed connection 1640.

[0227] In at least one embodiment, an accelerator integration circuit 1636 provides cache management, memory access, context management, and interrupt management services on behalf of a plurality of graphics processing machines 1631(1) to 1631(N) of the graphics acceleration module 1646. In at least one embodiment, the graphics processing machines 1631(1) to 1631(N) may each comprise a separate graphics processing unit (GPU). In at least one embodiment, a plurality of graphics processing machines 1631(1) to 1631(N) of the graphics acceleration module 1646 comprises one or more graphics cores 1900, as described in conjunction with the Fig. 19A and Fig.19B is discussed. In at least one embodiment, the graphics processing machines 1631(1) - 1631(N) can alternatively comprise different types of graphics processing machines within a graphics processor, such as graphics execution units, media processing machines (e.g., video encoders / decoders), samplers, and blith modules. In at least one embodiment, the graphics acceleration module 1646 can be a GPU with a plurality of graphics processing units 1631(1) - 1631(N), or the graphics processing units 1631(1) - 1631(N) can be individual GPUs integrated in a common package, line card, or chip.

[0228] In one embodiment, the accelerator integration circuit 1636 includes a memory management unit (MMU) 1639 to perform various memory management functions, such as translations from virtual to physical memory (also referred to as translations from effective to real memory) and memory access protocols for accessing the system memory 1614. In at least one embodiment, the MMU 1639 may also include a translation lookaside buffer (TLB) (not shown) to cache translations from virtual / effective to physical / real addresses. In at least one embodiment, instructions and data may be stored in a cache 1638 for efficient access by the graphics processing units 1631(1) - 1631(N).In at least one embodiment, the data stored in cache 1638 and in graphics memories 1633(1) - 1633(M) are kept coherent with the core caches 1662A-1662D, 1656 and the system memory 1614, possibly employing a retrieval unit 1644. As already mentioned, this can be accomplished via a proxy circuit 1625 on behalf of cache 1638 and memories 1633(1) - 1633(M) (e.g., sending updates to cache 1638 in connection with changes / accesses to cache lines in processor caches 1662A-1662D, 1656 and receiving updates from cache 1638).

[0229] In at least one embodiment, a set of registers 1645 stores context data for threads executed by graphics processing machines 1631(1) - 1631N, and a context management circuit 1648 manages thread contexts. For example, the context management circuit 1648 can perform save and restore operations to save and restore the contexts of different threads during context switching (e.g., when a first thread is saved and a second thread is saved so that a second thread can be executed by a graphics processing machine). During a context switch, the context management circuit 1648 can, for example, store current register values ​​in a specific area of ​​memory (e.g., identified by a context pointer). The register values ​​can then be restored upon returning to a context.In at least one embodiment, an interrupt management circuit 1647 receives and processes interruptions received by system devices.

[0230] In at least one embodiment, virtual / effective addresses from a graphics processing unit 1631 are translated by the MMU 1639 into real / physical addresses in system memory 1614. In at least one embodiment, the accelerator integration circuit 1636 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1646 and / or other accelerator devices. In at least one embodiment, the graphics accelerator module 1646 can be dedicated to a single application running on the processor 1607, or it can be shared by multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processors 1631(1) - 1631(N) are shared by multiple applications or virtual machines (VMs).In at least one embodiment, the resources can be divided into “slices” that are allocated to different VMs and / or applications based on processing requirements and priorities associated with VMs and / or applications.

[0231] In at least one embodiment, an accelerator integration circuit 1636 acts as a bridge to a system for the graphics acceleration module 1646 and provides address translation and system memory cache services. Furthermore, in at least one embodiment, the accelerator integration circuit 1636 can provide virtualization functions for a host processor to manage the virtualization of the graphics processing modules 1631(1) - 1631(N), interrupts, and memory management.

[0232] Since, in at least one embodiment, the hardware resources of the graphics processors 1631(1) - 1631(N) are explicitly mapped to a real address space seen by the host processor 1607, each host processor can directly address these resources with an effective address value. In at least one embodiment, a function of the accelerator integration circuit 1636 is the physical separation of the graphics processing units 1631(1) - 1631(N), so that they appear to a system as independent units.

[0233] In at least one embodiment, one or more graphics memories 1633(1) - 1633(M) are connected to each of the graphics processing machines 1631(1) - 1631(N), and N=M. In at least one embodiment, the graphics memories 1633(1) - 1633(M) store instructions and data that are processed by each of the graphics processing machines 1631(1) - 1631N. In at least one embodiment, the graphics memories 1633(1) - 1633(M) can be volatile memory such as DRAMs (including stacked DRAMs), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory such as 3D XPoint or Nano-RAM.

[0234] In at least one embodiment, allocation or biasing methods can be used to reduce data traffic over the high-speed connection 1640 by ensuring that the data stored in the graphics memories 1633(1) - 1633(M) is data most frequently used by the graphics processing units 1631(1) - 1631(N) and preferably not used (or at least not frequently) by the cores 1660A-1660D. Similarly, in at least one embodiment, an allocation or biasing mechanism attempts to keep data required by cores (and preferably not by the graphics processing units 1631(1) - 1631(N)) in the caches 1662A-1662D, 1656, and in system memory 1614.

[0235] Fig.Figure 16C shows another exemplary embodiment in which the accelerator integration circuit 1636 is integrated into the processor 1607. In this embodiment, the graphics processors 1631(1) - 1631(N) communicate directly with the accelerator integration circuit 1636 via the high-speed link 1640, using interface 1637 and interface 1635 (which in turn can use any type of bus or interface protocol). In at least one embodiment, the accelerator integration circuit 1636 can perform operations similar to those described in Figure 16C. Fig.16B, but possibly with a higher throughput, since it is located in close proximity to the coherence bus 1664 and the caches 1662A-1662D, 1656. In at least one embodiment, an accelerator integration circuit supports various programming models, including a programming model for dedicated processes (without virtualization of the graphics acceleration module) and shared programming models (with virtualization), which may include programming models controlled by the accelerator integration circuit 1636 and programming models controlled by the graphics acceleration module 1646.

[0236] In at least one embodiment, the graphics processing machines 1631(1) - 1631(N) are intended for a single application or a single process under a single operating system. In at least one embodiment, a single application can forward other application requests to the graphics processing machines 1631(1) - 1631(N), thereby enabling virtualization within a VM / partition.

[0237] In at least one embodiment, the graphics processing machines 1631(1) - 1631(N) can be shared by multiple VM / application partitions. In at least one embodiment, shared models can use a system hypervisor to virtualize the graphics processing machines 1631(1) - 1631(N) and allow access by any operating system. In single-partition systems without a hypervisor, the graphics processors 1631(1) - 1631(N) belong to an operating system. In at least one embodiment, an operating system can virtualize the graphics processing machines 1631(1) - 1631(N) to grant access to any process or application.

[0238] In at least one embodiment, the graphics acceleration module 1646 or a single graphics processing machine 1631(1) - 1631(N) selects a process element using a process handle. In at least one embodiment, process elements are stored in system memory 1614 and are addressable using an effective address-to-real address translation technique, as described herein. In at least one embodiment, a process handle can be an implementation-specific value provided to a host process when it registers its context with the graphics processing machine 1631(1) - 1631(N) (i.e., when it calls the system software to add a process element to a linked process element list). In at least one embodiment, the lower 16 bits of a process handle can be an offset of a process element within a linked process element list.

[0239] Fig.Figure 16D shows an exemplary accelerator integration slice 1690. In at least one embodiment, a "slice" comprises a specific portion of the processing resources of the accelerator integration circuit 1636. In at least one embodiment, an application is an effective application address space 1682 in system memory 1614 that stores process elements 1683. In at least one embodiment, the process elements 1683 are stored in response to GPU calls 1681 from applications 1680 running on the processor 1607. In at least one embodiment, a process element 1683 contains the process state for the corresponding application 1680. In at least one embodiment, a work descriptor (WD) 1684 contained in the process element 1683 can be a single job requested by an application or a pointer to a queue of jobs.In at least one embodiment, the WD 1684 is a pointer to a job request queue in the effective address space 1682 of an application.

[0240] In at least one embodiment, the graphics acceleration module 1646 and / or the individual graphics processing machines 1631(1)-1631(N) can be shared by all or a subset of the processes in a system. In at least one embodiment, an infrastructure for setting the process states and sending a WD 1684 to a graphics acceleration module 1646 to start a job in a virtualized environment can be provided.

[0241] In at least one embodiment, a programming model for dedicated processes is implementation-specific. In at least one embodiment, a single process in this model owns the graphics acceleration module 1646 or a single graphics processing machine 1631. When the graphics acceleration module 1646 is owned by a single process in at least one embodiment, a hypervisor initializes the accelerator integration circuit 1636 for an owning partition, and an operating system initializes the accelerator integration circuit 1636 for an owning process when the graphics acceleration module 1646 is allocated.

[0242] In operation, a WD retrieval unit 1691 in the accelerator integration slice 1690 retrieves the nearest WD 1684 in at least one embodiment. This WD contains information about the work to be performed by one or more graphics processing units of the graphics acceleration module 1646. In at least one embodiment, the data from the WD 1684 can be stored in registers 1645 and used by the MMU 1639, the interrupt management circuit 1647, and / or the context management circuit 1648, as shown. For example, one embodiment of the MMU 1639 includes a segment / page scrolling circuit for accessing segment / page tables 1686 in the virtual address space 1685 of the operating system. In at least one embodiment, the interrupt management circuit 1647 can process interrupt events 1692 received from the graphics acceleration module 1646.In at least one embodiment, when performing graphics operations, an effective address 1693, generated by a graphics processing machine 1631-1631, N, is translated into a real address by the MMU 1639.

[0243] In at least one embodiment, for each graphics processing machine 1631(1) - 1631(N) and / or each graphics acceleration module 1646, the same set of registers 1645 is duplicated and can be initialized by a hypervisor or operating system. Each of these duplicated registers can be present in an accelerator integration slice 1690 in at least one embodiment. Examples of registers that can be initialized by a hypervisor are listed in Table 1. Table 1 - Registers initialized by the hypervisor Register # Description 1 Slice control register 2 Real Address (RA) Area indicator of planned processes 3 Authority Mask Override Register 4 Break vector table entry offset 5 Break vector table entry boundary 6 Status register 7 Logical Partition ID 8 Real Address (RA) Hypervisor Accelerator Usage Record Pointer 9 Memory description register

[0244] Examples of registers that can be initialized by an operating system are listed in Table 2. Table 2 - Initialized registers of the operating system Register # Description 1 Process and thread identification 2 Effective Address (EA) Context Memory / Recovery Pointer 3 Virtual Address (VA) Accelerator Usage Record Pointer 4 Virtual Address (VA) Pointer to the memory segment table 5 Authority mask 6 Work descriptor

[0245] In at least one embodiment, each WD 1684 is specific to a particular graphics acceleration module 1646 and / or the graphics processing machines 1631(1) - 1631(N). In at least one embodiment, it contains all the information required by a graphics processing machine 1631(1) - 1631(N) to perform work, or it can be a pointer to a memory location where an application has established a queue of instructions for work to be performed.

[0246] Fig. Figure 16E illustrates additional details for an exemplary embodiment of a common model. This embodiment has a real hypervisor address space 1698 in which a process element list 1699 is stored. In at least one embodiment, the real hypervisor address space 1698 can be accessed via a hypervisor 1696, which virtualizes graphics acceleration module machines for the operating system 1695.

[0247] In at least one embodiment, shared programming models allow all or a subset of processes from all or a subset of partitions in a system to use a 1646 graphics acceleration module. In at least one embodiment, there are two programming models in which the 1646 graphics acceleration module is shared by multiple processes and partitions: namely, time-shared and graphically directed sharing.

[0248] In this model, in at least one embodiment, the SystemHypervisor 1696 owns the Graphics Acceleration Module 1646 and makes its functionality available to all Operating Systems 1695. For a Graphics Acceleration Module 1646 to support virtualization by the SystemHypervisor 1696, in at least one embodiment, the Graphics Acceleration Module 1646 may meet certain conditions, such as: 1) An application job request must be autonomous (i.e., the state does not need to be maintained between jobs), or the Graphics Acceleration Module 1646 must provide a context backup and recovery mechanism.2) A graphics acceleration module 1646 guarantees that the job request of an application will be completed within a certain time period, including any translation errors, or the graphics acceleration module 1646 provides the possibility to interrupt the processing of a job, and 3) the graphics acceleration module 1646 must be guaranteed fairness between processes when operating in a directed common programming model.

[0249] In at least one embodiment, the application 1680 must execute a system call of the operating system 1695 with a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes a specific acceleration function for a system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1646 and can be in the form of a graphics acceleration module 1646 instruction, an effective address pointer to a user-defined structure, an effective address pointer to an instruction queue, or another data structure that describes the work to be performed by the graphics acceleration module 1646.

[0250] In one embodiment, an AMR value is an AMR state to be used for a current process. In at least one embodiment, a value passed to an operating system is similar to an application setting an AMR. If the implementations of the accelerator integration circuit 1636 and the graphics acceleration module 1646 do not support a User Authority Mask Override Register (UAMOR) in at least one embodiment, an operating system can apply a current UAMOR value to an AMR value before an AMR is passed in a hypervisor call. The hypervisor 1696 can optionally apply a current AMR value before an AMR is placed in a process element 1683 in at least one embodiment.In at least one embodiment, CSRP is one of the registers 1645 that contain an effective address of a range in the effective address space 1682 of an application for the graphics acceleration module 1646 for storing and restoring context state. This pointer is optional in at least one embodiment if no state needs to be stored between jobs or if a job is prematurely terminated. In at least one embodiment, the context memory / restore area can be anchored in system memory.

[0251] Upon receiving a system call, the operating system 1695 can check whether the application 1680 is registered and has been granted permission to use the graphics acceleration module 1646. In at least one embodiment, the operating system 1695 then calls the hypervisor 1696 with the information shown in Table 3. Table 3 - Hypervisor call parameters from the operating system Parameter # Description 1 A working descriptor (WD) 2 An Authority Mask Register (AMR) value (possibly masked) 3 An effective address (EA) Context Backup / Restore Area Pointer (CSRP) 4 A process ID (PID) and optionally a thread ID (TID) 5 A virtual address (VA) accelerator usage record pointer (AURP) 6 Virtual address of a memory segment table pointer (SSTP) 7 A Logical Interrupt Service Number (LISN)

[0252] Upon receiving a hypervisor call, in at least one embodiment, the hypervisor 1696 checks whether the operating system 1695 is registered and has been granted permission to use the graphics acceleration module 1646. In at least one embodiment, the hypervisor 1696 then adds the process element 1683 to a linked process element list for a corresponding graphics acceleration module type 1646. In at least one embodiment, a process element can contain the information shown in Table 4. Table 4 - Process element information Parameter # Description 1 A working descriptor (WD) 2 An Authority Mask Register (AMR) value (possibly masked) 3 An effective address (EA) Context Backup / Restore Area Pointer (CSRP) 4 A process ID (PID) and optionally a thread ID (TID) 5 A virtual address (VA) accelerator usage record pointer (AURP) 6 Virtual address of a memory segment table pointer (SSTP) 7 A Logical Interrupt Service Number (LISN) 8 Break vector table derived from hypervisor call parameters 9 A status register (SR) value 10 Eine logische Partitions-ID (LPID) 11 Reale Adresse (RA) Hypervisor-Beschleuniger-Nutzungsdatensatzzeiger 12 Speicherbeschreibungsregister (SDR)

[0253] In at least one embodiment, the hypervisor initializes a plurality of registers 1645 for accelerator integration slices 1690.

[0254] As it is in Fig. As shown in Figure 16F, in at least one embodiment, a unified memory is used, which is addressable via a common virtual memory address space used for accessing physical processor memories 1601(1) - 1601(N) and GPU memories 1620(1) - 1620(N). In this implementation, the operations performed on the GPUs 1610(1) - 1610(N) use the same virtual / effective memory address space for accessing the processor memories 1601(1) - 1601(N) and vice versa, simplifying programmability. In at least one embodiment, a first section of a virtual / effective address space is allocated to the processor memory 1601(1), a second section to the second processor memory 1601(N), a third section to the GPU memory 1620(1), and so on.In at least one embodiment, this distributes an entire virtual / effective memory space (sometimes also referred to as effective address space) across each of the processor memory 1601 and GPU memory 1620, allowing each processor or GPU to access each physical memory with a virtual address assigned to that memory.

[0255] In at least one embodiment, the bias / coherence management circuit 1694A-1694E within one or more MMUs 1639A-1639E ensures cache coherence between the caches of one or more host processors (e.g., 1605) and GPUs 1610 and implements biasing procedures that specify in which physical memories certain data types should be stored. While in at least one embodiment multiple instances of the bias / coherence management circuit 1694A-1694E are located in Fig. As shown in Figure 16F, the bias / coherence circuit can be implemented within an MMU of one or more host processors 1605 and / or within the accelerator integration circuit 1636.

[0256] One embodiment allows GPU memory 1620 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, without the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access GPU memory 1620 as system memory without the cumbersome cache coherence overhead provides an advantageous operating environment for GPU offloading. This arrangement allows the host processor 1605 software, in at least one embodiment, to set operands and access computational results without the overhead of conventional I / O DMA data copies. Such conventional copies, in at least one embodiment, involve driver calls, interrupts, and memory-mapping I / O (MMIO) accesses, all of which are inefficient compared to simple memory accesses.In at least one embodiment, the ability to access GPU memory 1620 without cache coherence overhead can be critical for the execution time of an offloaded computation. In cases with significant streaming write memory traffic, the cache coherence overhead can, for example, significantly reduce the effective write bandwidth of a GPU 1610 in at least one embodiment. In at least one embodiment, the efficiency of operand setup, result access, and GPU computation can all play a role in determining the effectiveness of GPU offloading.

[0257] In at least one embodiment, the selection of a GPU bias and a host processor bias is controlled by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which can be a page-granular structure (i.e., controlled by the granularity of a memory page) having 1 or 2 bits per GPU-connected memory page. In at least one embodiment, a bias table can be implemented in a stolen memory area of ​​one or more GPU memory 1620s, with or without a bias cache in a GPU 1610 (e.g., to cache frequently / recently used entries of a bias table). Alternatively, in at least one embodiment, an entire bias table can be managed in a single GPU.

[0258] In at least one embodiment, before the actual access to a GPU memory, a bias table entry associated with each access to GPU memory 1620-1623 is accessed, which performs the following operations. First, in at least one embodiment, local requests from GPU 1610 that find their page in the GPU bias are forwarded directly to a corresponding GPU memory 1620. In at least one embodiment, local requests from a GPU that find their page in the host bias are forwarded to processor 1605 (e.g., via a high-speed connection). In at least one embodiment, requests from processor 1605 that find a requested page in the host processor bias are completed like a normal memory read access. Alternatively, requests directed to a GPU-biased or GPU-bound page can be forwarded to GPU 1610.In at least one embodiment, a GPU can transition a page into a host processor bias when it is not currently using that page. In at least one embodiment, the bias state of a page can be changed either by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited number of cases, a purely hardware-based mechanism.

[0259] In at least one embodiment, a mechanism for changing the bias state uses an API call (e.g., OpenCL) that in turn calls a GPU setup driver, which then sends a message to a GPU (or queues a command descriptor) to instruct it to change a bias state and, for some transitions, to perform a cache flushing operation on a host. In at least one embodiment, the cache flushing operation is used for a transition from the bias of the host processor 1605 to the bias of the GPU, but not for the reverse transition.

[0260] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU-bound pages that cannot be cached by the host processor 1605. To access these pages in at least one embodiment, the processor 1605 may request access from the GPU 1610, which may not grant access immediately. Therefore, to reduce communication between the processor 1605 and the GPU 1610 in at least one embodiment, it is advantageous to ensure that GPU-bound pages are those required by a GPU but not by the host processor 1605, and vice versa.

[0261] Hardware structure(s) 1015 are used to implement one or more embodiments. Details of the hardware structure(s) 1015 can be found here in conjunction with the Fig. 8A and / or 8B should be specified.

[0262] In at least one embodiment, at least one in Fig. The component shown or described in 16B is used to implement procedures and / or functions related to the Fig. 1-7 are described. In at least one embodiment, at least one component of Fig. 16B is used to initiate the generation and / or updating of a traffic model, to access one or more traffic scenes of the traffic model, to generate preference data of the one or more traffic scenes, to calculate a reward value, and / or to control an autonomous machine. In at least one embodiment, at least one component of Fig. 16B selects at least one aspect relating to the feedback collector 106, the model(s) 110, the reward modeler 112, the fine-tuning module 114, the processor 140 and / or the communication manager 120 of Fig. 1, the feedback collection 202, the reward modeling 204 and / or the model fine-tuning 206 of Fig. 2, the generated traffic scenarios 300 of Fig. 3, the collection of 400 scenario feedbacks from Fig. 4, the procedure 500 of Fig. 5, the procedure 600 of Fig. 6 and / or the 700 processor from Fig. 7 is described.

[0263] Fig. Figure 17 shows exemplary integrated circuits and associated graphics processors that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to the circuits shown, at least one embodiment may include further logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0264] Fig. Figure 17 is a block diagram illustrating an exemplary system-on-a-chip integrated circuit 1700, which can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1700 includes one or more application processors 1705 (e.g., CPUs), at least one graphics processor 1710, and may additionally include an image processor 1715 and / or a video processor 1720, each of which may be a modular IP core. In at least one embodiment, the integrated circuit 1700 includes peripheral or bus logic, including a USB controller 1725, a UART controller 1730, an SPI / SDIO controller 1735, and an I22S / I22C controller 1740.In at least one embodiment, the integrated circuit 1700 may include a display device 1745 connected to one or more HDMI (High-Definition Multimedia Interface) controllers 1750 and a MIPI (Mobile Industry Processor Interface) display interface 1755. In at least one embodiment, the memory may be provided by a flash memory subsystem 1760 comprising flash memory and a flash memory controller. In at least one embodiment, the memory interface may be provided via a memory controller 1765 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded safety machine 1770.

[0265] Logic 815 is used to perform inferencing and / or training operations in conjunction with one or more embodiments. Details of Logic 815 are given here in conjunction with the Fig. 8A and / or 8B described. In at least one embodiment, the logic 815 in the integrated circuit 1700 can be used for inferencing or prediction operations that are at least partially based on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0266] In at least one embodiment, at least one in Fig. 17. The component shown or described is used to implement procedures and / or functions that are associated with the Fig. 1-7 are described. In at least one embodiment, at least one component of Fig. 17 is used to initiate the generation and / or updating of a traffic model, to access one or more traffic scenes of the traffic model, to generate preference data of the one or more traffic scenes, to calculate a reward value, and / or to control an autonomous machine. In at least one embodiment, at least one component of Fig. 17 selects at least one aspect relating to the feedback collector 106, the model(s) 110, the reward modeler 112, the fine-tuning module 114, the processor 140 and / or the communication manager 120 of Fig. 1, the feedback collection 202, the reward modeling 204 and / or the model fine-tuning 206 of Fig. 2, the generated traffic scenarios 300 of Fig. 3, the collection of 400 scenario feedbacks from Fig. 4, the procedure 500 of Fig. 5, the procedure 600 of Fig. 6 and / or the 700 processor from Fig. 7 is described.

[0267] Fig. Figures 18A-18B show exemplary integrated circuits and associated graphics processors that can be fabricated using one or more IP cores according to various embodiments as described herein. In addition to the circuits shown, at least one embodiment may include further logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0268] Fig. Figures 18A - 18B are block diagrams showing exemplary graphics processors for use in a SoC according to the embodiments described herein. Fig. Figure 18A shows an exemplary graphics processor 1810 of an integrated circuit with a system on a chip, which according to at least one embodiment can be manufactured by means of one or more IP cores. Fig. 18B represents an additional exemplary graphics processor 1840 of an integrated circuit with a system on a chip, which can be manufactured according to at least one embodiment using one or more IP cores. Fig. Figure 18B shows another exemplary graphics processor 1840 of an integrated circuit with a system-on-a-chip, which, according to at least one embodiment, can be manufactured using one or more IP cores. In at least one embodiment, the graphics processor 1810 is of Fig. 18A is a power-saving graphics processor core. In at least one embodiment, the graphics processor is 1840. Fig. 18B is a higher-performance graphics processor core. In at least one embodiment, each of the graphics processors 1810, 1840 can be a variant of the graphics processor 1710. Fig. Be 17.

[0269] In at least one embodiment, the graphics processor 1810 comprises a vertex processor 1805 and one or more fragment processor(s) 1815A-1815N (e.g., 1815A, 1815B, 1815C, 1815D to 1815N-1 and 1815N). In at least one embodiment, the graphics processor 1810 can execute different shader programs via separate logic, such that the vertex processor 1805 is optimized for executing operations for vertex shader programs, while one or more fragment processor(s) 1815A-1815N execute fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the Vertex Processor 1805 performs a vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data.In at least one embodiment, the fragment processors 1815A-1815N use the primitive and vertex data generated by the vertex processor 1805 to create an image buffer that is displayed on a display device. In at least one embodiment, the fragment processor(s) 1815A-1815N is / are optimized for executing fragment shader programs as provided in an OpenGL API, which can be used to perform operations similar to those of a pixel shader program as provided in a Direct3D API.

[0270] In at least one embodiment, the graphics processor 1810 additionally comprises one or more memory management units (MMUs) 1820A-1820B, one or more caches 1825A-1825B, and one or more interconnects 1830A-1830B. In at least one embodiment, one or more MMUs 1820A-1820B provide the mapping of virtual to physical addresses for the graphics processor 1810, including for the vertex processor 1805 and / or the fragment processor(s) 1815A-1815N, which, in addition to the vertex or image / texture data stored in one or more caches 1825A-1825B, can refer to vertex or image / texture data stored in memory.In at least one embodiment, one or more MMU(s) 1820A-1820B can be synchronized with other MMUs within the system, including one or more MMUs connected to one or more application processors 1705, image processors 1715 and / or video processors 1720. Fig. 17 are assigned, so that each processor 1705-1720 can participate in a common or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1830A-1830B enable the graphics processor 1810 to connect to other IP cores within the SoC, either via an internal bus of the SoC or via a direct connection.

[0271] In at least one embodiment, the graphics processor 1840 has one or more shader core(s) 1855A-1855N (e.g. 1855A, 1855B, 1855C, 1855D, 1855E, 1855F to 1855N-1 and 1855N), as described in n Fig. Figure 18B illustrates a unified shader core architecture where a single core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the 1840 graphics processor includes an inter-core task manager 1845, which acts as a thread dispatcher to distribute execution threads to one or more shader cores 1855A-1855N and a tiling unit 1858 to accelerate tiling operations for tile-based rendering, where rendering operations for a scene are subdivided in image space to, for example, exploit local spatial coherence within a scene or optimize the use of internal caches.

[0272] Logic 815 is used to perform inferencing and / or training operations in conjunction with one or more embodiments. Details of Logic 815 are given here in conjunction with the Fig. 8A and / or 8B described. In at least one embodiment, the logic 815 in the graphics processor 1810 and / or 1840 can be used for inferencing or prediction operations that are at least partially based on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0273] In at least one embodiment, at least one is incorporated into the Fig. The component shown or described in 18A-B is used to implement procedures and / or functions related to the Fig. 1-7 are described. In at least one embodiment, at least one component of the Fig. 18A-B is used to initiate the generation and / or updating of a traffic model, to access one or more traffic scenes of the traffic model, to generate preference data of the one or more traffic scenes, to calculate a reward value, and / or to control an autonomous machine. In at least one embodiment, at least one component of the Fig. 18A-B selects at least one aspect relating to the feedback collector 106, the model(s) 110, the reward modeler 112, the fine-tuning module 114, the processor 140 and / or the communication manager 120 of Fig. 1, the feedback collection 202, the reward modeling 204 and / or the model fine-tuning 206 of Fig. 2, the generated traffic scenarios 300 of Fig. 3, the collection of 400 scenario feedbacks from Fig. 4, the procedure 500 of Fig. 5, the procedure 600 of Fig. 6 and / or the 700 processor from Fig. 7 is described.

[0274] Fig. Figures 19A-19B illustrate an additional exemplary graphics processor logic according to the embodiments described herein. In at least one embodiment, the components described in the Fig. 19A-19B are shown and described by these, are integrated into a single system, such as a graphics processing unit (GPU), a SoC or another type of processor. Fig. Figure 19A shows a graphics core 1900, which in at least one embodiment is integrated into the graphics processor 1710. Fig. 17 may be present and in at least one embodiment a uniform shader core 1855A-1855N as in Fig. It could be 18B. Fig. Figure 19B illustrates a highly parallel, general-purpose graphics processing unit (“GPGPU,” which may also be referred to as a graphics processing unit) 1930, which in at least one embodiment is suitable for use on a multi-chip module. In at least one embodiment, the graphics processing unit 1930 is a GPGPU comprising a graphics processor. In at least one embodiment, the integrated circuit 1700 comprises the graphics core 1900, for example, to form an integrated circuit and / or a system-on-a-chip (SoC), wherein such an integrated circuit and / or such an SoC performs the operations described herein.

[0275] In at least one embodiment, the graphics core 1900 includes a shared instruction cache 1902, a texture unit 1918, and a cache / shared memory 1920 (e.g., with L1, L2, L3, a last-level cache, or other caches) that are common to the execution resources within the graphics core 1900. In at least one embodiment, the graphics core 1900 can have multiple slices 1901A-1901N or partitions for each core, and a graphics processor can have multiple instances of the graphics core 1900. In at least one embodiment, each slice 1901A-1901N relates to the graphics core 1900. In at least one embodiment, the slices 1901A-1901N have sub-slices that are part of a slice 1901A-1901N. In at least one embodiment, the slices 1901A-1901N are independent of other slices or dependent on other slices.The slices 1901A-1901N can, in at least one embodiment, include support logic comprising a local instruction cache 1904A-1904N, a thread scheduler (control unit) 1906A-1906N, a thread dispatcher 1908A-1908N and a set of registers 1910A-1910N. In at least one embodiment, the slices 1901A-1901N can include a set of additional functional units (AFUs 1912A-1912N), floating-point units (FPUs 1914A-1914N), integer arithmetic logic units (ALUs 1916-1916N), address calculation units (ACUs 1913A-1913N), double-precision floating-point units (DPFPUs 1915A-1915N), and matrix processing units (MPUs 1917A-1917N). In at least one embodiment, the MPUs 1917A-1917N are referred to as matrix machines.

[0276] In at least one embodiment, each slice 1901A-1901N includes one or more engines or machines for floating-point and integer vector operations, as well as one or more machines for accelerating convolution and matrix operations in AI, machine learning, or large datasets. In at least one embodiment, one or more slices 1901A-1901N include one or more vector machines for computing a vector (e.g., for computing mathematical operations on vectors). In at least one embodiment, a vector machine can compute a vector operation in 16-bit floating-point (also referred to as "FP16"), 32-bit floating-point (also referred to as "FP32"), or 64-bit floating-point (also referred to as "FP64").In at least one embodiment, one or more slices 1901A-1901N comprise 16 vector machines paired with 16 matrix math units to compute matrix / tensor operations, the vector machines and math units being accessible via matrix extensions. In at least one embodiment, a slice comprises a specific portion of the processing resources of a processing unit, e.g., 16 cores and a ray tracing unit, or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units for a processor. In at least one embodiment, the graphics core 1900 comprises one or more matrix machines to compute matrix operations, e.g., when computing tensor operations.

[0277] In at least one embodiment, one or more slices 1901A-1901N have one or more ray tracing units to compute ray tracing operations (e.g., 16 ray tracing units per slice of slices 1901A-1901N). In at least one embodiment, a ray tracing unit computes a ray traversal, a triangle intersection, a bounding box intersection, or other ray tracing operations.

[0278] In at least one embodiment, one or more slices 1901A-1901N include a media slice that encodes, decodes and / or transcodes data, scales and / or formats data and / or performs operations to improve video quality on video data.

[0279] In at least one embodiment, one or more slices 1901A-1901N are connected to an L2 cache and memory structure, interconnects, HBM memory stacks (e.g., HBM2e, HDM3), and a media machine. In at least one embodiment, one or more slices 1901A-1901N have multiple cores (e.g., 16 cores) and multiple ray tracing units (e.g., 16) coupled to each core. In at least one embodiment, one or more slices 1901A-1901N have one or more L1 caches. In at least one embodiment, one or more slices 1901A-1901N have one or more vector machines, one or more instruction caches for storing instructions, one or more L1 caches for caching data, one or more shared local storage (SLMs) for storing data, etc.B, which correspond to commands; one or more samplers for sampling data; one or more ray tracing units for performing ray tracing operations; one or more geometries for performing operations in geometry pipelines and / or for applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image in vector graphics format (e.g., shape) and converting it into a raster image (e.g., a series of pixels, points, or lines that, when displayed together, create an image represented by shapes); one or more hierarchical depth buffers (Hiz) for buffering data; and / or one or more pixel backends. In at least one embodiment, the slice 1901A-1901N includes a memory structure, e.g., an L2 cache.

[0280] In at least one embodiment, the FPUs 1914A-1914N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 1915A-1915N perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 1916A-1916N can perform variable-precision integer operations at 8-bit, 16-bit, and 32-bit precision and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 1917A-1917N can also be configured for mixed-precision matrix operations, including floating-point and 8-bit half-precision integer operations. In at least one embodiment, the MPUs 1917-1917N can perform a variety of matrix operations to accelerate machine learning application frameworks, including support for accelerated general matrix-matrix multiplication (GEMM).In at least one embodiment, the AFUs 1912A-1912N can perform additional logical operations not supported by floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0281] Logic 815 is used to perform inferencing and / or training operations in conjunction with one or more embodiments. Details of Logic 815 are given here in conjunction with the Fig. 8A and / or 8B described. In at least one embodiment, the logic 815 in the graphics kernel 1900 can be used for inferencing or prediction operations that are at least partially based on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0282] In at least one embodiment, the graphics core 1900 has a connection and a link fabric sublayer that is connected to a switch and a GPU-to-GPU bridge, enabling multiple graphics processors 1900 (e.g., 8) to be connected without adhesive, with load / store units (LSUs), data transfer units, and synchronization semantics across multiple graphics processors 1900. In at least one embodiment, the connections have standardized connections (e.g., PCIe) or a combination thereof.

[0283] In at least one embodiment, the 1900 graphics core comprises multiple tiles. In at least one embodiment, a tile is a single die or one or more dies, wherein individual dies may be connected by a link (e.g., an embedded multi-die interconnect bridge (EMIB)). In at least one embodiment, the 1900 graphics core comprises a compute tile, a memory tile (e.g., when a memory tile can be accessed exclusively by different tiles or different chipsets, such as a Rambo tile), a substrate tile, a base tile, an HMB tile, a link tile, and an EMIB tile, wherein all tiles in the 1900 graphics core are combined as part of a GPU. In at least one embodiment, the 1900 graphics core may have multiple tiles in a single package (also referred to as a "multi-tile package").In at least one embodiment, a compute tile can have 8 Graphics Cores 1900, an L1 cache, and a base tile with a host interface including PCIe 5.0, HBM2e, MDFI, and EMIB, a link tile with 8 links, 8 ports, and an embedded switch. In at least one embodiment, the tiles are connected via face-to-face (F2F) chip-on-chip bonding using finely graduated 36-micrometer microbumps (e.g., copper pillars). In at least one embodiment, the Graphics Core 1900 has a memory structure containing a memory and is a tile accessible to multiple tiles. In at least one embodiment, the Graphics Core 1900 stores, accesses, or loads its own hardware contexts in memory, wherein a hardware context is a set of data loaded from registers before a process continues, and wherein a hardware context can indicate a state of the hardware (e.g., the state of a GPU).

[0284] In at least one embodiment, the 1900 graphics core includes a serialization / deserialization circuit (SERIALIZER / DESERIALIZER (SERDES)) that converts a serial data stream into a parallel data stream or converts a parallel data stream into a serial data stream.

[0285] In at least one embodiment, the graphics core 1900 features a coherent high-speed unified fabric (GPU to GPU), load / store units, mass data transfer and sync semantics, and GPUs connected via an embedded switch, wherein a GPU-GPU bridge is controlled by a controller.

[0286] In at least one embodiment, the graphics kernel 1900 executes an API, wherein the API abstracts the hardware of the graphics kernel 1900 and accesses libraries containing instructions for performing mathematical operations (e.g., math kernel library), deep neural network operations (e.g., deep neural network library), vector operations, collective communication, thread building blocks, video processing, data analysis library, and / or ray tracing operations.

[0287] In at least one embodiment, at least one in Fig. 19A component shown or described is used to implement procedures and / or functions that are associated with the Fig. 1-7 are described. In at least one embodiment, at least one component of Fig. 19A is used to initiate the generation and / or updating of a traffic model, to access one or more traffic scenes of the traffic model, to generate preference data of the one or more traffic scenes, to calculate a reward value, and / or to control an autonomous machine. In at least one embodiment, at least one component of Fig. 19A selects at least one aspect relating to the feedback collector 106, the model(s) 110, the reward modeler 112, the fine-tuning module 114, the processor 140 and / or the communication manager 120 of Fig. 1, the feedback collection 202, the reward modeling 204 and / or the model fine-tuning 206 of Fig. 2, the generated traffic scenarios 300 of Fig. 3, the collection of 400 scenario feedbacks from Fig. 4, the procedure 500 of Fig. 5, the procedure 600 of Fig. 6 and / or the 700 processor from Fig. 7 is described.

[0288] Fig. Figure 19B illustrates a GPGPU 1930, which in at least one embodiment can be configured to perform highly parallel computational operations through an array of graphics processing units. In at least one embodiment, the GPGPU 1930 can be directly connected to other instances of the GPGPU 1930 to form a multi-GPU cluster and improve the training speed for deep neural networks. In at least one embodiment, the GPGPU 1930 has a host interface 1932 to enable communication with a host processor. In at least one embodiment, the host interface 1932 is a PCI Express interface. In at least one embodiment, the host interface 1932 can be a vendor-specific communication interface or communication structure.In at least one embodiment, the GPGPU 1930 receives instructions from a host processor and uses a global scheduler 1934 (which can be described as a thread control unit and / or an asynchronous computational machine) to distribute the execution threads associated with these instructions across a set of compute clusters 1936A-1936H. In at least one embodiment, the compute clusters 1936A-1936H share a cache memory 1938. In at least one embodiment, the cache memory 1938 can serve as a higher-level cache for cache memories within compute clusters 1936A-1936H. In at least one embodiment, the compute clusters 1936A-1936H comprise a slice or are referred to as "slices". In at least one embodiment, the GPGPU 1930 is part of a system-on-a-chip (SoC), for example, part of the integrated circuit 1700. Fig. 17).

[0289] In at least one embodiment, the GPGPU 1930 has a memory 1944A-1944B coupled to compute clusters 1936A-1936H (e.g., one or more HBM2e controllers) via a series of memory controllers 1942A-1942B. In at least one embodiment, the memory 1944A-1944B can have different types of memory devices, including dynamic random-access memory (DRAM) or graphics random-access memory, such as synchronous graphics random-access memory (SGRAM), including graphics dual-rate memory (GDDR).

[0290] In at least one embodiment, the 1936A-1936H compute clusters each have a set of graphics cores, such as the 1900 graphics core from Fig. 19A, which can have several types of integer and floating-point logic units capable of performing arithmetic operations with a range of accuracies suitable for machine learning computations. For example, in at least one embodiment, at least one subset of floating-point units in each of the compute clusters 1936A-1936H can be configured to perform 16-bit or 32-bit floating-point operations, while another subset of floating-point units can be configured to perform 64-bit floating-point operations.

[0291] In at least one embodiment, multiple instances of the GPGPU 1930 can be configured to operate as a compute cluster. In at least one embodiment, the communication used by the compute clusters 1936A-1936H for synchronization and data exchange varies between the embodiments. In at least one embodiment, multiple instances of the GPGPU 1930 communicate via the host interface 1932. In at least one embodiment, the GPGPU 1930 has an I / O hub 1939 that couples the GPGPU 1930 to a GPU link 1940, enabling a direct connection to other instances of the GPGPU 1930. In at least one embodiment, the GPU link 1940 is coupled to a dedicated GPU-to-GPU bridge, enabling communication and synchronization between multiple instances of the GPGPU 1930.In at least one embodiment, the GPU link 1940 is coupled to a high-speed connection for sending and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, multiple instances of the GPGPU 1930 are located in separate data processing systems and communicate via a network device accessible through the host interface 1932. In at least one embodiment, the GPU link 1940 can be configured to provide a connection to a host processor in addition to or as an alternative to the host interface 1932.

[0292] In at least one embodiment, the GPGPU 1930 can be configured to train neural networks. In at least one embodiment, the GPGPU 1930 can be used within an inferencing platform. In at least one embodiment where the GPGPU 1930 is used for inferencing, the GPGPU can have fewer compute clusters 1936A-1936H than when the GPGPU is used for training a neural network. In at least one embodiment, the memory technology associated with the memory 1944A-1944B can differ between inferencing and training configurations, with higher-bandwidth memory technologies being assigned to the training configurations. In at least one embodiment, the inferencing configuration of the GPGPU 1930 can support inferencing-specific instructions.For example, in at least one embodiment, an inferencing configuration can provide support for one or more 8-bit integer dot product instructions that can be used during inferencing operations for deployed neural networks.

[0293] Logic 815 is used to perform inferencing and / or training operations in conjunction with one or more embodiments. Details of Logic 815 are given here in conjunction with the Fig. 8A and / or 8B described. In at least one embodiment, the logic 815 in the GPGPU 1930 can be used for inferencing or prediction operations that are at least partially based on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0294] In at least one embodiment, at least one in Fig. The component shown or described in 19B is used to implement procedures and / or functions related to the Fig. 1-7 are described. In at least one embodiment, at least one component of Fig. 19B is used to initiate the generation and / or updating of a traffic model, to access one or more traffic scenes of the traffic model, to generate preference data of the one or more traffic scenes, to calculate a reward value, and / or to control an autonomous machine. In at least one embodiment, at least one component of Fig. 19B selects at least one aspect relating to the feedback collector 106, the model(s) 110, the reward modeler 112, the fine-tuning module 114, the processor 140 and / or the communication manager 120 of Fig. 1, the feedback collection 202, the reward modeling 204 and / or the model fine-tuning 206 of Fig. 2, the generated traffic scenarios 300 of Fig. 3, the collection of 400 scenario feedbacks from Fig. 4, the procedure 500 of Fig. 5, the procedure 600 of Fig. 6 and / or the 700 processor from Fig. 7 is described.

[0295] Fig. Figure 20 is a block diagram showing a computing system 2000 according to at least one embodiment. In at least one embodiment, the computing system 2000 comprises a processing subsystem 2001 with one or more processors 2002 and a system memory 2004, which communicate via a connection path that may include a memory hub 2005. In at least one embodiment, the memory hub 2005 may be a separate component within a chipset component or be integrated into one or more processors 2002. In at least one embodiment, the memory hub 2005 is connected to an I / O subsystem 2011 via a communication link 2006. In at least one embodiment, the I / O subsystem 2011 includes an I / O hub 2007, which enables the computing system 2000 to receive input from one or more input devices 2008.In at least one embodiment, the I / O hub 2007 enables a display controller, which may be contained in one or more processor(s) 2002, to provide outputs to one or more display device(s) 2010A. In at least one embodiment, one or more display device(s) 2010A coupled to the I / O hub 2007 may comprise a local, internal, or embedded display device.

[0296] In at least one embodiment, the processing subsystem 2001 comprises one or more parallel processor(s) 2012 connected to the memory hub 2005 via a bus or other communication link 2013. In at least one embodiment, the communication link 2013 may be, but is not limited to, any number of standards-based communication link technologies or protocols, such as PCI Express, or a vendor-specific communication interface or communication structure. In at least one embodiment, some or all of the parallel processors 2012 form a computationally focused parallel or vector processing system, which may include a large number of processing cores and / or processing clusters, such as a many-integrated core (MIC) processor.In at least one embodiment, one or more parallel processor(s) 2012 form a graphics processing subsystem that can output pixels to one or more display devices 2010A coupled via the I / O hub 2007. In at least one embodiment, one or more parallel processor(s) 2012 can also include a display controller and a display interface (not shown) to enable a direct connection to one or more display devices 2010B. In at least one embodiment, the parallel processor(s) 2012 has one or more cores, such as the graphics cores 1900 discussed here.

[0297] In at least one embodiment, a system storage unit 2014 can be connected to the I / O hub 2007 to provide a storage mechanism for the computer system 2000. In at least one embodiment, an I / O switch 2016 can be used to provide an interface mechanism to enable connections between the I / O hub 2007 and other components, such as a network adapter 2018 and / or a wireless network adapter 2019, which may be integrated into the platform, and various other devices that may be added via one or more add-in devices 2020. In at least one embodiment, the network adapter 2018 can be an Ethernet adapter or another wired network adapter.In at least one embodiment, the wireless network adapter 2019 may include one or more Wi-Fi, Bluetooth, Near Field Communication (NFC) or other networking devices, which include one or more wireless radio devices.

[0298] In at least one embodiment, the Computing System 2000 may include other components not explicitly shown, including USB or other ports, optical storage drives, video recording devices, and the like, which may also be connected to the I / O Hub 2007. In at least one embodiment, communication paths connecting various components in Fig. 20 interconnect, be implemented using any suitable protocols, such as PCI (Peripheral Component Interconnect)-based protocols (e.g. PCI-Express) or other bus or point-to-point communication interfaces and / or protocols, such as NV-Link High-Speed ​​Interconnect or Interconnect protocols.

[0299] In at least one embodiment, one or more parallel processor(s) 2012 have a circuit optimized for graphics and video processing, which, for example, includes a video output circuit and represents a graphics processing unit (GPU). For example, the parallel processor(s) 2012 have the graphics core 1900. In at least one embodiment, one or more parallel processor(s) 2012 contain circuits optimized for general-purpose processing. In at least one embodiment, components of the computing system 2000 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processor(s) 2012, a memory hub 2005, a processor(s) 2002, and an I / O hub 2007 can be integrated in an integrated circuit with a system-on-a-chip (SoC).In at least one embodiment, the components of the Computer System 2000 can be integrated into a single enclosure to form a System-in-Package (SIP) configuration. In at least one embodiment, at least one section of the components of the Computer System 2000 can be integrated into a Multi-Chip Module (MCM), which can be interconnected with other Multi-Chip Modules to form a modular computer system.

[0300] Logic 815 is used to perform inferencing and / or training operations in conjunction with one or more embodiments. Details of Logic 815 are given here in conjunction with the Fig. 8A and / or 8B described. In at least one embodiment, the logic 815 in the system 2000 can be used for inferencing or prediction operations that are based at least partially on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0301] In at least one embodiment, at least one in Fig. 20 components shown or described are used to implement procedures and / or functions that are associated with the Fig. 1-7 are described. In at least one embodiment, at least one component of Fig. 20 is used to initiate the generation and / or updating of a traffic model, to access one or more traffic scenes of the traffic model, to generate preference data of the one or more traffic scenes, to calculate a reward value, and / or to control an autonomous machine. In at least one embodiment, at least one component of Fig. 20 select at least one aspect relating to the feedback collector 106, the model(s) 110, the reward modeler 112, the fine-tuning module 114, the processor 140 and / or the communication manager 120 of Fig. 1, the feedback collection 202, the reward modeling 204 and / or the model fine-tuning 206 of Fig. 2, the generated traffic scenarios 300 of Fig. 3, the collection of 400 scenario feedbacks from Fig. 4, the procedure 500 of Fig. 5, the procedure 600 of Fig. 6 and / or the 700 processor from Fig. 7 is described. PROCESSORS

[0302] Fig. Figure 21A illustrates a parallel processor 2100 according to at least one embodiment. In at least one embodiment, various components of the parallel processor 2100 can be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the parallel processor 2100 shown is a variant of one or more parallel processors 212, which are implemented in Fig. Figure 20 is shown according to an exemplary embodiment. In at least one embodiment, the parallel processor 2100 has one or more graphics cores 1900.

[0303] In at least one embodiment, the parallel processor 2100 includes a parallel processing unit 2102. In at least one embodiment, the parallel processing unit 2102 includes an I / O unit 2104, which enables communication with other devices, including other instances of the parallel processing unit 2102. In at least one embodiment, the I / O unit 2104 can be directly connected to other devices. In at least one embodiment, the I / O unit 2104 is connected to other devices via a hub or switch interface, such as the memory hub 2005. In at least one embodiment, the connections between the memory hub 2005 and the I / O unit 2104 form a communication link 213.In at least one embodiment, the I / O unit 2104 is connected to a host interface 2106 and a memory interface 2116, wherein the host interface 2106 receives commands for performing processing operations and the memory interface 2116 receives commands for performing storage operations.

[0304] In at least one embodiment, when the host interface 2106 receives an instruction buffer via the I / O unit 2104, the host interface 2106 can direct work operations to a front end 2108 for the execution of these instructions. In at least one embodiment, the front end 2108 is coupled to a scheduler 2110 (which can be referred to as a control unit) configured to distribute instructions or other work items to a processing cluster arrangement 2112. In at least one embodiment, the scheduler 2110 ensures that the processing cluster arrangement 2112 is properly configured and in a valid state before tasks are distributed to the cluster of the processing cluster arrangement 2112. In at least one embodiment, the scheduler 2110 is implemented via firmware logic running on a microcontroller.In at least one embodiment, the microcontroller-implemented scheduler 2110 is configured to perform complex sequence control and work distribution operations with coarse and fine granularity, enabling fast interruption and context switching of threads running on the processing cluster 2112. In at least one embodiment, the host software can detect workloads for scheduling on the processing cluster 2112 via one of several graphics processing paths. In at least one embodiment, the workloads can then be automatically distributed to the processing cluster 2112 by the logic of the scheduler 2110 within a microcontroller that incorporates the scheduler 2110.

[0305] In at least one embodiment, the processing cluster arrangement 2112 can have up to "N" processing clusters (e.g., cluster 2114A, cluster 2114B, up to cluster 2114N), where "N" is a positive integer (which may be a different positive integer "N" than the one used in the other figures). In at least one embodiment, each cluster 2114A-2114N of the processing cluster arrangement 2112 can execute a large number of concurrent threads. In at least one embodiment, the scheduler 2110 can allocate work to the clusters 2114A-2114N of the processing cluster arrangement 2112 by using various flow control and / or work distribution algorithms that can vary depending on the workload generated by each type of program or computation.In at least one embodiment, scheduling can be performed dynamically by the scheduler 2110 or partially supported by compiler logic during the compilation of the program logic, which is configured for execution by the processing cluster arrangement 2112. In at least one embodiment, different clusters 2114A-2114N of the processing cluster arrangement 2112 can be assigned for processing different types of programs or for performing different types of calculations.

[0306] In at least one embodiment, the processing cluster arrangement 2112 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster arrangement 2112 is configured to perform parallel general-purpose computing operations. For example, in at least one embodiment, the processing cluster arrangement 2112 can include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0307] In at least one embodiment, the processing cluster arrangement 2112 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster arrangement 2112 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster arrangement 2112 may be configured to execute graphics processing-related shader programs, such as vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2102 may transfer data from system memory via the I / O unit 2104 for processing.In at least one embodiment, the transmitted data can be stored in on-chip memory (e.g., in the parallel processor memory 2122) during processing and then written back to system memory.

[0308] In at least one embodiment, when the parallel processing unit 2102 is used to perform graphics processing, the scheduler 2110 can be configured to divide a processing load into approximately equal tasks to enable better distribution of the graphics processing operations across multiple clusters 2114A-2114N of the processing cluster arrangement 2112. In at least one embodiment, sections of the processing cluster arrangement 2112 can be configured to perform different types of processing.For example, in at least one embodiment, a first section can be configured to perform vertex shading and topology generation, a second section can be configured to perform tessellation and geometry shading, and a third section can be configured to perform pixel shading or other screenspace operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more clusters 2114A-2114N can be stored in buffers so that intermediate data can be transferred between clusters 2114A-2114N for further processing.

[0309] In at least one embodiment, the processing cluster arrangement 2112 can receive processing tasks to be executed via the scheduler 2110, which receives instructions for defining processing tasks from the frontend 2108. In at least one embodiment, the processing tasks can have indices of the data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and instructions that define how the data is to be processed (e.g., which program is to be executed). In at least one embodiment, the scheduler 2110 can be configured to retrieve indices corresponding to the tasks or to receive indices from the frontend 2108. In at least one embodiment, the frontend 2108 can be configured to ensure that the processing cluster arrangement 2112 is configured in a valid state before an incoming instruction buffer (e.g.,Batch buffer, push buffer, etc.) specified workload is initiated.

[0310] In at least one embodiment, each instance of the parallel processing unit 2102 can be coupled to the parallel processor memory 2122. In at least one embodiment, the parallel processor memory 2122 can be accessed via the memory coupling field 2116, which can receive memory requests from the processing cluster arrangement 2112 and the I / O unit 2104. In at least one embodiment, the memory coupling field 2116 can access the parallel processor memory 2122 via a memory interface 2118. In at least one embodiment, the memory interface 2118 can have several partition units (e.g., partition unit 2120A, partition unit 2120B to partition unit 2120N), each of which can be coupled to a section (e.g., a memory unit) of the parallel processor memory 2122.In at least one embodiment, the number of partition units 2120A-2120N is configured to correspond to the number of storage units, such that a first partition unit 2120A has a corresponding first storage unit 2124A, a second partition unit 2120B has a corresponding storage unit 2124B, and an Nth partition unit 2120N has a corresponding Nth storage unit 2124N. In at least one embodiment, the number of partition units 2120A-2120N cannot be equal to the number of storage units.

[0311] In at least one embodiment, the memory units 2124A-2124N can have different types of memory facilities, including dynamic random-access memory (DRAM) or graphics random-access memory, such as synchronous graphics random-access memory (SGRAM), including graphics dual-rate memory (GDDR). In at least one embodiment, the memory units 2124A-2124N can also have 3D stacked memory, including, but not limited to, high-bandwidth memory (HBM, HBM2e, or HBM3). In at least one embodiment, rendering targets, such as frame buffers or texture maps, can be stored across the memory units 2124A-2124N, so that the partition units 2120A-2120N can write sections of each rendering target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 2122.In at least one embodiment, a local instance of the parallel processor memory 2122 can be excluded in favor of a unified memory design that uses the system memory in conjunction with the local cache memory.

[0312] In at least one embodiment, each of the clusters 2114A-2114N of the processing cluster arrangement 2112 can process data written to each of the storage units 2124A-2124N in the parallel processor memory 2122. In at least one embodiment, the memory interface 2116 can be configured to transmit an output from each cluster 2114A-2114N to any partition unit 2120A-2120N or to another cluster 2114A-2114N, which can perform additional processing operations on an output. In at least one embodiment, each cluster 2114A-2114N can communicate with the memory interface 2118 via the memory interface 2116 to read from or write to various external devices.In at least one embodiment, the memory interconnect 2116 has a connection to the memory interface 2118 for communication with the I / O unit 2104, as well as a connection to a local instance of the parallel processor memory 2122, so that the processing units in the various processing clusters 2114A-2114N can communicate with the system memory or other memory that is not local to the parallel processing unit 2102. In at least one embodiment, the memory interconnect 2116 can use virtual channels to separate traffic flows between clusters 2114A-2114N and partition units 2120A-2120N.

[0313] In at least one embodiment, multiple instances of the Parallel Processing Unit 2102 can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of the Parallel Processing Unit 2102 can be configured to cooperate even if the different instances have a different number of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of the Parallel Processing Unit 2102 can have higher-precision floating-point units compared to other embodiments.In at least one embodiment, systems containing one or more instances of the Parallel Processing Unit 2102 or the Parallel Processor 2100 can be implemented in a variety of embodiments and form factors, including, but not limited to, desktop, laptop or handheld personal computers, servers, workstations, game consoles and / or embedded systems.

[0314] Fig. Figure 21B is a block diagram of a partition unit 2120 according to at least one embodiment. In at least one embodiment, the partition unit 2120 is an instance of one of the partition units 2120A-2120N. Fig. 21A. In at least one embodiment, the partition unit 2120 comprises an L2 cache 2121, a single-frame buffer interface 2125, and a ROP 2126 (raster operation unit). In at least one embodiment, the L2 cache 2121 is a read / write cache configured to perform load and store operations received from the memory coupling array 2116 and the ROP 2126. In at least one embodiment, read errors and urgent write-back requests are output from the L2 cache 2121 to the single-frame buffer interface 2125 for processing. In at least one embodiment, updates can also be sent to a single-frame buffer for processing via the single-frame buffer interface 2125. In at least one embodiment, the single-frame buffer interface 2125 is connected to one of the storage units in the parallel processor memory, such as the storage units 2124A-2124N of Fig. 21A (e.g., within the parallel processor memory 2122).

[0315] In at least one embodiment, the ROP 2126 is a processing unit that performs raster operations such as stenciling, Z-testing, blending, etc. In at least one embodiment, the ROP 2126 then outputs processed graphics data, which is stored in graphics memory. In at least one embodiment, the ROP 2126 has compression logic to compress depth or color data written to memory and to decompress depth or color data read from memory. In at least one embodiment, the compression logic can be lossless compression logic that uses one or more of several compression algorithms. In at least one embodiment, the type of compression performed by the ROP 2126 can vary based on statistical characteristics of the data to be compressed.For example, in at least one embodiment, delta color compression is performed on depth and color data on a per-tile basis.

[0316] In at least one embodiment, the ROP 2126 is in each processing cluster (e.g., clusters 2114A-2114N of Fig. 21) and not present in the partition unit 2120. In at least one embodiment, read and write requests for pixel data are transmitted via the memory coupling field 2116 instead of pixel fragment data. In at least one embodiment, processed graphics data can be displayed on a display device, such as one of one or more display devices 2010 of Fig. 20, for further processing by processor(s) 2002 or for further processing by one of the processing units within the parallel processor 2100 of Fig. 21A.

[0317] Fig. Figure 21C is a block diagram of a processing cluster 2114 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is an instance of one of the processing clusters 2114A-2114N of Fig. 21. In at least one embodiment, the processing cluster 2114 can be configured to execute many threads in parallel, where the term "thread" refers to an instance of a particular program running on a particular set of input data. In at least one embodiment, single-instruction, multiple-data (SIMD) instruction output techniques are used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single-instruction, multiple-thread (SIMT) techniques are used to support the parallel execution of a large number of generally synchronized threads, with a common instruction unit configured to issue instructions to a set of processing machines within each of the processing clusters.

[0318] In at least one embodiment, the operation of the processing cluster 2114 can be controlled via a pipeline manager 2132, which distributes the processing tasks to parallel SIMT processors. In at least one embodiment, the pipeline manager 2132 receives instructions from the scheduler 2110 of the Fig. 21 and manages the execution of these instructions via a graphics multiprocessor 2134 and / or a texture unit 2136. In at least one embodiment, the graphics multiprocessor 2134 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, different types of SIMT parallel processors with different architectures can be present in the processing cluster 2114. In at least one embodiment, one or more instances of the graphics multiprocessor 2134 can be present in a processing cluster 2114. In at least one embodiment, the graphics multiprocessor 2134 can process data, and a data coupling field 2140 can be used to distribute the processed data to one of several possible destinations, including other shader units.In at least one embodiment, the pipeline manager 2132 can facilitate the distribution of the processed data by specifying destinations for the processed data to be distributed via the data coupling field 2140.

[0319] In at least one embodiment, each graphics multiprocessor 2134 within the processing cluster 2114 can have an identical set of functional execution logic (e.g., arithmetic logic units, load memory units, etc.). In at least one embodiment, the functional execution logic can be configured in a pipeline so that new instructions can be issued before previous instructions have completed. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifting, and the computation of various algebraic functions. In at least one embodiment, the same hardware with functional units can be used to perform different operations, and any combination of functional units can be present.

[0320] In at least one embodiment, the instructions transmitted to the processing cluster 2114 form a thread. In at least one embodiment, a set of threads executed across a set of parallel processing machines is a thread group. In at least one embodiment, the thread group executes a common program with different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing machine within a graphics multiprocessor 2134. In at least one embodiment, a thread group can have fewer threads than the number of processing units in the graphics multiprocessor 2134.In at least one embodiment, if a thread group has fewer threads than the number of processing machines, one or more of the processing machines can be idle during the cycles in which that thread group is processed. In at least one embodiment, a thread group can also have more threads than the number of processing machines in the 2134 graphics multiprocessor. In at least one embodiment, if a thread group has more threads than the number of processing machines in the 2134 graphics multiprocessor, processing can occur over successive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on a 2134 graphics multiprocessor.

[0321] In at least one embodiment, the graphics multiprocessor 2134 has an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2134 can forgo an internal cache and use a cache memory (e.g., L1 cache 2148) within the processing cluster 2114. In at least one embodiment, each graphics multiprocessor 2134 also has access to L2 caches within partition units (e.g., partition units 2120A-2120N of Fig. 21), which are shared by all processing clusters 2114 and can be used for data transfer between threads. In at least one embodiment, the graphics multiprocessor 2134 can also access global memory off-chip, which may include one or more local parallel processor memories and / or system memories. In at least one embodiment, any memory outside the parallel processing unit 2102 can be used as global memory. In at least one embodiment, the processing cluster 2114 has multiple instances of the graphics multiprocessor 2134 that can share common instructions and data, which may be stored in the L1 cache 2148.

[0322] In at least one embodiment, each processing cluster 2114 can have an MMU 2145 (Memory Management Unit) configured to translate virtual addresses into physical addresses. In at least one embodiment, one or more instances of the MMU 2145 can be located within the memory interface 2118 of Fig. 21. In at least one embodiment, the MMU 2145 includes a set of page table entries (PTEs) used to map a virtual address to a physical address of a tile (see Tiles for more information), and optionally a cache row index. In at least one embodiment, the MMU 2145 may include address translation lookaside buffers (TLBs) or caches, which may be located in the graphics multiprocessor 2134, the L1 cache, or the processing cluster 2114. In at least one embodiment, a physical address is processed to distribute access to the surface data locally, enabling efficient request nesting between the partition units. In at least one embodiment, a cache row index may be used to determine whether a request for a cache row is a hit or a miss.

[0323] In at least one embodiment, a processing cluster 2114 can be configured such that each graphics multiprocessor 2134 is coupled to a texture unit 2136 to perform texture mapping operations, e.g., determining texture sampling positions, reading texture data, and filtering texture data. In at least one embodiment, the texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2134 and retrieved as needed from an L2 cache, local parallel processor memory, or system memory.In at least one embodiment, each graphics multiprocessor 2134 outputs processed tasks to the data interface 2140 to make the processed task available to another processing cluster 2114 for further processing or to store the processed task via the memory interface 2116 in an L2 cache, in local parallel processor memory, or in system memory. In at least one embodiment, a preROP 2142 (Pre-Raster Operations Unit) is configured to receive data from the graphics multiprocessor 2134 and forward data to ROP units that may be located in the partition units described herein (e.g., partition units 2120A-2120N of ). Fig. 21). In at least one embodiment, the preROP unit 2142 can perform color mixing optimizations, organize pixel color data, and perform address translations.

[0324] Logic 815 is used to perform inferencing and / or training operations in conjunction with one or more embodiments. Details of Logic 815 are given here in conjunction with the Fig. 8A and / or 8B described. In at least one embodiment, the logic 815 in the graphics processing cluster 2114 can be used for inferencing or prediction operations that are at least partially based on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0325] In at least one embodiment, at least one in Fig. 21. The component shown or described is used to implement procedures and / or functions that are associated with the Fig. 1-7 are described. In at least one embodiment, at least one component of Fig. 21 is used to initiate the generation and / or updating of a traffic model, to access one or more traffic scenes of the traffic model, to generate preference data of the one or more traffic scenes, to calculate a reward value, and / or to control an autonomous machine. In at least one embodiment, at least one component of Fig. 21 selects at least one aspect relating to the feedback collector 106, the model(s) 110, the reward modeler 112, the fine-tuning module 114, the processor 140 and / or the communication manager 120 of Fig. 1, the feedback collection 202, the reward modeling 204 and / or the model fine-tuning 206 of Fig. 2, the generated traffic scenarios 300 of Fig. 3, the collection of 400 scenario feedbacks from Fig. 4, the procedure 500 of Fig. 5, the procedure 600 of Fig. 6 and / or the 700 processor from Fig. 7 is described.

[0326] Fig. Figure 21D shows a graphics multiprocessor 2134 according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 2134 is coupled to the pipeline manager 2132 of the processing cluster 2114. In at least one embodiment, the graphics multiprocessor 2134 has an execution pipeline comprising, among other things, an instruction cache 2152, an instruction unit 2154, an address allocation unit 2156, a register file 2158, one or more GPGPU cores 2162, and one or more load / store units 2166, wherein one or more of the load / store units 2166 can perform load / store operations, which corresponds to the execution of the operation. In at least one embodiment, the GPGPU cores 2162 and the load / storage units 2166 are connected to the cache memory 2172 and the common memory 2170 via a memory and cache connection 2168.In at least one embodiment, the GPGPU cores 2162 are part of a SoC, such as part of an integrated circuit 1700 in . Fig. 17.

[0327] In at least one embodiment, the instruction cache 2152 receives a stream of instructions to be executed from the pipeline manager 2132. In at least one embodiment, the instructions are temporarily stored in the instruction cache 2152 and forwarded by the instruction unit 2154 for execution. In at least one embodiment, the instruction unit 2154 can send the instructions as thread groups (e.g., warps, wavefronts, waves), with each thread in the thread group being assigned to a different execution unit within the GPGPU cores 2162. In at least one embodiment, an instruction can access a local, shared, or global address space by specifying an address within a unified address space.In at least one embodiment, the address mapping unit 2156 can be used to translate addresses in a unified address space into a unique memory address that the load / store units 2166 can access.

[0328] In at least one embodiment, the register file 2158 provides a set of registers for functional units of the graphics multiprocessor 2134. In at least one embodiment, the register file 2158 provides temporary memory for operands associated with data paths of functional units (e.g., GPGPU cores 2162, load / store units 2166) of the graphics multiprocessor 2134. In at least one embodiment, the register file 2158 is partitioned among the individual functional units, such that each functional unit is assigned its own section of the register file 2158. In at least one embodiment, the register file 2158 is partitioned into different warps (also referred to as wavefronts and / or waves) executed by the graphics multiprocessor 2134.

[0329] In at least one embodiment, the GPGPU cores 2162 can each include floating-point units (FPUs) and / or integer arithmetic logic units (ALUs) used to execute instructions of the graphics multiprocessor 2134. The GPGPU cores 2162 can be similar or different in their architecture in at least one embodiment. In at least one embodiment, a first section of the GPGPU cores 2162 includes a single-precision FPU and an integer ALU, while a second section of the GPGPU cores includes a double-precision FPU. In at least one embodiment, the FPUs can implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic.In at least one embodiment, the graphics multiprocessor 2134 may additionally include one or more fixed-function or special-function units to perform specific functions such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0330] In at least one embodiment, the GPGPU cores 2162 feature SIMD logic capable of executing a single instruction across multiple data sets. In at least one embodiment, GPGPU cores 2162 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for GPGPU cores can be generated at compile time by a shader compiler or automatically during the execution of programs written and compiled for SPMD or SIMT (Single Program Multiple Data) architectures. In at least one embodiment, multiple threads of a program designed for a SIMT execution model can be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0331] In at least one embodiment, the memory and cache connection 2168 is a network link that connects each functional unit of the graphics multiprocessor 2134 to the register file 2158 and the shared memory 2170. In at least one embodiment, the memory and cache connection 2168 is a coupling field connection that allows the load / store unit 2166 to perform load and store operations between the shared memory 2170 and the register file 2158. In at least one embodiment, the register file 2158 can operate at the same frequency as the GPGPU cores 2162, so that data transmission between the GPGPU cores 2162 and the register file 2158 has very low latency. In at least one embodiment, the shared memory 2170 can be used to enable communication between threads running on functional units within the graphics multiprocessor 2134.In at least one embodiment, the cache memory 2172 can, for example, be used as a data cache to temporarily store texture data transferred between functional units and the texture unit 2136. In at least one embodiment, the shared memory 2170 can also be used as a programmatically controlled cache. In at least one embodiment, threads running on GPGPU cores 2162 can programmatically store data in the shared memory in addition to the automatically cached data stored in the cache memory 2172.

[0332] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to host / processor cores to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively connected to the host processor (processor cores) via a bus or other connection (e.g., a high-speed connection such as PCIe or NVLink). In at least one embodiment, a system-on-a-chip (SoC) includes a parallel processor or GPGPU, as described herein, with the parallel processor or GPGPU running on the SoC. In at least one embodiment, the GPU can be integrated in the same package or chip as the cores and communicate with the cores via an internal processor bus or connection (i.e., within the package or chip).In at least one embodiment, the processor cores can assign work to the GPU in the form of instruction sequences / instructions contained in a work descriptor, regardless of the type of GPU connection. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these instructions.

[0333] Logic 815 is used to perform inferencing and / or training operations in conjunction with one or more embodiments. Details of Logic 815 are given here in conjunction with the Fig. 8A and / or 8B described. In at least one embodiment, the logic 815 in the graphics multiprocessor 2134 can be used for inferencing or prediction operations that are at least partially based on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0334] In at least one embodiment, at least one in Fig. The component shown or described in Figure 21D is used to implement procedures and / or functions related to the Fig. 1-7 are described. In at least one embodiment, at least one component of Fig. 21D is used to initiate the generation and / or updating of a traffic model, to access one or more traffic scenes of the traffic model, to generate preference data of the one or more traffic scenes, to calculate a reward value, and / or to control an autonomous machine. In at least one embodiment, at least one component of Fig. 21D selects at least one aspect relating to the feedback collector 106, the model(s) 110, the reward modeler 112, the fine-tuning module 114, the processor 140 and / or the communication manager 120 of Fig. 1, the feedback collection 202, the reward modeling 204 and / or the model fine-tuning 206 of Fig. 2, the generated traffic scenarios 300 of Fig. 3, the collection of 400 scenario feedbacks from Fig. 4, the procedure 500 of Fig. 5, the procedure 600 of Fig. 6 and / or the 700 processor from Fig. 7 is described.

[0335] Fig. Figure 22 shows a multi-GPU computing system 2200 according to at least one embodiment. In at least one embodiment, the multi-GPU computing system 2200 can have a processor 2202 which is connected via a host interface switch 2204 to several universal graphics processing units (GPGPUs) 2206A-D. In at least one embodiment, the host interface switch 2204 is a PCI Express switch device which connects the processor 2202 to a PCI Express bus via which the processor 2202 can communicate with the GPGPUs 2206A-D. In at least one embodiment, the GPGPUs 2206A-D can be interconnected via a series of high-speed point-to-point GPU-to-GPU links 2216. In at least one embodiment, the GPU-to-GPU connections 2216 are connected to each of the GPGPUs 2206A-D via a separate GPU connection.In at least one embodiment, the P2P GPU connections 2216 enable direct communication between the individual GPGPUs 2206A-D without requiring communication via the host interface bus 2204 to which the processor 2202 is connected. In at least one embodiment where the GPU-to-GPU traffic is routed over P2P GPU connections 2216, the host interface bus 2204 remains available for system memory access or for communication with other instances of the multi-GPU computer system 2200, for example, via one or more network devices. While in at least one embodiment the GPGPUs 2206A-D are connected to the processor 2202 via the host interface switch 2204, in at least one embodiment the processor 2202 has direct support for P2P GPU connections 2216 and can be directly connected to the GPGPUs 2206A-D.In at least one embodiment, the GPGPUs 2206A-D are part of a SoC, such as part of the integrated circuit 1700 in . Fig. 17, where the GPGPUs 2206A-D perform the operations described here.

[0336] Logic 815 is used to perform inferencing and / or training operations in conjunction with one or more embodiments. Details of Logic 815 are given here in conjunction with the Fig. 8A and / or 8B described. In at least one embodiment, the logic 815 can be used in the multi-GPU computing system 2200 for inferencing or prediction operations that are based at least partially on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0337] In at least one embodiment, the multi-GPU computer system 2200 has one or more graphics cores 1900.

[0338] In at least one embodiment, at least one in Fig. 22. The component shown or described is used to implement procedures and / or functions that are associated with the Fig. 1-7 are described. In at least one embodiment, at least one component of Fig. 22 is used to initiate the generation and / or updating of a traffic model, to access one or more traffic scenes of the traffic model, to generate preference data of the one or more traffic scenes, to calculate a reward value, and / or to control an autonomous machine. In at least one embodiment, at least one component of Fig. 22 select at least one aspect relating to the feedback collector 106, the model(s) 110, the reward modeler 112, the fine-tuning module 114, the processor 140 and / or the communication manager 120 of Fig. 1, the feedback collection 202, the reward modeling 204 and / or the model fine-tuning 206 of Fig. 2, the generated traffic scenarios 300 of Fig. 3, the collection of 400 scenario feedbacks from Fig. 4, the procedure 500 of Fig. 5, the procedure 600 of Fig. 6 and / or the 700 processor from Fig. 7 is described.

[0339] Fig. Figure 23 is a block diagram of a graphics processor 2300 according to at least one embodiment. In at least one embodiment, the graphics processor 2300 comprises a ring interconnect 2302, a pipeline front end 2304, a media machine 2337, and graphics cores 2380A-2380N. In at least one embodiment, the ring interconnect 2302 connects the graphics processor 2300 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 2300 is one of many processors integrated into a multi-core processing system. In at least one embodiment, the graphics processor 2300 comprises a graphics core 1900.

[0340] In at least one embodiment, the graphics processor 2300 receives batches of instructions via the ring connection 2302. In at least one embodiment, the incoming instructions are interpreted by an instruction streamer 2303 in the pipeline front end 2304. In at least one embodiment, the graphics processor 2300 has scalable execution logic to perform 3D geometry processing and media processing via the graphics core(s) 2380A-2380N. In at least one embodiment, the instruction streamer 2303 provides instructions for 3D geometry processing to the geometry pipeline 2336. In at least one embodiment, the instruction streamer 2303 provides instructions for at least some media processing to a video front end 2334 coupled to a media machine 2337.In at least one embodiment, the media machine 2337 includes a video quality engine (VQE) 2330 for video and image post-processing and a multi-format encoder / decoder (MFX) 2333 to enable hardware-accelerated encoding and decoding of media data. In at least one embodiment, the geometry pipeline 2336 and the media machine 2337 each generate execution threads for thread execution resources provided by at least one graphics core 2380A.

[0341] In at least one embodiment, the 2300 graphics processor has scalable thread execution resources comprising 2380A-2380N graphics cores (which may be modular and are sometimes referred to as core slices), each of which has multiple 2350A-2350N and 2360A-2360N sub-cores (sometimes referred to as core sub-slices). In at least one embodiment, the 2300 graphics processor can have any number of 2380A to 2380N graphics cores. In at least one embodiment, the 2300 graphics processor has a 2380A graphics core with at least one first 2350A sub-core and one second 2360A sub-core. In at least one embodiment, the 2300 graphics processor is a low-performance processor with a single sub-core (e.g., 2350A). In at least one embodiment, the graphics processor 2300 has multiple graphics cores 2380A-2380N, each of...

Claims

[1] Computer-implemented method comprising: Capturing one or more traffic scenes of a traffic model; Collecting preference data indicating a realism of the one or more traffic scenes; calculating a reward value based at least in part on the preference data; Updating the traffic model using the reward value; and Moving an autonomous vehicle based on the traffic model update. [2] The computer-implemented method of claim 1, wherein the preference data is generated at least in part based on one or more sets of one or more traffic scenarios, wherein the one or more traffic scenarios are ranked by one or more human identifiers. [3] The computer-implemented method of claim 1 or 2, wherein the preference data comprises one or more pairs of traffic scenarios, each pair of traffic scenarios in the one or more pairs of traffic scenarios comprising a first traffic scenario indicated as preferred over a second traffic scenario. [4] A computer-implemented method according to any one of the preceding claims, wherein the reward value is calculated by comparing two or more traffic scenarios associated with the preference data to determine an average loss value over a sequence of the two or more traffic scenarios. [5] Computer-implemented method according to one of the preceding claims, wherein the traffic model comprises one or more neural networks. [6] A computer-implemented method according to any one of the preceding claims, wherein the one or more traffic scenes of the traffic model comprise one or more traffic scenarios indicating a position, a direction and a speed of one or more vehicles over a time interval. [7] The computer-implemented method of any preceding claim, wherein moving the autonomous vehicle comprises using the updated traffic model to determine one or more control inputs to the autonomous vehicle to cause the autonomous vehicle to navigate in an environment. [8] Non-transitory computer-readable storage medium on which executable instructions are stored which, as a result of execution by one or more processors of a computer system, cause the computer system to: to capture one or more traffic scenes of a traffic model; to collect preference data indicating a realism of the one or more traffic scenes; calculate a reward value based at least in part on the preference data; and update the traffic model using the reward value. [9] The non-transitory computer-readable storage medium of claim 8, wherein the preference data is generated at least in part based on one or more sets of one or more traffic scenarios, the one or more traffic scenarios being ranked by one or more human identifiers. [10] The non-transitory computer-readable storage medium of claim 8 or 9, wherein the preference data comprises one or more pairs of traffic scenarios, each pair of traffic scenarios in the one or more pairs of traffic scenarios comprising a first traffic scenario indicated as being preferred over a second traffic scenario. [11] The non-transitory computer-readable storage medium of any of claims 8 to 10, wherein the reward value is calculated by comparing two or more traffic scenarios associated with the preference data to determine an average loss value over a sequence of the two or more traffic scenarios. [12] A non-transitory computer-readable storage medium according to any one of claims 8 to 11, wherein the traffic model comprises one or more neural networks. [13] The non-transitory computer-readable storage medium of any of claims 8 to 12, wherein the one or more traffic scenes of the traffic model comprise one or more traffic scenarios indicating a position, a direction, and a speed of one or more vehicles over a time interval. [14] The non-transitory computer-readable storage medium of any of claims 8 to 13, wherein the computer system is further configured to cause an autonomous vehicle to navigate in an environment based at least in part on updating the traffic model. [15] System comprising: one or more processors: to capture one or more traffic scenes of a traffic model; to collect preference data indicating a realism of the one or more traffic scenes; to calculate a reward value using one or more neural networks based at least in part on the preference data; and to update the traffic model using the reward value. [16] The system of claim 15, wherein the preference data is generated at least in part based on one or more sets of one or more traffic scenarios, wherein the one or more traffic scenarios are ranked by one or more human identifiers. [17] The system of claim 15 or 16, wherein the preference data comprises one or more pairs of traffic scenarios, each pair of traffic scenarios in the one or more pairs of traffic scenarios comprising a first traffic scenario indicated as preferred over a second traffic scenario. [18] A system according to any one of claims 15 to 17, wherein the reward value is calculated by comparing two or more traffic scenarios associated with the preference data to determine an average loss value over a sequence of the two or more traffic scenarios. [19] The system of any of claims 15 to 18, wherein the one or more processors are further configured to cause an autonomous machine to navigate in an environment based at least in part on using the updated traffic model to determine one or more control inputs for the autonomous machine. [20] A system according to any one of claims 15 to 19, wherein the system comprises at least one of: a control system for an autonomous or semi-autonomous machine; a perception system for an autonomous or semi-autonomous machine; a first system for performing simulation operations; a second system for performing deep learning operations; a third system implemented using an edge device; a fourth system implemented using a robot; a fifth system containing one or more virtual machines, VMs; a sixth system that is at least partially implemented in a data center; a seventh system for performing operations on a digital twin; an eighth system for performing light transport simulations; a ninth system for conducting collaborative content creation for 3D assets; a tenth system for performing artificial intelligence operations in dialogue; an eleventh system for generating synthetic data; a twelfth system for implementing a web-hosted service for detecting inefficiencies in program utilization; an application as an application programming interface, API; a thirteenth system implemented at least in part using cloud computing resources; a fourteenth system for displaying virtual reality content, Augmented reality content and / or mixed reality content; or a fifteenth system that uses one or more large language models, LLMs, implemented.

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