VERTICALLY EMBEDDED PREFORMED DEEP TRENCH CAPACITOR VIODULES

Abstract

Devices, capacitor modules, assemblies, and techniques related to embedded package substrate capacitors are described. A capacitor module is formed by fabricating capacitor structures along a surface of one or more substrates, cutting the capacitor structures from the one or more substrates, and stacking the resulting capacitor structures and substrates into a capacitor module. The capacitor module is then vertically embedded in a package substrate or core.

Description

BACKGROUNDHigher performance, lower cost, increased miniaturization, and greater integrated circuit package density within integrated circuit devices are ongoing goals of the electronics industry. With these goals being achieved, integrating capacitors into package assemblies remains a region of interest. For example, capacitors may be embedded in package substrates. However, current capacitors have limitations on overall device thickness and others. Such limited device thicknesses cause assembly difficulties when installed in an opening having a thickness greater than the device thickness, including x, y, z misalignment, rotational displacement, tilt, encapsulation thickness variations, and others.Next generation products require capacitor devices to be integrated into the system efficiently and with a wide range of available device parameters and characteristics. However, current capacitor implementations do not meet these requirements. With these and other considerations in mind, there has been a need for the present improvements. Such improvements may become critical as the desire to employ advanced package assemblies in a variety of products is emerging.BRIEF DESCRIPTION OF THE DRAWINGSThe material described herein is illustrated by way of example and not limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements. In the figures, the following applies: FIG. 1 is a flow diagram illustrating methods of forming a capacitor module including a number of stacked substrates each including a number of capacitor structures; FIGS. 2, 3A, 4, 5, 6, 7, 8, 9, 10, 11, and 12 provide top and cross-sectional views of capacitor structures and capacitor modules developing with performing the methods of FIG. 1 ; FIG. 3B provides a top view illustrating multiple capacitor modules formed on a single substrate; FIGS. 3C, 3D, 3E, and 3F provide plan views illustrating example trench and capacitor shapes; FIG. 13 is a flow diagram illustrating methods for mounting a package including a vertical capacitor module including a number of stacked substrates, each including a number of capacitor structures embedded in a package substrate; FIGS. 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, and 26 illustrate cross-sectional side views of housing structures developing with the methods of FIG. 13 being performed; FIG. 27 illustrates an example microelectronic device assembly that includes a vertically embedded preformed 2D capacitor module; FIG. 28 illustrates example systems employing a vertically embedded preformed 2D capacitor module; and FIG. 29 is a functional block diagram of an electronic computing device, all arranged in accordance with at least some implementations of the present disclosure.DETAILED DESCRIPTIONOne or more embodiments or implementations will now be described with reference to the accompanying figures. While specific configurations and arrangements are discussed, this is for illustrative purposes only. Those skilled in the relevant art will appreciate that other configurations and arrangements may be employed without departing from the spirit and scope of the description. It will be apparent to those skilled in the art that techniques and / or arrangements described herein may also be employed in a variety of systems and applications other than those described herein.In the following detailed description, reference is made to the accompanying drawings that form a part hereof, wherein like numerals may refer to like parts throughout to indicate corresponding or analogous elements. It should be appreciated that for simplicity and / or clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, it is to be understood that other embodiments may be utilized and structural and / or logical changes may be made without departing from the scope of the claimed subject matter. It should also be noted that directions and references, for example, up, down, up, down, over, under, etc., may be used to facilitate the discussion of the drawings and embodiments, and are not intended to limit the application of the claimed subject matter. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of the claimed subject matter is defined by the appended claims and their equivalents.In the following description, numerous details are set forth. However, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In some instances, rather than in all detail, well-known methods and apparatus are shown in block diagram form in order to avoid obscuring the present invention. Throughout this specification, reference to "one embodiment" or "any implementations" means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase "in one embodiment" in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Moreover, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment wherever the specific features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.As used in the description of the invention and in the appended claims, the singular forms "a", "an" and "the / s" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.The terms "coupled" and "connected" along with their derivatives may be used herein to describe structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in certain embodiments, "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with each other. "coupled" may be used to indicate that two or more elements are in either direct or indirect (with other intervening elements) physical or electrical contact with each other, and / or that the two or more elements are working with or interacting with each other (e.g., as in a case of a cause-effect relationship, an electrical relationship, a functional relationship, etc.).As used herein, the terms "over," "under," "between," "on," etc., refer to a relative position of a layer of material or component with respect to other layers or components. For example, a layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. In addition, a layer disposed "between" two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer is "on" a second layer in direct contact with this second layer. Likewise, unless otherwise indicated, a feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening features. The term "immediately adjacent" indicates that such features are in direct contact. The terms "substantially", "nearly", "about", "near", and "about" also generally refer to between + / - 10% of a target value. The term layer, as used herein, may include a single material or multiple materials. As used throughout this specification and in the claims, a list of objects joined by the term "at least one(s / s) of" or "one(s) or more of" may mean any combination of the listed terms. For example, the phrase "at least one of A, B, or C" may mean A; B; C; A and B; A and C; B and C, or A, B, and C. The terms "lateral", "laterally adjacent", and similar terms indicate that two or more components are oriented along a plane orthogonal to a vertical direction of an overall structure. Here, the term "predominantly" indicates not less than 50% of a particular material or component, while the term "substantially pure" indicates not less than 99% of the particular material or component. Unless otherwise stated, such percentages of material are based on atomic percentages. As used herein, the terms "monolithic", "monolithically integrated", and similar terms indicate that the components of the overall monolithic structure form an indivisible entity that cannot be separated at low cost.The term "package" generally refers to a self-contained carrier of one or more dies, which dies are attached to the package substrate and may be encapsulated for protection, with integrated or wired connections between the dies and leads, pins, or bumps located on the exterior portions of the package substrate. The package may include a single die or dies that provides a specific function. The package is typically mounted on a printed circuit board for connection to other packaged integrated circuits and discrete components, thereby forming a larger circuit. Here, the term "dielectric" and the term "insulating" and any similar terms generally refer to any number of non-electrically conductive materials forming the structure of a package substrate. For purposes of this disclosure, the dielectric material may be incorporated into an integrated circuit package as layers of laminate film or as a resin molded over integrated circuit dies mounted on the substrate. Here, the term "metallization" generally refers to metal layers formed over and through the dielectric material of the package substrate. The metal layers are generally patterned to form metal structures such as conductive traces and bond pads. Metallization of a package substrate may be bounded to a single layer or may be in multiple layers separated by layers of dielectric. Here, the term "assembly" generally refers to the summary of parts into a single functional unit. The parts may be separate and are mechanically assembled into a functional unit, wherein the parts may be removable. In another case, the parts may be permanently bonded together. In some cases, the parts are integrated with each other. Throughout the specification and claims, the term "connected" means a direct connection, such as an electrical, mechanical or magnetic connection, between the things that are connected without any intervening devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, magnetic, or fluid connection between the things that are connected, or an indirect connection via one or more passive or active intermediary devices.Devices, systems, capacitor modules, and techniques are described herein with respect to vertically oriented preformed capacitor modules that may be embedded in a package substrate.As discussed, it is desirable to efficiently provide capacitors having a wide range of capabilities in a package assembly. Currently, embedded capacitors, such as deep trench capacitors (DTCs), may be fabricated in a silicon wafer such that the length of the capacitor extends orthogonally to the working surface of the silicon wafer substrate. Such DTCs then have a practical thickness limit of about 650 μm, which is the maximum thickness of a silicon wafer. When the DTCs are then embedded in a cavity extending into or through a relatively thick package substrate or substrate core having a thickness of about 1.4 mm, there are processing difficulties with respect to x, y, z misalignment, rotational displacement, tilt, encapsulation thickness variations after attachment of the DTC, encapsulation processing within the cavity, and others. For example, the DTC device embedded in the substrate core is much thinner than the core cavity depth, causing the discussed challenges. Moreover, there are challenges related to surface area limiting for capacitance when the capacitors are fabricated in a silicon wafer such that the length of the capacitor extends orthogonally to the working surface of the silicon wafer substrate.In some embodiments, such difficulties are solved or alleviated by forming a capacitor module such that the capacitors are formed along the surface of a substrate (i.e., not with a length of the capacitor extending along a substrate surface rather than orthogonal to the working surface of the substrate). By forming the capacitors with the capacitor's length extending planar to the working surface of the substrate, the capacitor's length is limited not by the depth of the substrate but instead by its lateral dimensions, which are much larger. For example, after forming the capacitors within openings running along the surface(s) of the substrate(s), the substrate and capacitor structures are cut substantially orthogonal to the length of the capacitors, providing, for example, contact access to the capacitor structures at an edge of the substrate created by the cut. The formed capacitor structures include any number of capacitors having a length along a surface of the substrate and access to the capacitors for later contact at an edge. These capacitor structures may then be stacked and adhered, for example, at their surfaces such that the edges are substantially coplanar and allow electrical access to the capacitor structures. This provides a capacitor module having insulated capacitors with a length not limited by the depth of the substrate used to form it and electrical access to a surface formed by the combined edges.This capacitor module, including any number of capacitors and substrates, may then be embedded within an opening or cavity within a package substrate, such as an organic package substrate or an organic cure. Due to the manufacturing characteristics, the capacitor module may have any suitable thickness (as defined by the cut or cuts used to form it), such as a thickness corresponding to the depth of the opening or cavity, or a thickness conducive to insertion of the capacitor module within the opening or cavity. This attenuates or cancels the discussed x, y, z misalignment, rotational displacement, tilt, encapsulation thickness variations after mounting, encapsulation processing within the cavity, and others. Furthermore, by cancelling the restrictions of forming the capacitors in a deep trench manner orthogonal to the substrate surface, much longer capacitors may be formed, other materials may be used, and so on. In particular, using vertically embedded preformed 2D DTC patches or modules as discussed herein may balance the total capacitor thickness that may be matched to the core opening thickness discussed. In this way, more accurate capacitor placement can be performed. Moreover, since capacitors can be prefabricated on a substrate such as a glass plate, there is substantially no limitation on the surface area that can be used to increase the capacitance of the capacitors. This provides a wide range of capacitor characteristics and flexibility. Other advantages will be apparent based on the present disclosure.FIG. 1 is a flow diagram illustrating methods 100 of forming a capacitor module including a number of stacked substrates each including a number of capacitor structures arranged according to some embodiments of the disclosure. For example, the methods 100 may be performed to fabricate any capacitor structures, capacitor modules, devices, or systems discussed herein. FIGS. 2, 3A, 4, 5, 6, 7, 8, 9, 10, 11, and 12 provide top and cross-sectional views of capacitor structures and capacitor modules developing with execution of the methods 100 and arranged in accordance with some embodiments of the disclosure. FIG. 3B provides a top view illustrating multiple capacitor modules 310 formed on a single substrate and arranged in accordance with some embodiments of the disclosure. FIGS. 3C, 3D, 3E, and 3F provide plan views illustrating example trench and capacitor shapes arranged in accordance with some embodiments of the disclosure. For example, the methods 100 illustrate a process flow for fabricating preformed 2D capacitor patches or modules for later use in package assemblies.The methods 100 begin at input operation 101 where a workpiece including a substrate on which capacitors may be formed is received. The workpiece includes any suitable substrate material or material layers on which capacitor structures may be formed. The substrate may include any materials discussed herein and may have any suitable format or architecture. In some embodiments, the substrate is a glass plate, such as a glass support plate 500 mm x 510 mm in size. In some embodiments, the substrate is a silicon wafer, such as a 300 mm silicon wafer.FIG. 2 provides a top view 210 and a cross-sectional side view 220 of a capacitor structure 200 illustrating a received substrate 201. For example, cross-sectional side view 220 is taken in the A-A' plane as shown in plan view 210. In the following, the top view 210 and the cross-sectional side view 220 are maintained while the methods 100 are being performed. In the illustrated example, a portion of the substrate 201 is illustrated as having a rectangular shape factor. The substrate 201 may have a length L (see FIG. 3B ), a width W (see FIG. 3B ), and a thickness t (shown in FIG. 2 ). However, the substrate 201 may have any suitable shape factor. FIG. 3B below illustrates an example of a capacitor structure 200 formed on a substrate 201 in an enlarged view.In some embodiments, the substrate 201 is a glass substrate, such as a glass layer (e.g., a glass core). In some embodiments, the substrate 201 is an amorphous solid glass layer. In some embodiments, the substrate 201 is a glass layer, which is, for example, aluminosilicate, borosilicate, aluminosilicate, silica, and fused silica. The glass layer may include one or more additives including Al 2 O 3, B 2 O 3, MgO, CaO, SrO, BaO, SnO 2, NazO, K 2 O, P 2 O 3, ZrO 2, Li 2 O, Ti, or Zn. For example, the glass layer may include an additive including one or more of aluminum, boron, magnesium, calcium, strontium, barium, tin, sodium, potassium, phosphorus, zirconium, lithium, titanium, or zinc. In some embodiments, the glass layer may include silicon and oxygen and one or more of aluminum, boron, magnesium, calcium, strontium, barium, tin, sodium, potassium, phosphorus, zirconium, lithium, titanium, and zinc. In some embodiments, the glass layer includes at least 23 weight percent silicon and at least 26 weight percent oxygen, and further includes at least 5 weight percent aluminum. In some embodiments, the glass layer has a rectangular shape in plan view. However, other shapes may be used. In some embodiments, the substrate 201 does not include an organic adhesive or other organic material. In some embodiments, the substrate 201 has a thickness t in the range of 50 micrometers to 1.4 mm (i.e., in the z-dimension). In some embodiments, the substrate 201 has a length L (see FIG. 3B ) in the range of about 500 mm to 600 mm and a width W (see FIG. 3B ) in the range of about 500 mm to 600 mm. In some embodiments, the substrate 201 is a glass plate having a size of 500 mm x 510 mm. In some embodiments, the substrate is a multilayer glass substrate. In some embodiments, the substrate 201 is a single crystal silicon wafer. However, other substrate materials such as polycrystalline silicon and silicon on insulator (SOI) may be used. In some embodiments, the substrate 201 is an inorganic substrate or material. As used herein, the term inorganic material refers to materials that do not have carbon as a base component or materials that do not have carbon-hydrogen bonds.Returning to FIG. 1, processing continues at operation 102 where a trench opening is formed along a surface of the workpiece or substrate received at operation 102. The trench opening may be formed in the surface of the workpiece or substrate using any suitable technique or techniques. In some embodiments, the trench openings are formed using patterning and etching techniques. However, other techniques such as laser scribing, mechanical scribing, or the like may be used.FIG. 3A illustrates a capacitor structure 300 similar to the capacitor structure 200 after forming openings 301 in a surface 302 of the substrate 201. As shown, surface 302 is an upper, front, or working surface of substrate 201 and is opposite surface 303 of substrate 201. The surface 303 may be characterized as a back surface. As discussed, in some embodiments, openings 301 are formed using patterning and etching techniques. The openings 301 extend along a length L of the surface 302 of the substrate 201 such that the length L is in the x-y plane and is orthogonal to the depth of the substrate 201. The openings 301 may also be characterized as trench openings, trenches, or the like. In some embodiments, the openings 301 have a U-shaped cross-sectional profile, as illustrated in FIG. 3A. In other embodiments, the openings 301 have a V-shaped cross-sectional profile. In some embodiments, the openings 301 extend from the surface 302 to the surface 303, as illustrated in FIG. 10 below.The openings 301 may have any suitable length Lt, width Wt, and depth d. In some embodiments, the length Lt is longer than a desired capacitor structure length such that capacitor structures formed in the openings 301 are later cut to the desired capacitor structure length. The desired capacitor structure length (less than Lt), width Wt, and depth d may be determined based on the characteristics of the fabricated capacitor, the materials used, and so forth. An advantage of the present techniques is that very long capacitor structure lengths can be fabricated for use in a vertical orientation, as discussed further below. In some embodiments, the width Wt and the depth d of the openings 301 are in the range of about 5 to 100 μm. Other dimensions may be used. Although illustrated as having multiple parallel openings 301 of the same size, any desired shapes and patterns may be employed in the capacitor structure 300 as illustrated further below.FIG. 3B provides a plan view illustrating a plurality of capacitor modules 311 formed on the substrate 201 in an enlarged view. FIG. 3B illustrates the length L and width W of the substrate 201. In some embodiments, the substrate 201 has a length L in the range of about 500 mm to 600 mm and a width W in the range of about 500 mm to 600 mm. In some embodiments, the substrate 201 is a glass plate having a size of 500 mm x 510 mm. FIG. 3B illustrates that a number of capacitor structures 300 (and a corresponding capacitor structure as they develop) may be fabricated on a single substrate 201, where the capacitor structures are then segmented from the substrate 201 for deployment. Furthermore, FIG. 3B illustrates that the capacitor structure size is limited only by the lateral dimensions of the substrate 201 rather than by the depth of the substrate 201. Thereby, the size of the capacitor structures can be changed to satisfy almost any desired design without practical limitation. For example, capacitor structures having a length Lc (see FIG. 9 ) in the range of 2 mm to 4 mm may be fabricated on the substrate 201, as well as capacitor structures having a length Lc of more than 4 mm nearly up to the length L and width W of the substrate 201. This capacitor size and flexibility capability is an important advantage of the techniques discussed.FIG. 3C provides plan views illustrating an example capacitor structure 320 having a cross-trench shape 321 for the capacitor structures discussed herein. For example, in the x-y plane (e.g., orthogonal to a vertical inset discussed herein below), capacitor structures 300 (and corresponding capacitor structure as they develop) may have any suitable shape. Again, the forming of the capacitor structures is done without limitation to the processing typically employed along the depth of the substrate 201. Instead, the discussed patterning may form cross-trench shapes 321 or other suitable shapes for improving performance of the capacitor structures. FIG. 3D provides plan views illustrating an example capacitor structure 330 having a diagonal line trench shape 331 for the capacitor structures discussed herein. For example, diagonal line trench shape 331 may insert diagonal lines or diagonal trenches at an angle with respect to a later cut to expose capacitor structures for inclusion in a package. FIG. 3E provides plan views illustrating an example capacitor structure 340 having a T-shaped trench shape 341 for the capacitor structures discussed herein. FIG. 3F provides plan views illustrating an example capacitor structure 350 having an oval trench shape 351 for the capacitor structures discussed herein.Referring now to FIGS. 8 and 9, capacitor structures are segmented or cut for inclusion in a capacitor module. Note that the segmentation or the cut may be performed at any position of the transverse trench shape 321, the diagonal line trench shape 331, the T-shaped trench shape 341, and the oval trench shape 351, such as segmentation operation 801 (see FIG. 8 ) or cut in the x-z plane. In the context of the cross-trench shape 321 (see FIG. 3C ), the segmentation may be performed at the top of the cross-shape (i.e., at or near an uppermost position 322 in the y-dimension) such that the stacked capacitor structure has a cross-shape in the x-y plane). In the context of diagonal line trench shape 331 (see FIG. 3D ), the segmentation may be performed at positions 332 to generate a stacked capacitor structure with diagonal lines in the x-y plane). In the context of the T-shaped trench shape 341 (see FIG. 3E ), the segmentation may be performed at the top of the T-shape (i.e., at or near an uppermost position 342 in the y-dimension) or at a bottom of the T-shape (not shown) such that the stacked capacitor structure has a cross-shape in the x-y plane). In the context of the oval trench shape 351 (see FIG. 3F ), the segmentation may be performed at any position 352 of the oval shape (e.g., at or near an uppermost position 352 in the y-dimension or near a midpoint 353) such that the stacked capacitor structure has a cross-shape in the x-y plane). Other shapes and cuts may be used.Returning to FIG. 1, processing continues at operation 103, where capacitor structures are formed in the trench openings formed at operation 102. In some embodiments, a first electrode metal layer is formed within the trench openings, a capacitor dielectric layer is formed on the first electrode metal layer, and a second electrode metal layer is formed on the capacitor dielectric layer. After such material deposition, planarization may be performed to form the capacitor structures such that each of the capacitor structures has a first surface conformal to the trench openings and a second surface substantially coplanar with the sub-state surface. The materials may be deposited using any suitable technique or techniques, such as plating techniques, chemical vapor deposition techniques, atomic layer deposition techniques, and the like.FIG. 4 illustrates a capacitor structure 400 similar to the capacitor structure 300 after forming a conformal metal electrode layer 401 on the surface 303 and within openings 301 of the substrate 201. Although illustrated with respect to substantially linear shapes, capacitor structures of any shapes discussed herein may be formed. The conformal metal electrode layer 401 may be formed using any suitable technique or techniques discussed above, and the conformal metal electrode layer 401 may have any suitable thickness, such as a thickness in the range of 500 nm to 1 μm. Other thicknesses may be used. The conformal metal electrode layer 401 may include any suitable conductive material or materials, such as a metal or metals. The conformal metal electrode layer 401 may be a single-layer or multilayer conductive film. In some embodiments, the conformal metal electrode layer 401 is or includes titanium nitride (TiN, e.g., titanium and nitrogen), tungsten (W), tantalum nitride (TaN, e.g., tantalum and nitrogen), ruthenium (Ru), iridium (Ir), aluminum (Al), copper (Cu), titanium (Ti), cobalt (Co), chromium (Cr), molybdenum (Mo), nickel (Ni), gold (Au), or platinum (Pt).FIG. 5 illustrates a capacitor structure 500 similar to the capacitor structure 400 after forming a conformal capacitor dielectric layer 501 on the conformal metal electrode layer 401 and over the surface 302 and within openings 301 of the substrate 201. The conformal capacitor dielectric layer 501 may be formed using any suitable technique or techniques discussed above, and the conformal capacitor dielectric layer 501 may have any suitable thickness, such as a thickness in the range of 500 nm to 1 μm. The conformal capacitor dielectric layer 501 may include any suitable insulation material. The conformal capacitor dielectric layer 501 may be a single layer or multilayer dielectric that includes one or more suitable dielectric materials, such as titanium oxide, zirconium oxide, aluminum oxide, hafnium oxide, silicon carbide, gallium nitride, silicon oxide, strontium titanate, barium titanate, strontium barium titanate, tantalum oxide, or combinations thereof, optionally doped with oxygen or nitrogen. Other material systems including ferroelectric capacitor materials may be used.FIG. 6 illustrates a capacitor structure 600 similar to the capacitor structure 500 after forming a metal electrode layer 601 on the conformal capacitor dielectric layer 501 and over the surface 302 and within openings 301 of the substrate 201. The metal electrode layer 601 may be formed using any suitable technique or techniques discussed above, and the metal electrode layer 601 may have any suitable thickness, such as a thickness in the range of 500 nm to 1 μm. In some embodiments, the metal electrode layer 601 is formed from multiple layers or materials, such as a conformal metal layer followed by a metal fill. For example, the metal electrode layer 601 may be formed by metal deposition followed by a metal plating operation. The metal electrode layer 601 may include any suitable conductive material or materials, such as a metal or metals, including, but not limited to, those discussed with respect to the conformal capacitor dielectric layer 501. For example, the metal electrode layer 601 may include one or more of titanium nitride (TiN, e.g., titanium and nitrogen), tungsten (W), tantalum nitride (TaN, e.g., tantalum and nitrogen), ruthenium (Ru), iridium (Ir), aluminum (Al), copper (Cu), titanium (Ti), cobalt (Co), chromium (Cr), molybdenum (Mo), nickel (Ni), gold (Au), or platinum (Pt).FIG. 7 illustrates a capacitor structure 700 similar to the capacitor structure 600 after the planarization processing removes excess materials of the conformal metal electrode layer 401, the conformal capacitor dielectric layer 501 from the surface 302 of the substrate 201 and from over the openings 301 to form capacitor components 705 that each include a first electrode layer 701, a dielectric layer 702, and a second electrode layer 703. The planarization processing may be performed using any suitable technique or techniques and provides planar capacitor surfaces 706 of the capacitor components 705 that are substantially coplanar with the surface 302 of the substrate 201 (i.e., in the x-y plane). After planarization, each of the capacitor components 705 includes a planar capacitor surface 706 (i.e., substantially planar in the x-y plane) and a conformal capacitor surface 707 that is substantially conformal to the trench 301. Thereby, each of the capacitor components 705 may have a shape in the x-z plane cross section that has a planar edge or surface and a non-planar edge or surface defined by the trench 301, and that may be an angular U shape, a round U shape, a V shape, or the like. As shown, the conformal capacitor surface 707 includes only the first electrode layer 701, while the planar capacitor surface 706 includes a region of each of the first electrode layer 701, the dielectric layer 702, and the second electrode layer 703, wherein the dielectric layer 702 is a dielectric material between the metal materials of the first electrode layer 701 and the second electrode layer 703.Returning to FIG. 1, processing continues at operation 104 where the substrate workpiece and the capacitor components formed therein are cut or otherwise segmented to form sub-modules, patches, or sub-patches that both have a desired length for use in a package substrate cavity or opening (as discussed herein below) and include capacitor components having a desired capacitor length based on the desired capacitance, materials used, width and depth dimensions, etc., of the current capacitor applications. In particular, the cut or segmentation also exposes final electrode contact regions at edges of the substrate and capacitor components used to contact the vertically embedded capacitor components.FIG. 8 illustrates a capacitor structure 800 similar to the capacitor structure 700 during a segmentation operation 801 to divide the substrate 201 and the capacitor components 705 such that a segmented portion of the substrate 201 and the capacitor components 705 may optionally be vertically stacked and inserted within a package substrate. The segmentation operation 801 may be performed using any suitable technique or techniques, such as slice techniques. In some embodiments, segmentation operation 801 forms an intersection orthogonal to capacitor components 705. Although linear capacitor components 705 are illustrated, other shapes may be used, as discussed with reference to FIGS. 3C, 3D, 3E, 3F, and elsewhere herein.FIG. 9 illustrates a capacitor structure 800 similar to the capacitor structure 800 after the segmentation operation 801 divides the substrate 201 and the capacitor components 705 to form substrates 901 and trench capacitor structures 903. In the illustrated example, the substrate 201 and the capacitor components 705 are divided into identical substrates 901 and trench capacitor structures 903. However, the formed substrates and trench capacitor structures 903 may be different. Furthermore, multiple segmentation operations 801 may be performed along the capacitor components 705 to divide the capacitor components 705 into any number of capacitor structures, including capacitor structures with contact access from two sides of the capacitor structures. In the example of FIG. 9, the capacitor structures 903 are linear capacitor structures. However, any suitable shapes may be formed, including a cross shape, a T shape, a partially oval shape, a diagonal line, or the like.As shown, the substrate 201 is divided into a substrate 901 having a length Ls. Ls may be any suitable structure length, and the length may ultimately be defined as a depth, as the substrate 901 is vertically integrated into a package assembly. In particular, an advantage of the techniques discussed herein is the ability to employ capacitor structures 903 having any suitable shape (e.g., in the x-y plane) and nearly any length in the y-dimension. For example, the length and size of the capacitor structures 903 in the x-y plane are limited only by the size of the substrate 201. In some embodiments, the length Ls is in the range of 0.2 mm to about 500 mm. In some embodiments, the length Ls is not less than 1 mm. In some embodiments, the length Ls matches or is within 10% of a substrate core thickness into which the substrate 901 is inserted. In some embodiments, the length Ls is in the range of 1 to 7 mm, but longer lengths may be used, as discussed above. In some embodiments, the length Ls is not less than 2 mm, not less than 4 mm, or not less than 5 mm, not less than 10 mm, or more. Likewise, the segmentation operation 801 and the patterning of the openings 301 define a length Lc of the trench capacitor structures 903. The length Lc of the trench capacitor structures 903 may be any suitable length to provide the electrical characteristic desired by the trench capacitor structures 903. Again, the length Lc of the capacitor structures 903 is limited only by the size of the substrate 201. In some embodiments, the length Lc is not less than 0.75 mm. In some embodiments, the length Lc is in the range of 1 to 7 mm, but longer lengths may be used. In some embodiments, the length Lc is in the range of 2 mm to 4 mm. In some embodiments, the length Lc is not less than 1 mm, not less than 2 mm, not less than 4 mm, not less than 5 mm, not less than 10 mm, or more. Other lengths may be used.As also shown, segmentation operation 801 exposes an edge 911 of substrates 901 that includes locations or regions (as shown in cross-sectional side view 220) for contacting trench capacitor structures 903 by metallization, metal contacts, or the like. For example, the region 912 may be contacted by a metallization structure to provide electrical routing to the first electrode layer 701 and the region 913 may be contacted by a metallization structure to provide electrical routing to the second electrode layer 703. Such regions 912, 913 may be formed on each of the trench capacitor structures 903 and the regions 912, 913 may define metallization patterns, contact patterns or the like for coupling with the trench capacitor structures 903. The regions 912, 913 may have any suitable structure, shape, contact area, etc.As discussed, the trench capacitor structures 903 are embedded in openings 301 (see FIG. 3 ), and both the trench capacitor structures 903 and the openings 301 extend along a length of the surface 302 of the substrate 201. As used herein, the terminology indicates along a length of a surface of a substrate that the component is aligned with the planar working surface of the substrate (e.g., the longest or principal component) and is substantially orthogonal to the planar working surface. For example, the length (e.g., the longest or principal component) extends along the surface 302 of the substrate 201, the surface 302 being in the x-y plane and orthogonal to the depth or thickness of the substrate 201 located in the z-dimension. Referring to FIG. 3, the trench capacitor structures 903 and openings 301 extend along the length Lt, which is in the x-y plane and orthogonal to the z-dimension.FIG. 9 further provides a cross-sectional side view 930 of the capacitor structure 900 to illustrate the embedded type of trench capacitor structures 903. For example, cross-sectional side view 930 is taken in the B-B' plane as shown in plan view 210. In the cross-sectional side view 930, an outline of the trench capacitor structures 903 illustrates that the trench capacitor structures 903 extend partially over the length Ls of the substrate 901 in the y-dimension such that a portion 904 of the bulk material of the substrate 201, 901 is located between each of the trench capacitor structures 903 and an edge 914 of the substrate 901 such that the edge 914 is opposite the edge 911 (i.e., the edge including the contact regions 912, 913 and corresponding exposed portions of the first electrode layer 701 and the second electrode layer 703).FIG. 10 illustrates a capacitor structure 1000 similar to the capacitor structure 900, illustrating an alternative embodiment in which the first electrode layer 701, the dielectric layer 702, and the second electrode layer 703 extend completely through the substrate 201. As shown, in some embodiments, the trenches 301 may extend completely through the substrate 201 such that the first electrode layer 701, the dielectric layer 702, and the second electrode layer 703 also extend through the surface 303. Such embodiments may provide an increased capacitor area for trench capacitor structures 903. The planarization processing discussed with reference to FIG. 7 may be performed on both surfaces 302, 303 to provide planar capacitor surfaces 706, 1007 of capacitor components 705 that are substantially coplanar with surface 302, 303 of substrate 201 (i.e., in the x-y plane).Returning to FIG. 1, processing continues at operation 105, where the capacitor sub-modules formed at operation 104 may be stacked or assembled one above the other and bonded together by adhesive layers between the sub-modules. Any number of sub-modules may be stacked together to form a capacitor module with multiple capacitor sub-modules, such as 2, 3, 4, 5, or more sub-modules. In some embodiments, such submodule stacking is bypassed and a single submodule may be deployed. The submodules may be stacked using any suitable technique or techniques such as placement operations, and the submodules may be bonded together by any suitable adhesive, tape, or the like. In some embodiments, the adhesive is a polymeric material, such as epoxy. As used herein, the term polymeric material indicates a large molecule material having substantially repeating subunits, and epoxides are thermoset polymeric materials. Processing continues at operation 106 where the assembled capacitor modules are dispensed and prepared for further assembly by rotating the assembled capacitor modules and applying an optional adhesive layer or film to a non-functional surface of the capacitor module.FIG. 11 illustrates a capacitor module 1100 assembled by stacking multiple capacitor structures, such as capacitor structures 900. FIG. 11 provides a rotated side view 1110 and a side view 1120, the side view 1120 being taken in the C-C' shown in the rotated side view 1110. Although illustrated with respect to capacitor structures 900 of the same size, capacitor structure 1000 may be employed in capacitor module 1100, and capacitor module 1100 may include capacitor structures having any different characteristics. As shown in FIG. 11, the capacitor module 1100 includes a number of capacitor structures 900 each having trench capacitor structures 903 embedded in substrates 901.Each of the substrates 901 is bonded to an adjacent one of the substrates 901 through an adhesive layer 1101 coupling adjacent substrates 901. The adhesion layer 1101 also provides isolation for the trench capacitor structures 903, and the adhesion layer 1101 may be characterized as an insulator layer, a bond layer, an adhesive, or the like. The adhesive layer 1101 may be any suitable material, such as a polymeric material. In some embodiments, the adhesion layer 1101 is an epoxy.As shown, in some embodiments, capacitor module 1100 includes capacitor structures 900 each including trench capacitor structures 903 embedded within corresponding openings 301 extending along a length of surface 302 of substrate 901 (see FIG. 3 ). The capacitor module 1100 further includes an insulator layer or adhesion layer 1101 on the surface 302 of one of the substrates 901 and on an opposing surface 303 of an adjacent one of the substrates 901. The trench capacitor structures 903 are exposed at a combined edge 911, which is a coplanar combination of each edge 911 of the trench capacitor structures 903. For example, each edge 911 extends between the surfaces 302, 303, as discussed herein.In some embodiments, each surface 302 of the substrate 901 (e.g., surfaces with trench capacitor structures 903) is in the same direction (e.g., the z-dimension) such that the surface 302 is on one side of the adhesion layer 1101 and the surface 303 of an adjacent substrate 901 is on the other side of the adhesion layer, as shown. In other embodiments, the directions of substrates may be varied such that both surfaces 302 (e.g., surfaces with trench capacitor structures 903) are on opposite sides of the same adhesion layer 1101, or surfaces 303 (e.g., surfaces opposite trench capacitor structures 903) are on opposite sides of the same adhesion layer 1101.FIG. 12 illustrates a capacitor module 1200 similar to the capacitor module 1100 after rotation and preparation for embedding in an organic package assembly substrate and after the application of an optional adhesive film 1201. As shown, the capacitor module 1200 may be rotated 90 degrees into vertical integration in preparation for further assembly by mounting the vertically oriented capacitor module 1200 in a substrate core cavity. Such rotation and alignment may be performed using any suitable technique or techniques, such as placement operations. Additionally, the adhesive film 1201 may be applied using any suitable technique or techniques. The adhesive film 1201 may be any adhesive layer such as adhesive tape or liquid adhesive. The adhesive film 1201 may aid in assembly during placement of the capacitor module 1200 into a cavity in a package substrate.FIG. 13 is a flow diagram illustrating method 1300 of mounting a package including a vertical capacitor module including a number of stacked substrates, each including a number of capacitor structures embedded in a package substrate disposed in accordance with some embodiments of the disclosure. The methods 1300 may be performed, for example, to fabricate any housing, package, device, or packaging system discussed herein. FIGS. 14, 15, 16, 17, 18, 19, 20, 21, 21, 22, 23, 24, 25, 26, and 27 illustrate cross-sectional side views of housing structures developing with execution of the methods 1300 and arranged in accordance with some embodiments of the disclosure. For example, the methods 1300 illustrate a process flow for assembling preformed 2D capacitor patches or module housing architectures.The methods 1300 begin at input operation 1301, where a workpiece including a package substrate or similar substrate into which a capacitor module is to be embedded is received. The workpiece includes any suitable substrate material or material layers. In some embodiments, the received workpiece is a package substrate, such as an organic substrate that includes an organic core. In some embodiments, the substrate is or includes a thick organic core. However, other substrate materials may be used.FIG. 14 illustrates a cross-sectional side view of a package structure 1400 illustrating a received substrate 1401. The substrate 1401 may be characterized as an organic substrate, an electronic substrate, a circuit board, or the like. The substrate 1401 may be any suitable structure including, but not limited to, an interposer, a board, or the like. The substrate 1401 may have a first or top surface 1404 and an opposing second or bottom surface 1405. The substrate 1401 may include multiple dielectric material layers (not shown) that may include build-up films and / or solder stop layers, and may be made of a suitable dielectric material including, but not limited to, bismaleimide triazine resin, class 4 fire retardant material, polyimide material, silicon dioxide filled epoxy material, glass reinforced epoxy material, and the like, as well as low-k and ultra-low-k dielectrics (dielectric constants less than about 3.6), including, but not limited to, carbon doped dielectrics, fluorine doped dielectrics, porous dielectrics, organic polymeric dielectrics, and the like. In some embodiments, the substrate 1401 includes a core 1402 and build-up layers 1403. However, the substrate may have any suitable characteristics that provide a substrate thickness Tos that enables embedding and mounting of devices, circuitry, and the like. For example, the core 1402 may be a substrate of an integrated circuit package built on a board, card, or wafer comprising a non-flexible rigid material. A relatively small circuit board may be used as the core 1402, and an integrated circuit device and other components may be soldered to a surface of the board. In some embodiments, the core 1402 has vias extending from side to side, thereby allowing circuitry on one side of the core to be directly coupled to circuitry on the opposite side of the core 1402. In some embodiments, the core 1402 also serves as a platform for building layers of conductors and dielectric materials.Returning to FIG. 13, processing continues at operation 1302, where metallization may be patterned on the received substrate, an opening or cavity may be formed to receive a capacitor module, and the substrate may be attached to a temporary carrier or support substrate. Metallization may be patterned using any suitable technique or techniques, such as subtractive or additive metallization patterning techniques. In some embodiments, the metallization includes patterned copper for routing to the capacitor module and / or external devices. In some embodiments, the metallization includes patterned vias to provide electrical coupling to the front side and the back side of the substrate. The aperture or cavity may be formed using any suitable technique or techniques, such as mechanical drilling techniques. The opening or cavity may be formed with any suitable dimensions to accommodate one or more of the discussed capacitor modules and optionally other components. The substrate may be attached to the temporary carrier or support substrate using any suitable technique or techniques, such as by applying a releasable adhesive. The carrier or support substrate may be any suitable material.FIG. 15 illustrates a package structure 1500 similar to package structure 1400 after formation of metallization 1501. Metallization 1501 may be formed using subtractive or additive metallization patterning techniques, and metallization 1501 may include any suitable conductive metals, such as copper. In some embodiments, metallization 1501 includes patterned vias (not shown) that provide electrical coupling between top surface 1404 and bottom surface 1405 of substrate 1401.FIG. 16 illustrates a package structure 1600 similar to the package structure 1500 after the opening 1601 is formed. As shown, in some embodiments, the opening 1601 extends through the entirety of the thickness Tos of the substrate 1401. In some embodiments, the opening 1601 extends through only a portion of the thickness Tos of the substrate 1401, leaving a portion of the substrate 1401 that extends to the bottom surface 1405. Although illustrated with reference to the opening 1601 extending through the entirety of the thickness Tos of the substrate 1401, the following structures relate to examples in which a part of the thickness Tos of the substrate 1401 remains.FIG. 17 illustrates a package structure 1700 similar to the package structure 1600 after the temporary carrier 1701 is attached. The package structure 1600 may be attached to the temporary carrier 1701 using any suitable technique or techniques, such as a releasable adhesive layer. The temporary support 1701 may provide a surface for mounting a capacitor module as well as rigidity during mounting.Returning to FIG. 13, processing continues at operation 1303, where a capacitor module fabricated as discussed with respect to the methods 100 is mounted or attached within the opening formed at operation 1302. The capacitor module may include any number of substrates bonded together. Likewise, each capacitor module may include any number of capacitors having any suitable characteristics. In some embodiments, the capacitor module is a single substrate. In some embodiments, the capacitor module includes multiple substrates stacked and bonded using an adhesive layer, such as 2, 3, 4, 5, or more substrates and corresponding capacitor structures.FIG. 18 illustrates a package structure 1800 similar to package structure 1700 after mounting capacitor module 1200 within opening 1601. Although illustrated with respect to capacitor module 1200, any capacitor module discussed herein may be mounted within opening 1601. As shown, in some embodiments, the adhesive film 1201 is used to bond the capacitor module 1200 to the temporary carrier 1701. Furthermore, the length Ls of the substrates 901 extends over a total of the thickness Tos of the substrate 1401. For example, FIG. 18 illustrates an example vertically oriented glass substrate deep trench capacitor mounting within the opening 1601 of the substrate 1401. In some embodiments, the length Ls of the substrates 901 is substantially the same as the thickness Tos of the substrate 1401. In some embodiments, the length Ls of the substrates 901 is substantially the same as the thickness Tos of the substrate 1401 plus the thickness of the metallization 1501.As shown in FIG. 18, the thickness Tos (i.e., extending in the z-dimension) of the substrate 1401 is orthogonal to the top surface 1404 of the substrate 1401 (i.e., the top surface 1404 is in the x-y plane), so that the surfaces 302 (i.e., in the y-z plane) and the surfaces 303 (i.e., in the y-z plane) of each of the substrates 901 are also orthogonal to the top surface 1404 of the substrate 1401. That is, the substrates 901 have an orthogonal orientation with respect to the substrate 1401 such that the substrates 901 and the capacitor module 1200 are vertically oriented with respect to the working surface 1404 of the substrate 1401 (which is horizontally or laterally oriented).Such thickness adjustment (and vertical alignment) reduces process difficulties with respect to x, y, z alignment, rotational displacement, tilt, and the like with respect to mounting the capacitor module 1200 within the opening 1601 in the substrate 1401. Furthermore, the thickness adjustment and processing discussed enables the same registration marks to be used in the mechanical drilling process used to form the aperture 1601 and the placement operation used to mount the capacitor module 1200, which provides improved alignment. For example, the placement of the capacitor module 1200 may be characterized as direct alignment because the placement operation uses the same registration marks as the mechanical drilling process used to form the opening 1601.Returning to FIG. 13, processing continues at operation 1304, where the volume of the opening not filled by the one or more assembled capacitor modules and any other components is filled with a potting material, and the potting material is subsequently planarized. The potting material may be any suitable insulator material, such as a polymer, an epoxy, a build material, an organic fill material, or the like. The potting material may be characterized as an encapsulation dielectric, an encapsulation dielectric layer, a dielectric encapsulation material or the like. In some embodiments, the potting material is the same material used in the adhesion layer 1101 to bond substrates 901 together. However, the adhesive layer 1101 and the potting material may be different. The potting material may be formed within the remaining portion of the opening using any suitable technique or techniques. In some embodiments, the old material is laminated, coated, or filled by an encapsulation process. For example, the encapsulation process may be vacuum lamination, liquid coating, a potting process, or the like. Subsequently, the potting material is planarized using any suitable technique or techniques such as grinding or polishing operations to remove a supernatant of the potting material.FIG. 19 illustrates a package structure 1900 similar to package structure 1800 after the formation of a potting material 1901 within the remaining portions of opening 1601. The potting material 1901 may be a polymer, an epoxy, a building material, an organic filling material, or the like, and the potting material 1901 fills or substantially fills the remaining parts of the opening 1601. In some embodiments, the potting material 1901 and the adhesion layer 1101 are the same material, although they may be different. As shown, in some embodiments, the planar capacitor surface 706 (see FIG. 7 ) of the trench capacitor structures 903 of the leftmost substrate 901 may be in direct contact with a portion 1902 of the potting material 1901 such that the potting material 1901 provides isolation of the corresponding trench capacitor structures 903. As shown, portion 1902 extends from surface 302 (i.e., surface with trench capacitor structures 903) of leftmost substrate 901 to sidewall 1903 of substrate 1401.FIG. 20 illustrates a package structure 2000 similar to the package structure 1900 after planarization of the potting material 1901 to remove the protrusion material and expose a surface 2001 exposing regions such as the regions 912, 913 at the edge 911 (see FIG. 9 ) for making electrical contact to the trench capacitor structures 903.Returning to FIG. 13, processing continues at operation 1305, where contact electrode contacts are patterned for coupling to the vertically aligned capacitor structures, the temporary carrier is removed, and additional dielectric (e.g., laminate) and additional metallization may be formed. The electrode contacts may be formed using any suitable technique or techniques, such as subtractive or additive metallization patterning techniques. The temporary carrier may be removed using any suitable technique or techniques, such as UV-based detachment, chemical treatment, heat treatment, or others. The additional dielectric (e.g., laminate) and metallization may be formed using any suitable technique or techniques known in the art.FIG. 21 illustrates a package structure 2100 similar to the package structure 2000 after forming electrode contacts 2101. The electrode contacts 2101 may be formed using any suitable technique or techniques, such as subtractive or additive metallization patterning techniques, and the electrode contacts 2101 may include any suitable conductive material, such as copper. For example, the electrode contacts 2101 may be characterized as copper pads, bond pads, electrode pads, or the like. FIG. 21 further provides a top view 2120 of the package structure 2100 to illustrate how at the edge 911 an electrode contact 2101 a makes contact with the second electrode layer 703 and an electrode contact 2101 b makes contact with the first electrode layer 701. In some embodiments, one or both of the electrode contacts 2101 a, 2101 bincludes a conductive path portion extending from the second electrode layer 703 or the first electrode layer 701. For example, the electrode contacts 2101 provide contact to the trench capacitor structures 903 and may further provide routing to and from the trench capacitor structures 903. In some embodiments, the electrode contacts 2101 provide contact, and such routing or redistribution routing is provided by higher level metallization features.FIG. 22 illustrates a package structure 2200 similar to the package structure 2100 after removal of the temporary carrier 1701. The temporary carrier 1701 may be removed using any suitable technique or techniques, such as UV-based detachment, chemical treatment, heat treatment, or others. As shown, removing the temporary carrier 1701 exposes the bottom surface 1405 of the capacitor module 1200. In particular, if the capacitor module 1200 includes contacts at both edges of the capacitor module 1200 (e.g., if two cuts are made in segmentation operation 801), electrode contacts analogous to the electrode contacts 2101 may be formed to trench capacitor structures 903 at the bottom surface 1405.FIG. 23 illustrates a package structure 2300 similar to the package structure 2200 after forming the dielectric layers 2301, 2302. The dielectric layers 2301, 2302may be formed using any suitable technique or techniques, such as lamination techniques. In some embodiments, the dielectric layers 2301, 2302 are build-up layers or films. As shown, in some embodiments, dielectric layer 2301 is over top surface 1404 and dielectric layer 2301 is over bottom surface 1405. In some embodiments, only the dielectric layer 2301 is formed over the top surface 1404.FIG. 24 illustrates a package structure 2400 similar to the package structure 2300 after forming openings 2401 in the dielectric layers 2301, 2302. The openings 2401 may be formed using any suitable technique or techniques, such as laser drilling techniques, to expose underlying electrode contacts 2101. In embodiments where trench capacitor structures 903 are accessible from the bottom surface 1405, openings may be formed in the dielectric layer 2302.FIG. 25 illustrates a package structure 2500 similar to package structure 2400 after formation of metallization features 2501 coupled to electrode contacts 2101. Metallization features 2501 may be formed using any suitable technique or techniques, such as additive or subtractive metallization processes. In some embodiments, metallization features 2501 include a via portion 2502 extending through opening 2401 and a line portion 2503 extending from via portion 2502 and located on dielectric layer 2301. As shown, in some embodiments, the via portion 2502 is coupled to electrode contacts 2101, and the lead portion 2503 of the metallization feature 2501 extends over the substrate 1401.FIG. 26 illustrates a package structure 2600 similar to package structure 2500, illustrating an alternative embodiment employing a single substrate 901 and corresponding trench capacitor structures 903. In such embodiments, the planar capacitor surface 706 (see FIG. 7 ) of the trench capacitor structures 903 may be in direct contact with the potting material 1901 such that the potting material 1901 provides isolation of the respective trench capacitor structures 903 and the potting material extends to the sidewall 1903 of the substrate 1401. For example, returning to FIG. 13, processing continues at operation 1306, where any remaining interconnect features, including dielectric deposition, metallization routing, and the like, may be completed, the package substrate may be mounted by attaching integrated circuit dies and other processing, and the resulting structure may be output.In some embodiments, the terminals or metallization features coupled to the capacitor structure are bonded to integrated circuit dies or other circuitry, and the package substrate is assembled into an assembly including the integrated circuit dies, the package substrate, optional interconnect bridges, an optional board such as a motherboard, and optional thermal solutions as known in the art. The assembly or package substrate may then be installed in any suitable electronic device, such as a laptop, netbook, notebook, ultrabook, smart phone, tablet, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, digital video recorder, or the like.FIG. 27 illustrates an example microelectronic device assembly 2700 including a vertically embedded preformed 2D capacitor module, in accordance with some embodiments. Although illustrated as including capacitor module 1200 and package structure 2500, any capacitor module or substrate capacitor structure discussed herein may be embedded in any suitable package structure for use in microelectronic device assembly 2700. As shown in FIG. 27, microelectronic device assembly 2700 may include any number of integrated circuit dies 2706 and / or bridge dies 2707 mounted to package structure 2500 via die-level interconnects, redistribution layers, metallization routings, and the like. For example, integrated circuit dies 2706 may be coupled to trench capacitor structures 903. In some embodiments, such interconnect or conductive features are embedded in a potting material, such as potting material 1901. Although illustrated with reference to three integrated circuit dies 2706 (e.g., a computing die, a memory die, and a transceiver) and two bridge dies 2707 (e.g., embedded multi-die interconnect bridges), any number of integrated circuit dies, a 3D stacked multichip device, a multichip package, or the like may be employed in microelectronic device package 2700. In some embodiments, package structure 2500 is coupled to a board 2711 via package level interconnects 2709, and partially encapsulated by an underfill material 2712.Microelectronic device assembly 2700 further includes a power supply 2713 coupled to one or more of circuit board 2711, packaging structure 2500, integrated circuit die 2706, or other components of microelectronic device assembly 2700. The power supply 2713 may include a battery, a voltage converter, a power supply circuitry, or the like. Microelectronic device assembly 2700 further includes a thermal conductive material (TIM) 2701 disposed on top surfaces of integrated circuit dies 2706. The TIM 2701 may include any suitable thermally conductive material and may be characterized as TIM 1. A heat spreader integrated 2702 having a surface on the TIM 2701 extends over the integrated circuit die 2706 and the package structure 2500 and is mounted on the board 2711. The board 2711 may include any suitable substrate, such as a motherboard, interposer, or the like. Microelectronic device assembly 2700 further includes a TIM 2703 disposed on a surface of integrated heat spreader 2702. The TIM 2703 may include any suitable thermally conductive material and may be characterized as TIM 2. TIM 2701 and TIM 2703 may be the same materials or may be different. A heat sink 2704 (e.g., an example heat sink or thermal solution) is located on the TIM 2703 and dissipates heat. Microelectronic device assembly 2700 may be used in desktop and server form factors. In other contexts, a thermal solution, such as a heat pipe or a heat spreader, may be mounted directly on the TIM 2701. Such assemblies can be used in smaller form factor devices. Other heat dissipation devices may also be used.FIG. 28 illustrates example systems employing a vertically embedded preformed 2D capacitor module, in accordance with some embodiments. The system may be, for example, a mobile computing platform 2805 and / or a data server machine 2806. Both may employ a component assembly that includes a vertically embedded preformed 2D capacitor module as described herein. The server machine 2806 may be any commercial server including, for example, any number of high performance computing platforms disposed within a rack and networked together for electronic data processing, which in the embodiment includes an integrated circuit (IC) die package 2850 having a vertically embedded preformed 2D capacitor module as described elsewhere herein. The mobile computing platform 2805 may be any portable device configured for electronic data display, electronic data processing, wireless electronic data transmission, or the like, respectively. For example, mobile computing platform 2805 may be any of a tablet, a smartphone, a laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touch screen), a chip- or package-level integrated system 2810, and a battery 2815. Although illustrated with respect to mobile computing platform 2805, in other examples, integrated system 2810 may be implemented at a chip or package level and a battery 2815 in a desktop computing platform, an automotive computing platform, an Internet of Things platform, or the like. As discussed below, in some examples, the disclosed systems may include a subsystem 2860 such as a system-on-a-chip (SOC) or an integrated system of multiple ICs, which is illustrated with respect to the mobile computing platform 2805.Regardless of whether disposed within the integrated system 2810 illustrated in the extended view 2820 or as a stand-alone encapsulated device within the data server machine 2806, the subsystem 2860 may include memory circuitry and / or processor circuitry 2840 (e.g., RAM, microprocessor, multi-core microprocessor, graphics processor, etc.), a power management integrated circuit (PMIC) 2830, a controller 2835, and a radio frequency integrated circuit (RFIC) 2825 (e.g., including a broadband RF transmitter and / or receiver (TX / RX)). As shown, one or more IC dies, such as memory circuitry and / or processor circuitry 2840 may be encapsulated, mounted, and implemented such that the package includes one or more vertically embedded preformed 2D capacitor modules as described herein. In some embodiments, the RFIC 2825 includes digital baseband and an analog front end module that further includes a power amplifier on a transmit path and a low noise amplifier on a receive path. Functionally, the PMIC 2830 may perform battery power regulation, DC-DC conversion, etc., and thus has an input coupled to the battery 2815 and an output providing power supply to all other functional modules. As further illustrated in FIG. 28, in the embodiment, RFIC 2825 has an output coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are referred to as 3G, 4G, 5G, and beyond. Memory circuitry and / or processor circuitry 2840 may provide memory functions for subsystem 2860, high level control, data processing, and the like for subsystem 2860. In alternative implementations, each of the SOC modules may be integrated on separate ICs coupled to a package substrate, interposer, or board.FIG. 29 is a functional block diagram of an electronic computing device 2900, in accordance with some embodiments. For example, the apparatus 2900 may employ, via any suitable component therein, a vertically embedded preformed 2D capacitor module according to any embodiments described elsewhere herein. The device 2900 further includes a motherboard or package substrate 2902 that houses a number of components, such as, but not limited to, a processor 2904 (e.g., an application processor). The processor 2904 may be physically and / or electrically coupled to the package substrate 2902. In some examples, processor 2904 is located within an encapsulated IC package that includes a vertically embedded preformed 2D capacitor module as described elsewhere herein. In general, the term "processor" or "microprocessor" may refer to any device or portion of a device that processes electronic data from registers and / or from a memory to transform that electronic data into other electronic data that may be further stored in registers and / or a memory.In various examples, one or more communication chips 2906 may also be physically and / or electrically coupled to the package substrate 2902. In further implementations, communication chips 2906 may be part of processor 2904. Depending on its applications, computing device 2900 may include other components that may or may not be physically and electrically coupled to package substrate 2902. These other components include, but are not limited to, volatile memory (e.g., DRAM 2932), nonvolatile memory (e.g., ROM 2935), flash memory (e.g., NAND or NOR), magnetic memory (MRAM 2930), graphics processor 2922, a digital signal processor, a crypto processor, a chipset 2912, an antenna 2925, touch screen display 2915, touch screen controller 2965, battery 2916, audio codec, video codec, power amplifier 2921, global positioning system (GPS) device 2940, compass 2945, accelerometer, gyroscope, speaker 2920, camera 2941, and mass storage device (such as hard disk drive, a solid state drive (SSD), a compact disk (CD), a digital versatile disk DVD), and so forth), or the like.The communication chips 2906 may enable wireless communications for the transmission of data to and from the computing device 2900. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain any. Communication chips 2906 may implement any of a number of wireless standards or protocols, including, but not limited to, those described elsewhere herein. Computing device 2900 may include a plurality of communication chips 2906 as discussed. For example, a first communication chip may be dedicated to wireless communications in closer areas, such as WLAN and Bluetooth, and a second communication chip may be dedicated to wireless communications in more remote areas, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.Although certain features set forth herein have been described with reference to various implementations, this description is not intended to be interpreted in a limiting sense. Accordingly, various modifications of the implementations described herein, as well as other implementations, that are apparent to those skilled in the art to which the present disclosure pertains are deemed to be within the spirit and scope of the present disclosure.It is to be understood that the invention is not limited to the embodiments thus described, but may be carried out with modification and modification without departing from the scope of the appended claims. For example, the above embodiments may include specific combinations of features as further provided below.The following relates to exemplary embodiments.In one or more first embodiments, a device includes one or more first capacitor structures embedded within respective first openings extending along a length of a first surface of a first substrate, the first surface opposing a second surface of the first substrate, each of the first capacitor structures including a capacitor surface substantially coplanar with the first surface of the first substrate, an insulator layer on the first surface of the first substrate and on each capacitor surface, first electrodes and second electrodes of the first capacitor structures being exposed at an edge of the first substrate extending between the first surface and the second surface of the first substrate, and one or more second capacitor structures embedded within respective second openings extending along a length of a first surface of a second substrate, wherein the first surface is opposite a second surface of the second substrate, wherein the first or second surface of the second substrate is on the insulator layer.In one or more second embodiments, in addition to the first embodiments, each of the capacitor surfaces includes a region of each of the first electrode, the second electrode, and a dielectric material between the first electrode and the second electrode.In one or more third embodiments, in addition to the first or second embodiments, the second surface of the second substrate is on the insulator layer, and the apparatus further comprises a second insulator layer on the first surface of the second substrate and on the second capacitor structures, and one or more third capacitor structures embedded within corresponding third openings extending along a length of a first surface of a third substrate, the first surface opposing a second surface of the second substrate, the second surface of the third substrate being on the second insulator layer.In one or more fourth embodiments, in addition to the first through third embodiments, the edge of the first substrate is a first edge, and wherein a portion of the first substrate is between each of the first capacitor structures and a second edge of the first substrate opposite the first edge of the first substrate.In one or more fifth embodiments, in addition to the first to fourth embodiments, the insulator layer comprises a polymer material.In one or more sixth embodiments, in addition to the first to fifth embodiments, the first substrate and the second substrate each include a glass layer having a rectangular shape along the first surface of the first substrate and the first surface of the second substrate.In one or more seventh embodiments, in addition to the first through sixth embodiments, the first capacitor structures, the first substrate, the insulator layer, the second capacitor structures, and the second substrate comprise a capacitor module, the capacitor module extending at least partially through a thickness of an organic substrate orthogonal to a top surface of the organic substrate, the first surface of the first substrate being substantially orthogonal to the top surface of the organic substrate.In one or more eighth embodiments, in addition to the first to seventh embodiments, the thickness of the organic substrate is not less than 1 mm, and a length of the first capacitor structures extending along the thickness is not less than 0.75 mm.In one or more ninth embodiments, in addition to the first to eighth embodiments, the device further includes a first contact coupled to one of the first electrodes at the edge, a second contact coupled to one of the second electrodes at the edge, a metallization coupled to the first contact and extending over the organic substrate, and an integrated circuit die coupled to the metallization.In one or more tenth embodiments, a system includes an IC die and / or a power supply coupled to the one or more first capacitor structures of the first through eighth embodiments.In one or more eleventh embodiments, a device comprises one or more capacitor structures embedded within corresponding openings in a first surface of an inorganic substrate, the first surface opposing a second surface of the inorganic substrate, an organic substrate, the inorganic substrate extending at least partially through a thickness of the organic substrate orthogonal to a top surface of the organic substrate such that the first surface of the inorganic substrate is orthogonal to the top surface of the organic substrate, a polymeric material on the first surface of the inorganic substrate and the capacitor structures, and first and second contacts coupled to first and second electrodes of one of the capacitor structures at an edge of the inorganic substrate extending from the first surface of the inorganic substrate to the second surface of the inorganic substrate.In one or more twelfth embodiments, in addition to the eleventh embodiments, the polymer material is located on a second surface of the inorganic substrate opposite to the first surface of the inorganic substrate and on a sidewall of the organic substrate.In one or more thirteenth embodiments, in addition to the eleventh or twelfth embodiments, the apparatus further comprises one or more second capacitor structures embedded within respective openings in a first surface of a second inorganic substrate, wherein the polymer material is on the first surface of the second inorganic substrate or on a second surface of the second inorganic substrate opposite to the first surface of the second inorganic substrate.In one or more fourteenth embodiments, in addition to the eleventh to thirteenth embodiments, the polymer material is an epoxy adhesive, and the device further comprises a potting material on a second surface of the inorganic substrate opposite to the first surface of the inorganic substrate and on a sidewall of the organic substrate.In one or more fifteenth embodiments, in addition to the eleventh to fourteenth embodiments, the thickness of the organic substrate is not less than 1 mm, and wherein a length of the first capacitor structures extending along the thickness is not less than 0.75 mm.In one or more sixteenth embodiments, in addition to the eleventh to fifteenth embodiments, the openings in the first surface of the inorganic substrate have a cross-sectional shape orthogonal to the first surface, the cross-sectional shape including one of a cross shape, a T shape, a partial oval shape, and a diagonal line.In one or more seventeenth embodiments, in addition to the eleventh to sixteenth embodiments, the apparatus further comprises an integrated circuit die coupled to one of the capacitor structures.In one or more eighteenth embodiments, a system includes an IC die and / or a power supply coupled to the one or more first capacitor structures of the eleventh through seventeenth embodiments.In one or more nineteenth embodiments, a method includes forming one or more trench capacitor structures embedded within corresponding openings extending along a length of a surface of a substrate, segmenting the substrate and the one or more trench capacitor structures to form a first capacitor submodule including a portion of the substrate and portions of the trench capacitor structures, and stacking a plurality of capacitor submodules including the first capacitor submodule via one or more adhesive layers between surfaces of substrates of the capacitor submodules to form a capacitor module, electrodes of the trench capacitor structures being exposed at a first edge of the capacitor module.In one or more twentieth embodiments, in addition to the nineteenth embodiments, forming each of the one or more trench capacitor structures includes forming a first electrode layer in the trench, forming a dielectric layer on the first electrode layer, forming a second electrode layer on the dielectric layer, planarizing the first electrode layer, the dielectric layer, and the second electrode layer to form a capacitor structure layer coplanar with the surface of the substrate, wherein one of the adhesive layers is directly on the capacitor structure layer.In one or more twenty-first embodiments, in addition to the nineteenth or twentieth embodiments, the method further comprises inserting the capacitor module into an opening extending at least partially through an organic substrate, and securing the capacitor module to the organic substrate by a polymeric material contacting one or more exposed trench capacitor structures.In one or more twenty-second embodiments, in addition to the nineteenth to twenty-first embodiments, the method further comprises contacting the electrodes of the trench capacitor structures with a plurality of metallization features, wherein at least one of the metallization features extends over the organic substrate.However, the above embodiments are not limited in this respect, and in various implementations, the above embodiments may include performing only a subset of such features, performing a different order of such features, performing a different combination of such features, and / or performing additional features than those features explicitly listed. The scope of the invention should therefore be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

An apparatus comprising: one or more first capacitor structures embedded within respective first openings extending along a length of a first surface of a first substrate, the first surface opposing a second surface of the first substrate, each of the first capacitor structures comprising a capacitor surface substantially coplanar with the first surface of the first substrate; an insulator layer on the first surface of the first substrate and on each capacitor surface, wherein first electrodes and second electrodes of the first capacitor structures are exposed at an edge of the first substrate extending between the first surface and the second surface of the first substrate; and one or more second capacitor structures embedded within corresponding second openings extending along a length of a first surface of a second substrate, the first surface opposing a second surface of the second substrate, the first or second surface of the second substrate being on the insulator layer.The device of claim 1, wherein each of the capacitor surfaces comprises a region of each of the first electrode, the second electrode, and a dielectric material between the first electrode and the second electrode.The device of claim 1 or 2, wherein the second surface of the second substrate is on the insulator layer, the device further comprising: a second insulator layer on the first surface of the second substrate and on the second capacitor structures; and one or more third capacitor structures embedded within corresponding third openings extending along a length of a first surface of a third substrate, the first surface opposing a second surface of the second substrate, the second surface of the third substrate being on the second insulator layer.The apparatus of any of claims 1 to 3, wherein the edge of the first substrate is a first edge, and wherein a portion of the first substrate is located between each of the first capacitor structures and a second edge of the first substrate opposite the first edge of the first substrate.The device of any of claims 1 to 4, wherein the insulator layer comprises a polymeric material.The device of any one of claims 1 to 5, wherein the first substrate and the second substrate each comprise a glass layer having a rectangular shape along the first surface of the first substrate and the first surface of the second substrate.The device of any of claims 1 to 6, wherein the first capacitor structures, the first substrate, the insulator layer, the second capacitor structures, and the second substrate comprise a capacitor module, the capacitor module extending at least partially through a thickness of an organic substrate orthogonal to a top surface of the organic substrate, the first surface of the first substrate being substantially orthogonal to the top surface of the organic substrate.The device of claim 7, wherein the thickness of the organic substrate is not less than 1 mm, and wherein a length of the first capacitor structures extending along the thickness is not less than 0.75 mm.The device of claim 7 or 8, further comprising: a first contact coupled to one of the first electrodes at the edge; a second contact coupled to one of the second electrodes at the edge; a metallization coupled to the first contact and extending over the organic substrate; and an integrated circuit die coupled to the metallization.An apparatus comprising: one or more capacitor structures embedded within corresponding openings in a first surface of an inorganic substrate, the first surface opposing a second surface of the inorganic substrate; an organic substrate, the inorganic substrate extending at least partially through a thickness of the organic substrate orthogonal to a top surface of the organic substrate such that the first surface of the inorganic substrate is orthogonal to the top surface of the organic substrate; a polymeric material on the first surface of the inorganic substrate and the capacitor structures; and first and second contacts coupled to first and second electrodes of one of the capacitor structures at an edge of the inorganic substrate extending from the first surface of the inorganic substrate to the second surface of the inorganic substrate.The device of claim 10, wherein the polymeric material is on a second surface of the inorganic substrate opposite the first surface of the inorganic substrate and on a sidewall of the organic substrate.The apparatus of claim 10 or 11, further comprising: one or more second capacitor structures embedded within corresponding openings in a first surface of a second inorganic substrate, wherein the polymer material is on the first surface of the second inorganic substrate or on a second surface of the second inorganic substrate opposite the first surface of the second inorganic substrate.The device of claim 12, further comprising: a potting material on a second surface of the inorganic substrate opposite the first surface of the inorganic substrate and on a sidewall of the organic substrate.The device of claim 12 or 13, wherein the polymeric material is an epoxy adhesive.The device of any of claims 10 to 14, wherein the thickness of the organic substrate is not less than 1 mm, and wherein a length of the capacitor structures extending along the thickness is not less than 0.75 mm.The device of any one of claims 10 to 15, wherein the openings in the first surface of the inorganic substrate have a cross-sectional shape orthogonal to the first surface, wherein the cross-sectional shape comprises one of a cross shape, a T shape, a partially oval shape, and a diagonal line.The device of any of claims 10 to 16, wherein each of the capacitor structures comprises a first electrode layer separated by a second electrode layer by a dielectric layer.The device of any of claims 17, wherein each of the capacitor structures comprises a planar surface comprising a portion of the first electrode layer, the dielectric layer, and the second electrode layer.The device of any of claims 10 to 18, further comprising: an integrated circuit die coupled to one of the capacitor structures.A method comprising: forming one or more trench capacitor structures embedded within corresponding openings extending along a length of a surface of a substrate; segmenting the substrate and the one or more trench capacitor structures to form a first capacitor submodule comprising a portion of the substrate and portions of the trench capacitor structures; and stacking a plurality of capacitor submodules including the first capacitor submodule via one or more adhesive layers between surfaces of substrates of the capacitor submodules to form a capacitor module, wherein electrodes of the trench capacitor structures are exposed at a first edge of the capacitor module.The method of claim 20, wherein forming each of the one or more trench capacitor structures comprises: forming a first electrode layer in the trench; forming a dielectric layer on the first electrode layer; forming a second electrode layer on the dielectric layer; and planarizing the first electrode layer, the dielectric layer, and the second electrode layer to form a capacitor structure layer coplanar with the surface of the substrate, wherein one of the adhesive layers is directly on the capacitor structure layer.The method of claim 20 or 21, further comprising: inserting the capacitor module into an opening that extends at least partially through an organic substrate; and securing the capacitor module to the organic substrate by a material contacting one or more exposed trench capacitor structures.The method of claim 22, wherein the material comprises a polymeric material.The method of any of claims 20 to 23, further comprising: contacting the electrodes of the trench capacitor structures with a plurality of metallization features, wherein at least one of the metallization features extends over the organic substrate.

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