SEMICONDUCTOR DEVICE

Abstract

High-speed analog-to-digital conversion is achieved in a semiconductor device. A voltage quantization circuit comprises: a first comparator with a first input transistor that inputs differential input voltages and defines the value of the first bit of a digital signal; and a second comparator with a second input transistor, different from the first input transistor, that defines the value of the second bit of the digital signal. A correction code decision circuit determines a correction code to correct the common-mode voltage of the differential input voltages based on a conversion output signal from the voltage quantization circuit. A common-mode voltage regulator circuit regulates the common-mode voltage by adding or subtracting a corrected voltage from the differential input voltages based on the correction code.

Description

Cross-Reference to Related ApplicationsThe disclosure of Japanese Patent Application No. 2023-174228 filed on Oct. 6, 2023 is incorporated herein fully, including the application text, the drawings and the abstract, by reference.Technical Field of the InventionThe present invention relates to a semiconductor device such as a semiconductor device including an analog / digital converter.A disclosed technique is given below.[Non-Patent Document 1] "Single-Channel, 1.25-GS / s, 6-bit, Loop-Unrolled Asynchronous SAR ADC in 40 nm-COM", IEEE CICC 2010, Tao Jiang, and four others.BACKGROUND OF THE INVENTIONNon-Patent Document 1 describes an asynchronous "analog / digital converter" with "successive approximation register" (SAR ADC) capable of performing high-speed operations. The SAR ADC includes as many comparators as bits of a digital signal. A comparator closer to the most significant bit outputs an enable signal to a comparator closer to the least significant bit when a comparison operation is completed. As a result, each comparator successively performs the comparison operation (approximation operation) in an order from the most significant bit to the least significant bit.SummaryFor example, a system in which each bit of a digital signal is successively defined while a comparator is repeatedly used is known as a typical configuration of the SAR ADC. However, the system must reset the comparator at each repetition, and thus it may be difficult to achieve the high-speed operation. Therefore, as described in, for example, Non-Patent Document 1, use of the asynchronous SAR ADC, particularly a rolled-loop SAR ADC that does not require repetitive operation because it has as many comparators as bits of the digital signal can be considered.However, the use of such an asynchronous SAR ADC risks a long comparison time of the comparators due to the influence of a common mode differential input voltage. Consequently, there is a risk of an insufficient speed of the A / D converter.The embodiments described below have been made under such circumstances, and other objects and novel features will become apparent from the description of the specification and drawings.A semiconductor device according to an embodiment includes: a voltage quantization circuit that converts differential input voltages for each sampling period into a digital signal having multiple bits and activates a conversion end signal upon completion of a conversion operation; a correction code decision circuit that receives the conversion end signal as its input output from the voltage quantization circuit; and a common mode voltage regulator circuit that regulates a common mode voltage of the differential input voltages. The voltage quantization circuit includes: a first comparator including a first input transistor that receives the differential input voltages as its input and defines a first bit value of the digital signal; and a second comparator including a second input transistor different from the first input transistor and defines a second bit value of the digital signal. The correction code decision circuit decides a correction code for correcting the common mode voltage of the differential input voltages on the basis of the conversion end signal output from the voltage quantization circuit. The common mode voltage regulator circuit adjusts the common mode voltage by adding or subtracting a corrected voltage based on the correction code to or from the differential input voltages.Using the semiconductor device according to an embodiment, the speed of an A / D converter can be increased.Brief Description of the DrawingsFIG. 1 is a block diagram showing an exemplary schematic configuration of a semiconductor device according to a first embodiment. FIG. 2A is a circuit block diagram showing an exemplary configuration of a voltage quantization circuit as a main part of an A / D converter of FIG. 1. FIG. 2B is a circuit diagram showing an exemplary schematic configuration of the voltage quantization circuit of FIG. 2A. FIG. 3 is a circuit diagram showing an exemplary configuration of the relationship of clock signals in the voltage quantization circuit of FIG. 2. FIG. 4 is a timing diagram showing an example normal operation of the voltage quantization circuit of FIGS. 2 and 3. FIG. 5A is a circuit diagram showing an exemplary configuration of each comparator of FIG. 2A. FIG. 5B is a circuit diagram showing an exemplary configuration of each comparator different from that of FIG. 5A. FIG. 6 is a circuit block diagram showing an exemplary schematic configuration of an analog / digital conversion unit of FIG. 1. FIG. 7 is a diagram for explaining an exemplary operation of a common mode voltage regulator circuit of FIG. 6. FIG. 8A is a circuit diagram showing an exemplary configuration of the common mode voltage regulator circuit of FIG. 6. FIG. 8B is a timing diagram showing an example schematic operation of the control logic of FIG. 8A. FIG. 9A is a flowchart showing an exemplary processing content of a correction code decision circuit of FIG. 6. FIG. 9B is a flowchart showing an example processing content different from that of FIG. 9A. FIG. 10A is a diagram showing an exemplary result of a correction code decision using the flowchart of FIG. 9A or 9B. FIG. 10B is a diagram showing an exemplary result different from that of FIG. 10A. FIG. 11A is a circuit diagram showing an exemplary configuration of a group of comparators of FIG. 6. FIG. 11B is a circuit diagram for explaining various modification examples of FIG. 11A. FIG. 12A is a diagram showing a method of generating a sampling clock signal in FIG. 6 and an example operation timing of the correction code decision circuit based on the method. FIG. 12B is a diagram showing a method of generating a sampling clock signal in FIG. 6 and an example operation timing of the correction code decision circuit based on the method. FIG. 13 is a circuit block diagram showing an exemplary schematic configuration of an analog / digital conversion unit of FIG. 1 in a semiconductor device according to a second embodiment. FIG. 14 is a circuit diagram showing an exemplary configuration of a group of comparators of FIG. 6 or 13 in a semiconductor device according to a third embodiment. FIG. 15 is a schematic diagram showing an exemplary transition of differential input voltages of FIG. 6 or 13 in the semiconductor device according to the third embodiment. FIG. 16 is a timing diagram showing an example change in common mode voltage by the group of comparators of FIG. 14. FIG. 17A is a schematic diagram showing an exemplary problem in the case of simply using the voltage quantization circuit of FIG. 2A. FIG. 17B is a schematic diagram showing an exemplary problem in the case of simply using the voltage quantization circuit of FIG. 2A. FIG. 18 is a schematic diagram showing an exemplary relationship between the common mode voltage of the differential input voltages and the comparison time in the voltage quantization circuit of FIG. 2A. FIG. 19 is a schematic diagram showing an exemplary operation in the case of a designed configuration of the group of comparators in the voltage quantization circuit of FIG. 2A. FIG. 20A is a diagram for explaining the influence of an initial value of the common mode voltage, assuming the system of FIG. 19. FIG. 20B is a diagram for explaining the influence of an initial value of the common mode voltage, assuming the system of FIG. 19. FIG. 21 is a timing chart showing an exemplary operation of the voltage quantization circuit in the case of an improper common mode voltage in FIGS. 20A and 20B.Detailed DescriptionIn the embodiments described below, the invention is described in several sections or embodiments, as required, for simplicity. However, these portions or embodiments are not unrelated to each other unless otherwise specified, and one refers to the whole or a part of the other for a modification example, details, or supplementary explanation thereof. In addition, in the embodiments described below, the number of elements when referring to the number of elements (including unit number, values, amount, range, and the like) is not limited to a specific number unless otherwise stated or except in the case where the number is obviously fundamentally limited to a specific number. A number greater than or less than the indicated number is also applicable.Further, in the embodiments described below, it goes without saying that the components (including elemental steps) are not always indispensable unless otherwise specified or except in the case where the components are obviously fundamentally indispensable. Also, in the embodiments described below, when the shape of the components, their positional relationship, and the like are mentioned, the substantially approximate and similar shapes and the like are included therein unless otherwise specified or except in the case where it is conceivable that they are obviously basically excluded. The same applies to the numerical value and range described above.Although not particularly limited, circuit elements constituting function blocks according to the embodiments are formed on a semiconductor substrate of single crystal silicon or the like by an integrated circuit technique such as known complementary MOS (CMOS) transistors and the like. Note that in the embodiments, a metal oxide semiconductor field effect transistor (MOSFET) is used as an exemplary metal insulator semiconductor field effect transistor (MISFET). However, a non-oxide film is not excluded as a gate insulating film. Further, in the embodiments, an n-channel MOS transistor is referred to as an nMOS transistor, while a p-channel MOS transistor is referred to as a pMOS transistor.Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. Note that components having the same function are denoted by the same reference numerals throughout the drawings for describing the embodiments, and repeated description is omitted. Moreover, the description of the same or similar portions is not basically repeated unless it is expressly required in the following embodiments.(First Embodiment)<Konfiguration of Semiconductor Device>FIG. 1 is a block diagram showing an exemplary schematic configuration of a semiconductor device according to a first embodiment. A semiconductor device DEV illustrated in FIG. 1 is a system-on-chip (SoC) or the like used in, for example, a digital key for a vehicle and having a wireless communication function based on ultra wide band (UWB) standards. In fact, the semiconductor device DEV is not limited in configuration to FIG. 1, and only needs to include at least one analog / digital converter ADC described later.The semiconductor device DEV illustrated in FIG. 1 includes a processor PRC, a memory MEM, a peripheral circuit PERI, a UWB digital circuit UWB_D, a UWB analog circuit UWB_A, and a bus BS. The bus BS connects the processor PRC, the memory MEM, the peripheral circuit PERI and the UWB digital circuit UWB_D to each other. The UWB analog circuit UWB_A is connected to the UWB digital circuit UWB_D.The processor PRC is a central processing unit (CPU), a graphics processing unit (GPU), or the like. The memory MEM is composed of a combination of a volatile memory such as static RAM (SRAM) and a nonvolatile memory such as flash memory or magnetoresistive RAM (MRAM). The peripheral circuit PERI includes various communication interfaces such as a controller area network (CAN) interface or a serial peripheral interface (SPI).The UWB digital circuit UWB_D also serves as a baseband processing circuit that is responsible for processing in a baseband on the basis of the UWB standards. The processings in the baseband include, for example, encoding / decoding, modulation / demodulation, encryption / decryption, and the like. The UWB analog circuit UWB_A also serves as a high-frequency circuit that is responsible for processing in a high-frequency band on the basis of the UWB standards. The UWB analog circuit UWB_A includes a high-frequency transmission circuit RF_TX configured to process a transmission signal, a high-frequency reception circuit RF_RX configured to process a reception signal, and a clock generation circuit CKG.The clock generating circuit CKG generates various clock signals used in a high frequency band and supplies them to the high frequency transmitting circuit RF_TX and the high frequency receiving circuit RF_RX. The transmission circuit RF_TX includes a power amplifier and the like. The high-frequency transmission circuit RF_TX converts a transmission baseband signal output from the UWB digital circuit UWB_D into a high-frequency transmission signal consisting of short pulses using a clock signal output from the clock generation circuit CKG, and transmits the high-frequency transmission signal to an antenna, not illustrated.The high-frequency receiving circuit RF_RX includes a low-noise amplifier LNA, a mixing unit MIXU, a filter unit FLTU, an analog / digital conversion unit ADCU, and the like. The low noise amplifier LNA amplifies a high frequency reception signal received by the antenna, not shown. The mixing unit MIXU includes, for example, a plurality of mixing circuits and down converts an output signal of the low-noise amplifier LNA into a baseband reception signal using a clock signal output from the clock generating circuit CKG. The filter unit FLTU comprises a plurality of filter circuits and limits the baseband reception signal output by the mixing unit MIXU to a band of, for example, approximately 500 MHz.The analog / digital conversion unit ADC comprises a plurality of analog / digital converters ADC. The analog / digital converter ADC is, for example, the asynchronous SAR ADC. The analog / digital converter ADC converts an analog input voltage VA output from the filter unit FLTU into a digital signal D having m bits, for example, 6 bits. Then, the analog / digital converter ADC outputs the resultant digital signal D to the UWB digital circuit UWB_D as digital data of the baseband reception signal.In this example, the analog / digital conversion unit ADCU includes two analog / digital converters ADC to perform conversion into a digital signal D having "2×m" bits. The ADC is supplied with a master clock signal CKm from the clock generator circuit CKG. For example, the analog / digital converter ADC generates a sampling clock signal of 1 GHz or 2 GHz based on the master clock signal CKm, and operates in synchronization with the sampling clock signal.<Analog / Digital Converter>FIG. 2A is a circuit block diagram showing an exemplary configuration of a voltage quantization circuit serving as a main part of the A / D converter of FIG. 1. FIG. 2B is a circuit diagram showing an exemplary schematic configuration of the voltage quantization circuit of FIG. 2A. FIG. 3 is a circuit diagram showing an exemplary configuration of the relationship of clock signals in the voltage quantization circuit of FIG. 2. FIG. 4 is a timing diagram showing an example normal operation of the voltage quantization circuit of FIGS. 2 and 3.A voltage quantization circuit QCT of Fig. 2A serves as the main part of the analog / digital converter ADC of Fig. 1, in particular the asynchronous rolled-loop SAR ADC. The voltage quantization circuit QCT includes a sampling switch SSW, a digital / analog converter CDAC, and "m" comparators, which in this example are six comparators CMP[0] to CMP[5]. For the differential input nodes NinP and NinN, particularly for the conversion capacitors in the digital / analog converter CDAC, the sampling switch SSW samples the positive and negative side analog input voltages VAp and VAn as differential signals in an activation period of a sampling clock signal CKs.The comparators CMP[ 0] to CMP[ 5] define bit values of digital signals, in other words, values of positive-side digital signals Dp[ 0] to Dp[ 5] and values of negative-side digital signals Dn[ 0] to Dn[ 5] on the opposite side of the positive-side digital signals. The D / A converter CDAC adds or subtracts a predetermined voltage to or from the differential input voltages INp and INn of the differential input nodes NinP and NinN according to the values of the digital signals Dp[ 0] to Dp[ 5] and Dn[ 0] to Dn[ 5]. As a result, the DAC updates the differential input voltages INp and INn.The D / A converter CDAC is, for example, specifically of the capacitor type as shown in FIG. 2B. The digital / analog converter CDAC includes five capacitors Cp[ 1] to Cp[ 5] serving as conversion capacitors, a dummy capacitor CpD, five capacitors Cn[ 1] to Cn[ 5] serving as conversion capacitors, and a dummy capacitor CnD. However, the D / A converter is not limited to the capacitor type, but may be a resistor type, for example. Alternatively, the dummy capacitors CpD and CnD may be external capacitors.One end of each of the five capacitors Cp[ 1] to Cp[ 5] and the dummy capacitor CpD is connected to the positive-side differential input node NinP. The positive-side digital signals Dp[ 1] to Dp[ 5] are respectively applied to the other ends of the five capacitors Cp[ 1] to Cp[ 5]. The other end of the dummy capacitor CpD is fixed to a ground power voltage GND.Similarly, one end of each of the five capacitors Cn[ 1] to Cn[ 5] and the dummy capacitor CnD is connected to the negative-side differential input node NinN. The negative-side digital signals Dn[ 1] to Dn[ 5] are respectively applied to the other ends of the five capacitors Cn[ 1] to Cn[ 5]. The other end of the dummy capacitor CnD is fixed to the ground power voltage GND.Each capacitor Cp[k] (k=1, 2,..., 5) has a capacitance value of, for example, "2 k-1 × Cu". Also, each capacitor Cn[k] has a capacitance value of "2 k-1 × Cu". The capacitance values of the dummy capacitors CpD and CnD are defined to be the same value based on the ranges of the analog input voltages VAp and VAn or the like.Each of the comparators CMP[ 0] to CMP[ 5] compares the zero voltage and a voltage difference "INp-INn" between the positive-side differential input voltage INp and the negative-side differential input voltage INn in terms of magnitude relationship. At this time, each comparator CMP[i] (i=5, 4,..., 0) starts the comparison operation in response to the activation of the clock signal CK[i]. Upon completion of the comparison operation, the comparator CMP[i] activates a clock signal CK[i-1] for a next comparator CMP[i-1].Thereby, the comparison operation is sequentially performed in an order from the comparator CMP[5] to the comparator CMP[0]. As a comparison result, each comparator CMP[i] outputs a positive digital signal Dp[i] and a negative digital signal Dn[i] on the opposite side of the positive digital signal. On the other hand, at each completion of the comparison operation of each comparator CMP[i], the D / A converter CDAC updates the differential input voltages INp and INn based on the digital signals Dp[i] and Dn[i], respectively, resulting from the comparison by adding or subtracting a predetermined voltage different from the differential input voltages INp and INn by "1 / 2 n".The next comparator CMP[i-1] performs the comparison operation on the differential input voltages INp and INn updated as described above. Thus, the analog / digital converter ADC can convert the analog input voltages VAp and VAn serving as a differential signal, in other words, "VAp-VAn", into the 6-bit digital signals Dp[ 0] to Dp[ 5].As shown in FIG. 4, since the sampling clock signal CKs is input first, the positive-side differential input voltage INp is defined at the level of the positive-side analog input voltage VAp, while the negative-side differential input voltage INn is defined at the level of the negative-side analog input voltage VAn. Subsequently, the clock signal CK[5] is set from the "L" level to the "H" level by a logic circuit not shown. As a result, the comparator CMP[5] starts the comparison operation.A comparator CMP[5] shifts from the level "L" to the level "H", for example, based on the magnitude relationship between the zero voltage and the voltage difference "INp-INn" between the differential input voltages INp and INn in the comparison operation of one of the digital signals Dp[5] and Dn[5]. Upon completion of the comparison operation, the comparator CMP[5] activates a clock signal CK[4].On the other hand, in the D / A converter CDAC, the charge of the capacitor Cp[5] or Cn[5] is redistributed to the "H" level in response to the shift of one of the digital signals Dp[5] and Dn[5]. Specifically, for example, through control logic not shown, one of the digital signals Dp[5] and Dn[5] shifts from the "L" level to the "H" level, while the other shifts from the "H" level to the "L" level. Consequently, one of the differential input nodes NinP and NinN is electrically charged / discharged to add / subtract a predetermined voltage "Vref" to / from the differential input voltages INp and Inn, in other words, the voltage difference "INp-INn". Note that the amount of "Vref" is regulated by the capacitance values of the dummy capacitors CpD and CnD.While the differential input voltages INp and INn are updated as described above, the comparator CMP[4] starts the comparison operation in response to the activation of the clock signal CK[4]. The comparator CMP[4] shifts from the level "L" to the level "H" based on the magnitude relationship between the zero voltage and the voltage difference "INp-INn" in the comparison operation of one of the digital signals Dp[4] and Dn[4]. When the comparison operation is completed, the comparator CMP[4] then activates a clock signal CK[3].In contrast, in the D / A converter CDAC, charges in the capacitors Cp[4] and Cn[4] are redistributed to the level "H" in response to the shift of one of the digital signals Dp[4] and Dn[4]. Specifically, one of the digital signals Dp[4] and Dn[4] shifts from the level "L" to the level "H", while the other shifts from the level "H" to the level "L". Consequently, a predetermined voltage "Vref / 2" is added / subtracted from the differential input voltages INp and Inn, in other words, the voltage difference "INp-Inn".Subsequently, the same processing is successively performed in the order up to the comparator CMP[0] while the predetermined voltage is successively changed to "Vref / 4", "Vref / 8",.... The comparator CMP[0] outputs the digital signals Dp[0] and Dn[0] in the comparison operation, and activates a clock signal CKfin when the comparison operation is completed. Here, as shown in FIG. 3, the clock signal CKfinis input to a flip-flop circuit FFedprovided in addition to the voltage quantization circuit QCT. The flip-flop circuit FFed outputs a conversion end signal CED by latching the clock signal CKfin in response to the sampling clock signal CKs.The conversion end signal CED indicates whether the conversion operation by the analog / digital converter ADC has been successfully completed. That is, the conversion operation has been successfully completed when the conversion end signal CED is activated, in other words, at the time of shifting to the level "H" in this example. The analog input voltages VAp and VAn are resampled in response to the sampling clock signal CKs. Further, the clock signals CK[5] to CK[0] and CKfin are negated to the level "L", and the digital signals Dp[1] to Dp[5] and Dn[1] to Dn[5] are reset to the initial values.< Of Comparator>FIG. 5A is a circuit diagram showing an exemplary configuration of each comparator of FIG. 2A. FIG. 5A shows an n-channel comparator CMPn including n-channel transistors serving as initial input transistors (first and second input transistors). The comparator CMPn shown in FIG. 5A is also referred to as a dynamic comparator and operates in synchronism with a positive-side clock signal CKp[i] at low power consumption.The comparator CMPn includes an amplifier circuit AMPn, a latch circuit unit LTUn, and an OR gate OR 1. The amplifier circuit AMPn differentially amplifies the differential input voltages INp and INn. The latch circuit unit LTUn outputs a positive-side digital signal Dp[i] and a negative-side digital signal Dn[i] by latching an output signal from the amplifier circuit AMPn. The OR gate OR 1 generates a next positive-side clock signal CKp[i-1] by performing an OR operation on the digital signals Dp[i] and Dn[i].Specifically, the amplifier circuit AMPn includes nMOS transistors MNOa, MN0b and MN1, and pMOS transistors MP0a and MP0b. The nMOS transistors MNOa and MNOb are initial input transistors (first and second input transistors) forming a differential pair. The positive-side / negative-side differential input voltage INp / INn is input to the nMOS transistors MN0a / MN0b, respectively.In a period in which the clock signal CKp[i] is at the level "L", the pMOS transistors MP0a and MP0b precharge the initial output nodes N0n and NOp serving as drains of the nMOS transistors MN0a and MNOb to a power voltage VDD. In a period in which the clock signal CKp[i] is at the "H" level, the nMOS transistor MN1 connects the sources of the nMOS transistors MNOa and MN0b to a ground power voltage GND to activate the amplifier circuit AMPn.The latch circuit unit LTUn includes the nMOS transistors MN2a, MN3a, MN2b and MN3b, the pMOS transistors MP2a and MP2b, and a CMOS latch circuit CLT. The CMOS latch circuit CLT includes a CMOS inverter IVa consisting of a pMOS transistor MP4a and an nMOS transistor MN4a, and a CMOS inverter IVb consisting of a pMOS transistor MP4b and an nMOS transistor MN4b.The input of one of the CMOS inverters IVa and IVb is connected to the output of the other. That is, a latch node N 1 pthat serves as an output node of the CMOS inverter IVa also serves as an input node of the CMOS inverter IVb. Similarly, a latch node N1n serving as an output node of the CMOS inverter IVb also serves as an input node of the CMOS inverter IVa. The positive-side digital signal Dp[i] is output to the latch node N 1 p, and the negative-side digital signal Dn[i] is output to the latch node N 1 n.The pMOS transistor MP2a and the nMOS transistor MN2a constitute a CMOS inverter. A negative-side output signal at the output node N 0 nis input to the CMOS inverter, and a high-potential-side power voltage of the CMOS inverter IVa in the CMOS latch circuit CLT is defined according to the input level. Similarly, the pMOS transistor MP2b and the nMOS transistor MN2b constitute a CMOS inverter. A positive-side output signal at the output node NOp is input to the CMOS inverter, and a high-potential-side power voltage of the CMOS inverter IVb in the CMOS latch circuit CLT is defined according to the input level.A negative side output at the output node N0n is input to the nMOS transistor MN3a, while a positive side output at the output node NOp is input to the nMOS transistor MN3b. The nMOS transistor MN3a connects the latch node N1p to the ground power voltage GND when it receives the level "H" as its input. Similarly, nMOS transistor MN3b connects latch node N1n to ground power voltage GND when it receives level "H" as its input.The operations performed by the comparator CMPn as described above are classified into an operation in a reset period in which the clock signal CKp[i] is at the level "L" and an operation in a comparison period after the clock signal CKp[i] changes from the level "L" to the level "H". In the reset period, the nMOS transistor MN1 is off while the pMOS transistors MP0a and MP0b are on, and therefore both output nodes NOn and NOp are precharged to the level "H". Accordingly, the nMOS transistors MN3a and MN3b are turned on, and therefore both the digital signals Dp[i] and Dn[i] are at the level "L". The clock signal CKp[i-1] output from the OR gate OR1 is also at the level "L".In the comparison period after this period, the nMOS transistor MN1 is turned on, while the pMOS transistors MPOa and MPOb are turned off. As a result, in the amplifier circuit AMPn, the differential amplification by the input transistors (MNOa and MN0b) serving as the differential pair is performed according to the voltage difference "INp-INn" between the differential input voltages INp and INn. For example, in the case of "INp>INn", the potential of the output node NOn falls from the level "H" to the level "L" more rapidly than the potential of the output node NOp.Consequently, the CMOS inverter IVa in the CMOS latch circuit CLT is supplied with the power voltage VDD as a high potential side power voltage through the CMOS inverter comprised of the pMOS transistor MP2a and the nMOS transistor MN2a. On the other hand, the CMOS inverter IVb in the CMOS latch circuit CLT is supplied with the ground power voltage GND as a high-potential side power voltage through the CMOS inverter consisting of the pMOS transistor MP2b and the nMOS transistor MN2b.As a result, the pMOS transistor MP4a is turned on and the digital signal Dp[i] at the latch node N1p changes from the level "L" to the level "H". On the other hand, in the CMOS latch circuit CLT, the ground power voltage GND is supplied as the high-potential-side power voltage to the CMOS inverter IVb, and thus the digital signal Dn[i] at the latch node N 1 nis maintained at the level "L". The clock signal CKp[i-1] output from the OR gate OR1 is set to the "H" level when the digital signal Dp[i] changes to the "H" level, in other words, at the time of completion of the comparison operation.FIG. 5B is a circuit diagram showing an exemplary configuration of each comparator different from that in FIG. 5A. In contrast to FIG. 5A, FIG. 5B shows a p-channel comparator CMPp having p-channel transistors as initial input transistors (which are a second or a first input transistor). In contrast to FIG. 5A, the comparator CMPp illustrated in FIG. 5B operates in synchronization with a negative-side clock signal CKn[i].The comparator CMPp includes an amplifier circuit AMPp, a latch circuit unit LTUp, and an AND gate AD 1. The amplifier circuit AMPp and the latch circuit unit LTUp are formed similarly to FIG. 5A. The AND gate AD 1 generates a next negative-side clock signal CKn[i-1] by performing an AND operation on the digital signals Dp[i] and Dn[i] output from the latch circuit unit LTUp.Specifically, the amplifier circuit AMPp and the latch circuit unit LTUp are configured such that the power voltage VDD and the ground power voltage GND are interchanged while the nMOS transistors and the pMOS transistors are interchanged in the configuration of FIG. 5A. Accordingly, the amplifier circuit AMPp includes pMOS transistors MP5a, MP5b and MP6 and nMOS transistors MN5a and MN5b. The pMOS transistor MP5a or MP5b is an initial input transistor (second or first input transistor) forming a differential pair. The positive-side / negative-side differential input voltage INp / INn are input to the pMOS transistors MP5a / MP5b, respectively.The nMOS transistors MN5a and MN5b precharge the initial output nodes N5n and N5p to the ground voltage GND in a period in which the clock signal CKn[i] is at the level "H", in other words, in a period in which the clock signal CKp[i] is at the level "L". The pMOS transistor MP 6 connects the sources of the pMOS transistors MP 5 aand MP 5 bto the power voltage VDD to activate the amplifier circuit AMPp in a period in which the clock signal CKn[i] is at the level "L", in other words, in a period in which the clock signal CKp[i] is at the level "H".The latch circuit unit LTUp includes pMOS transistors MP7a, MP8a, MP7b and MP8b, nMOS transistors MN7a and MN7b, and a CMOS latch circuit CLT. The CMOS latch circuit CLT includes a CMOS inverter IVa consisting of a pMOS transistor MP9a and an nMOS transistor MN9a, and a CMOS inverter IVb consisting of a pMOS transistor MP9b and an nMOS transistor MN9b.A latch node N 6 pserving as an output node of the CMOS inverter IVa also serves as an input node of the CMOS inverter IVb. Similarly, a latch node N6n serving as an output node of the CMOS inverter IVb also serves as an input node of the CMOS inverter IVa. A positive-side digital signal Dp[i] is output to the latch node N6p, while a negative-side digital signal Dn[i] is output to the latch node N6n.The pMOS transistor MP7a and the nMOS transistor MN7a constitute a CMOS inverter. A negative-side output signal at the output node N 5 nis input to the CMOS inverter, and a low-potential-side power voltage of the CMOS inverter IVa in the CMOS latch circuit CLT is defined according to the input level. Similarly, the pMOS transistor MP7b and the nMOS transistor MN7b constitute a CMOS inverter. A positive-side output signal at the output node N 0 pis input to the CMOS inverter, and a low-potential-side power voltage of the CMOS inverter IVb in the CMOS latch circuit CLT is defined according to the input level.A negative side output at the output node N5n is input to the pMOS transistor MP8a, while a positive side output at the output node N5p is input to the pMOS transistor Mp8b. The pMOS transistor MP8a connects the latch node N6p to the power voltage VDD when it receives the level "L" as its input. Similarly, pMOS transistor MP8b connects latch node N6n to power voltage VDD when it receives level "L" as its input.The operations of the comparator CMPp of FIG. 5B are almost identical to those of the comparator CMPn of FIG. 5A. Differences between them are that both digital signals Dp[i] and Dn[i] are at level "H" in the reset period. In the comparison period, one of the digital signals Dp[i] and Dn[i] changes from the level "H" to the level "L". Accordingly, the negative clock signal CKn[i-1] output from the AND gate AD1 is activated from the level "H" to the level "L". In other words, the positive clock signal CKp[i-1] is activated from the level "L" to the level "H" similarly to the case of FIG. 5A.< Of Voltage Quantization Circuit>For example, the UWB must process a signal having a frequency band of about 500 MHz. Therefore, in the analog / digital converters ADC of FIG. 1, a high conversion speed of, for example, 1 GS / s or more is required. Such a requirement for the conversion speed can be ideally satisfied using the voltage quantization circuit QCT as shown in FIG. 2A. However, in fact, there is a risk that the high speed is prevented due to the influence of the common mode voltage of the differential input voltages.FIGS. 17A and 17B are schematic diagrams showing an exemplary problem when the voltage quantization circuit of FIG. 2A is simply used. FIG. 17A shows an exemplary operation in a case where all the comparators CMP[ 0] to CMP[ 5] in the voltage quantization circuit QCT are composed of p-channel comparators CMPp of FIG. 5B. In contrast, FIG. 17B shows an exemplary operation in a case where all the comparators CMP[ 0] to CMP[ 5] in the voltage quantization circuit QCT are composed of n-channel comparators CMPn of FIG. 5A.As illustrated in FIG. 17A, when only the p-channel comparators CMPp are used, the common mode voltage of the differential input voltages is increased by the amplifier circuit AMPp in the comparator CMPp for each comparison operation. Specifically, the electric current output from the power voltage VDD flows to the pMOS transistors MP5a and MP5b in response to the negative side clock signal CKn being shifted to the level "L" via the pMOS transistor MP6. As a result, step-up kickback phenomena may be caused in the differential input voltages INp and INn via a gate-source capacitance or a gate-drain capacitance of the pMOS transistors MP 5 aand MP 5 b. The common mode voltage is defined by "(INp+INn) / 2".On the other hand, as illustrated in FIG. 17B, when only the n-channel comparators CMPn are used, the common mode voltage of the differential input voltages is decreased by the amplifier circuit AMPn in the comparator CMPn for each comparison operation. Specifically, the electric current output from the drains of the nMOS transistors MN0a and MN0b precharged with the power voltage VDD flows to the ground power voltage GND in response to the shift of the positive side clock signal CKp to the level "H" via the nMOS transistor MN1. As a result, step-down kickback phenomena may be caused in the differential input voltages INp and INn via a gate-source capacitance or a gate-drain capacitance of the nMOS transistors MNOa and MNOb.FIG. 18 is a schematic diagram showing an exemplary relationship between the common mode voltage of the differential input voltages and the comparison time in the voltage quantization circuit of FIG. 2A. The lower the common mode voltage, the higher the driving capability of the pMOS transistors MP5a and MP5b serving as input transistors in the amplifier circuit AMPp, and the higher their operation speed. On the other hand, the higher the common mode voltage, the higher the driving capability of the nMOS transistors MNOa and MNOb serving as input transistors in the amplifier circuit AMPn, and the higher their operation speed.As a result, as shown in FIG. 18, the comparison time of the comparators CMPp and CMPn largely depends on the common mode voltage. In particular, the comparator CMPp's comparison time is exponentially longer the higher the common mode voltage, as indicated by property 10p. On the other hand, the lower the common mode voltage, the exponentially longer the comparison time of the comparator CMPn, as indicated by characteristic 10n. Therefore, when only comparators of one type are used, there is a risk of an excessively long comparison time due to the increased or decreased common mode voltage as shown in FIG. 17A or 17B.FIG. 19 is a schematic diagram illustrating an exemplary operation in a case of the devised configuration of the group of comparators in the voltage quantization circuit of FIG. 2A. FIG. 19 shows an exemplary operation in a case where p-channel comparators CMPp and n-channel comparators CMPn are alternately arranged as the comparators CMP[5] to CMP[0] in the voltage quantization circuit QCT. Since the p-channel comparators CMPp and the n-channel comparators CMPn are alternately arranged as described above, the variation of the common mode voltage can be compensated. Consequently, an excessively long comparison time can be prevented.The voltage quantization circuit QCT of FIG. 2A is a system in which the plurality of comparators CMP[5] to CMP[0] are successively operated. Thus, the conversion time of the ADC is occupied by the comparison time of the comparators CMP[5] to CMP[0]. The use of the system of FIG. 19 may suppress the variations of the common mode voltage to some extent and therefore may prevent the phenomenon of the excessively long comparison time and ultimately the excessively long conversion time of the ADC. However, in order to further reduce the conversion time of the ADC, the initial value of the common mode voltage provided before starting the series of comparison operations is important in addition to suppressing the variation of the common mode voltage due to the comparison operations.FIGS. 20A and 20B are diagrams for explaining the influence of the initial value of the common mode voltage on the assumption of the system of FIG. 19. That is, as shown in FIG. 20B, assuming the system of FIG. 19, there is a common mode voltage having the shortest comparison time. The suitable range 11 is a range in which the common mode voltage having the shortest comparison time is centered and in which the comparison time is at a target value or less. Moreover, the appropriate region 11 is a region around the intersection between the two characteristics 10 nand 10 pin FIG. 16.FIG. 21 is a timing chart showing an exemplary operation of the voltage quantization circuit in a case where the common mode voltage is unsuitable in FIGS. 20A and 20B. In contrast to FIG. 4, in the example of FIG. 21, the clock signal CK[ 0] of the last comparator CMP[ 0] is not activated due to the increase in the comparison time. Accordingly, the conversion end signal CED is not activated either. That is, the conversion operation of the analog / digital converter ADC is not completed within the period of the sampling clock signal CKs.As described above, even if the variation of the common mode voltage of the differential input voltages is suppressed, if the initial value of the common mode voltage is insufficient, there is a risk that the speed of the ADC is not sufficiently increased. When only one of the two types of comparators CMPp and CMPn is used, the appropriate common mode voltage can be easily generated. That is, the common mode voltage needs to be low when only the p-channel comparators CMPp are used, and high when only the n-channel comparators CMPn are used. However, when both kinds of comparators CMPp and CMPn are used as shown in FIG. 19, the appropriate common mode voltage cannot be easily generated.One of the reasons for this is that the suitable range 11 of the common mode voltage is narrow. Another reason is that the common mode voltage is basically defined by an external circuit of the analog / digital converter ADC, for example the filter unit FLTU in the example of FIG. 1. In this case, the external circuit of the analog / digital converter ADC must be regulated to generate the appropriate common mode voltage in the analog / digital converter ADC. As a result, the configuration of the semiconductor device may be complicated. Therefore, the use of the following system according to the embodiment is advantageous.<Schematische Configuration of Analog / Digital Conversion Unit>FIG. 6 is a circuit block diagram showing an exemplary schematic configuration of the analog / digital conversion unit of FIG. 1. The analog / digital conversion unit ADCU of FIG. 6 comprises an analog / digital converter ADC and a correction code decision circuit CDCT. The analog / digital converter ADC includes a common mode voltage regulator circuit CMCT in addition to the voltage quantization circuit QCT illustrated in FIGS. 2A and 3.The voltage quantization circuit QCT converts the differential input voltages INp and INn for each sampling period based on the sampling clock signal CKs into m-bit digital signals such as 6-bit digital signals Dp[5:0] and Dn[5:0]. Then, the voltage quantization circuit QCT activates the conversion end signal CED when the conversion operation is completed.The correction code decision circuit CDCT is connected to the voltage quantization circuit QCT and receives the conversion end signal CED as an input from the voltage quantization circuit QCT. It should be noted that the term "connection" described in the specification denotes not only a physical connection but also an electrical connection. Based on the conversion end signal CED, the correction code decision circuit CDCT decides a plurality of bits for correcting the common mode voltage of the differential input voltages INp and INn, such as a 4-bit correction code CAL_CD[3:0] in this example.Schematically, the correction code decision circuit CDCT changes the correction code CAL_CD[3:0] at this time when a sampling period in which the conversion end signal CED is not activated, in other words, a sampling period in which the conversion operation is not completed, is detected. Then, the correction code decision circuit CDCT successively changes the correction code CAL_CD[3:0] until the sampling period in which the conversion end signal CED is not activated is detected.The common mode voltage regulator circuit CMCT is connected to the correction code decision circuit CDCT and the voltage quantization circuit QCT. The common mode voltage regulator circuit CMCT adjusts the common mode voltage by adding or subtracting a corrected voltage to or from the differential input voltages INp and INn based on the correction code CAL_CD[3:0].< Of Common Mode Voltage Regulator Circuit>FIG. 7 is a diagram for explaining an exemplary operation of the common mode voltage regulator circuit of FIG. 6, for example, as illustrated in FIG. 7, the common mode voltage regulator circuit CMCT adds or subtracts a corrected voltage that is "M" ("M" is an integer of 1 to 7) times larger than a unit voltage ΔV on the basis of the value of the correction code CAL_CD[3:0] to or from the differential input voltages INp and Inn. In this example, it is defined by "1" / "0" of the correction code CAL_CD[3:0] whether the corrected voltage is to be added or subtracted. A magnitude "M×ΔV" of the corrected voltage is defined based on a value of a correction code CAL_CD[2:0]. For example, "M=1" is defined at "CAL_CD[2:0] = 001" and "M=7" is defined at "CAL_CD[2:0] = 111".FIG. 8A is a circuit diagram showing an exemplary configuration of the common mode voltage regulator circuit of FIG. 6. FIG. 8B is a timing diagram showing an example schematic operation of the control logic of FIG. 8A. The common mode voltage regulator circuit CMCT of FIG. 8A includes a plurality of capacitors Ccp[ 0] to Ccp[ 2] and Ccn[ 0] to Ccn[ 2] serving as correction capacitors and connected to the differential input nodes NinP and NinN. The common mode voltage regulator circuit CMCT also includes the control logic LGC for controlling these correction capacitors.Similar to the digital-to-analog converter CDAC, the common mode voltage regulator circuit CMCT schematically distributes the charges of the differential input nodes NinP and NinN by using a correction capacitor selected based on the correction code CAL_CD[2:0] among the plurality of correction capacitors. As a result, the common mode voltage regulator circuit CMCT adjusts the common mode voltage of the differential input voltages INp and INn. It should be noted that the common mode voltage regulator circuit may be not of the capacitor type but may be of the resistor type, for example. However, the capacitor type is preferably used in view of the consumed power and the like.One ends of the positive-side capacitors Ccp[ 0] to Ccp[ 2] are connected to the positive-side differential input node NinP. Common shift signals CSF[0] to CSF[2] are applied to the other ends of the capacitors Ccp[0] to Ccp[2], respectively. Similarly, the one ends of the negative-side capacitors Ccn[ 0] to Ccn[ 2] are connected to the negative-side differential input node NinN. The common shift signals CSF[0] to CSF[2] are also applied to the other ends of the capacitors Ccn[0] to Ccn[2], respectively.The capacitance values of the capacitors Ccp[0] to Ccp[2] differ by 2 k. for example. That is, both capacitors Ccp[0] and Ccn[0] have a capacitance value of "Cc". In this case, both capacitors Ccp[ 1] and Ccn[ 1] have a capacitance value of "2×Cc", and both capacitors Ccp[ 2] and Ccn[ 2] have a capacitance value of "4×Cc".The control logic LGC includes, for example, an exclusive NOR gate ENR1 and an AND gate AD2. The exclusive NOR gate ENR1 receives as its inputs an inverted sampling clock signal ( / CKs) and a correction code CAL_CD[3] for defining a sign of the corrected voltage, and outputs a trigger signal TG. The AND gate AD2 receives as its inputs the correction code CAL_CD[2:0] and the trigger signal TG, and outputs the common shift signals CSF[0] to CSF[2]. That is, the number of AND gates AD 2 is so high specifically for three bits.As shown in FIG. 8B, when the correction code CAL_CD[3] is "0", the exclusive NOR gate ENR1 outputs a decay trigger signal TG in response to a rise of the inverted sampling clock signal ( / CKs), in other words, a fall of the sampling clock signal CKs. When the correction code CAL_CD[0] is "1", the AND gate AD2 shifts the common shift signal CSF[0] from the "H" level to the "L" level in response to a drop of the trigger signal TG. Consequently, charges of the capacitors Ccp[0] and Ccn[0] are redistributed, and the unit voltage "ΔV" is subtracted from the common mode voltage, in other words, both differential input voltages INp and Inn, as shown in FIG. 7.On the other hand, when the correction code CAL_CD[3] is "1", the exclusive NOR gate ENR1 outputs a rise trigger signal TG in response to a rise of the inverted sampling clock signal ( / CKs). When the correction code CAL_CD[0] is "1", the AND gate AD2 shifts the common shift signal CSF[0] from the level "L" to the level "H" in response to a rise of the trigger signal TG. Consequently, the charges of the capacitors Ccp[0] and Ccn[0] are redistributed, and the unit voltage "ΔV" is added to the common mode voltage. Similarly, for example, when two common shift signals CSF[0] and CSF[1] are shifted to the level "H", "(1+2)×ΔV" is added to the common mode voltage.< Of Correction Code Decision Circuit>FIG. 9A is a flowchart showing an exemplary processing content of the correction code decision circuit of FIG. 6. FIG. 9B is a flowchart showing an example processing content different from that of FIG. 9A. The correction code decision circuit CDCT is implemented by, for example, a sequencer circuit or the like configured to perform the processes illustrated in FIG. 9A or FIG. 9B. The flow of FIG. 9A is executed in the foreground in a correction period included in a period in which the voltage quantization circuit QCT does not perform the normal operation. The correction period is included in, for example, an initial period of the voltage quantization circuit QCT resulting from the start-up of the semiconductor device DEV, a standby period of the voltage quantization circuit QCT, or the like.In FIG. 9A, the correction code decision circuit CDCT first resets the correction code CAL_CD[3:0] to zero (step S101). Subsequently, the correction code decision circuit CDCT causes the voltage quantization circuit QCT to sample the initial values such as "VAp - VAn = 0 V" of the external analog input voltages VAp and VAn to perform the conversion operation (step S102). The correction code decision circuit CDCT then holds information on whether the conversion end signal CED output from the voltage quantization circuit QCT has been activated or has remained negated, in other words, information on whether the conversion end signal CED is at the level "H" or the level "L" (step S103).Next, the correction code decision circuit CDCT determines whether the information of the conversion end signal CED has been kept preset "N" times ("N" needs to be an integer greater than or equal to 2) (step S 104). If the number of times is less than N (step S104: No), the correction code decision circuit CDCT returns to step S102 and repeatedly executes the processings in steps S102 and S103. On the other hand, when the frequency reaches N (step S104: Yes), the correction code decision circuit CDCT determines whether N pieces of information of the conversion end signal CED include one or more negation levels (step S105).If the information does not contain a level of negation (step S105: No), the correction code decision circuit CDCT fixes a current value as the value of the correction code CAL_CD[3:0]. On the other hand, if the information has a negation level (step S105: Yes), the correction code decision circuit CDCT increments the correction code CAL_CD[3:0] (by +1) (step S106). Then, the correction code decision circuit CDCT returns the processings to step S102 to detect the information of the conversion end signal CED again N times while the incremented correction code CAL_CD[3:0] is reflected on the common mode voltage regulator circuit CMCT.The value of the correction code CAL_CD[3:0] fixed in the case of "No" in step S105 is applied in the subsequent normal operation. Specifically, as can be seen from FIG. 8B, for example, the common mode voltage of the differential input voltages INp and INn is immediately regulated after the external analog input voltages VAp and VAn in the differential input nodes NinP and NinN are sampled in response to the sampling clock signal CKs.On the other hand, the flow of FIG. 9B is executed in the background in a period in which the voltage quantization circuit QCT performs the normal operation. In FIG. 9B, the correction code decision circuit CDCT first acquires the information as to whether the conversion end signal CED output from the voltage quantization circuit QCT has been activated or remains negated N times so as to be preset (N is to be an integer greater than or equal to 2) (step S 201). In other words, for each of the sampling periods, the correction code decision circuit CDCT confirms N times whether the conversion end signal CED has been activated.Subsequently, the correction code decision circuit CDCT determines whether one or more negation levels are included in the N information elements of the conversion end signal CED (step S202). If no negation level is included (step S202: No), the correction code decision circuit CDCT maintains the current value as the value of the correction code CAL_CD[3:0], and ends the processing. In this case, the flow of FIG. 9B is executed again as necessary.On the other hand, if an negation level is included (step S202: Yes), the correction code decision circuit CDCT determines whether the correction code CAL_CD[3:0] has reached the maximum value, for example, "1111" (step S203). When the maximum value has been reached (step S203: Yes), the correction code decision circuit CDCT resets the value of the correction code CAL_CD[3:0] to the minimum value, for example, "0000", and proceeds to the processing in step S201 (step S204).If the maximum value has not been reached in step S203 (No), the correction code decision circuit CDCT increments the correction code CAL_CD[3:0] (by +1) (step S205). Then, the correction code decision circuit CDCT returns to step S 201 to re-acquire the information of the conversion transmission signal CED N times while the increased correction code CAL_CD[3:0] is reflected on the common mode voltage regulator circuit CMCT.FIGS. 10A and 10B are diagrams each showing an exemplary result of the correction code determined using the flow of FIG. 9A or 9B. Similarly to the case of FIG. 7, FIGS. 10A and 10B show an exemplary relationship between the value of the correction code CAL_CD[3:0] and the regulated common mode voltage value, which is a corrected voltage. As shown in FIG. 20A and others, the common mode voltage and ultimately the regulated common mode voltage value have the appropriate range 11. The appropriate range 11 is on the positive side in FIG. 10A and on the negative side in FIG. 10B with respect to the initial value of the common mode voltage.When the common mode voltage is within the appropriate range 11, the conversion end signal CED is always activated for each sampling period. On the other hand, the conversion end signal CED may not be activated for each sampling period when the common mode voltage is not within the appropriate range 11. When the correction code CAL_CD[3:0] is successively changed until the conversion end signal CED is always activated, the value of the correction code CAL_CD[3:0] is decided as soon as the regulated common mode voltage value is within the appropriate range 11 as shown in FIG. 10A or 10B.As described above, using the procedures of FIGS. 9A and 9B, the common mode voltage can be regulated to be within the appropriate range 11 in both foreground and background. Consequently, the comparison time of the comparators CMP[5] to CMP[0] can be reduced and the speed of the voltage quantization circuit QCT and ultimately the A / D converter ADC can be increased. In particular, the common mode voltage is regulated in the background, and therefore the regulation can be performed in real time even in response to changes in an operating state such as voltage or temperature during normal operation.Since this is the system for monitoring the conversion speed of the analog / digital converter ADC using the conversion transmission signal CED and regulating the common mode voltage based on the monitoring result, there is no need to additionally provide, for example, a common mode voltage detector circuit and the like, and the excessive circuit area or the like can be suppressed. Moreover, the common mode voltage can be regulated in the analog / digital conversion unit ADCU, and thus the limitation of the common mode voltage in the external circuits configured to output the analog input voltages VAp and VAn can be mitigated. Consequently, the design of the semiconductor device DEV including the external circuits can be facilitated and the versatility of the analog / digital converter ADC can be improved.Note that the flow of FIG. 9A or 9B is not limited to the illustrated examples, and may be modified as appropriate. For example, the flow of FIG. 9A may be modified such that, for example, an intermediate value is adopted as a decision code, the intermediate value belonging to the respective values of the correction code CAL_CD[3:0] corresponding to the upper limit and the lower limit of the appropriate range 11 illustrated in FIG. 10A, and detected based on the conversion end signal CED. Alternatively, the flow of FIG. 9A may be modified to be a flow using binary search, for example.< Of Comparator Group>FIG. 11A is a circuit diagram showing an exemplary configuration of a comparator group of FIG. 6. In FIG. 11A, the p-channel comparators and the n-channel comparators are alternately connected similarly to FIG. 19. In this example, the comparators CMP[5], CMP[3], and CMP[1] shown in FIG. 6 are composed of the p-channel comparators CMPp[5], CMPp[3], and CMPp[1] shown in FIG. 5B. On the other hand, the comparators CMP[4], CMP[2], and CMP[0] shown in FIG. 6 are composed of the n-channel comparators CMPn[4], CMPn[2], and CMPn[0] shown in FIG. 5A.FIG. 11B is a circuit diagram for explaining various modification examples of FIG. 11A. As illustrated in FIG. 11B, the group of comparators may be configured such that the p-channel comparators CMPp and the n-channel comparator CMPn connected in parallel to the differential input nodes NinP and NinN perform the predetermined output via the logic gate LG. Alternatively, the p-channel comparators CMPp and the n-channel comparators CMPn are not always alternately switched, and only the comparators of one type may be sequentially switched. Actually, the number of the p-channel comparators CMPp and the number of the n-channel comparators CMPn constituting the group of comparators are defined to be equal to some extent.< Instruction of Correction Code Decision Circuit>FIGS. 12A and 12B are diagrams each showing a method of generating the sampling clock signal in FIG. 6 and an exemplary operation timing of the correction code decision circuit in the method. In FIG. 12A, a sampling clock generator circuit CKSG is provided in the analog / digital converter ADC. The sampling clock generating circuit CKSG receives a master clock signal CKm as an input / output signal from the outside and generates a sampling clock signal CKs of 1 GHz, 2 GHz, or the like by, for example, thinning out the sampling clock generating circuit CKSG as illustrated in FIG. 12B.At a rising edge of the sampling clock signal CKs, the flip-flop circuit FFed latches the clock signal CKfin output from the comparator CMP[ 0] and outputs the conversion end signal CED. On the other hand, at the rising edge of the sampling clock signal CKs, the clock signal CKfin of the activation level is negated. The flip-flop circuit FFed may latch and hold the clock signal CKfin of the activation level before the negation as the conversion end signal CED.The correction code decision circuit CDCT receives the conversion end signal CED held as described above as input. The correction code decision circuit CDCT is supplied with the master clock signal CKm as shown in Fig. 12A. As a result, the correction code decision circuit CDCT, as illustrated in FIG. 12B, may detect the conversion end signal CED at, for example, a leading edge of the master clock signal CKm caused immediately after the sampling clock signal CKs. Consequently, the correction code decision circuit CDCT at the early stage may reflect the information of the conversion end signal CED to decide the value of the correction code CAL_CD[3:0].<Haupt Effects of First Embodiment>As described above, using the system according to the first embodiment, the correction code CAL_CD[3:0] can be decided using the conversion end signal CED, and the common mode voltage of the differential input voltages INp and INn can be regulated in the foreground or the background based on the decided correction code. Consequently, typically, the comparison time of each comparator can be reduced and the speed of the analog / digital converter ADC can be increased. In particular, even the change of the operating state such as voltage or temperature can be handled immediately by the regulation in the background, and the high-speed operations of the ADC can be maintained.(Second Embodiment)<Schematische Configuration of Analog / Digital Conversion Unit>FIG. 13 is a circuit block diagram showing an exemplary schematic configuration of the analog / digital conversion unit of FIG. 1 in a semiconductor device according to a second embodiment. The analog / digital conversion unit ADCU of FIG. 13 is different from that in the exemplary configuration of FIG. 6 in that capacitors Csp and Csn, which are the sampling capacitors, and switches SW 1 and SW 2 are added in a voltage quantization circuit QCTa.One of the two electrodes of the capacitor Csp is connected to the sampling switch SSW, while the other of the two electrodes is connected to the positive-side differential input node NinP. Similarly, one of the two electrodes of the capacitor Csn is connected to the sampling switch SSW, while the other of the two electrodes is connected to the negative-side differential input node NinN. The switch SW 1 is connected to the differential input nodes NinP and NinN, and applies a predetermined power voltage VC to the differential input nodes NinP and NinN when turned on. The switch SW2 short-circuits the electrodes of the two capacitors Csp and Csn, which electrodes are closer to the sampling switch SSW when it is turned on.The sampling switch SSW and the switch SW1 are controlled to be turned on in the sampling period. Consequently, the analog input voltages VAp and VAn are sampled in the capacitors Csp and Csn, respectively. In the comparison period after the period, the sampling switch SSW and the switch SW 1 are controlled to be turned off, and the switch SW 2 is instead controlled to be turned on. Consequently, the charges of the capacitors Csp and Csn in the capacitors are redistributed in the D / A converter CDAC.As described in the first embodiment, the predetermined voltage "Vref" of the D / A converter CDAC is regulated by the capacitance values of the dummy capacitors CpD and CnD of FIG. 2B. In particular, the larger the capacitance values of the dummy capacitors CpD and CnD, the smaller the predetermined voltage "Vref". When the predetermined voltage "Vref" is small, the dynamic range of the ADC is narrowed and the system may not be applicable to, for example, the analog input voltages VAp and VAn having large differential amplitudes.Further, in the system according to the second embodiment, as illustrated in FIG. 8A, the capacitors Ccp[ 0] to Ccp[ 2] and Ccn[ 0] to Ccn[ 2] in the common mode voltage regulator circuit CMCT are connected to the differential input nodes NinP and NinN. The capacitors Ccp[ 0] to Ccp[ 2] and Ccn[ 0] to Ccn[ 2] can be equivalently regarded as the other of the dummy capacitors CpD and CnD. Consequently, the predetermined voltage "Vref" can be made smaller and the dynamic range of the ADC can be made narrower.In such a state, for example, the sampling is performed in the upper plates of the capacitors in the DDAC of FIG. 2B, and therefore the voltage quantization circuit QCT of FIG. 6 is also referred to as an upper plate type. In the top plate type, the differential input voltages INp and INn at the early stage of the comparison period are equal to the analog input voltages VAp and VAn. Therefore, the capacitance values of the capacitors Ccp[ 0] to Ccp[ 2] and Ccn[ 0] to Ccn[ 2] in the common mode voltage regulator circuit CMCT may be limited to maintain the dynamic range of the ADC.On the other hand, since the sampling is performed in the lower plates of the capacitors CsP and Csn, the voltage quantization circuit QCTa of FIG. 13 is also referred to as a sub-plate type. In the sub-plate type, the larger the capacitance values of the dummy capacitors CpD and CnD and the capacitors Ccp[0] to Ccp[2] and Ccn[0] to Ccn[2] in the common mode voltage regulator circuit CMCT, the smaller the differential input voltages INp and INn at the early stage of the comparison period. Thus, for example, even when the capacitance values of the capacitors Ccp[ 0] to Ccp[ 2] and Ccn[ 0] to Ccn[ 2] are large, the dynamic range of the ADC can be secured.<Haupt Effects of Second Embodiment>Also by using the system according to the second embodiment, similar effects to various effects of the first embodiment, namely, typically, the high speed of the ADC can be obtained. Unlike the system according to the first embodiment, the limitation of the capacitance values of the capacitors Ccp[ 0] to Ccp[ 2] and Ccn[ 0] to Ccn[ 2] in the common mode voltage regulator circuit CMCT can be alleviated, thereby simplifying the configuration. Moreover, the dynamic range of the ADC can be easily secured.(Third Embodiment)< Of Comparator Group>FIG. 14 is a circuit diagram showing an exemplary configuration of a group of comparators of FIG. 6 or 13 in a semiconductor device according to a third embodiment. In contrast to FIG. 11A, in FIG. 14, all comparators CMP[0] to CMP[5] consist of n-channel comparators CMPn[0] to CMPn[5]. Moreover, in this example, the input transistors are different between the comparators CMPn[5] to CMPn[3] deciding the most significant bits of the digital signal and operating in the former period of the successive comparison and the comparators CMPn[2] to CMPn[O] deciding the least significant bits of the digital signal and operating in the latter period of the successive comparison.Specifically, a gate width W1 of the nMOS transistors MN0a and MNOb serving as input transistors in the comparators CMPn[5] to CMPn[3] is designed to be smaller than a gate width W2 of the nMOS transistors MN0a and MN0b serving as input transistors in the comparators CMPn[2] to CMPn[0]. Note that all the comparators CMP[0] to CMP[5] may be composed of the p-channel comparators CMPp[0] to CMPp[5] instead of the n-channel comparators. Also in this case, the relationship between the gate widths is the same as that of the n-channel comparators.FIG. 15 is a schematic diagram showing an exemplary transition of the differential input voltage of FIG. 6 or 13 in the semiconductor device according to the third embodiment. As illustrated in FIG. 15, the voltage difference |INp-INn| between the differential input voltages INp and INn is updated by the D / A converter CDAC each time the comparison operation is completed, and is gradually decreased. Thus, increasing the speed of the comparison operation at the early stage and increasing the accuracy of the comparison operation at the late stage, more specifically, reducing the noise, are efficient in terms of a balance between the speed and the accuracy.FIG. 16 is a timing diagram showing an example change in common mode voltage by the group of comparators of FIG. 14. As shown in FIG. 16, the common mode voltage gradually decreases with the use of the n-channel comparators CMPn every time the comparison operation is performed. In contrast to the first embodiment, by actively utilizing this reduction in the common mode voltage, both the speed increase and the accuracy increase can be achieved. That is, as illustrated in FIG. 16, a suitable range 15 aof the common mode voltage for the speed is present in a relatively high range, and a suitable range 15 bof it for the accuracy is present in a relatively low range. Thus, the high speed can be achieved in the initial comparison operations, and then the common mode voltage is gradually decreased, so that the high speed is suppressed but the high accuracy is achieved.However, the common mode voltage must be kept within the appropriate range to balance the speed and accuracy. Therefore, it is desirable to properly define the initial value of the common mode voltage. In particular, it is desirable to appropriately define the initial value of the common mode voltage to have a characteristic shown by a solid line in FIG. 16. That is, as is apparent from a characteristic illustrated with a broken line in FIG. 16, the accuracy may not be sufficient if the initial value of the common mode voltage is too high, and the speed may not be sufficient if the initial value of the common mode voltage is too low.In order to properly define the initial value of the common mode voltage, the correction code decision circuit CDCT and the common mode voltage regulator circuit CMCT may be provided similarly to those of the first embodiment. As is apparent from FIG. 16, when using the n-channel comparators CMPn, the common mode voltage can be found, which has, for example, the lower limit that can satisfy the appropriate range 15 afor the speed. Similarly, by using the p-channel comparators CMPp, the common mode voltage can be found, which has, for example, the upper limit that can satisfy the appropriate range for the speed.In the example of FIG. 16, the gate widths W 1 and W 2 are made different to achieve a difference "W 1<W 2" to more effectively balance between the speed and the accuracy. In particular, with a small gate width, high speed operation is achieved while noise is large, and finally high accuracy is made difficult. On the other hand, with a large gate width, high speed operation is made difficult, while the noise is small and high accuracy is finally obtained. With a small gate width, the suitable common mode voltage is relatively high. With a large gate width, the common mode voltage is relatively low.<Haupt Effects of Third Embodiment>Also by using the system according to the third embodiment, similar effects to various effects of the first embodiment can be obtained, which typically means the high speed of the ADC. Moreover, the system according to the third embodiment can suppress the excessively high speed and achieve the high accuracy of the ADC by the degree of suppression.In the above, the invention of the inventors of the present application has been concretely described based on the embodiments. However, it is needless to say that the present invention is not limited to the above embodiments, and various modifications may be made within the scope of the present invention.References included in the specificationThis list of documents cited by the applicant has been produced in an automated manner and is only included for the better information of the reader. The list is not part of the German patent application or utility model application. The DPMA does not take any adhesion for any faults or omissions.Patent Literature citedJP 2023-174228

[0001] Cited Non-Patent LiteratureSingle Channel, 1.25-GS / s, 6-bit, Loop-Unrolled Asynchronous SAR ADC in 40 nm-COM", IEEE CICC 2010, Tao Jiang, and four more

[0004]

Claims

A semiconductor device comprising: a voltage quantization circuit that converts differential input voltages to be applied to differential input nodes into a digital signal having a plurality of bits for each sampling period and outputs a conversion transmission signal when a conversion operation is completed; a correction code decision circuit that is electrically connected to the voltage quantization circuit and receives the conversion transmission signal as its input output from the voltage quantization circuit; and a common mode voltage regulator circuit that is electrically connected to the correction code decision circuit and the voltage quantization circuit, wherein the voltage quantization circuit comprises: a first comparator that includes a first input transistor that receives the differential input voltages as its input and defines a value of a first bit of the digital signal; A second comparator comprising a second input transistor that receives the differential input voltages as an input and is different from the first input transistor and defines a value of a second bit of the digital signal, wherein the correction code decision circuit decides a correction code for correcting the common mode voltage of the differential input voltages based on the conversion end signal output from the voltage quantization circuit, and the common mode voltage regulator circuit adjusts the common mode voltage by adding or subtracting a corrected voltage to or from the differential input voltages based on the correction code.The semiconductor device according to claim 1, wherein the voltage quantization circuit further comprises: a sampling switch that samples an external analog input voltage for the differential input nodes; and a digital / analog converter that updates the differential input voltages by adding or subtracting a predetermined voltage to or from the differential input voltages according to the value of the first bit, and the second comparator receives the differential input voltages updated by the digital / analog converter as its input.The semiconductor device according to claim 1, wherein the correction code decision circuit changes the correction code when detecting the sampling period in which the conversion transmission signal is not activated.The semiconductor device according to claim 3, wherein the correction code decision circuit changes the correction code until it does not detect the sampling period in which the conversion transmission signal is not activated.The semiconductor device according to claim 3, wherein the correction code decision circuit and the common mode voltage regulator circuit operate in the background in a period in which the voltage quantization circuit performs a normal operation.The semiconductor device according to claim 5, wherein the correction code decision circuit and the common mode voltage regulator circuit operate by causing the voltage quantization circuit to sample an initial value of an external analog input voltage in a correction period included in a period in which the voltage quantization circuit does not perform the normal operation.The semiconductor device according to claim 2, wherein the common mode voltage regulator circuit comprises a plurality of correction capacitors electrically connected to the differential input nodes, and regulates the common mode voltage by redistributing charges of the differential input nodes using a correction capacitor, which is defined based on the correction code, among the plurality of correction capacitors.The semiconductor device according to claim 1, wherein one of the first input transistor and the second input transistor is a p-channel transistor, while the other of the first input transistor and the second input transistor is an n-channel transistor.The semiconductor device of claim 2, wherein each of the first input transistor and the second input transistor is p-channel transistors or n-channel transistors, and a gate width of the first input transistor is smaller than a gate width of the second input transistor.The semiconductor device according to claim 7, comprising: wherein the digital / analog converter comprises a plurality of conversion capacitors electrically connected to the differential input nodes and updates the differential input voltages by redistributing charges of the differential input nodes using a conversion capacitor corresponding to the first bit among the plurality of conversion capacitors, the semiconductor device further comprising: two sampling capacitors each having a first electrode electrically connected to the differential input nodes and a second electrode electrically connected to the sampling switch; a first switch that applies a predetermined power voltage to the differential input nodes when turned on; and a second switch that makes a short circuit between the second electrodes of the two sampling capacitors when turned on.A semiconductor device comprising: a baseband processing circuit that performs processing in baseband wireless communication; a high-frequency circuit that performs processing in a high-frequency band of the wireless communication and comprises a high-frequency transmission circuit that processes a transmission signal and a high-frequency reception circuit that processes a reception signal using an analog / digital conversion unit; and a processor connected to the baseband processing circuit via a bus, wherein the analog / digital conversion unit comprises: a voltage quantization circuit that converts differential input voltages to be applied to differential input nodes into a digital signal having multiple bits for each sampling period and outputs a conversion transmission signal when a conversion operation is completed; a correction code decision circuit electrically connected to said voltage quantization circuit and receiving said conversion transmission signal as its input output from said voltage quantization circuit; and a common mode voltage regulator circuit electrically connected to said correction code decision circuit and said voltage quantization circuit, said voltage quantization circuit comprising: a first comparator including a first input transistor receiving said differential input voltages as its input and defining a value of a first bit of said digital signal; A second comparator comprising a second input transistor that receives the differential input voltages as an input and is different from the first input transistor and defines a value of a second bit of the digital signal, the correction code decision circuit decides a correction code for correcting the common mode voltage of the differential input voltages on the basis of the conversion end signal output from the voltage quantization circuit, and the common mode voltage regulator circuit adjusts the common mode voltage by adding or subtracting a corrected voltage to or from the differential input voltages on the basis of the correction code.The semiconductor device according to claim 11, wherein the voltage quantization circuit further comprises: a sampling switch that samples an external analog input voltage for the differential input nodes; and a digital / analog converter that updates the differential input voltages by adding or subtracting a predetermined voltage to or from the differential input voltages according to the value of the first bit, and the second comparator receives the differential input voltages updated by the digital / analog converter as its input.The semiconductor device according to claim 11, wherein the correction code decision circuit changes the correction code when it detects the sampling period in which the conversion transmission signal is not activated.The semiconductor device according to claim 13, wherein the correction code decision circuit changes the correction code until it does not detect the sampling period in which the conversion transmission signal is not activated.The semiconductor device according to claim 13, wherein the correction code decision circuit and the common mode voltage regulator circuit operate in the background in a period in which the voltage quantization circuit performs a normal operation.The semiconductor device according to claim 12, wherein the common mode voltage regulator circuit comprises a plurality of correction capacitors electrically connected to the differential input nodes, and regulates the common mode voltage by redistributing charges of the differential input nodes using a correction capacitor, which is defined based on the correction code, among the plurality of correction capacitors.The semiconductor device according to claim 11, wherein one of the first input transistor and the second input transistor is a p-channel transistor, while the other of the first input transistor and the second input transistor is an n-channel transistor.The semiconductor device of claim 12, wherein each of the first input transistor and the second input transistor is p-channel transistors or n-channel transistors, and a gate width of the first input transistor is smaller than a gate width of the second input transistor.The semiconductor device according to claim 11, wherein the wireless communication is communication based on an ultra wide band (UWB) standard.

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