Semiconductor device housing with internal magnetic shielding for a Hall sensor

Abstract

A described example includes: a heatsink coupled to a package substrate, wherein the heatsink is configured to conduct current between the terminals of the package substrate; a first magnetic shield mounted to a top surface of the package substrate, wherein the first magnetic shield includes a die mounting area; a semiconductor die flip-chip mounted onto the die mounting area; a second magnetic shield mounted to the package substrate, wherein the second magnetic shield has a cantilevered section extending over a portion of the semiconductor die including a Hall element; electrical connections of wire bonds or tape bonds between the bond contact surfaces of the semiconductor die and the terminal elements on the package substrate;and a potting compound covering the electrical connections, the semiconductor die, the first magnetic shield and the second magnetic shield, leaving a section of the heat insert free, thereby forming a heat conduction surface for a semiconductor device housing.

Description

TECHNICAL FIELD

[0001] This disclosure generally relates to semiconductor device packages having semiconductor dies incorporating Hall sensors. BACKGROUND

[0002] Semiconductor devices for magnetic sensing include Hall-effect sensors with circuitry. Magnetic sensing can be used for motor control, automation, current measurement, and other applications. Hall-effect sensors integrated into semiconductor devices can be formed by doping regions to contain carriers sensitive to a magnetic field. A voltage proportional to a magnetic field is output from the Hall sensor while a current is applied to the Hall sensor. The Hall sensor is most sensitive to magnetic fields normal to a plane within the Hall sensor.

[0003] Current sensing using the Hall effect is increasingly used in the control of high-voltage motors and in power systems. The sensing of currents greater than 100 A is increasingly required. Solutions for semiconductor devices with Hall sensors for these applications currently involve expensive, combined, and / or bulky packages. Examples include package-in-a-package solutions, where a packaged semiconductor device with a Hall sensor is mounted within a second module with a magnetic core, and the components are then housed in a separate package. Other known solutions use custom semiconductor packages for the Hall sensors. Non-standardized contours for packaged Hall sensors increase assembly costs.

[0004] One aspect of a Hall sensor is the need for magnetic shielding. Because the Hall sensor uses a magnetic field caused by a current flowing through a metal conductor to detect the current, stray magnetic fields in the surrounding environment can adversely affect sensing and lead to an error in current measurements. Magnetic shielding and magnetic concentrators are used to improve performance. Magnetic concentrators can improve the performance of Hall sensors by better aligning the magnetic field to be detected to the plane of the Hall sensor.

[0005] Materials for magnetic shielding for use in semiconductor processes may contain magnetic materials. These magnetic materials cannot be easily integrated into a semiconductor die using semiconductor device processes, making forming magnetic shields during semiconductor die manufacturing expensive. What is needed is a reliable and robust semiconductor device package that integrates a Hall current sensor device with magnetic shields at a low cost. SUMMARY

[0006] In one described example, a method of forming a semiconductor device package includes: forming a package substrate having a circuit board-side surface and an opposite top surface, and having a thermal insert coupled to the package substrate, and wherein the thermal insert is configured to conduct a current between terminals of the package substrate; mounting a first magnetic shield to the package substrate, wherein the first magnetic shield includes a die mounting area facing the circuit board-side surface, wherein the die mounting area is exposed and not covered by the package substrate and the thermal insert; mounting a semiconductor die having a Hall element on the die mounting area, wherein the semiconductor die is flip-chip mounted and faces away from the circuit board-side surface of the package substrate;Mounting a second magnetic shield to the package substrate and the thermal insert, the second magnetic shield having a cantilevered portion extending over a portion of the semiconductor die including the Hall element, while the bonding pads on the semiconductor die remain exposed and are not covered by the second magnetic shield; forming electrical connections from wire bonds or tape bonds between the bonding pads of the semiconductor die and the terminal elements on the package substrate; and covering the electrical connections, the semiconductor die and portions of the package substrate, the first magnetic shield, and the second magnetic shield with a potting compound, wherein a portion of the thermal insert is kept exposed and not covered by the potting compound, thereby forming a thermally conductive surface for the semiconductor device package.

[0007] In another described example, a device includes: a package substrate having a circuit board-side surface and an opposite top surface, and a thermal insert coupled to the package substrate, and wherein the thermal insert is configured to conduct a current between terminals of the package substrate. A first magnetic shield is mounted on top of the package substrate, the first magnetic shield including a die mounting area facing the circuit board-side surface, the die mounting area being exposed in an opening and not covered by the package substrate and the thermal insert. A semiconductor die having a Hall element is mounted on the die mounting area, the semiconductor die being flip-chip mounted and facing away from the circuit board-side surface of the package substrate.A second magnetic shield is mounted to the package substrate and the thermal insert, the second magnetic shield having a base portion and a cantilevered portion extending over a portion of the semiconductor die including the Hall element, while the bond pads on the semiconductor die remain exposed and are not covered by the second magnetic shield. Electrical connections are formed from wire bonds or tape bonds between the bond pads of the semiconductor die and the terminal elements on the package substrate. A potting compound covers the electrical connections, the semiconductor die, portions of the package substrate, the first magnetic shield, and the second magnetic shield, with a portion of the thermal insert left exposed and not covered by the potting compound, thereby forming a thermal interface for a semiconductor device package.

[0008] In another described example, a Hall current sensor device includes: a lead frame comprising a first group of terminals in a high-voltage sector and a second group of terminals in a low-voltage sector electrically isolated from the high-voltage sector, the lead frame having a board-side surface and an opposite top surface; a thermal insert coupled to the first group of terminals of the high-voltage sector, the thermal insert configured to conduct a current between the terminals formed from the first group of terminals of the high-voltage sector; a first magnetic shield mounted on top of the lead frame and comprising a die mounting area in an opening that is exposed and not covered by the lead frame and the thermal insert;a semiconductor die having a Hall element and mounted on the die mounting area, wherein the semiconductor die is flip-chip mounted and faces away from the circuit board-side surface of the package substrate; a second magnetic shield mounted to the thermal insert, wherein the second magnetic shield has a base portion and a cantilever portion extending over a portion of the semiconductor die including the Hall element, while the bond pads on the semiconductor die remain exposed and are not covered by the second magnetic shield; electrical connections comprising wire bonds or ribbon bonds between the bond pads of the semiconductor die and the second group of terminal elements on the low-voltage sector of the lead frame;and a molding compound covering the electrical connections, the semiconductor die, portions of the lead frame, the first magnetic shield, and the second magnetic shield, with a portion of the thermal insert left exposed and not covered by the molding compound, thereby forming a thermal interface for a semiconductor device package; BRIEF DESCRIPTION OF THE DRAWINGS The Fig. 1A and Fig. 1B illustrate a semiconductor wafer and an individual semiconductor die, respectively. Fig. 1C illustrates in a circuit block diagram an application for a Hall sensor according to one embodiment. Fig. 2 illustrates, in a projection view, a semiconductor device package that may be used in one embodiment. Fig. 3 illustrates a cross-sectional view of a semiconductor device package according to one embodiment. The Fig. 4A and 4AA, 4B and 4BB, 4C and 4CC, 4D to 4DDD, 4E and 4EE, and 4F illustrate, in a series of plan and side views, selected steps for forming a semiconductor device package according to an example embodiment. Fig. 5 illustrates, in a projection view from a circuit board side, an exemplary semiconductor device package according to an embodiment. Fig. 6 illustrates in a flowchart an exemplary method for forming an embodiment. DETAILED DESCRIPTION

[0009] Like reference numerals and symbols in the various figures generally refer to like parts, unless otherwise indicated. The figures are not necessarily drawn to scale.

[0010] Here, elements are described as "coupled" to each other. The term "coupled" includes elements that are directly connected to each other and elements that are indirectly connected to each other. Elements that are themselves electrically connected to intermediate elements or wires are also coupled.

[0011] The term "semiconductor die" is used here. Semiconductor dies may include a discrete semiconductor device such as a bipolar transistor or several discrete devices such as a pair of power FET switches fabricated together on a single semiconductor die, or a semiconductor die may be an integrated circuit with multiple semiconductor devices such as multiple capacitors in an A / D converter. The semiconductor die may include passive devices such as resistors, inductors, filters, sensors, or active devices such as transistors. The semiconductor die may be an integrated circuit with hundreds or thousands of transistors coupled to form a functional circuit, for example, a microprocessor or a memory device.

[0012] The term "semiconductor device package" is used herein. A semiconductor device package includes at least one semiconductor die coupled to terminals and includes a package body that protects and covers the semiconductor die. In some embodiments, multiple semiconductor dies may be mounted together in a package. For example, a semiconductor die of a metal-oxide-semiconductor power field-effect transistor (power MOSFET) and a logic semiconductor die (such as a gate driver die or a control unit die) may be mounted together in a package to form a single packaged electronic device. Additional components, such as passive elements, may be included in the packaged electronic device.The semiconductor die is mounted to a package substrate providing conductive terminals, with a portion of the conductive terminals forming the terminals for the packaged device. The semiconductor die may be mounted to the package substrate with a device-facing surface facing away from the substrate and a backside surface facing and mounted to a die contact pad of the package substrate. In wire-bonded semiconductor device packages, bond wires couple the conductive terminals of a package substrate to the bond contact pads of the semiconductor die. The semiconductor device package may include a package body formed from a thermosetting epoxy resin in a molding process or by using epoxy, plastics, or resins that are liquid at room temperature and subsequently cured.The package body can provide a hermetic enclosure for the packaged device. The package body can be formed in a mold using an encapsulation process, but a portion of the terminals of the package substrate is left uncovered during encapsulation; these exposed terminal portions provide the terminals for the semiconductor device package.

[0013] The term "packaging substrate" is used herein. A packaging substrate is a substrate suitable for receiving a semiconductor die and supporting the semiconductor die in a completed semiconductor device package. The packaging substrates useful in the embodiments include conductive lead frames, which can be formed from copper, aluminum, stainless steel, steel, and alloys such as Alloy 42 and copper alloys. The lead frames can be provided in strips or arrays. The conductive lead frames can be provided as a panel with strips or arrays of unit device sections in rows and columns. The semiconductor dies can be placed on corresponding unit device sections within the strips or arrays.A semiconductor die may be placed on a die mounting area for each packaged device, and a die attach compound or die adhesive may be used to mount the semiconductor dies to the die mounting areas. In wire-bonded packages, the bond pads may be coupled to the terminals of the lead frames on the semiconductor dies by bond wires. The lead frames may have plated portions in areas configured for wire bonding, for example, using silver plating. Once the bond wires are in place, a portion of the package substrate, the semiconductor die, and at least a portion of the die pad may be covered with a protective material, such as a potting compound.

[0014] In the exemplary embodiments, a lead frame with insulated terminal element sections may be used. The lead frame includes a high-voltage section with a first group of terminal elements configured to couple to high-voltage signals or supplies, such as voltages greater than 20 volts. The lead frame includes a low-voltage section with a second group of terminal elements configured to couple to low-voltage signals or supplies, such as logic-level signals with voltages less than 20 volts. The high-voltage section and the low-voltage section are electrically isolated from each other.

[0015] When mounting semiconductor devices in packages, a potting compound may be used to partially cover a package substrate, to cover the semiconductor die, and to cover the electrical connections from the semiconductor dies to the package substrate. This may be referred to as an "encapsulation process," although some portions of the package substrates are not covered by the potting compound during encapsulation; for example, terminals and connectors are kept clear of the potting compound. Encapsulation is often a compressive molding process that may use a thermosetting potting compound such as a resin epoxy. A potting compound that is solid or powdered at room temperature may be heated to a liquid state, and then molding may be performed by forcing the liquid potting compound into a mold. Injection molding may be used.Individual molds can be used, designed to enclose a single device, or block molding can be used to form the packages for multiple devices simultaneously from the encapsulant. The devices can be provided in an array of several, hundreds, or even thousands of devices in rows and columns, which are molded together. After molding, the individual packaged devices are cut apart in a sawing operation by cutting through the encapsulant and package substrate in saw lines formed between the devices. Some portions of the package substrate terminals are left free of the encapsulant to form terminals for the packaged semiconductor device.

[0016] The term "scribe track" is used here. A scribe track is a section of a semiconductor wafer between the semiconductor dies. Sometimes, the term "scribe street" is used in related literature. Once semiconductor processing is finished and the semiconductor devices are complete, the semiconductor devices are separated into individual semiconductor dies by dicing the semiconductor wafer along the scribe tracks. The separated dies can then be removed and handled individually for further processing. This process of removing the dies from a wafer is referred to as "singling" or sometimes referred to as "division." The scribe tracks are arranged on four sides of the semiconductor dies, and when the dies are singulated from each other, rectangular semiconductor dies are formed.

[0017] The term "saw line" is used here. A saw line is an area between molded electronic devices used to allow a saw, such as a mechanical blade saw, a laser, or other cutting tool, to cut between the molded electronic devices to separate the devices from each other. The process is another form of singulation. When the molded electronic devices are provided in a strip with one device adjacent to another along the strip, the saw lines are parallel and perpendicular to the length of the strip.When the molded electronic devices are provided in an array of devices in rows and columns, the saw lines include two groups of parallel saw lines, the two groups being perpendicular to each other and the saw passing through the packaged electronic devices in two different directions to cut the molded electronic devices in the array from each other.

[0018] The term "Quad Flat No-lead" or "QFN" is used herein to refer to a type of electronic device package. A QFN package has conductive leads that are coplanar with the sides of a molded package body, and in a quad package, the leads are located on four sides. Alternatively, flat packages without projecting leads may have the leads on two sides or only on one side. These may be referred to as "Small Outline No-lead" or "SON" packages. Electronic devices packaged without projecting leads may be surface-mounted on a printed circuit board. Packages with projecting leads may be used in designs where the leads extend out from the package and are configured to form a portion for soldering to a printed circuit board.A dual in-line package (DIP) can be used in the embodiments. A small outline package (SOP) can be used in the embodiments. A small outline no-lead package (SON) can be used, and a small outline transistor package (SOT) is a package with protruding leads that can be used in the embodiments. Leads for packages with protruding leads are suitable for solder mounting on a printed circuit board. The leads can be designed to extend toward the printed circuit board and form a mounting surface. Gull-wing leads, J-lead leads, or other lead shapes can be used.A small outline integrated circuit package (SOIC) can be used in the designs. Wide SOIC packages can be used in the designs. Dual in-line packages (DIPs) can be used. In DIPs, the terminals terminate in pin-shaped sections that can be inserted into conductive openings formed in a printed circuit board, and solder is used to couple the terminals to the conductive traces within the openings.

[0019] The term "magnetic material" is used herein. A magnetic material useful in the embodiments includes iron oxide, Fe2O3, with useful examples including nickel ferrite (NiFe), nickel zinc ferrite (NiZnFe), and manganese zinc ferrite (MnZnFe). Ferrites are ferromagnetic and become magnetized in the presence of a magnetic field. The term "magnetic shield" is used herein. In the embodiments, magnetic shields are formed by integrating a magnetic layer of a soft ferrite material above or below a semiconductor die containing one or more Hall sensors within a semiconductor device package. The integrated magnetic shields prevent stray magnetic fields from affecting the sensors with Hall elements in the semiconductor die.A current flowing through the lead frame in the semiconductor device package creates a local magnetic field, which the Hall sensors use to measure the current. Integrated magnetic shields prevent external magnetic fields from introducing unwanted error into the current measurements.

[0020] The term "cantilevered portion" is used herein. In an exemplary embodiment, a magnetic shield within a semiconductor device package includes a cantilevered portion extending in a horizontal direction from a base, the cantilevered portion being unsupported along its length and extending over a Hall element in a semiconductor die, while a portion of the semiconductor die is not covered by the cantilevered portion of the magnetic shield.

[0021] The term "heat sink" is used herein. A heat sink is a conductive material that conducts heat. In embodiments, a heat sink is used to carry a current that can be sensed. The heat sink is mounted to and electrically coupled to the high-voltage portion of a lead frame and forms part of a current path between one or more input terminals and one or more output terminals, wherein the heat sink is configured to be coupled to a high voltage at the input terminal and to carry a current. In embodiments, the heat sink may be a C-shaped conductor in a plan view. The heat sink carries the current to a location in the semiconductor package that is proximate to a semiconductor die that includes a Hall element.The Hall element functions by detecting the magnetic field generated by the current flowing through the heat insert. In an exemplary embodiment, a copper heat insert is used that is thicker than the lead frame, and the copper heat insert has a board-side surface that is exposed and not covered by a molding compound body of the semiconductor device package to transfer heat from the semiconductor device package.

[0022] The Fig. 1A and Fig. 1B illustrate steps used in forming semiconductor dies, such as those used in wire bonding embodiments. In Fig. 1A shows a semiconductor wafer 101 having an array of semiconductor dies 105 arranged in rows and columns. The semiconductor dies 105 are formed using manufacturing processes in a semiconductor manufacturing facility, including ion implantation for carrier doping, annealing, oxidation, deposition of dielectrics and conductive lines, photolithography, patterning, etching, chemical mechanical polishing (CMP), electroplating, and other processes for fabricating semiconductor devices. The devices are formed on a device-side surface of the semiconductor dies. Scribing tracks 103 and 104, which are perpendicular to each other and extend in parallel groups through the semiconductor wafer 101, separate the rows and columns of the completed semiconductor dies 105 and provide the areas for dicing the wafer to separate the semiconductor dies 105 from each other.

[0023] Fig. 1B illustrates a single semiconductor die 105 with bond pads 102, which are conductive pads that are electrically coupled to devices (not shown for simplicity) formed in the semiconductor die 105. The semiconductor dies 105 are separated from the semiconductor wafer 101 by splitting the wafer, or they are formed using scribe tracks 103, 104 (see Fig. 1A) are separated from each other. The wafer can be divided using a mechanical saw or by laser cutting along the scribe lines. Fig. The semiconductor die 105 shown in Figure 1B includes one or more Hall elements (not shown). In an exemplary embodiment, the Hall elements are configured as a current sensor.

[0024] Fig. 1C is a circuit block diagram for an exemplary semiconductor device 100 that may be used in one embodiment. The exemplary semiconductor device 100 is a Hall current sensor. The semiconductor device 100 includes an isolation barrier 112 that uses galvanic isolation to isolate high-voltage signals (signals with voltages of 20 V to 100 V or more) from a semiconductor die 105 within the package, and to separate the high-voltage signals (ON+, ON- in Fig. 1C) of low-voltage signals (such as logic level voltage signals between 0.5 and 20 V, for example the VAUS in Fig. 1C) coupled to and output from the semiconductor die 105.

[0025] With respect to the device 100 of the Fig. 1C, in an exemplary application, an input IN+ may be coupled to a first node and may receive a signal carrying a current labeled "I," where the node at IN+ may be coupled, for example, to a high-voltage signal or power supply, and an output IN- may be coupled to a second node, the output IN-, that outputs the current I. The semiconductor die 105 within the semiconductor device package 100 includes at least one Hall element 108. Circuitry required to control and monitor the Hall element 108 is provided and includes a bias circuit 107 for the Hall element, a temperature compensation and offset cancellation circuit 113, a precision amplifier 109, and an output amplifier 111.Additional circuitry to improve reliability and performance, such as overvoltage, overcurrent, and temperature sensors with corresponding control and output signals, may be provided in the semiconductor die 105.

[0026] In operation, the output amplifier 111 drives an output VAUS that corresponds to the magnitude of the current I or that changes a voltage with variations in the current I. A magnetic field due to the current I is detected by the Hall element 108, and the voltage VAUS corresponding to the magnitude of the magnetic field is output by the semiconductor die 105. In one system, a calibration scheme can be used to determine a value of the current I from the voltage appearing at the output VAUS. An isolation barrier 112 is shown, the isolation barrier 112 being formed by using a package substrate with insulated sections to mount the semiconductor die 105 within a magnetic field due to the current I, while keeping the semiconductor die 105 electrically isolated from the high-voltage signals at the input IN+ and the output IN- to which the current I is applied.The semiconductor die 105 may be made of one or more materials that cannot withstand the high voltages applied to the ON+ terminal, and it may be made of silicon, and it may operate at lower voltages, such as 10 V or less. This aspect of the embodiments reduces the cost of the Hall current sensors and allows for the use of conventional semiconductor processing to form the semiconductor die 105. Although in the illustrated example, the . Fig. 1C shows a single Hall element 108, an alternative embodiment employing differential sensing by an amplifier similar to a precision amplifier 109 may utilize two spaced-apart Hall elements. This alternative embodiment allows for conventional noise reduction by using differential sensing to remove the conventional noise detected by both Hall elements from the output signal. In one example, conventional noise reduction is achieved by differential sensing to remove noise present in both Hall elements.

[0027] Fig. Figure 2 illustrates, in a projection view, a semiconductor device package 200 that may be used in an exemplary embodiment. The semiconductor device package includes a molding compound 223 that forms the body of the device package and the terminals 210. In Fig. 2, a small footprint integrated circuit (SOIC) package 200 having a width of sixteen pins is shown. The use of a semiconductor device package with a standard pinout with the Hall element sensor according to the embodiments reduces the cost of mounting the devices on a system board or system module (compared to custom packages used in some prior Hall sensor solutions). In these embodiments, a semiconductor device package with a standard footprint may be used. Although the exemplary SOIC package 200 shown in Fig. 2, which includes terminals 210 that are external terminals configured for surface mounting to a printed circuit board using surface mount technology (SMT), packages without protruding terminals, such as quad-flat no-lead (QFN) packages, may also be used. Other standard semiconductor package outlines, such as dual in-line (DIP) packages, may also be used. The semiconductor device packages of the exemplary embodiments may be thicker than standard semiconductor device packages due to the use of an integrated thermal insert, as discussed further below, but the use of a standard outline for the packages enables assembly using standard tools and equipment.

[0028] Fig. 3 illustrates a cross-sectional view of an exemplary semiconductor device package 300 in which an embodiment is incorporated. In Fig. 3, a lead frame 307 is used with terminals 310 that extend outwardly from the potting compound 323 forming the package body. The lead frame 307 is an insulating lead frame that includes a high-voltage sector 3071 and a low-voltage sector 3072. An internal heat insert 321 is mounted to the circuit board side of the lead frame 307 in the high-voltage sector 3071 and is made of a thermal and electrical conductor, such as copper or a copper alloy. The heat insert 321 is electrically coupled to the high-voltage sector 3071 of the lead frame 307 and forms a low-impedance current path to transfer the current I from an input section to an output section (see the input and output signals IN+ and IN- and the current I in Fig. 1C) of the high-voltage sector 3071 of the lead frame 307, and wherein the heat insert 321 is designed to transport the current I to a location near the semiconductor die 305. In a plan view, the heat insert 321 may have a C-, U-, V-, D-, or similar shape with a portion for transporting the current I near the semiconductor die 305 in the semiconductor device package 300. Together with the high-voltage sector 3071 of the lead frame 307, the heat insert 321 forms a serial path (see IN+ in Fig. 1C) to an output (see IN- in Fig. 1C) to conduct a current for the signal to be monitored, which may be a high current of more than one ampere and up to more than 100 A. The thermal insert 321 may also include an external thermal interface 322 that is exposed and not covered by the encapsulant 323. The thermal interface 322 is configured to transfer heat from the semiconductor device package 300 to a thermal path of a circuit board or module to dissipate the thermal energy from the semiconductor device package 300 during operation.

[0029] The semiconductor device package 300 includes a semiconductor die 305 mounted in a "flip-chip" orientation with the device-side bond pads facing the circuit board side 326 of the semiconductor device package 300. The semiconductor die 305 includes one or more (not visible) Hall elements placed near the thermal insert 321 such that a magnetic field corresponding to the current I flowing through the thermal insert 321 can be detected by the Hall element within the semi-custom die 305. However, the semiconductor die is electrically isolated from the thermal insert 321 and the high-voltage sector of the lead frame 307.

[0030] An electrically insulating layer 317, such as a polyimide, or a laminate, such as a bismaleimide triazine resin laminate (BT resin laminate) or a glass fiber reinforced epoxy resin laminate (FR4 laminate), is used to provide electrical insulation between the back surface of the semiconductor die 305 and a first magnetic shield 313. The first magnetic shield 313 faces the top side 328 of the semiconductor device package 300 and provides a die mounting area spaced from the first thermal insert 321 for supporting the semiconductor die 305. Electrical connections, such as the bond wires 325 or the ribbon bonds, connect the bond pads (not shown here, but, for example, as the bond pads 102 in Fig. 1B) on the semiconductor die 305 with terminal elements of the low voltage sector 3072 of the lead frame 307. A second magnetic shield 315 has a portion extending in a cantilevered manner to cover the (not visible) Hall element within the semiconductor die 305 such that the Hall element has magnetic shields 315, 313 over the device-side surface of the semiconductor die 305 and the backside surface of the semiconductor die 305 to prevent stray magnetic fields from affecting the Hall element within the semiconductor die 305 and introducing error into the measurements by the current sensor.

[0031] The Fig. 4A and 4AA, 4B and 4BB, 4C and 4CC, 4D to 4DDD, 4E and 4EE, and 4F illustrate selected steps for forming embodiments in a series of plan and side views. Fig. Figure 4A illustrates a top view of a portion 330 of the lead frame 307, an exemplary heat insert 321 mounted to the high-voltage sector 3071 of the lead frame 307. The terminal elements 331 are shown forming the low-voltage sector 3072 of the lead frame 307. It should be noted that the lead frame 307 in Fig. 4A so that the thermal insert 321 is facing upward and is located above the lead frame 307, which orientation is used in an assembly step as described in more detail below. As previously mentioned, although the thermal insert 321 has a "C" shape in the illustrated examples, other shapes for the thermal insert 321 may be used. The thermal insert 321 provides a low-resistance path to transport current from the lead frame 307 through the thermal insert 321 into the high-voltage sector 3071. The lead frame portion 330 is the portion of the lead frame 307 that is within the confines of the package body and supports the external connection elements (see, for example, 310 in Fig. 3) are not shown in this section 330. In an exemplary assembly process, the lead frame 307 is provided in a strip, grid, or array comprising multiple units of lead frames temporarily connected together by tie bars formed from the lead frame material that support the lead elements during assembly. Multiple packaged semiconductor devices are formed simultaneously to increase throughput and reduce costs. The completed packaged devices are then cut apart to form the individual semiconductor device packages.

[0032] Fig. 4AA is a side view corresponding to the top view of Fig. 4A, and shows the lead frame 307 with the heat insert 321 mounted thereon. The heat insert 321 and the lead frame 307 may be provided as an assembly by a lead frame vendor; alternatively, the heat insert 321 may be mounted to the lead frame 307 in the first part of an assembly process. The heat insert 321 is electrically coupled to the high-voltage sector 3071 of the lead frame 307, forming a low-resistance current conduction path. Welding and brazing operations may be used to mount the heat insert 321 to the lead frame 307, and alternatively, a solder may be used.

[0033] Fig. Figure 4B is a plan view of the lead frame 307 and the heat insert 321 of the Fig. 4A and Fig. 4AA in a top view, shown after an additional process step. In Fig. 4B, a first magnetic shield 313 is mounted to the upper portion or top of the thermal insert 321. In this exemplary embodiment, the first magnetic shield has an "I" shape in a plan view and is made of a magnetic material. Example magnetic materials useful in the embodiments include nickel ferrite, NiFe, nickel zinc ferrite, NiZnFe, and manganese zinc ferrite, MnZnFe. The first magnetic shield 313 is mounted to the thermal insert 321 such that a portion of the first magnetic shield 313 extends into an opening between the thermal insert 321 and the low-voltage sector 3072 of the lead frame 307 and provides a die mounting area in the opening at a distance from the thermal insert 321.In one exemplary process, a die attach film (DAF) (not shown) is used to mount the first magnetic shield to the thermal insert 321. Alternatives include a die attach material dispensed and cured as a liquid, paste, or gel. The die attach material provides insulation to isolate the first magnetic shield from the other elements.

[0034] Fig. Figure 4BB illustrates the first magnetic shield 313, the heat insert 321 and the lead frame 307 of the Fig. 4B in a side view, wherein the lead frame assembly is shown in relation to Fig. 4B has been rotated so that the top of the thermal insert 321 is now facing down, showing the first magnetic shield 313 at the bottom of the elements. This orientation is used to show the die mounting area 314 of the first magnetic shield 313, which is located on the circuit board side of the first magnetic shield 313 and which is exposed and not covered by the low-voltage sector 3072 of the lead frame 307 or the thermal insert 321. When the semiconductor device package is mounted to a circuit board, the die mounting area 314 faces the circuit board, and a semiconductor die mounted to the first magnetic shield 313 is oriented with its major surface facing down (toward a circuit board surface of the package) or mounted in a flip-chip orientation, as described above.

[0035] Fig. Figure 4C shows in a further top view the elements of the Fig. 4B after an additional processing step. In Fig. 4C, the leadframe portion 330 is shown from a view from the circuit board side, such that the first magnetic shield 313 is shown over the heat insert 321, and with the die mounting area 314 facing the viewer. A semiconductor die 305 including at least one Hall element 308 is shown after being mounted onto the die mounting area 314 of the first magnetic shield 313. The semiconductor die 305 is spaced from the first magnetic shield 313 and electrically insulated therefrom by an insulating material comprising a polyimide layer (which is shown in Fig. 4C is not visible, see the corresponding side view in Fig. 4CC) or an insulating substrate material, such as a BT resin or FR4. The semiconductor die 305 can be mounted using a die attach film (DAF) or a die attach material that is dispensed and subsequently cured.

[0036] Fig. 4CC is a side view of the elements used in Fig. 4C. In Fig. 4CC, the elements are shown with the circuit board side of the lead frame 307 facing upwards, so that the thermal insert 321 is shown above the lead frame 307. The semiconductor die 305 with the Hall element 308 is shown on the die mounting area 314 of the first magnetic shield 313. The semiconductor die is spaced from the lead elements 331 of the low-voltage sector 3072 and is spaced from the thermal insert 321 in an opening between these elements. The insulation layer 317, which may be a polyimide layer, a BT resin, or an FR4 laminate, for example, is shown between the back surface of the semiconductor die 305 and the first magnetic shield 313. The semiconductor die is therefore electrically isolated from the first magnetic shield 313.The Hall element is located near a portion of the heat insert 321 so that, during operation, a current flowing through the heat insert 321 creates a magnetic field that can be detected by the Hall element 308.

[0037] Fig. Figure 4D illustrates in a plan view from the circuit board side of the lead frame 307 and the heat insert 321 the elements of the Fig. 4C and Fig. 4CC after an additional processing step. In Fig. 4D shows a second magnetic shield 315 mounted to the first magnetic shield 313 and extending over the Hall element 308 on the semiconductor die 305, which is mounted on the die mounting area 314 of the first magnetic shield 313. The second magnetic shield 315 does not cover the entire device-side surface of the semiconductor die 305, which aspect enables a wire bonding operation, as shown below, to connect the semiconductor die 305 to the terminals 331 of the low-voltage sector 3072 of the lead frame 307. The second magnetic shield 315 can be mounted using a DAF or a die attach material. The second magnetic shield 315 can be mounted to the first magnetic shield, but the semiconductor die 305 is not in electrical or physical contact with the second magnetic shield 315.However, a cantilevered portion of the second magnetic shield 315 extends over the device side of the semiconductor die 305 and covers the Hall element 308 within the semiconductor die 305.

[0038] Fig. 4DD illustrates in a side view the Fig. 4D, the elements of the Fig. 4D including the second magnetic shield 315, wherein in Fig. 4DD, the elements are oriented with the circuit board side of the lead frame 307 facing upward. The second magnetic shield 315 includes a base portion 318 and a cantilever portion 316 that form an "L" shape in a cross-sectional view. The base portion 318 of the second magnetic shield 315 is mounted to the first magnetic shield 313 using, for example, a DAF or die attach material, and the cantilever portion 316 of the second magnetic shield 315 extends over a portion of the thermal insert 321 and extends over the Hall element 308 on the semiconductor die 305. The first magnetic shield 313 and the second magnetic shield 315 are disposed above and below the semiconductor die 305 and provide magnetic shielding for the Hall element 308.

[0039] Fig. 4DDD repeats the Fig. 4D, but adds curve 342, which illustrates with a dashed arrow the path of the current flowing through the heat insert 321. The current originates from a signal designated as “I EINGANG ' and which is coupled to an input terminal formed in the high-voltage sector 3071 of the lead frame 307, which is coupled to the heat insert 321 and an output terminal of the high-voltage sector 3071 of the lead frame 307 to form a current path for the current 342 which is output as a signal designated as 'I AUSGANG", flows to the output terminal. In operation, the current 342 will flow through the heat sink 321 at a location near the Hall element 308 on the semiconductor die 305, and the Hall element will detect a magnetic field caused by and proportional to the current 342. The first magnetic shield 313 and the second magnetic shield 315 are mounted above and below the semiconductor die 305 and shield the Hall element 308 from stray magnetic fields, resulting in error reduction.

[0040] Fig. Figure 4E shows a plan view of the elements of the Fig. 4D after an additional processing step. In Fig. 4E shows the view from a circuit board side of the lead frame 307 on the device-side surface of the semiconductor die 305. In Fig. 4E shows the semiconductor die 305 with electrical connections, such as the bond wires 325, formed on the terminals 331 of the low-voltage sector 3072 of the lead frame 307. The electrical connections may be formed using a ball bonding process, such as a ball and stitch wire bonding tool. Alternatively, ribbon bonds may be used to connect the semiconductor die 305 to the terminals 331.

[0041] An exemplary ball and stitch wire bonding process uses a capillary with a bond wire extending through an aperture. A flame or electronic arc can be used to form a ball at the end of the extended bond wire. The capillary uses mechanical force and sonic vibration to push the molten ball onto the conductive bond pad on the semiconductor die, forming a ball bond between the bond wire and the bond pad. As the capillary is moved away from the bond pad, the bond wire is allowed to extend in an arc from the ball bond. The capillary is moved over a terminal, and a stitch bond is formed using mechanical force and sonic vibration energy to push the bond wire onto the terminal.The capillary is moved a short distance away from the stitch bond, and the bond wire is cut off, leaving a small tail. This ball and stitch operation is automated and fast, and many wire bonds can be formed in a few seconds, allowing for rapid throughput. Bond wires made of copper, gold, silver, and aluminum can be used. One example process uses copper bond wires. When copper is used, an anoxic atmosphere can be used in the wire bonding tool to reduce oxidation of the copper bond wires.

[0042] Fig. 4EE illustrates the elements of Fig. 4E in a side view. In Fig. 4E, the elements are shown with the board side of the lead frame 307 facing upward. The bond wires 325 are shown between the (not visible) bond pads on the semiconductor die 305 and the terminal elements 331 of the low-voltage sector 3072 of the lead frame 307. The second magnetic shield 315 is shown with the base 318 and the cantilevered portion 316 extending above, but not covering, the device-side surface of the semiconductor die 305 to allow a wire bonder to reach the bond pads for the wire bonding processes. The Hall element 308 has the second magnetic shield 315 above it and the first magnetic shield 313 below it (as the elements in Fig. 4EE, meaning that the circuit board side is facing upwards), providing magnetic shielding against stray magnetic fields.

[0043] Fig. 4F illustrates in a side view the elements of the Fig. 4E, after an injection molding process has formed a housing body from the potting compound 323. The potting compound 323 is shown in a transparent view to clearly show the other elements. The portion 330 of the lead frame 307 of the Fig. 4E, the lead frame 307 and the other elements are oriented in such a way that the circuit board side of the lead frame 307 faces upward. The encapsulant 323 is shown formed over the semiconductor die 305, the first magnetic shield 313, the second magnetic shield 315, the portions of the terminal elements 331 of the low-voltage sector 3072 of the lead frame 307, and the portions of the high-voltage sector 3071 of the lead frame 307, covering a majority of the thermal insert 321, while a circuit board-side surface of the thermal insert 321 is kept clear and not covered by the encapsulant 323 to form the thermal interface 322. In an exemplary transfer molding process, the lead frame 303, as shown in Fig. 4E, after wire bonding, is mounted in an injection-molded package. An electronic mold compound (EMC) may be used as the encapsulant 323, which may be poured starting with a room-temperature solid disc or powder that is placed in the mold and heated to a liquid state. In one example, an epoxy resin encapsulant with solid fillers is used, where the fillers add strength and heat dissipation to the encapsulant.After the encapsulant has liquefied, a mechanical plunger is used to force the encapsulant through guide grooves into the molded package. The encapsulant surrounds the lead frame 307 and other elements, leaving portions of the lead elements that extend from the encapsulant to form terminals and thermal interfaces exposed and uncoated by the encapsulant. The encapsulant cures and becomes a solid. Encapsulant 323 is a thermosetting material and will remain solid after molding to protect the elements of the semiconductor device package.

[0044] Fig. Figure 5 illustrates a projection view of the finished semiconductor device package 300 as seen from the circuit board side. Fig. 5, the semiconductor die 305 is shown mounted to the first magnetic shield, with the Hall element 308 mounted near a portion of the thermal insert 321. The low-voltage sector 3072 of the lead frame 307 is shown with the terminals 331 extending from the potting compound 323 to form the terminals 310. The high-voltage sector 3071 of the lead frame 308 is shown with the terminals extending from the potting compound 323 to form the terminals 332, 334 for the high-voltage signals (at terminals 332 (IN+)) (and at terminals 334 (IN-)). The thermal insert 321 is shown with the second magnetic shield 315 mounted such that a cantilevered portion of the second magnetic shield extends over the Hall element 308 of the semiconductor die 305. The wire bonds 325 are shown between the semiconductor die 305 and the terminals 331 of the lead frame 307.The high-voltage sector 3071 of the lead frame is connected to the heat insert 321 and electrically coupled thereto to form a current path (see 342 in . Fig. 4DDD) from the "ON+" terminals 332 to the "ON-" terminals 334 through the thermal insert 321. The semiconductor die 305 is mounted between the first magnetic shield 313 and the second magnetic shield 315, so that the Hall element 308 has a magnetic shield above and below it.

[0045] The exemplary semiconductor device package 300 shown in Fig. 5 and Fig. 3 is a wide SOIC package with sixteen terminals, however, the first magnetic shield and the second magnetic shield can be used in semiconductor devices with Hall sensors and with package substrates in other package types, such as packages without protruding terminals and packages with different widths, to form a Hall current sensor in a standard package outline. The use of the heat insert in the embodiments can cause the finished semiconductor device package 300 to have a thickness greater than a standard package thickness, yet the circuit board layout required to assemble the package can still be accommodated in a standard package outline, reducing the cost of circuit board design and simplifying assembly.

[0046] Fig. 6 is a flowchart illustrating steps for forming a semiconductor device package according to embodiments.

[0047] In Fig. 6, the method begins in step 601 by forming a package substrate having a circuit board-side surface and an opposite top surface, and having a thermal insert coupled to the package substrate, and wherein the thermal insert is configured to conduct a current between the terminals of the package substrate. (See, for example, Fig. 4A and Fig. 4AA, the heat insert 321 and the housing substrate and the lead frame 307.)

[0048] In step 603, the method continues with mounting a first magnetic shield to the package substrate, wherein the first magnetic shield includes a die mounting area facing the circuit board-side surface, wherein the die attachment area is exposed and not covered by the package substrate and the thermal insert. (See, for example, Fig. 4B and Fig. 4BB with the first magnetic shield 313 mounted to the package substrate and the lead frame 307).

[0049] In step 605, the method continues with mounting a semiconductor die having a Hall element on the die attachment area, wherein the semiconductor die is flip-chip mounted and faces away from the circuit board-side surface of the package substrate. (See, for example, semiconductor die 305 and Hall element 308 in the Fig. 4C and Fig. 4CC).

[0050] In step 607, the method continues with mounting a second magnetic shield to the package substrate and the heat insert, wherein the second magnetic shield has a cantilevered portion extending over a portion of the semiconductor die including the Hall element, while the bonding pads on the semiconductor die remain exposed and are not covered by the second magnetic shield. (See, for example, the Fig. 4D to 4DDD with the second magnetic shield 315 mounted on the lead frame 307).

[0051] In step 609, the method continues with forming electrical connections from wire bonds or ribbon bonds between the bond pads of the semiconductor die and the terminal elements on the package substrate. (See, for example, the Fig. 4E and Fig. 4EE with the wire bond connections 325).

[0052] In step 611, the method continues by covering the electrical connections, the semiconductor die, and portions of the package substrate, the first magnetic shield, and the second magnetic shield with a potting compound, leaving a portion of the thermal insert exposed and not covered by the potting compound, thereby forming a thermal interface for the semiconductor device package. (See, for example, the potting compound 323 in Fig. 4F).

[0053] The use of the embodiments provides a packaged semiconductor device including one or more Hall sensors with integrated magnetic shields. The packaged semiconductor devices are current sensors configured for high-power or high-current applications, such as currents greater than one ampere and up to 100 amperes or more. The embodiments are formed using existing methods, materials, and manufacturing tools for fabricating the devices, and they are cost-effective. The magnetic shields are formed from readily available magnetic materials.By providing the magnetic shields as an integral part of the semiconductor package and mounting them over the semiconductor die using materials compatible with typical semiconductor packaging processes and techniques, the present invention provides an economical and robust device with integrated Hall current sensors for high-performance applications. The packaged semiconductor devices can be used with a variety of semiconductor package types, including lead-out packages, SOIC packages, and leadless packages, which in turn include QFN and SON packages.

[0054] Modifications to the described embodiments are possible and further alternative embodiments are possible within the scope of the claims.

Claims

[1] A method of forming a semiconductor device package, comprising: Forming a package substrate having a circuit board-side surface and an opposite top surface, and having a thermal insert coupled to the package substrate, and wherein the thermal insert is configured to conduct a current between the terminals of the package substrate; Mounting a first magnetic shield to the package substrate, the first magnetic shield comprising a die mounting area facing the circuit board-side surface, the die mounting area being exposed and not covered by the package substrate and the thermal insert; Mounting a semiconductor die having a Hall element on the die mounting area, the semiconductor die being flip-chip mounted and facing away from the circuit board-side surface of the package substrate; Mounting a second magnetic shield to the package substrate and the heat insert, the second magnetic shield having a cantilevered portion extending over a portion of the semiconductor die including the Hall element, while the bonding pads on the semiconductor die remain exposed and are not covered by the second magnetic shield; Forming electrical connections from wire bonds or tape bonds between the bonding pads of the semiconductor die and the connection elements on the package substrate; and Covering the electrical connections, the semiconductor die and portions of the package substrate, the first magnetic shield and the second magnetic shield with a potting compound, wherein a portion of the heat insert is kept free and not covered by the potting compound, thereby forming a thermal interface for the semiconductor device package. [2] The method of claim 1, wherein mounting the semiconductor die having the Hall element on the die mount region further comprises forming an insulation layer on the die mount region prior to mounting the semiconductor device die. [3] The method of claim 2, wherein the insulating layer is a polyimide. [4] The method according to claim 2, wherein the insulation layer is a bismaleimide triazine resin laminate (BT resin laminate) or a glass fiber reinforced epoxy resin laminate (FR4 laminate). [5] The method of claim 1, wherein the first magnetic shield comprises a magnetic material. [6] The method of claim 5, wherein the magnetic material is a nickel ferrite (NiFe), a nickel-zinc ferrite (NiZnFe) or a manganese-zinc ferrite (MnZnFe). [7] The method of claim 1, wherein the first magnetic shield has an "I" shape in a plan view. [8] The method of claim 1, wherein the second magnetic shield has a rectangular base and the cantilevered portion extending from the rectangular base. [9] The method of claim 8, wherein the second magnetic shield has an "L" shape in a cross-sectional view. [10] The method of claim 1, wherein the heat insert is made of copper or a copper alloy. [11] The method of claim 1, wherein the package substrate is an isolation lead frame having a high-voltage sector with a first set of terminals coupled to the thermal insert and a low-voltage sector with a second set of terminals spaced from the high-voltage sector and electrically insulated. [12] The method of claim 11, wherein the insulation lead frame is made of copper, aluminum, stainless steel, steel or alloys thereof. [13] The method of claim 12, wherein the insulation lead frame is made of copper or a copper alloy. [14] Facility comprising: a package substrate having a circuit board-side surface and an opposite top surface, and a thermal insert coupled to the package substrate, and wherein the thermal insert is configured to conduct a current between the terminals of the package substrate; a first magnetic shield mounted on top of the package substrate, the first magnetic shield including a die mounting area facing the circuit board side surface, the die mounting area being exposed in an opening and not covered by the package substrate and the thermal insert; a semiconductor die having a Hall element and mounted on the die mounting area, the semiconductor die being flip-chip mounted and facing away from the board-side surface of the package substrate; a second magnetic shield mounted to the package substrate and the thermal insert, the second magnetic shield having a base portion and a cantilever portion extending over a portion of the semiconductor die including the Hall element, while the bonding pads on the semiconductor die remain exposed and are not covered by the second magnetic shield; electrical connections consisting of wire bonds or tape bonds between the bonding pads of the semiconductor die and the connection elements on the package substrate; and a molding compound covering the electrical interconnections, the semiconductor die, portions of the package substrate, the first magnetic shield, and the second magnetic shield, wherein a portion of the thermal insert is kept free and not covered by the molding compound, thereby forming a thermal interface for a semiconductor device package. [15] The device according to claim 14, wherein the first magnetic shield and the second magnetic shield are made of a magnetic material. [16] The device of claim 15, wherein the magnetic material comprises a nickel ferrite (NiFe), a nickel-zinc ferrite (NiZnFe) or a manganese-zinc ferrite (MnZnFe). [17] The device of claim 14, wherein the package substrate comprises a lead frame having a first set of terminal elements in a high-voltage sector coupled to the thermal insert and a second set of terminal elements in a low-voltage sector coupled to the semiconductor die by the electrical connections. [18] The device of claim 17, wherein the first set of terminal elements of the high-voltage sector of the lead frame and the thermal insert are configured to transport a current to a portion of the thermal insert located proximate the Hall sensor on the semiconductor die. [19] Device with Hall current sensors, comprising: a lead frame comprising a first group of lead elements in a high-voltage sector and a second group of lead elements in a low-voltage sector electrically insulated from the high-voltage sector, the lead frame having a circuit board-side surface and an opposite top side; a thermal insert coupled to the first group of terminal elements of the high-voltage sector, the thermal insert configured to conduct a current between the terminals formed from the first group of terminal elements of the high-voltage sector; a first magnetic shield mounted on top of the lead frame and including a die mounting area in an opening that is exposed and not covered by the lead frame and the thermal insert; a semiconductor die having a Hall element and mounted on the die mounting area, the semiconductor die being flip-chip mounted and facing away from the board-side surface of the package substrate; a second magnetic shield mounted to the heat insert, the second magnetic shield having a base portion and a cantilevered portion extending over a portion of the semiconductor die including the Hall element, while the bonding pads on the semiconductor die remain exposed and are not covered by the second magnetic shield; electrical connections comprising wire bonds or ribbon bonds between the bonding pads of the semiconductor die and the second group of terminal elements on the low-voltage sector of the lead frame; and a molding compound covering the electrical connections, the semiconductor die, portions of the lead frame, the first magnetic shield, and the second magnetic shield, wherein a portion of the heat insert is kept free and not covered by the molding compound, thereby forming a thermal interface for a semiconductor device package. [20] The Hall current sensor device of claim 19, wherein the first magnetic shield and the second magnetic shield comprise a nickel ferrite (NiFe), a nickel-zinc ferrite (NiZnFe) or a manganese-zinc ferrite (MnZnFe).

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