Machine arrangement and vehicle

Abstract

A machine arrangement (20) comprises an electric machine (31), a first pulse inverter (41) and a second pulse inverter (42), wherein the electric machine (31) comprises a stator arrangement (33) and a rotor arrangement (34), wherein the stator arrangement (33) comprises a stator core (35), a first winding arrangement (36) and a second winding arrangement (37), wherein the first winding arrangement (36) is configured as a multiphase winding arrangement with at least three first windings (361, 362, 363) and with at least three first winding terminals (3611, 3621, 3631), wherein the second winding arrangement (37) is configured as a multiphase winding arrangement with at least three second windings (371, 372, 373) and with at least three second winding terminals (3711, 3721, 3731).wherein the first pulse inverter (41) is a multi-phase pulse inverter and wherein the second pulse inverter (42) is configured as a two-phase pulse inverter. The first winding arrangement (36) and the second winding arrangement (37) do not include a common winding.

Description

[0001] The invention relates to a machine arrangement and a vehicle.

[0002] DE 10 2020 126 054 A1 shows an electrical machine having two winding arrangements with three phases, with each of the two winding arrangements having an inverter assigned to it.

[0003] The CN 115 158 040 A shows an electric machine that has two winding arrangements with three phases.

[0004] DE 10 2023 200 118 A1 shows a T-type power converter with three stages.

[0005] DE 10 2014 013 195 A1 shows a six-phase electric machine for a hybrid vehicle.

[0006] GB 2 624 533 A discloses an electrical system with a winding arrangement in which the windings have a first winding section and a second winding section, wherein a first converter produces a first alternating current in the first winding section and in the second winding section, and wherein a second converter produces a second alternating current exclusively in the second winding section. The first converter is used, for example, at high power, and the second converter at low power.

[0007] The subsequently published DE 10 2023 132 712 A1 shows a drive system for a vehicle comprising an electric motor configured to generate torque to propel the vehicle.

[0008] DE 44 39 932 A1 discloses an inverter device with isolated DC current sources, which are provided separately for a first inverter and a second inverter, two DC current sources whose terminals are connected in parallel by a choke coil to reduce the in-phase current.

[0009] DE 10 2017 203 233 A1 shows an inverter with an AC voltage connection, a DC voltage connection and a module mount.

[0010] DE 10 2011 122 576 A1 shows a superimposed structure of a power converter for reducing heat sinks.

[0011] DE 10 2021 211 409 A1 discloses an inverter structure of an electronic module for an electric drive of a vehicle, in which the inverter has at least one current phase arranged along a first axis and each current phase has an input-side current connection for coupling in a DC input current generated by an energy source.

[0012] DE 10 2021 003 941 A1 discloses a three- or multi-stage inverter circuit for controlling a multi-phase electrical machine, with two supply connections that can be coupled to a first and a second supply potential of a voltage supply.

[0013] It is therefore an object of the invention to provide a new machine arrangement and a new vehicle.

[0014] These tasks are solved by the subject matter of the independent claim and the subsidiary claim.

[0015] A machine arrangement comprises an electric machine, a first pulse inverter, and a second pulse inverter, wherein the electric machine comprises a stator arrangement and a rotor arrangement, the stator arrangement comprising a first winding arrangement and a second winding arrangement, the first winding arrangement being configured as a multiphase winding arrangement with at least three first windings and at least three first winding terminals, the second winding arrangement being configured as a multiphase winding arrangement with at least three second windings and at least three second winding terminals, the first pulse inverter comprising a first DC terminal, a second DC terminal, a third DC terminal, and at least three first pulse inverter terminals for connection to the first winding terminals.wherein the second pulse inverter has a fourth DC terminal, a fifth DC terminal and at least three second pulse inverter terminals for connection to the second winding terminals, wherein the first pulse inverter terminals are each connected to the first DC terminal via a first semiconductor switch arrangement, to the second DC terminal via a second semiconductor switch arrangement and to the third DC terminal via a third semiconductor switch arrangement,The second pulse inverter connections are each connected to the fourth DC connection via a fourth semiconductor switch arrangement and to the fifth DC connection via a fifth semiconductor switch arrangement. Such a machine arrangement enables drive efficiency during normal operation while simultaneously providing high maximum power when required. Using only one winding arrangement in combination with two pulse inverters leads to charging and parallelization losses. Therefore, using two winding arrangements has proven to be very advantageous for this solution. Compared to a solution with two multi-stage pulse inverters, the present solution offers the advantage of less complex control of the two pulse inverters.

[0016] According to a preferred embodiment, the machine arrangement has a first capacitor and a second capacitor, wherein the third DC voltage terminal is connected to the first DC voltage terminal via the first capacitor and to the second DC voltage terminal via the second capacitor. This allows an average potential to be generated.

[0017] According to a preferred embodiment, the machine arrangement comprises first modules, each of which includes the first, second, and third semiconductor switch arrangements associated with one of the first pulse inverter connections. Such modules can be cooled effectively and allow for a space-saving arrangement.

[0018] According to a preferred embodiment, the machine arrangement comprises second modules, each of which includes the fourth and fifth semiconductor switch arrangements associated with one of the second pulse inverter connections. Such modules can be cooled effectively and allow for a space-saving arrangement.

[0019] According to a preferred embodiment, the first semiconductor switch arrangement has a first current-carrying capacity, the second semiconductor switch arrangement has a second current-carrying capacity, and the third semiconductor switch arrangement has a third current-carrying capacity, wherein the third current-carrying capacity is lower than the first current-carrying capacity and the third current-carrying capacity is lower than the second current-carrying capacity. This enables three-stage operation at low power requirements with low switching losses and two-stage operation at high power.

[0020] According to a preferred embodiment, the first semiconductor switch arrangement comprises a first number of first semiconductor switches connected in parallel, and the second semiconductor switch arrangement comprises a second number of second semiconductor switches connected in parallel, wherein the first number is at least two, and wherein the second number is at least two. The parallel connection allows for higher maximum currents.

[0021] According to a preferred embodiment, the third semiconductor switch arrangement comprises a third number of third semiconductor switches connected in parallel, wherein the third number is smaller than the first number, and wherein the third number is smaller than the second number. This reduces the circuit losses in the third semiconductor switch arrangement, although it is not used at very high power levels.

[0022] According to a preferred embodiment, the first number is located in at least one first area, which first area is selected from a first group of areas consisting of: - Range between 2 and 10 semiconductor switches, - Range between 3 and 9 semiconductor switches, - Range between 4 and 8 semiconductor switches, and - Range between 4 and 7 semiconductor switches.

[0023] These ranges represent a preferred compromise between the possible maximum current and the level of switching losses.

[0024] According to a preferred embodiment, the second number is located in at least a second area, which second area is selected from a second group of areas consisting of: - Range between 2 and 10 semiconductor switches, - Range between 3 and 9 semiconductor switches, - Range between 4 and 8 semiconductor switches, and - Range between 4 and 7 semiconductor switches.

[0025] According to a preferred embodiment, the first number and the second number are the same. This is advantageous so that approximately the same maximum currents can flow through the first semiconductor switch arrangement and the second semiconductor switch arrangement.

[0026] According to a preferred embodiment, the first winding arrangement and the second winding arrangement are each configured as a star connection or a delta connection. Mixed combinations of star and delta connections are also possible.

[0027] According to a preferred embodiment, the machine arrangement includes a control device for controlling the first pulse inverter and the second pulse inverter. The control device can thus coordinate the control signal.

[0028] According to a preferred embodiment, the control device is configured to operate the first pulse inverter as a multi-stage pulse inverter in a first state. Such operation is very efficient and advantageous for low power levels.

[0029] According to a preferred embodiment, the second pulse inverter is inactive in the first state. Since the second pulse inverter can only be operated in two stages, inactivity is advantageous.

[0030] According to a preferred embodiment, the control device is configured to operate the first pulse inverter and the second pulse inverter as two-stage pulse inverters in a second state. The third semiconductor switch arrangement thus remains non-conductive. This operation enables a very high power output of the machine arrangement.

[0031] According to a preferred embodiment, the control device is configured to drive the first pulse inverter and the second pulse inverter with an antiphase clocking in the second state in order to improve electromagnetic compatibility.

[0032] A vehicle features such a machine configuration. Under normal operating conditions, such a vehicle can drive very economically in the first state. However, when high performance is required, such as during an overtaking maneuver, the second state can be activated. This machine configuration expands the vehicle's range of applications.

[0033] Further details and advantageous embodiments of the invention will become apparent from the exemplary embodiments described below and illustrated in the drawings, which are in no way to be understood as limiting the invention, as well as from the dependent claims. It is understood that the features mentioned above and those to be explained below can be used not only in the combinations specified, but also in other combinations or individually, without departing from the scope of the present invention. It shows: Fig. 1 in a schematic representation a vehicle with a first embodiment of a machine arrangement, Fig. 2 in a schematic representation a vehicle with a second embodiment of a machine arrangement, Fig. 3 a first pulse inverter, Fig. 4 a second pulse inverter, Fig. 5 a control of the machine arrangement, Fig. 6 a first embodiment of a semiconductor switch arrangement, and Fig. 7 a second embodiment of a semiconductor switch arrangement.

[0034] In the following, identical or similarly functioning parts are designated with the same reference symbols and are usually described only once. The description builds upon itself across figures to avoid unnecessary repetition.

[0035] Fig. Figure 1 shows a schematically indicated vehicle 10 with a machine arrangement 20.

[0036] The machine arrangement 20 has an electric machine 31, a first pulse inverter 41 and a second pulse inverter 42.

[0037] The electric machine 31 has a stator arrangement 33 and a rotor arrangement 34.

[0038] The stator arrangement 33 has a stator core 35, a first winding arrangement 36 and a second winding arrangement 37.

[0039] The stator core 35 is preferably designed as a laminated core.

[0040] The winding arrangement 36 is designed as a multi-phase winding arrangement with at least three windings 361, 362, 363 and with at least three winding terminals 3611, 3621, 3631.

[0041] The winding arrangement 37 is designed as a multi-phase winding arrangement with at least three windings 371, 372, 373 and with at least three winding terminals 3711, 3721, 3731.

[0042] The windings are also called phases, and each can have one or more winding strands.

[0043] In the exemplary embodiment, windings 361, 362, 363 and windings 371, 372, 373 are each connected in a star configuration. Each star configuration has a star point, which can be connected to an additional winding terminal.

[0044] The winding connections 3611, 3621, 3631 are each connected to the pulse inverter 41.

[0045] The winding connections 3711, 3721, 3731 are each connected to the pulse inverter 42.

[0046] The pulse inverter 41 has a DC voltage connection 11, a DC voltage connection 12 and at least three pulse inverter connections 411, 412, 413 for connection to the winding connections 3611, 3621, 3631. It is designed as a multi-stage or three-stage pulse inverter.

[0047] The pulse inverter 42 has a DC voltage connection 15, a DC voltage connection 16 and at least three pulse inverter connections 421, 422, 423 for connection to the winding connections 3711, 3721, 3731. It is designed as a two-stage pulse inverter.

[0048] The DC terminals 11, 12 are used for connection to a DC voltage source 13. The DC voltage source 13 can be, for example, a battery or a DC power supply.

[0049] The DC terminals 15, 16 are used for connection to a DC voltage source 17. The DC voltage source 17 can be, for example, a battery or a DC power supply.

[0050] A control device 90 is provided for controlling the pulse inverters 41, 42.

[0051] Fig. Figure 2 shows an alternative embodiment of the machine arrangement 20. In contrast to the embodiment of Fig. 1. The windings 361, 362, 363 and the windings 371, 372, 373 are each connected in a delta configuration.

[0052] The windings 361, 362, 363 and the windings 371, 372, 373 can therefore each be connected in a star or delta configuration.

[0053] Fig. Figure 3 shows an embodiment of the pulse inverter 41.

[0054] In addition to the DC voltage connections 11, 12, an additional DC voltage connection 63 is provided, which provides an additional potential.

[0055] The pulse inverter 41 has a capacity of 61 and a capacity of 62.

[0056] The DC terminal 63 is connected to the DC terminal 11 via the capacitor 61 and to the DC terminal 12 via the capacitor 62.

[0057] With equal capacitances 61, 62, the potential at the DC terminal 63 is approximately in the middle of the potentials at the DC terminals 11 (e.g. HV+ in a high-voltage system) and 12 (e.g. HV- in a high-voltage system), i.e. approximately at (HV+ - HV-) / 2.

[0058] The pulse inverter terminals 411, 412, 413 are each connected to the DC voltage terminal 11 via a semiconductor switch arrangement 71, to the DC voltage terminal 12 via a semiconductor switch arrangement 72 and to the DC voltage terminal 63 via a semiconductor switch arrangement 73.

[0059] This wiring configuration is known in English as 3 Level T-Type.

[0060] In the exemplary embodiment, the semiconductor switches of the semiconductor switch assemblies 71, 72 are unidirectional, so that freewheeling diodes 77, 78 are connected antiparallel to prevent damage to the semiconductor switch assemblies 71, 72 in the event of backfeeding into the intermediate circuit. Alternatively, bidirectional semiconductor switches can be used.

[0061] The semiconductor switch arrangement 73 is preferably designed to be bidirectional, thus enabling current flow in both directions when switched in a conductive manner.

[0062] The pulse inverter 41 comprises modules 81, each module 81 comprising the first semiconductor switch arrangement 71, second semiconductor switch arrangement 72, and third semiconductor switch arrangement 73, respectively, assigned to one of the pulse inverter terminals 411, 412, 413. The use of modules 81 facilitates the interconnection and cooling of the semiconductor switches contained in the modules 81.

[0063] The pulse inverter 41 is designed as a multi-stage pulse inverter, in the exemplary embodiment as a three-stage pulse inverter.

[0064] A two-stage pulse-controlled inverter can provide two different potentials at each terminal 411, 421, 431, for example, HV+ and HV- in a high-voltage system. It can also switch each terminal 411, 421, 431 to a high-impedance state by making the semiconductor switching arrangements of the pulse inverter non-conductive. However, this is not referred to as an additional stage. The pulse inverter 42 is designed as a two-stage pulse inverter.

[0065] The multi-level pulse-controlled inverter 41 can provide at least three different potentials at the respective terminals 411, 421, 431, for example in a high-voltage system HV+, HV- and (HV+ - HV-) / 2.

[0066] The multi-stage pulse inverter 41 can be operated as a three-stage pulse inverter (with switching of the semiconductor switch arrangement 73) or as a two-stage pulse inverter (without conducting circuit of the semiconductor switch arrangement 73) by appropriate control.

[0067] The semiconductor switch assembly 71 has a first current carrying capacity, the semiconductor switch assembly 72 has a second current carrying capacity, and the semiconductor switch assembly 73 has a third current carrying capacity.

[0068] The current-carrying capacity of a semiconductor switch assembly is the maximum electrical current it can safely transmit without overheating or damage. Current-carrying capacity is also referred to as current-handling capability. When determining current-carrying capacity, a load current is typically considered for a duration of 10 seconds.

[0069] Preferably, the third current-carrying capacity is lower than the first, and the third is lower than the second. Studies have shown that three-stage operation is advantageous for low power levels. The lower design of the third current-carrying capacity reduces the number of components required and results in lower circuit losses. At high power levels, however, two-stage operation is advantageous, and therefore high first and second current-carrying capacities are beneficial.

[0070] Alternatively, the third current-carrying capacity can be chosen to be the same as the first and second current-carrying capacities.

[0071] Fig. Figure 4 shows an embodiment of the pulse inverter 42.

[0072] In this device, the pulse inverter connections 421, 422, 423 are each connected to the DC voltage connection 15 via a semiconductor switch arrangement 74 and to the DC voltage connection 16 via a semiconductor switch arrangement 75.

[0073] This corresponds to a bridge circuit.

[0074] In the exemplary embodiment, the semiconductor switches of the semiconductor switch assemblies 74, 75 are unidirectional, so that freewheeling diodes 79, 80 are connected antiparallel to prevent damage to the semiconductor switch assemblies 74, 75 in the event of backfeeding into the intermediate circuit. Alternatively, bidirectional semiconductor switches can be used.

[0075] The pulse inverter 42 has modules 82, wherein the modules 82 each comprise the semiconductor switch arrangement 74 and semiconductor switch arrangement 75 assigned to one of the second pulse inverter terminals 411, 412, 413.

[0076] Fig. Figure 5 shows a schematic representation of the winding arrangements 36, 37 and two modules 81, 82.

[0077] The pulse inverter connection 411 of module 81 is connected to the winding connection 3611, and the pulse inverter connection 421 of module 82 is connected to the winding connection 3711.

[0078] The semiconductor switch arrangement 73 comprises two semiconductor switch arrangements 91 and 92 connected in series and arranged in opposite directions. Semiconductor switch arrangement 91 enables current flow from left to right via a semiconductor switch and an opposite current flow via the antiparallel diode. Semiconductor switch arrangement 92 enables current flow from right to left via a semiconductor switch and an opposite current flow via the antiparallel diode. By appropriately switching the semiconductor switch arrangements 91 and 92, current flow in the corresponding direction or in both directions is thus possible.

[0079] The designations L5 and L2 are shown as examples on the respective semiconductor switch arrangements 71, 72, 73, 74, and 75. L5, for example, indicates a logic semiconductor switch arrangement in which five semiconductor switches are connected in parallel. L2, accordingly, indicates two semiconductor switches connected in parallel.

[0080] For example, if the five semiconductor switches are designed for a current (square mean) of A each RMS = 120 A, a total current (square mean) of A can be achieved. RMS = 600 A flow, with two semiconductor switches corresponding to A RMS = 240 A.

[0081] In the exemplary embodiment, the semiconductor switch arrangement 73 (L2) has two semiconductor switches connected in parallel in the sub-semiconductor switch arrangement 91 and two more semiconductor switches connected in parallel in the sub-semiconductor switch arrangement 92.

[0082] The semiconductor switches shown are MOSFETs (metal-oxide-semiconductor field-effect transistors). Other semiconductor switches can also be used, for example insulated-gate bipolar transistors (IGBTs) or bipolar transistors.

[0083] Fig. Figure 6 shows an example of an L5 semiconductor switch arrangement 71 in which five semiconductor switches 711, 712, 713, 714, 715 are connected in parallel to allow a high current flow.

[0084] Fig. Figure 7 shows an example of an L2 semiconductor switch arrangement 73 in which two semiconductor switches 731, 732 are connected in parallel. Provided these semiconductor switches are identical to the semiconductor switches 711 to 715 of Fig. 6, the possible maximum current is lower than with the L5 semiconductor switch arrangement 71 of Fig. 6.

[0085] With reference to Fig. 5 preferably has the semiconductor switch arrangement 71 having a first number of semiconductor switches (L5) connected in parallel to each other, the semiconductor switch arrangement 72 having a second number of semiconductor switches (L5) connected in parallel to each other, wherein the first number is at least two, and wherein the second number is at least two.

[0086] Preferably the first number and the second number are the same, since in two-stage operation the current must be able to flow alternately through both semiconductor switch arrangements 71, 72.

[0087] Preferably, the semiconductor switch arrangement 73 has a third number of semiconductor switches (L2) connected in parallel to each other, wherein the third number is smaller than the first number, and wherein the third number is smaller than the second number.

[0088] A large number of semiconductor switches allows for a high maximum current. However, the circuit losses are also higher due to the large number of switches.

[0089] Tests have shown that the semiconductor switch arrangement 73 required for three-stage operation is needed at a lower power, so that the number of semiconductor switches connected in parallel can be low to enable efficient operation.

[0090] In contrast, the semiconductor switch arrangements 71, 72 are required in two-stage operation at high power levels, and therefore it is advantageous if the first number and second number are higher than the third number.

[0091] The first number is preferably located in at least one first area, which first area is selected from a first area group consisting of: - Range between 2 and 10 semiconductor switches, - Range between 3 and 9 semiconductor switches, - Range between 4 and 8 semiconductor switches, and - Range between 4 and 7 semiconductor switches.

[0092] The second number is preferably located in at least one second area, which second area is selected from a second group of areas consisting of: - Range between 2 and 10 semiconductor switches, - Range between 3 and 9 semiconductor switches, - Range between 4 and 8 semiconductor switches, and - Range between 4 and 7 semiconductor switches.

[0093] In these areas, the ratio between the maximum possible current and the circuit losses is particularly advantageous.

[0094] The following are explanations regarding the preferred control of the pulse inverters 41, 42 from Fig. 1 and Fig. 2.

[0095] The control device 90 is preferably configured to operate the first pulse inverter 41 as a multi-stage pulse inverter in a first state Z1.

[0096] This first state is preferred at low power levels. The pulse inverter 42 is not required in this case. High power is not necessary for a vehicle 10 operating at lower speeds. The multi-stage operation, thanks to the additional voltage stage, enables low differential voltages between the winding terminals and thus also low switching losses in the pulse inverter 41. This gives the vehicle 10 a long range and high efficiency.

[0097] The control device 90 is preferably configured to operate the pulse inverter 41 and the pulse inverter 42 as two-stage pulse inverters in a second state Z2.

[0098] The second state allows for very high performance with the same machine arrangement, if required.

[0099] The vehicle 10 can therefore be operated very efficiently with lower power in the first state, while in the second state it can generate very high power.

[0100] Preferably, the control device 90 is configured to control the pulse inverter 41 and the pulse inverter 42 with an antiphase clocking in the second state Z2 in order to improve electromagnetic compatibility.

[0101] Naturally, various variations and modifications are possible within the scope of the present invention.

[0102] The windings can each have parallel strands, which should be symmetrical.

[0103] The winding arrangements 36, 37 are not electrically coupled, but only via the magnetic flux.

[0104] The winding arrangements 36, 37 can be offset from each other, but do not have to be.

[0105] Preferably the stator arrangement 33 or the stator core has stator slots.

[0106] Preferably, the windings of the winding arrangements 36, 37 run through the stator slots.

[0107] Preferably, the windings of the winding arrangements 36, 37 run at least partially through the same stator slots; thus, at least partially, winding wires of both the winding arrangement 36 and the winding arrangement 37 are provided in the stator slots. This allows a phase shift of 0° between the winding arrangements 36, 37 to be achieved.

Claims

[1] Machine arrangement (20) comprising an electric machine (31), a first pulse inverter (41) and a second pulse inverter (42), wherein the electric machine (31) has a stator arrangement (33) and a rotor arrangement (34), wherein the stator arrangement (33) comprises a first winding arrangement (36) and a second winding arrangement (37), wherein the first winding arrangement (36) is designed as a multi-phase winding arrangement with at least three first windings (361, 362, 363) and with at least three first winding terminals (3611, 3621, 3631), wherein the second winding arrangement (37) is designed as a multi-phase winding arrangement with at least three second windings (371, 372, 373) and with at least three second winding terminals (3711, 3721, 3731), wherein the first winding arrangement (36) and the second winding arrangement (37) do not include a common winding, wherein the first pulse inverter (41) is designed as a multi-stage pulse inverter, has a first DC voltage connection (11), a second DC voltage connection (12), a third DC voltage connection (63) and at least three first pulse inverter connections (411, 412, 413) for connection to the first winding connections (3611, 3621, 3631), wherein the second pulse inverter (42) is designed as a two-stage pulse inverter, has a fourth DC voltage connection (15), a fifth DC voltage connection (16) and at least three second pulse inverter connections (421, 422, 423) for connection to the second winding connections (3711, 3721, 3731), wherein the first pulse inverter terminals (411, 412, 413) are each connected via a first semiconductor switch arrangement (71) to the first DC voltage terminal (11), via a second semiconductor switch arrangement (72) to the second DC voltage terminal (12) and via a third semiconductor switch arrangement (73) to the third DC voltage terminal (63), wherein the second pulse inverter terminals (421, 422, 423) are each connected to the fourth DC terminal (15) via a fourth semiconductor switch arrangement (74) and to the fifth DC terminal (16) via a fifth semiconductor switch arrangement (75). [2] Machine arrangement (20) according to claim 1, which has a first capacitor (61) and a second capacitor (62), wherein the third DC terminal (63) is connected via the first capacitor (61) to the first DC terminal (11) and via the second capacitor (62) to the second DC terminal (12). [3] Machine arrangement (20) according to claim 1 or 2, comprising first modules (81), wherein the first modules (81) each comprise the first semiconductor switch arrangement (71), second semiconductor switch arrangement (72) and third semiconductor switch arrangement (73) associated with one of the first pulse inverter connections (411, 412, 413). [4] Machine arrangement (20) according to one of the preceding claims, which has second modules (82), wherein the second modules (82) each comprise the fourth semiconductor switch arrangement (74) and fifth semiconductor switch arrangement (75) assigned to one of the second pulse inverter connections (411, 412, 413). [5] Machine arrangement (20) according to one of the preceding claims, wherein the first semiconductor switch arrangement (71) has a first current carrying capacity, wherein the second semiconductor switch arrangement (72) has a second current carrying capacity, wherein the third semiconductor switch arrangement (73) has a third current carrying capacity, wherein the third current carrying capacity is lower than the first current carrying capacity, and wherein the third current carrying capacity is lower than the second current carrying capacity. [6] Machine arrangement (20) according to one of the preceding claims, wherein the first semiconductor switch arrangement (71) has a first number of first semiconductor switches (711, 712, 713, 714, 715) connected in parallel to each other, wherein the second semiconductor switch arrangement (72) has a second number of second semiconductor switches connected in parallel to each other, wherein the first number is at least two, and wherein the second number is at least two. [7] Machine arrangement (20) according to claim 6, wherein the third semiconductor switch arrangement (73) has a third number of third semiconductor switches (731, 732) connected in parallel to each other, wherein the third number is smaller than the first number, and wherein the third number is smaller than the second number. [8] Machine arrangement (20) according to claim 6 or 7, wherein the first number is located in at least one first area, which first area is selected from a first area group consisting of: - Range between 2 and 10 semiconductor switches, - Range between 3 and 9 semiconductor switches, - Range between 4 and 8 semiconductor switches, and - Range between 4 and 7 semiconductor switches. [9] Machine arrangement (20) according to one of claims 6 to 8, wherein the second number is located in at least a second area, which second area is selected from a second area group consisting of: - Range between 2 and 10 semiconductor switches, - Range between 3 and 9 semiconductor switches, - Range between 4 and 8 semiconductor switches, and - Range between 4 and 7 semiconductor switches. [10] Machine arrangement (20) according to one of claims 6 to 9, wherein the first number and the second number are the same. [11] Machine arrangement (20) according to one of the preceding claims, wherein the first winding arrangement (36) and the second winding arrangement (37) are each configured as a star connection or as a delta connection. [12] Machine arrangement (20) according to one of the preceding claims, comprising a control device (90) for controlling the first pulse inverter (41) and the second pulse inverter (42). [13] Machine arrangement (20) according to claim 12, wherein the control device (90) is configured to operate the first pulse inverter (41) as a multi-stage pulse inverter in a first state (Z1). [14] Machine arrangement (20) according to claim 12 or 13, wherein the control device (90) is configured to operate the first pulse inverter (41) and the second pulse inverter (42) as two-stage pulse inverters in a second state (Z2). [15] Machine arrangement (20) according to claim 14, wherein the control device (90) is configured to drive the first pulse inverter (41) and the second pulse inverter (42) with an antiphase clocking in the second state (Z2) in order to improve electromagnetic compatibility. [16] Vehicle (10) comprising a machine arrangement (20) according to any of the preceding claims.

Images