Semiconductor structure with magnetic tunnel junction and inductance, as well as methods for its fabrication

Abstract

The invention provides a semiconductor structure with a magnetic tunneling junction (MTJ) and an inductor. The semiconductor structure comprises a substrate, a cell region, and an inductor region defined on the substrate, wherein a magnetic tunneling junction (MTJ) is arranged in the cell region and the MTJ comprises a first MTJ material layer. An inductor is arranged in the inductor region, the inductor comprising a multilayer structure, the multilayer structure comprising at least one second MTJ material layer, wherein the material of the first MTJ material layer is the same as that of the second MTJ material layer, and viewed in cross-section, the first MTJ material layer extends along a horizontal direction, and the second MTJ material layer comprises one horizontal part and two vertical parts, the vertical part extending along a vertical direction.

Description

BACKGROUND OF THE INVENTION 1. AREA OF THE INVENTION

[0001] The present invention relates to a semiconductor structure integrating a magnetoresistive direct access memory (MRAM) and an inductor, and a manufacturing method therefor, in particular a semiconductor structure with an inductor capable of storing high magnetic energy, and a manufacturing method therefor. 2. DESCRIPTION OF THE STATE OF THE ART

[0002] Many modern electronic devices have electronic memory. Electronic memory can be volatile or non-volatile. Non-volatile memory retains its stored data even without power, while volatile memory loses its data when power is lost. Magnetoresistive random-access memory (MRAM) has great potential for the next generation of non-volatile memory technology due to its advantages over current electronic memory.

[0003] Currently, multi-channel memory (MRAM) chips are not integrated with inductors to enable radio frequency (RF) applications. Most inductors are assembled with MRAM chips outside the chip, increasing costs. However, external inductors require additional PCB space. Therefore, if MRAM chips and inductors can be integrated on a single process and chip, the level of integration can be significantly improved and costs reduced.

[0004] MRAMs and inductances are known from publications US 9 397 139 B1, US 2011 / 0 233 695 A1, DE 100 40 811 A1 and US 2006 / 0 273 418 A1.

[0005] The task is to improve corresponding semiconductor structures.

[0006] The problem is solved by the semiconductor structure according to claim 1 and by the method according to claim 10. Further embodiments are set out in the dependent claims. SUMMARY OF THE INVENTION

[0007] The invention provides a semiconductor structure comprising: a magnetic tunneling junction (MTJ) and an inductor, with a substrate, wherein a cell region and an inductor region defined on the substrate are arranged adjacent to the cell region, a magnetic tunneling junction (MTJ) is arranged in the cell region, the MTJ comprising a first MTJ material layer, and an inductor is arranged in the inductor region, the inductor comprising a multilayer structure, the multilayer structure comprising at least a second MTJ material layer, the material of the first MTJ material layer being the same as that of the second MTJ material layer, and viewed in a cross-sectional view, the first MTJ material layer extending along a horizontal direction, and the second MTJ material layer comprising a horizontal part and two vertical parts, the vertical part extending along a vertical direction.

[0008] The invention also provides a method for fabricating a semiconductor structure with a magnetic tunnel junction and an inductor, comprising the following steps: providing a substrate, wherein a cell region and an inductor region defined on the substrate are arranged adjacent to the cell region; forming a magnetic tunnel junction (MTJ) in the cell region, wherein the MTJ comprises a first MTJ material layer; and forming an inductor in the inductor region, wherein the inductor comprises a multilayer structure, the multilayer structure comprising at least a second MTJ material layer, wherein the material of the first MTJ material layer is the same as that of the second MTJ material layer; and, viewed from a cross-section, the first MTJ material layer extends along a horizontal direction, and the second MTJ material layer comprises a horizontal part and two vertical parts.and the vertical part extends along a vertical direction.

[0009] The invention provides a semiconductor structure integrated with an MRAM and an inductor, as well as a manufacturing process for it. In this process, an inductor is formed during the MRAM fabrication process, thus eliminating process steps. Furthermore, the inductors are arranged vertically and penetrate the multilayer dielectric layers vertically, effectively utilizing the unused space within the stacked dielectric layers. Additionally, the inductor of the invention is surrounded by a helical coil structure, which is formed by connecting a plurality of notched metal layers and conductive vias in series. This allows for the generation of a larger electric field when the coil structure is electrified, thereby enhancing the magnetic energy stored in the inductor.Therefore, the invention has the effect of improving the quality of semiconductors and simplifying the manufacturing process.

[0010] Preferred embodiments are shown in the various figures and drawings. BRIEF DESCRIPTION OF THE FIGURES

[0011] To facilitate understanding of the following explanations, the reader may refer to the drawings and their detailed descriptions while reading the present invention. Based on the specific embodiments in this description and with reference to the corresponding drawings, the specific embodiments of the present invention are explained in detail, and the operating principle of the specific embodiments of the present invention is presented. Furthermore, for the sake of simplicity, the features in the drawings may not be shown to scale, so that the dimensions of some features are intentionally enlarged or reduced in some drawings. The Fig. 1 to Fig. Figure 8 shows schematic cross-sectional views of a semiconductor structure with integrated MRAM and inductance according to an embodiment of the present invention. Fig. Figure 9 is a top view of the MTJ material layer and the coil structure in the inductance area of ​​the present invention. Fig. Figure 10 is a schematic view illustrating the structure of the coil structure C of the present invention. DETAILED DESCRIPTION

[0012] Preferred embodiments are described below for a better understanding of the present invention. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements to clarify the content and the effects to be achieved.

[0013] It should be noted that the drawings are for illustrative purposes only and are not necessarily to scale. The scale may be further modified depending on the specific design considerations. When the words "top" or "bottom" are used to describe the relationship between components in the text, it is well known in the art and should be clearly understood that these words refer to relative positions that can be reversed to obtain a similar structure, and these structures should therefore not be excluded from the scope of the claims of the present invention.

[0014] Although the terms "first," "second," "third," etc., are used in the context of the present invention to describe elements, components, regions, layers, and / or sections, such elements, components, regions, layers, and / or sections should not be limited by such terms. These terms are used only to distinguish one element, component, region, layer, and / or block from another. They do not imply or represent any prior ordinal number of the element, nor do they represent the order of arrangement of one element and another element, or the sequence of manufacturing methods.Therefore, the first element, first component, first area, first layer or first block referred to below can also be called the second element, second component, second area, second layer or second block, without this deviating from the specific embodiments of the present invention.

[0015] The terms “approximately” or “essentially” used in the present invention generally mean that the quantity is within 20% of a certain value or range, e.g., within 10%, 5%, 3%, 2%, 1%, or 0.5%. It should be noted that the quantities provided in the specification are approximate; that is, the meaning of “approximately” or “essentially” can also be implied without explicitly stating “approximately” or “essentially”.

[0016] The terms “coupling” and “electrical connection” used in the present invention encompass all direct and indirect means of electrical connection. For example, when it is described that the first component is coupled to the second component, this means that the first component may be directly electrically connected to the second component or indirectly electrically connected to the second component via other devices or connecting means.

[0017] Although the present invention is described below with reference to specific embodiments, the inventive principles of the present invention can also be applied to other embodiments. Furthermore, certain details are omitted so as not to obscure the spirit of the present invention, and these omitted details are known to a person skilled in the art.

[0018] It will be directed to the Fig. 1 to Fig. Reference is made to Figure 8, which illustrates schematic cross-sectional structures of a semiconductor structure with integrated MRAM and an inductor of an embodiment of the present invention. As in Fig. As illustrated in Figure 1, a substrate S is first provided, e.g., a silicon substrate or a material layer containing electronic components (e.g., transistors). A multilayer structure is then sequentially formed on the substrate S. Fig. As an example, Figure 1 comprises a mask layer 10, a first dielectric layer IMD1, a mask layer 12, a second dielectric layer IMD2, a mask layer 14, a third dielectric layer IMD3, a mask layer 16, and a fourth dielectric layer 18. The materials of the first dielectric layer IMD1, the second dielectric layer IMD2, the third dielectric layer IMD3, and the fourth dielectric layer 18 are, for example, silicon oxide, while the materials of the mask layers 10, 12, 14, and 16 are, for example, silicon nitride or silicon oxynitride, but the present invention is not limited thereto. Furthermore, the number of components in the mask layer can be varied. Fig. The masking and dielectric layers illustrated in Figure 1 can be adjusted according to actual requirements. In other words, in other embodiments of the present invention, the semiconductor structure can also contain more or fewer masking and dielectric layers, and these variations are also within the scope of the present invention.

[0019] Mask layer 10 and the first dielectric layer IMD1 contain conductive vias V1 and the first metal layer M1; mask layer 12 and the second dielectric layer IMD2 contain conductive vias V2 and the second metal layer M2; mask layer 14 and the third dielectric layer IMD3 contain conductive vias V3 and the third metal layer M3; and mask layer 16 and the fourth dielectric layer 18 contain conductive vias 20. The conductive vias V1, V2, V3, and the first metal layer M1, the second metal layer M2, and the third metal layer M3 are made of highly conductive materials such as tungsten, cobalt, copper, aluminum, gold, silver, etc. The first metal layer M1, the second metal layer M2, and the third metal layer M3 are primarily used for the electrical connection of various components in the horizontal direction, i.e.,They are used for the electrical connection of various electronic components within the same structure. The conductive vias V1, V2, V3, and V4 primarily serve to connect the electronic components vertically (i.e., in different layers). The technology of metal layering and conductive vias is well-established in this field and will therefore not be described in detail here.

[0020] Furthermore, the semiconductor component in Fig. 1. A cell region R1 and an inductance region R2, wherein the cell region R1 and the inductance region R2 are preferably adjacent to each other. In the following steps, devices such as MRAM in the cell region R1 and inductors in the inductance region R2 for storing magnetic energy are further formed.

[0021] It should be noted that the conductive vias V1, V2, V3, the first metal layer M1, the second metal layer M2 and the third metal layer M3 in the inductance region R2 together form a helical coil structure C, wherein the first metal layer M1, the second metal layer M2 and the third metal layer M3 are located in a ring or frame structure with openings and are connected to each other by the conductive vias V1-V3 to form a continuous structure, and the properties of the coil structure C are described in more detail in the following sections.

[0022] Then, as in Fig. Figure 2 illustrates that a groove 22 is formed in the inductance region R2 by an etching process. In this embodiment, the groove 22 sequentially penetrates the fourth dielectric layer 18, the mask layer 16, the third dielectric layer IMD3, the mask layer 14, the second dielectric layer IMD2, the mask layer 12 and the first dielectric layer IMD1, exposing the surface of the mask layer 10.

[0023] In the next step, an inductance structure is formed in groove 22, which penetrates the several dielectric layers in a vertical direction, so that an inductance with a larger area is formed in a limited space, which is advantageous for storing more magnetic energy, and the details are described in the following sections.

[0024] As in Fig. As illustrated in Figure 3, a bottom electrode layer 24, an MTJ material layer 26, a top electrode layer 28, and a mask layer 30 are sequentially formed in the cell region R1 and in the inductance region R2, wherein the materials of the bottom electrode layer 24 and the top electrode layer 28 are, for example, titanium, titanium nitride, tantalum, or tantalum nitride, but are not limited to these. The function of the bottom electrode layer 24 and the top electrode layer 28 is to electrically connect the subsequently formed magnetoresistive tunnel junction (MTJ). The MTJ material layer 26 is subsequently used as the magnetoresistive tunnel junction (MTJ) of the MRAM, where the MTJ material layer 26 can contain multilayer structures, e.g., magnetic materials and insulating materials.Common magnetic materials include CoPt (cobalt-platinum) alloy, CoFe (cobalt-iron) alloy, FePt (iron-platinum) alloy, IrMn (iridium-manganese) alloy, PtMn (platinum-manganese) alloy, Co / Pt multilayer film, or Co / Pd multilayer film. Common insulating materials include, for example, MgO (magnesium oxide) or Al₂O₃ (aluminum oxide), but the present invention is not limited to these. The main function of the mask layer 30 is to protect the magneto-tunnel junction (MTJ). The material of the mask layer 30 is, for example, silicon dioxide, but is not limited to this.

[0025] It should be noted that the bottom electrode layer 24, the MTJ material layer 26, the top electrode layer 28 and the mask 30 are formed on the surface of the fourth dielectric layer 18 in the cell area R1 and also in the groove 22 in the inductance area R2, i.e. the aforementioned material layers are stacked successively on the side wall and the bottom surface of the groove 22, and the cross-sectional view illustrates a U-shaped cross-section.

[0026] Then, as in Fig. Figure 4 illustrates a structuring step performed to remove a portion of the top electrode layer 28 and the mask layer 30 in cell region R1 to define a predetermined MTJ pattern in cell region R1 and to remove the redundant top electrode layer 28 and the mask layer 30. Simultaneously, several steps are performed in inductance region R2, removing a portion of the top electrode layer 28 and the mask layer 30 in cell region R1, and also removing the top electrode layer 28 and the mask layer 30 in inductance region R2. In this embodiment, at this point, the top surfaces of the top electrode layer 28 and the mask layer 30 in inductance region R2 are flush with the top surface of the MTJ material layer 26 in cell region R1 in the horizontal direction, as shown in Figure 4. Fig. Figure 4 illustrates the horizontal plane L1. However, the present invention is not limited to this. In other embodiments of the present invention, it is also possible to adjust the parameters during the structuring step such that the upper surfaces of the top electrode layer 28 and the mask layer 30 in the inductance region R2 are not aligned with the upper surfaces of the MTJ material layer 26 in the cell region R1, which is also within the scope of the present invention.

[0027] As in Fig. As illustrated in Figure 5, an etching step is continued using the mask layer 30 as a mask to remove a portion of the MTJ material layer 26, the bottom electrode layer 24, and the fourth dielectric layer 18 in the cell R1 region. The mask layer 30 is then removed in a dry etching step. At this point, the remaining bottom electrode layer 24, the MTJ material layer 26, and the top electrode layer 28 in the cell R1 region are defined as the magnet tunnel junction (MTJ). The magnet tunnel junction (MTJ) is electrically connected to the underlying conductive via 20. After the etching step, the MTJ material layer 26 in the cell R1 region is separated from the MTJ material layer 26 in the inductance region R2. For the sake of simplicity, the MTJ material layer 26 in the cell area R1 is defined as MTJ material layer 26A and the MTJ material layer 26 in the inductance area R2 as MTJ material layer 26B.Here, MTJ material layer 26A is used as part of the magnet tunnel junction MTJ, and MTJ material layer 26B is used as part of the inductor to be formed later. It should be understood that MTJ material layer 26A and MTJ material layer 26B consist of the same material layer, i.e., they comprise the same material. Furthermore, MTJ material layer 26B, viewed from the cross-section, has a U-shaped cross-section, such that MTJ material layer 26B has one horizontal section 26BH and two vertical sections 26BV, with the horizontal section 26BH and the two vertical sections 26BV together forming MTJ material layer 26B.

[0028] Furthermore, in the dry etching step described above for removing the mask layer 30, since the etching process involves vertical ion bombardment, if the mask layer 30 in cell region R1 is completely removed, the mask layer 30 located on the lower surface of groove 22 in inductance region R2 can also be completely removed, thus exposing the upper surface of the underlying top electrode layer 28. However, some of the mask layers 30 on the side walls of groove 22 are not completely removed; these mask layers 30 remain in groove 22. Then, a nitride layer 32 is formed in cell region R1 and in inductance region R2, covering the magnet tunnel junctions MTJ and the material layers in groove 22, such as the side surface of the mask layer 30 and the upper surface of the top electrode layer 28.In this embodiment, the material of the nitride layer comprises 32 silicon nitride.

[0029] Furthermore, during the etching process, after defining the desired MTJ in cell region R1, a mask layer (not illustrated) can be used to cover and protect the MTJ, and the mask layer can be removed before the nitride layer 32 is formed. Since the inductance region R2 is not covered by the mask layer, some material layers in the inductance region R2 are etched more extensively. For example, in Fig. As illustrated in Figure 5, the upper surface of the fourth dielectric layer 18 in the inductance region R2 is lower than the upper surface of the fourth dielectric layer 18 in the cell region R1, resulting in the formation of a stepped structure ST at the interface between the cell region R1 and the inductance region R2.

[0030] As in Fig. As illustrated in Figure 6, an oxide layer 34 is then formed to fill the spaces between the MTJs and the grooves 22. The oxide layer 34 can be formed by atomic layer deposition (ALD) because the size of the spaces between the MTJs is small, but the present invention is not limited to this. The excess oxide layer 34 is subsequently removed. Up to this point, the bottom electrode layer 24, the MTJ material layer 26, the top electrode layer 28, the mask layer 30, the nitride layer 32, and the oxide layer 34 formed in the recess 22 are defined as inductance I. Inductance I comprises an MTJ material layer 26B, and the MTJ material layer 26B of inductance I and the MTJ material layer 26A in the magnet-tunnel junction MTJ are formed simultaneously and both contain the same material. Furthermore, the inductance I is surrounded by the coil structure C.Furthermore, when removing the excess oxide layer 34, a portion of the nitride layer 32 can also be removed. In this embodiment, a portion of the nitride layer 32 is removed in the inductance region R2, but a portion of the nitride layer 32 still covers the upper surfaces of the bottom electrode layer 24, the MTJ material layer 26B, the top electrode layer 28, and the mask layer 30.

[0031] As in Fig. As illustrated in Figure 7, a fifth dielectric layer 36 is formed in the cell region R1 and in the inductance region R2, wherein the fifth dielectric layer 36 comprises a material with an extremely low dielectric constant (ULK), such as silicon oxycarbide (SiCOH) or organosilicate glass (OSG), although the present invention is not limited thereto.

[0032] As in Fig. As illustrated in Figure 8, a fourth metal layer M4 is formed in the cell region R1 and in the inductance region R2, wherein the fourth metal layer M4 is electrically connected to the top electrode layer 28 of the magnet tunnel junction MTJ. A fourth metal layer M4 and a conductive via V4 are formed in the inductance region R2, wherein the conductive via V4 is electrically connected to the lower third metal layer M3. Subsequently, a mask layer 38 is formed, which covers the above structure. Up to this step, the semiconductor structure with an MRAM and an inductor in the present invention is complete.

[0033] A feature of the present invention is that, during the formation of the magnet tunnel junction MTJ, the inductance I can simultaneously be formed in the inductance region R2 adjacent to the cell region R1, thus eliminating the need for additional process steps. The inductance I comprises the MTJ material layer 26B, which contains magnetic materials such as CoPt (cobalt-platinum) alloy, CoFe (cobalt-iron) alloy, FePt (iron-platinum) alloy, IrMn (iridium-manganese) alloy, PtMn (platinum-manganese) alloy, Co / Pt or Co / Pd multilayer film, etc. Therefore, the inductance I can be used for storing magnetic energy. It should be noted that in this embodiment, the inductance I is not electrically connected to other elements; that is, the inductance I is in a floating state.

[0034] Another feature of the present invention is that the inductor I penetrates several dielectric layers, i.e., a portion of each material layer of the inductor I extends in the vertical direction. Therefore, the vertical height of the inductor I is relatively large within a limited space. Furthermore, the inductor I covers the side wall of the groove 22 (in cross-section, there are two vertical side walls), so that the inductor I has a larger effective area, which can effectively increase the magnetic energy that the inductor I can store.

[0035] Furthermore, it should be noted that in this embodiment, the inductor I is primarily located in the first dielectric layer IMD1, the second dielectric layer IMD2, and the third dielectric layer IMD3, while the magnet tunnel junction MTJ is located above the fourth dielectric layer 18 and at the same level as the fifth dielectric layer 36. This means that the horizontal position of the inductor I in this embodiment is lower than the horizontal position of the magnet tunnel junction MTJ. In the conventional structure, the inductor can be formed in the same dielectric layer as the MTJ, and the space in the dielectric layer below the inductor cannot be used to accommodate components, thus becoming unused space.According to the invention, the space of the dielectric layer in the inductance region R2 is effectively utilized, and the space is used for adjusting the inductance I, so that the unused space in the inductance region R2 can be effectively utilized and the waste of space can be avoided.

[0036] See Fig. Figure 9 illustrates the top view of the MTJ material layer and the coil structure C in the inductance region of the present invention. For the sake of simplicity, it is illustrated Fig. 9 mainly the MTJ material layer 26B and the coil structure C in the inductor area, while other elements are omitted. As in Fig. As illustrated in the top view in Figure 9, the MTJ material layer 26B is, for example, ring-shaped, while the coil structure C comprises a ring-shaped metal layer Mx with a gap G, as well as a conductive via Vx and a conductive via Vx-1, which electrically connect both ends of the ring-shaped metal layer Mx with a gap, wherein the ring-shaped metal layer Mx is, for example, the first metal layer M1, the second metal layer M2, or the third metal layer M3, as described above. Fig. 1 to Fig. 8 are illustrated, while the conductive vias Vx and Vx-1 represent conductive vias that connect metal layers, such as the conductive vias V1, V2, V3, V4, etc.

[0037] See Fig. Figure 10, which illustrates a schematic view of the coil structure C of the present invention. As an example, the one shown in the Fig. 1 to Fig. The coil structure C shown in Figure 8 comprises a first metal layer M1, a second metal layer M2, and a third metal layer M3, each metal layer having a gap G. Conductive vias at both ends of the gap in each metal layer are electrically connected to electrically link the metal layers to other metal layers. For example, the two ends of the gap G of the second metal layer M2 are each connected to a conductive via V2 and a conductive via V3, respectively, so that the second metal layer is electrically connected to the first metal layer M1 and the third metal layer M3.This arrangement allows a large number of metal layers to be connected in series to form a continuous spiral coil structure, and the coil structure surrounds the inductance I, so that a larger electric field can be generated when the coil structure C is excited, thereby improving the magnetic energy stored in the inductance I.

[0038] The above described Fig. 1 to Fig. Figure 10 illustrates a semiconductor structure containing an MRAM and an inductor, as well as its fabrication method according to one embodiment of the present invention. In other embodiments of the present invention, modifications can be made to the semiconductor structure shown above. For example, it is also possible within the scope of the present invention to change the number of dielectric layers so that the semiconductor structure contains more or fewer dielectric layers, or to change the shape of the magnet-tunnel junction MTJ, the inductor I, or the coil structure C, for example, from a ring shape to a frame shape when viewed from above.

[0039] Furthermore, in the present invention, the horizontal position of the inductor I is lower than the horizontal position of the magnet-tunnel junction MTJ, so that the unused dielectric layer space can be effectively utilized. In other embodiments of the present invention, the setting position of the inductor I can also be changed; for example, the horizontal position of the inductor I can be set higher than the horizontal position of the magnet-tunnel junction MTJ, so that the advantage of effective space utilization can also be achieved. This variant is also possible within the scope of the present invention.

[0040] Based on the above description and drawings, the semiconductor structure of the present invention comprises a magnetic tunnel junction (MTJ) and an inductor, including a substrate S, a cell region R1 and an inductor region R2 defined on the substrate S, arranged adjacent to the cell region R1, and a magnetic tunnel junction MTJ located in the cell region R1.Where the magnet tunnel junction MTJ comprises a first MTJ material layer (namely the MTJ material layer 26A arranged in the cell region R1 in the magnet tunnel junction MTJ), and an inductance I is arranged in the inductance region R2, wherein the inductance I comprises a multilayer structure, the multilayer structure comprising at least one second MTJ material layer 26B, wherein the first MTJ material layer 26A is the same as the second MTJ material layer 26B, and viewed from a cross-sectional perspective, the first MTJ material layer 26A extends along a horizontal direction, and the second MTJ material layer 26B comprises a horizontal part 26BH and two vertical parts 26BV, and the vertical part 26BV extends along a vertical direction.

[0041] In some embodiments of the present invention, the inductance I in the inductance region R2 is arranged in a first dielectric layer IMD1, and the magnet tunnel junction MTJ in the cell region R1 is arranged in a fifth dielectric layer 26, wherein the first dielectric layer IMD1 and the fifth dielectric layer 36 are arranged in different planes.

[0042] In some embodiments of the present invention, the horizontal position of the first dielectric layer IMD1 is lower than that of the fifth dielectric layer 36.

[0043] In some embodiments of the present invention, a coil structure C is arranged in the inductance region R2, and the coil structure C is arranged around and surrounds the inductance I.

[0044] In some embodiments of the present invention, the coil structure C comprises a plurality of ring-shaped structuring layers (such as the first metal layer M1, the second metal layer M2 and the third metal layer M3) arranged along the vertical direction, and each ring-shaped structuring layer includes a space G when viewed from above.

[0045] In some embodiments of the present invention, the two ends of the space G of the annular structuring layer are defined as a head end and a tail end, respectively, and at least one conductive via is further included to electrically connect the head end of one annular structuring layer and the tail end of another adjacent annular structuring layer, such that a plurality of annular structuring layers are electrically connected to each other and form a spiral structure (see Fig. 9 and Fig. 10).

[0046] In some embodiments of the present invention, the MTJ material layer 26B of the inductance I, viewed in plan view, has a ring structure or a frame structure and comprises an oxide layer 34 which is arranged in the middle of the ring structure or the frame structure.

[0047] In some embodiments of the present invention, the multilayer structure of the inductor I comprises a bottom electrode layer 24, a second MTJ material layer 26B, a top electrode layer 28, a mask layer 30, a nitride layer 32 and an oxide layer 34, wherein in cross-section the bottom electrode layer 24, the second MTJ material layer 26B, the top electrode layer 28 and the nitride layer 32 have a U-shaped profile and the mask layer 30 has an I-shaped profile.

[0048] In some embodiments of the present invention, the nitride layer 32 covers an upper surface of the bottom electrode layer 24, an upper surface of the second MTJ material layer 26B, an upper surface of the upper electrode layer 28 and an upper surface of the mask layer 30, but not an upper surface of the oxide layer 34.

[0049] The invention also provides a method for producing a semiconductor structure with a magnetic tunnel junction (MTJ) and an inductor, comprising providing a substrate S, wherein a cell region R1 and an inductor region R2, defined on the substrate S, are arranged adjacent to the cell region R1, and forming a magnetic tunnel junction MTJ located in the cell region R1, wherein the MTJ comprises a first MTJ material layer 26A, wherein an inductor I is formed in the inductor region R2, the inductor I comprising a multilayer structure, the multilayer structure comprising at least a second MTJ material layer 26B, wherein the first MTJ material layer 26A and the second MTJ material layer 26B are made of the same material, and the first MTJ material layer 26A extends along a horizontal direction when viewed from a cross-section.and the second MTJ material layer 26B comprises a horizontal part 26BH and two vertical parts 26BV, and the vertical part 26BV extends along a vertical direction.

[0050] In some embodiments of the present invention, the inductance I in the inductance region R2 is arranged in a first dielectric layer IMD1, and the magnet tunnel junction MTJ in the cell region R1 is arranged in a fifth dielectric layer 26, wherein the first dielectric layer IMD1 and the fifth dielectric layer 36 are arranged in different planes.

[0051] In some embodiments of the present invention, the horizontal position of the first dielectric layer IMD1 is lower than that of the fifth dielectric layer 36.

[0052] In some embodiments of the present invention, it further comprises forming a coil structure C which is arranged in the inductance region R2, and the coil structure C is arranged around and surrounds the inductance I.

[0053] In some embodiments of the present invention, the coil structure C comprises a plurality of annular structuring layers arranged along the vertical direction (such as the first metal layer M1, the second metal layer M2 and the third metal layer M3), and each annular structuring layer has a gap G in plan view.

[0054] In some embodiments of the present invention, the two ends of the space G of the annular structuring layer are defined as a head end and a tail end, respectively, and at least one conductive via is further included to electrically connect the head end of one annular structuring layer and the tail end of another adjacent annular structuring layer, such that a plurality of annular structuring layers are electrically connected to each other and form a spiral structure (see Fig. 9 and Fig. 10).

[0055] In some embodiments of the present invention, at least one conductor layer (including the first metal layer M1, the second metal layer M2 and the third metal layer M3 in the cell region, etc.) is formed below the magnet tunnel junction MTJ in the cell region R1, and the conductor layer is electrically connected to the magnet tunnel junction MTJ, wherein the conductor layer and one of a plurality of annular structuring layers of the coil structure C are formed simultaneously (i.e., at least one of the first metal layer M1, the second metal layer M2 and the third metal layer M3 is formed simultaneously in the cell region R1 and the inductance region R2).

[0056] In some embodiments of the present invention, the MTJ material layer 26B of the inductance I, viewed in plan view, has a ring structure or a frame structure and comprises an oxide layer 34 which is arranged in the middle of the ring structure or the frame structure.

[0057] In some embodiments of the present invention, the multilayer structure of the inductor I comprises a bottom electrode layer 24, a second MTJ material layer 26B, a top electrode layer 28, a mask layer 30, a nitride layer 32 and an oxide layer 34, wherein in cross-section the bottom electrode layer 24, the second MTJ material layer 26B, the top electrode layer 28 and the nitride layer 32 have a U-shaped profile and the mask layer 30 has an I-shaped profile.

[0058] In some embodiments of the present invention, the nitride layer 32 covers an upper surface of the bottom electrode layer 24, an upper surface of the second MTJ material layer 26B, an upper surface of the upper electrode layer 28 and an upper surface of the mask layer 30, but not an upper surface of the oxide layer 34.

[0059] In some embodiments of the present invention, the first MTJ material layer 26A of the magnet tunnel junction and the second MTJ material layer 26B in the inductance I are formed at the same time.

[0060] In summary, the invention provides a semiconductor structure with integrated MRAM and an integrated inductor, as well as a manufacturing process for it. The inductor is formed during the MRAM fabrication process, thus eliminating process steps. Furthermore, the inductors are arranged vertically and penetrate the multilayer dielectric layers vertically, effectively utilizing the unused space within the stacked dielectric layers. Additionally, the inductor of the invention is surrounded by a helical coil structure, which is formed by connecting a plurality of notched metal layers and conductive vias in series. This allows for the generation of a larger electric field when the coil structure is electrified, thereby enhancing the magnetic energy stored in the inductor.Therefore, the invention has the effect of improving the quality of semiconductors and simplifying the manufacturing process.

Claims

[1] Semiconductor structure with a magnetoresistive tunnel junction (MTJ) and an inductor (I), comprising: a substrate (S) on which a cell region (R1) and an inductance region (R2) are defined, wherein the inductance region (R2) is arranged next to the cell region (R1); a magnetic tunnel junction (MTJ) arranged in the cell region (R1), wherein the magnetic tunnel junction comprises a first MTJ material layer (26A); and an inductance (I) arranged in the inductance region (R2), wherein the inductance comprises a multilayer structure, the multilayer structure comprising at least one second MTJ material layer (26B), wherein the material of the first MTJ material layer (26A) is the same as the material of the second MTJ material layer (26B), and the first MTJ material layer (26A) extends along a horizontal direction when viewed from a cross-section, and the second MTJ material layer (26B) has a U-shaped cross-section when viewed from a cross-section, with a horizontal part (26BH) and two vertical parts (26BV) extending along a vertical direction. [2] Semiconductor structure with a magnet tunnel junction and an inductor according to claim 1, wherein the inductor is arranged in the inductance region (R2) in a first dielectric layer (IMD1) and the magnet tunnel junction is arranged in the cell region (R1) in a second dielectric layer (36), wherein the first dielectric layer (IMD1) and the second dielectric layer (36) are arranged on different planes. [3] Semiconductor structure with a magnet tunnel junction and an inductor according to claim 2, wherein the horizontal reference line of the first dielectric layer (IMD1) is lower than the horizontal reference line of the second dielectric layer (36). [4] Semiconductor structure with a magnetic tunnel junction and an inductor according to claim 1, further comprising a coil structure (C) arranged in the inductor region, wherein the coil structure (C) is arranged around and surrounds the inductor. [5] Semiconductor structure with a magnet tunnel junction and an inductor according to claim 4, wherein the coil structure (C) comprises a plurality of ring-shaped structuring layers arranged along the vertical direction and each ring-shaped structuring layer has a gap (G) in plan view. [6] Semiconductor structure with a magnetic tunnel junction and an inductor according to claim 5, wherein both ends of the space (G) of the annular structure layer are each defined as a head end and a tail end, and further comprising at least one conductive via that electrically connects the head end of one of the annular structure layers and the tail end of another adjacent annular structure layer, and the annular structure layers are electrically connected to each other and form a spiral structure. [7] Semiconductor structure with a magnet tunnel junction and an inductor according to claim 1, wherein the second MTJ material layer (26B) contained in the inductor has a ring structure or a frame structure in the top view and an oxide layer is arranged in the middle of the ring structure or the frame structure. [8] Semiconductor structure with a magnet tunnel junction and an inductor according to claim 1, wherein the multilayer structure of the inductor comprises a bottom electrode layer (24), the second MTJ material layer (26B), a top electrode layer (28), a mask layer (30), a nitride layer (32) and an oxide layer (34), wherein the cross-sections of the bottom electrode layer (24), the second MTJ material layer (26B), the top electrode layer (28) and the nitride layer (34) are U-shaped, and the mask layer (30) is I-shaped. [9] Semiconductor structure with a magnet tunnel junction and an inductor according to claim 8, wherein the nitride layer (34) covers an upper surface of the lower electrode layer (24), an upper surface of the second MTJ material layer (26B), an upper surface of the upper electrode layer (28) and an upper surface of the mask layer (30), but not an upper surface of the oxide layer (34). [10] Method for fabricating a semiconductor structure with a magnetic tunnel junction, MTJ, and an inductor (I), comprising: Providing a substrate (S) on which a cell region (R1) and an inductance region (R2) arranged next to the cell region are defined; Forming a magnetic tunnel junction (MTJ) arranged in the cell region (R1), wherein the magnetic tunnel junction comprises a first MTJ material layer (26A); and Forming an inductance (I) in the inductance region (R2), wherein the inductance comprises a multilayer structure, the multilayer structure comprising at least one second MTJ material layer (26B), wherein the material of the first MTJ material layer (26A) is the same as the material of the second MTJ material layer (26B), and the first MTJ material layer (26A) extends along a horizontal direction when viewed from a cross-section, and the second MTJ material layer (26B) has a U-shaped cross-section when viewed from a cross-section, with a horizontal part (26BH) and two vertical parts (26BV) extending along a vertical direction. [11] Method for producing a semiconductor structure with a magnet tunnel junction and an inductor according to claim 10, wherein the inductor is arranged in the inductance region (R2) in a first dielectric layer (IMD 1) and the magnet tunnel junction is arranged in the cell region (R1) in a second dielectric layer (36), wherein the first dielectric layer (IMD1) and the second dielectric layer (36) are arranged on different planes. [12] Method for producing a semiconductor structure with a magnet tunnel junction and an inductance according to claim 11, wherein the horizontal reference line of the first dielectric layer (IMD1) is lower than the horizontal reference line of the second dielectric layer (36). [13] Method for producing a semiconductor structure with a magnetic tunnel junction and an inductor according to claim 10, further comprising forming a coil structure (C) in the inductor region which is arranged around and surrounds the inductor. [14] Method for producing a semiconductor structure with a magnetic tunnel junction and an inductor according to claim 13, wherein the coil structure (C) comprises a plurality of ring-shaped structuring layers arranged along the vertical direction and each structuring layer has a gap (G) in plan view. [15] Method for producing a semiconductor structure with a magnetic tunnel junction and an inductance according to claim 14, wherein both ends of the space (G) of the annular structuring layer are each defined as a head end and a tail end, and further comprising forming at least one conductive via to electrically connect the head end of one of the annular structuring layers and the tail end of another adjacent annular structuring layer, such that the annular structuring layers are electrically connected to each other and form a spiral structure. [16] Method for producing a semiconductor structure with a magnetic tunnel junction and an inductor according to claim 14, further comprising forming at least one conductor layer arranged under the magnetic tunnel junction in the cell region (R1) and electrically connected to the magnetic tunnel junction, wherein the conductor layer is formed simultaneously with one of the plurality of ring-shaped structuring layers of the coil structure. [17] Method for producing a semiconductor structure with a magnet tunnel junction and an inductor according to claim 10, wherein the second MTJ material layer (26B) contained in the inductor has a ring structure or a frame structure in the top view and an oxide layer is arranged in the middle of the ring structure or the frame structure. [18] Method for producing a semiconductor structure with a magnet tunnel junction and an inductor according to claim 10, wherein the multilayer structure of the inductor comprises a bottom electrode layer (24), the second MTJ material layer (26B), a top electrode layer (28), a mask layer (30), a nitride layer (34) and an oxide layer (34), wherein the cross-sections of the bottom electrode layer (24), the second MTJ material layer (36B), the top electrode layer (28) and the nitride layer (34) are U-shaped, and the mask layer (30) is I-shaped. [19] Method for producing a semiconductor structure with a magnet tunnel junction and an inductance according to claim 18, wherein the nitride layer (28) covers an upper surface of the bottom electrode layer (24), an upper surface of the second MTJ material layer (26B), an upper surface of the upper electrode layer (28) and an upper surface of the mask layer (30), but not an upper surface of the oxide layer (34). [20] Method for producing a semiconductor structure with a magnet tunnel junction and an inductor according to claim 10, wherein the first MTJ material layer (26A) of the magnet tunnel junction and the second MTJ material layer (26B) of the inductor are formed simultaneously.

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