PROTECTION AGAINST LOAD DAMAGE FOR TRENCH INSULATION

Abstract

Systems, devices, and methods are described to protect isolation trench structures from charge damage during plasma-based BEOL deposition and etching steps. Devices and methods can include image sensors featuring array isolation trenches in an array section of the image sensor substrate, which encloses a pixel array. A peripheral section of the substrate can include isolation trenches coupled to a metallization layer on a front face of the substrate. The peripheral section can also include contacts between substrate segments and the metallization layer. The substrate and the peripheral trenches remain at the same potential during BEOL processing, thereby reducing the risk of charge damage to the isolation trenches.In some embodiments, the peripheral trenches can remain isolated from the array trenches until BEOL processing is complete, for example, by coupling them with conductive material after thinning the back surface. The array trenches can be coupled across the peripheral section to generate a bias in the completed image sensor.

Description

BACKGROUND

[0001] This application relates generally to image sensors and in particular to image sensors with trench isolation structures inserted between adjacent pixels.

[0002] Image sensors are used in many electronic devices, such as cameras, smartphones, computers, and so on, to capture images and / or videos, among other possible functions. Image sensors typically comprise an array of image pixels arranged in rows and columns. Each pixel can be a photodiode to generate a charge in response to incident photons. The pixel array may include insulating structures between each pixel to prevent electrical crosstalk, light leakage, improve internal reflection, and so forth.

[0003] The pixel array can be covered by a color filter array. Various circuit arrangements can be coupled to each pixel, pixel column, and / or pixel row for storing the generated charge, transferring the charge, converting the charge into a digital representation, and / or for other readout and processing purposes. Therefore, one or more conductive signal lines (hereafter referred to as metal conduction layers or metal layers) can be connected to each pixel and / or various structures of the pixel array. The conductive signal lines can run within the array and outside the array (hereafter referred to as the sensor periphery or simply the periphery). In some cases, the insulating structures can be biased to reduce dark current.

[0004] In a backside image sensor (BSI), processing steps can initially be performed from the front side (FS) of the image sensor substrate. Such processing steps can include the modeling of the various pixel structures within the substrate, such as the photodiode, transfer transistor, and other functional components, as well as isolation structures. The front-side processing can also include the modeling of various structures, circuit arrangements, and the like in the periphery, as well as one or more metal conduction layers for the image sensor.

[0005] Various plasma processes can be used to perform the etching, deposition, and similar operations required to form the image sensor, particularly during the formation of the metal conduction layers. However, plasma processes can charge various metal layers and intermediate compounds. In image sensors with prestressed insulation structures, while the insulation structures can be brought into contact from the front, excess charge from plasma processes can build up within the insulation structures. This excess charge can generate electric fields that can affect the surrounding materials. Dielectric materials such as silicon dioxide or low-k dielectrics can be susceptible to damage from these electric fields. For example, high electric fields can cause dielectric breakdown and lead to the formation of undesirable defects such as pinholes, voids, or similar features.To avoid cargo damage, backside insulation structures can be formed after frontside processing, but forming the backside trench and backside contact to the trench can be costly.

[0006] It would therefore be desirable to provide improved devices and methods for image sensors with prestressed insulation structures. BRIEF DESCRIPTION OF THE DRAWING FIGURES Fig. Figure 1 is a schematic diagram showing an exemplary device including an image sensor according to various embodiments. Fig. Figure 2A is a top view of a first exemplary arrangement of isolation trenches for an image sensor according to various embodiments. Fig. 2B is a lateral cross-sectional view along and in the direction of line 1-1 in Fig. Figure 2A illustrates the isolation trenches after BEOL processing according to various embodiments. Fig. 2C is a lateral cross-sectional view along and in the direction of line 1-1 in Fig. Figure 2A illustrates the isolation trenches after thinning the back side according to various embodiments. Fig. Figure 3A is a top view of a second exemplary arrangement of isolation trenches for an image sensor according to various embodiments. Fig. 3B is a lateral cross-sectional view along and in the direction of line 2-2 in Fig. Figure 3A illustrates the isolation trenches after BEOL processing according to different embodiments. Fig. 3C is a lateral cross-sectional view along and in the direction of line 2-2 in Fig. Figure 3A illustrates the isolation trenches after thinning the back side according to various embodiments. Fig. Figure 4A is a lateral cross-sectional view illustrating a third exemplary arrangement of isolation trenches after BEOL processing according to different embodiments. Fig. Figure 4B is a lateral cross-sectional view illustrating a third exemplary arrangement of isolation trenches after thinning the back side according to various embodiments. Fig. Figure 5A is a top view of a fourth exemplary arrangement of isolation trenches for an image sensor according to various embodiments. Fig. 5B is a lateral cross-sectional view along and in the direction of line 3-3 in Fig. Figure 5A illustrates the isolation trenches after thinning the back side according to various embodiments. Fig. Figure 6A is a top view of a fifth exemplary arrangement of isolation trenches for an image sensor according to various embodiments. Fig. 6B is a lateral cross-sectional view along and in the direction of line 4-4 in Fig. Figure 6A illustrates the isolation trenches after thinning the back side according to various embodiments. Fig. 6C is a lateral cross-sectional view along and in the direction of line 4-4 in Fig. Figure 6A illustrates the isolation trenches coupled to a rear side of the image sensor for pre-tensioning according to various embodiments. Fig. Figure 7A is a top view of a sixth exemplary arrangement of isolation trenches for an image sensor according to various embodiments. Fig. 7B is a lateral cross-sectional view along and in the direction of line 5-5 in Fig. Figure 7A illustrates the isolation trenches coupled for pre-tensioning on a rear side of the image sensor according to various embodiments. Fig. Figure 8A is a top view of a seventh exemplary arrangement of isolation trenches for an image sensor according to various embodiments. Fig. 8B is a lateral cross-sectional view along and in the direction of line 6-6 in Fig. Figure 8A illustrates the isolation trenches coupled to a rear side of the image sensor for pre-tensioning according to various embodiments. Fig. Figure 9A is a top view of an eighth exemplary arrangement of isolation trenches for an image sensor according to various embodiments. Fig. 9B is a lateral cross-sectional view along and in the direction of line 7-7 in Fig. Figure 9A illustrates the isolation trenches coupled for pre-tensioning on a rear side of the image sensor according to various embodiments. Fig. Figure 10A is a top view of a first arrangement of an array section and several peripheral sections according to different embodiments. Fig. Figure 10B is a top view of a second arrangement of the array section and several peripheral sections according to different embodiments. Fig. Figure 11 is a simplified flowchart illustrating a method for protecting array trenches during manufacturing according to different embodiments. SUMMARY

[0007] Various embodiments relate to systems, devices and methods for protecting prestressed array trenches from charge damage during the manufacture of an image sensor or other similar devices.

[0008] In various embodiments, a semiconductor device can include a substrate comprising an array section and a peripheral section, a plurality of substrate segments defined by a plurality of array trenches in the substrate, a first array trench of the plurality of array trenches, wherein the first array trench traverses the array section and the peripheral section, a second array trench of the plurality of array trenches in the array section, wherein the first array trench intersects the second array trench in the array section, a first trench contact coupled to the first array trench in the peripheral section, and a first substrate contact coupled to a first substrate segment of the plurality of substrate segments in the peripheral section, wherein the first trench contact and the first substrate contact are electrically coupled by a conductive signal line.

[0009] In various embodiments, a semiconductor device can include a substrate comprising an array section and a peripheral section; a plurality of array trenches comprising a first array trench traversing both the array section and the peripheral section, and a second array trench in the array section, wherein the first array trench intersects the second array trench and is electrically coupled to it; a peripheral trench in the peripheral section, wherein the peripheral trench does not intersect any of the plurality of array trenches; a trench contact coupled to the peripheral trench in the peripheral section, wherein the trench contact is located on a front side of the substrate; and a conductive layer on a back side of the substrate, wherein the conductive layer couples the peripheral trench to the first array trench at the peripheral section.

[0010] In various embodiments, a method for forming an image sensor on a substrate can include forming a plurality of deep trenches from a front side of the substrate during front-end-of-line (FEOL) processing, wherein the plurality of deep trenches are formed in an array section of the substrate and in a peripheral section of the substrate, and a first trench of the plurality of deep trenches comprises an array trench traversing the array section and the peripheral section; forming, in the peripheral section, a substrate contact with the substrate adjacent to the first trench on the front side of the substrate during back-end-of-line (BEOL) processing; forming an electrical contact with the first trench in the peripheral section; and thinning the substrate from a back side of the substrate after BEOL processing.

[0011] These and other examples are described in more detail below. DETAILED DESCRIPTION

[0012] The following detailed description is intended to provide several examples illustrating the broader concepts set forth herein, but it is not intended to limit the invention or its application and use. Furthermore, there is no intention to be bound by the theory set forth in the preceding background or in the following detailed description.

[0013] Embodiments according to the present description reduce charge damage caused by BEOL processes on deep trench structures, such as those used in image sensor pixel arrays. According to various embodiments, array isolation trench structures forming the pixel array of an image sensor can be coupled to metal conductors for prestressing after BEOL processing. The array trenches can be coupled via backside connections to trench or other prestressed structures in a peripheral section of the image sensor. According to various embodiments, the array trenches can extend to the peripheral section, with the trenches and the substrate in the peripheral section being electrically short-circuited to the same potential by metal conductors or other conductive material during BEOL processing.

[0014] Various embodiments provide array trenches that can be biased by electrical coupling in the peripheral section of the image sensor. After BEOL processing, the substrate in the array section can be isolated from the trenches and the substrate in the peripheral section, and during image sensor operation, it can be biased (e.g., grounded) separately from the substrate in the peripheral section. In some embodiments, the substrate in the peripheral section can be biased to the same voltage as the trenches in the periphery (e.g., -4 V). Some embodiments can provide stacked via contacts to the trenches, which have a minimized area to minimize the metal-to-antenna ratio. Some embodiments can provide a protection diode in the substrate adjacent to a trench in the peripheral section.

[0015] Advantageously, systems, devices, and methods according to the present description provide improved trench isolation structures that can be prestressed during the operation of the image sensor 14. The improved trench isolation structures can exhibit enhanced performance due to fewer defects and damage caused by BEOL processing and can be implemented with relatively inexpensive process steps.

[0016] Fig. Figure 1 illustrates an electronic device 10, for example as described above, which includes a camera module. The camera module 12 (sometimes referred to as an imaging device or imaging system) can include one or more image sensors 14 and one or more lenses 28. During operation, the lenses 28 focus light onto the image sensor 14. The image sensor 14 includes photosensitive elements, such as photodiodes, which convert incident photons into an electrical charge. Image sensors can have any number of pixels (e.g., hundreds, thousands, millions, or more), each containing a photosensitive element.The image sensor 14 can include a bias circuit arrangement, a sample-and-hold circuit arrangement, a dual sampling correlation circuit arrangement (CDS circuit arrangement), an amplifier circuit arrangement, an analog-to-digital converter circuit arrangement (ADC converter circuit arrangement), a data output circuit arrangement, a memory circuit arrangement, an addressing circuit arrangement, and the like.

[0017] Still image and video image data from the image sensor 14 can be provided to the image processing circuitry 16, for example via a communication path 26. The image processing circuitry 16 can be used to perform image processing functions such as autofocus, depth sensing, data formatting, white balance and exposure adjustment, video image stabilization, face detection, or the like. The image processing circuitry 16 can also be used, if desired, to compress camera raw image files, for example, into the Joint Photographic Experts Group or JPEG format.

[0018] In some arrangements, sometimes referred to as system-on-a-chip (SOC) arrangements, the image sensor 14 and the image processing circuitry 16 are implemented on a common integrated circuit. In other arrangements, the image sensor 14 and the image processing circuitry 16 can be implemented using separate integrated circuits. For example, the image sensor 14 and the image processing circuitry 16 can be implemented on separate substrates that are stacked together.

[0019] In some arrangements, the image sensor can incorporate 14 bonded substrates. For example, in a back-illuminated image sensor (BSI image sensor), the pixel array, peripheral structures and circuitry, as well as metal conduction layers, can be formed from the front side of a first substrate before the first substrate is flipped over for further processing steps, such as back-side thinning, passivation, color filter array, and microlens formation. The metal conduction layers can be used to connect the various components of the pixel, such as the photodiode and the readout circuitry, to control and data processing circuitry or other relevant circuitry or structures located elsewhere on the image sensor 14.The front side of the first substrate can be bonded to a second substrate which may contain, for example, additional pixel control and / or storage structures, a readout circuit arrangement and / or other control and processing circuit arrangements.

[0020] The camera module 12 can transmit captured image data to host subsystems 20 via a communication path 18. For example, the image processing circuitry 16 can transmit image data to subsystems 20. The electronic device 10 can provide a user with numerous sophisticated functions. In the case of a computer or a smartphone, for example, a user can be provided with the ability to run user applications. To implement these functions, the host subsystem 20 of the electronic device 10 can include a storage and processing circuitry 24 and input / output devices 22, such as keyboards, input / output ports, joysticks, and displays. The storage and processing circuitry 24 can include volatile and / or non-volatile memory.The storage and processing circuit arrangement 24 can also include microprocessors, microcontrollers, digital signal processors, application-specific integrated circuits or other processing circuits.

[0021] Fig. Figure 2A illustrates a top view of an exemplary image sensor 14 with prestressed isolation structures according to various embodiments. The image sensor includes a semiconductor substrate 254, for example, silicon. The image sensor 14 can have an array section 220 and a peripheral section 210. The array section 220 can include the array of pixels 222 arranged in rows and columns. The peripheral section 210 can be located outside the array section 220, for example, adjacent to the array section 220, and can include other supporting circuit arrangements and structures. The peripheral section 210 need not encompass the entire portion of the substrate 254 outside the array section 220. The isolation structures for the pixel section 220 can be prestressed from the peripheral section 210.

[0022] In some embodiments, the peripheral section 210 includes structures configured to protect the array section 220 from charge damage during processing and to provide adequate bias during operation of the image sensor 14. In some embodiments, the peripheral section 210 may further include other structures that support the functionality and operation of the image sensor 14. These structures may include, for example, an input / output circuit (I / O circuit), an analog and / or digital signal processing circuit, control logic, clock generation and distribution, power distribution, and / or the like. The peripherals may also include structures related to the delimitation of the pixel array, such as row and column address decoders for accessing individual pixels.

[0023] For the sake of clarity, in the Fig. Figures 2A to C show a simplified subset of the array section 220 and the peripheral section 210. The actual number of trench structures, pixels, substrate and trench connections, and the like may be much higher in many embodiments. Furthermore, since the various trench structures in the entire array section 220 and / or peripheral section 210 may be electrically coupled, some embodiments may only include a subset of the various trench structures and / or substrate sections, each of which has trench and / or substrate connections.

[0024] The image sensor 14 can include array trench isolation structures 230. The array trenches 230 are those trenches that extend laterally along the substrate 254 through the array section 220 and are arranged between adjacent pixels of the pixel array to act as isolation structures. In some embodiments, the array trenches 230 can also extend into the peripheral section 210. The array trenches 230 can include full trenches (FT trenches), deep trenches (DT trenches), and / or any other suitable trench isolation structures. In some embodiments, the array trenches 230 can include deep trench isolation structures (DTI structures) such as front-side deep trench isolation (FDTI) and / or back-side deep trench isolation (BDTI). Referring to Fig. 2B, in some embodiments, the array trenches 230 can be formed by etching a trench in the front surface 256 (also referred to as the front or FS) of the substrate 254 of the image sensor 14. The array trenches 230 can be partially etched through the substrate 254 in both the array section 220 and the peripheral section 210, such that the array trenches 230 do not intersect a rear surface 258 of the substrate and the substrate remains electrically intact throughout the entire array section 220 and peripheral section 210, as for example in Fig. Figure 2B shows that the trenches can be lined with an insulating material 234 such as silicon dioxide, silicon nitride, another high-k or low-k dielectric, and / or the like. The insulating material 234 can be selected based on electrical properties, optical properties, or other desired characteristics and / or functions.

[0025] The array trenches 230 can then be filled with a conductive material 232 such as polysilicon, metal, and / or another material suitable for pre-tensioning. In some embodiments, the conductive material 232 can include tungsten and / or doped polysilicon. The array trenches 230 of the array section 220 and the peripheral section 210 can be electrically coupled, for example, by the conductive filler 232, so that they remain at the same electrical potential. For example, during operation of the image sensor 14, the array trenches 230 can be positively pre-tensioned, negatively pre-tensioned, or grounded, as desired.

[0026] The formation of the array trenches 230 can occur during the front-end-of-line (FEOL) processing of the image sensor 14, for example, together with the formation of other semiconductor structures such as the pixels, control logic, and so on. Therefore, in some embodiments, the substrate remains electrically intact or otherwise configured to maintain a constant electrical potential throughout the entire peripheral section 210 and array section 220 at the end of the FEOL processing.

[0027] One or more trench contacts 270 can be formed to one or more array trenches 230 in the peripheral section 210. One or more substrate contacts 272 can be formed to one or more segments of the substrate 254 in the peripheral section 210. The segments of the substrate 254 can be those sections of the substrate located between successive trenches. The trench contacts 270 and substrate contacts 272 can be formed during or after FEOL processing, as desired. In some embodiments, the trench contacts 270 and / or substrate contacts 272 include conductive vias.

[0028] One or more metal conduction layers can be formed on the front face 256 of the substrate 254 during back-end-of-line (BEOL) processing. The metal conduction layers can alternate with layers of insulating material, such as various oxides. Vias can extend through one or more insulating layers to connect multiple metal layers. For clarity, the various insulating layers are not illustrated. A surface-mount passivation layer 252 (for example, an oxide) on the front face 256 can be part of a first insulating layer (not shown) between the substrate 254 and a first metal layer 260. The trench contacts 270 and substrate contacts 272 can extend through the passivation layer 252 to be electrically coupled to the trenches and segments of the substrate 254, respectively.

[0029] The first metal layer 260 can be formed during BEOL processing. In some embodiments, the first metal layer 260 can be electrically coupled to the trench contacts 270 and substrate contacts 272. Due to the first metal layer 260, the substrate segments 254 and the array trenches 230 in the peripheral section 210 are at essentially the same electrical potential. The array trenches 230 in the peripheral section 210 and the array section 220 are also at essentially the same electrical potential due to the continuous metal filler 232, which extends into both the peripheral section 210 and the array section 220.The segments of the substrate 254 in the peripheral section 210 and the array section 220 are essentially at the same electrical potential due to the electrically intact sections of the substrate that extend along the rear surface 258 (hereinafter also referred to as the back or BS) in both the peripheral section 210 and the array section 220.

[0030] Therefore, in some exemplary embodiments, the substrate 254 and the array trenches in both the peripheral section 210 and the array section 220 can remain at essentially the same electrical potential during BEOL processing. If various plasma processes performed during BEOL generate excess charge on one or more metal layers, the array trenches 230 and the segments of the substrate 254 remain at an equivalent electrical potential, thereby minimizing or otherwise reducing the electric field between the array trenches 230 and the surrounding substrate 254. This significantly reduces the risk of charge damage during plasma or other processes that induce charge in the structures of the image sensor 14. After BEOL processing is completed from the FS 256, there may be a small additional risk of charge damage from further processing steps.Referring to . Fig. 2C, after BEOL processing, the substrate can be flipped from the FS 256, for example attached to a support wafer, and further processed from the BS 258. In some embodiments, the segments of the substrate 254 of the pixel section 220 can be electrically separated from the substrate 254 of the peripheral section after BEOL processing, thus enabling the array trenches 230 to be biased independently of the segments of the substrate 254 of the array section 220 during operation of the image sensor 14.

[0031] In some embodiments, the substrate 254 can be thinned from the BS 258, for example by grinding and / or etching. The substrate 254 can be thinned to at least the array trenches 230, such that one or more segments of the substrate 254 are no longer electrically connected. For example, after thinning, the segments of the substrate 254 in the array section 220 can be electrically isolated from the segments of the substrate 254 in the peripheral section 210. The segments of the substrate 254 in the peripheral section 210 can be electrically isolated from the substrate 254 in other sections of the image sensor 14 outside the array section 220. In some embodiments, thinning the substrate 254 results in the segments of the substrate 254 being physically and / or electrically isolated from each other for each pixel in the array section 220, based on the desired performance and functionality of each pixel.The segments of substrate 254 in the peripheral section 210 can remain electrically coupled to the array trenches 230 via the trench contacts 270 and substrate contacts 272 on the FS 256.

[0032] In some embodiments, a passivation region 240 can be formed on the BS 258 after thinning. The passivation region 240 can include antireflection coatings (ARC), chemical passivation layer(s), electrically insulating layer(s) such as high-k or low-k dielectrics, and / or the like. For example, the passivation region 240 can include an insulating layer 238, for example, silicon dioxide or silicon nitride, and a high-k dielectric layer 236. Additional processing from the BS 258 can include forming a color filter array, microlenses, and / or other desired structures (not shown).

[0033] Advantageously, according to various embodiments, charge damage to the array trenches 230 during BEOL processing can be prevented, and a bias voltage can be provided to the array trenches 230 during operation of the image sensor 14 by using only contacts on the FS 256 to the substrate 254 and / or the array trenches 230. In other words, devices and methods according to various exemplary embodiments can be implemented without including corresponding contacts on the BS 258.

[0034] Referring to Fig. 3A, in some exemplary embodiments, the array trenches 230 may form an interrupted or otherwise incomplete grid in the peripheral section 210 and / or may not each be individually coupled to the first metal layer 260 by a trench contact 270. The array trenches 230 may nevertheless be fully electrically coupled by intersecting them with other array trenches 230 in the peripheral section 210 and / or array section 220. The number and placement of the substrate contacts 272 and trench contacts 270 can be selected based on the desired protection during or after BEOL processing, the desired performance based on various process parameters and / or requirements, the desired functionality during operation of the image sensor 14, and / or any other suitable criteria. Referring to Fig. Figure 3B, which illustrates the image sensor 14 after thinning the back surface, shows that in some embodiments, the substrate 254 can include heavily doped regions 354 in the peripheral section 210. These regions are formed and arranged near the FS 256 and aligned with the substrate contacts 272 to provide enhanced electrical coupling with the substrate contacts 272. For example, a lightly doped p-type substrate 254 can include heavily doped p-type regions 354 in the peripheral section 210, positioned so that the substrate contacts 272 rest on them. The heavily doped regions 354 can provide an enhanced discharge path through the substrate 254 during various plasma processes or other charge-generating processes.

[0035] In some embodiments, the array contacts 270 and / or substrate contacts 272 can be coupled by one or more reduced-area metal conduction layers to a higher-level metal conduction layer spanning a larger portion of the peripheral section 210. The relatively small metal area can serve to further protect the substrate 254 and the array trenches 230 from charge damage, since charge can accumulate on metal structures with a larger area.

[0036] For example, the number of substrate contacts 272 and array contacts 270 can be reduced as described above, thereby enabling the use of short segments of the first metal layer 260 for coupling adjacent contacts 270, 272. The first metal layer 260 can be coupled to a fourth metal layer 266 with a larger area via conductive vias 274 and a second metal layer 262 and a third metal layer 264 (each with a small area). The fourth metal layer 266 can span a larger section of the peripheral area 210 and can be coupled to several shorter segments of the first metal layer 260, and can store more of the charge generated during various plasma processes. Furthermore, if desired, the fourth metal layer 266 can be coupled to additional metal layers, such as a fifth metal layer 268, via a conductive via 274.

[0037] Referring to Fig. Figure 3C, which illustrates the image sensor 14 after back-side thinning, shows that in some embodiments a protection diode can be formed in the substrate 254 to protect the array trenches 230 during BEOL processing. In some embodiments, a highly doped region 354 can be formed in a well 450 with opposite doping to the substrate 254. For example, a highly doped p-type region 354 can be formed in an n-type well 450, with the highly doped p-type region 354 forming the anode of the protection diode. The substrate contact 272 can be coupled to the anode of the protection diode. In other embodiments, the diode can be formed using a region doped oppositely to the doping of the substrate 254. For example, the diode can be formed from a highly doped n-type region in a p-type substrate.

[0038] During processing that can generate charge on the metal layers 260, 262, 264, 266, 268, the protection diode can be forward-biased due to the charging, thus enabling a path for charge flow into the substrate. This forward biasing of the protection diode can occur simultaneously with the charge flow into the array trenches 230, and therefore the electrical potential of the array trenches 230 and the segments of the substrate 254 remains essentially the same.

[0039] During normal operation of the image sensor 14, the segments of the substrate 254 in the peripheral section 210 can be essentially electrically isolated from the array trenches 230 by the protection diode. In some embodiments, biasing the array trenches 230 to a negative value, for example, about -4 V, also results in a reverse bias of the protection diode and essentially prevents the substrate 254 from assuming the same electrical potential as the array trenches 230.

[0040] Advantageously, embodiments with a protection diode for the connection between the substrate contact 272 and the substrate 254 may not require thinning of the back surface to isolate the substrate 254 in the peripheral section 210 from other sections of the substrate 254 in the image sensor 14. Therefore, in some embodiments, the various trenches may remain partial-depth trenches after complete thinning of the back surface (not shown), allowing the substrate 254 to remain electrically intact after completion of the back surface processing 258.

[0041] Fig. Figure 4A illustrates an exemplary image sensor 14 after FEOL processing. In some embodiments, during FEOL processing, spacer etching can be performed on the insulating material 234 lining the array trenches 230 before filling with the conductive material 232. The spacer etching can open the insulating material 234 at a bottom surface of the array trenches 230. This opening exposes the bottom of the array trenches 230 to the substrate 254, thus enabling subsequent conductive coupling of the conductive material 232 to the substrate 254 through the opening. During BEOL processing, excess charge can be discharged through the conductive material 232 and into the substrate 254 at the bottom of the array trench 230. The substrate 254 and the array trenches 230 can remain essentially at the same electrical potential through the conductive coupling at the bottom of the array trenches 230.In some embodiments, one or more substrate contacts 272 can be provided in the peripheral section 210, as desired, to further facilitate the equalization of the electrical potential between the substrate 254 and the array trenches 230. (Referring to...) Fig. 4B, the substrate 254 can be turned over after BEOL processing and thinning of the BS 258 can be performed as described above. Thinning the BS 258 allows the lower section of the array trenches with the opening in the insulating material 234 to be removed. Thinning the BS 258 can therefore electrically insulate each segment of the substrate 254 from the conductive material 232 of the array trenches 230. Advantageously, the formation of the image sensors 14 according to various such embodiments can protect the array trenches 230 from charge damage during BEOL processing by using only structures and processing from the FS 256. For example, image sensors 14 according to various such embodiments do not require contacts on the BS 258 to protect or pre-stress the array trenches 230.

[0042] Referring to Fig. In some embodiments, the substrate 254 in the peripheral section 210 can be electrically isolated from the array trenches 230. For example, the peripheral section 210 can be free of any substrate contacts 272. The array trenches 230 can be protected from charge damage during BEOL processing by forming a tall stack of vias and metal layers with a small cross-sectional area that remains unconnected until the end of the BEOL processing for trench pre-stressing.

[0043] Referring to Fig. 5B, in some embodiments, a trench contact 270 can be coupled by several vias 274 and areas of two or more metal layers 260, 262, 264, 266, 268 with a small cross-sectional area. For example, the respective vias and metal layers can have the minimum size required to establish electrical connections with lower and / or upper layers, for example, based on various process design rules. In one exemplary embodiment, the trench contacts 270 are coupled during BEOL processing to small areas of the first metal layer 260, the second metal layer 262, the third metal layer 264, and the fourth metal layer 566-1. The small cross-sectional area reduces the risk of charge damage, as described above.

[0044] During BEOL processing, a large area of ​​a metal layer other than the topmost metal layer can also be formed, which can be configured to be coupled to other circuit arrangements of the image sensor 14 to ultimately provide trench prestressing during operation of the image sensor 14. For example, a large area 566-2 of the fourth metal layer 566-2 can be formed and configured to prestress the array trenches 230. The large area 566-2 can retain excess charge during BEOL processing but remains unconnected to the array trenches 230 until the end of BEOL processing. The risk of charge damage to the array trenches 230 and the surrounding structures during BEOL processing is therefore significantly reduced.

[0045] The large area 566-2 and the small areas 566-1 of the non-top-level metal layer can be coupled to a top-level metal layer, for example, the fifth metal layer 268, at the end of the BEOL processing by means of additional vias. Coupling these areas 566-1, 566-2 by the top-level metal layer provides a path for pre-stressing the array trenches 230 during operation of the image sensor 14. Forming the top-level metal layer at the end of the BEOL processing reduces the risk of charge damage to the array trenches 230. It can be seen that some embodiments can include substrate contacts 272 in the peripheral section 210, depending on requirements.It can also be seen that other arrangements of vias and conductive signal lines of the different metal layers can be used to couple the array trenches 230 and / or the substrate 254, with large conductive signal lines remaining unconnected until the end of BEOL processing.

[0046] Fig. Figure 6A illustrates a top view of an exemplary image sensor 14 with array isolation structures that are separated during BEOL processing and coupled by the BS 258 after BEOL processing to allow pre-tensioning of the array isolation structures during operation of the image sensor 14 according to various embodiments. As with respect to Fig. As described in sections 2A to C, the image sensor 14 can have an array section 220 and a peripheral section 210. The peripheral section 210 need not encompass the entire section of the substrate 254 outside the array section 220. The isolation structures for the pixel section 220 can be prestressed after BEOL processing by connecting the BS 258 in the peripheral section 210.

[0047] For the sake of clarity, in the Fig. Figures 6A to C show a simplified subset of the array section 220 and the peripheral section 210. The actual number of trench structures, pixels, substrate and trench connections, and the like may be much higher in many embodiments. Furthermore, since the various trench structures in the entire array section 220 and / or peripheral section 210 may be electrically coupled, some embodiments may only include a subset of the various trench structures and / or substrate sections, each of which has trench and / or substrate connections.

[0048] The image sensor 14 can include arrangements of array trenches 230 and peripheral trenches 630. The array trenches 230 can be configured as described above. The peripheral trenches 630 can include trenches that extend laterally along the substrate 254 through the peripheral section 210, but not through the array section 230. The peripheral trenches 630 do not intersect the array trenches 230 and are therefore not directly electrically coupled to the array trenches 230 by intersecting the different trenches.

[0049] The peripheral trenches 630 can include full trenches (FT trenches), deep trenches (DT trenches), and / or any other suitable trench isolation structures. In some embodiments, the peripheral trenches 630 can include deep trench isolation structures (DTI structures) such as front-end deep trench isolation (FDTI) and / or back-end deep trench isolation (BDTI). In some embodiments, the peripheral trenches 630 are formed at the same time and using the same processes as the array trenches 230.

[0050] Referring to Fig. 6B, in some embodiments, the array trenches 230 and the peripheral trenches 630 can be formed by etching a trench into the FS 256 of the substrate 254 of the image sensor 14. In some embodiments, the array trenches 230 and the peripheral trenches 630 can be partially etched through the substrate 254 in both the array section 220 and the peripheral section 210, such that the substrate 254 remains electrically intact throughout the entire array section 220 and peripheral section 210, as for example in Fig. 2B shown. In some embodiments, the array trenches 230 and peripheral trenches 630 can be completely etched through the substrate 254 in both the array section 220 and the peripheral section 210, so that the substrate 254 in the peripheral section 210 is isolated from the substrate 254 in the array section 220.

[0051] The array trenches 230 and peripheral trenches 630 can be lined with an insulating material 234 as described above. The array trenches 230 and the peripheral trenches 630 can then be filled with a conductive filler 232 as described above. The array trenches 230 of the array section 220 and the peripheral section 210 can be electrically coupled, for example by the conductive filler 232, so that they remain at the same electrical potential. The array trenches 230 can be electrically isolated from the peripheral trenches 630 during FEOL processing.

[0052] The formation of the array trenches 230 and the peripheral trenches 630 can be performed during the FEOL processing of the image sensor 14. In embodiments where the array trenches 230 and peripheral trenches 630 are only partially formed through the substrate 254, the substrate 254 remains electrically intact or is otherwise configured to maintain a constant electrical potential throughout the entire peripheral section 210 and array section 220 at the end of the FEOL processing. In embodiments where the array trenches 230 and peripheral trenches 630 are completely formed through the substrate 254, the substrate 254 in the peripheral section 210 is electrically isolated from the substrate 254 in the array section 220 at the end of the FEOL processing.

[0053] One or more trench contacts 270 can be formed with respect to one or more peripheral trenches 630 in the peripheral section 210. One or more substrate contacts 272 can be formed with respect to one or more segments of the substrate 254 in the peripheral section 210. In some embodiments, no FS contacts are formed with respect to the array trenches 230 during or after FEOL processing, thus electrically isolating the array trenches 230 from the peripheral trenches 630 and the segments of the substrate 254 of the peripheral section 210. The trench contacts 270 and substrate contacts 272 can be formed during or after FEOL processing as desired.

[0054] One or more metal conduction layers can be formed on the front face 256 of the substrate 254 during back-end-of-line (BEOL) processing, as described above. An FS passivation layer 252 (for example, an oxide) on the front face 256 can be part of a first insulating layer (not shown) between the substrate 254 and a first metal layer 260. The trench contacts 270 and substrate contacts 272 can extend through the passivation layer 252 to be electrically coupled to the peripheral trenches 630 and the segments of the substrate 254, respectively.

[0055] The first metal layer 260 can be formed during BEOL processing. In some embodiments, the first metal layer 260 can be electrically coupled to the trench contacts 270 and substrate contacts 272. Through the first metal layer 260, the substrate segments 254 and the peripheral trenches 630 in the peripheral section 210 are essentially at the same electrical potential. In other words, the first metal layer 260 can electrically short-circuit the substrate segments 254 and the peripheral trenches 630.

[0056] During BEOL processing, the array trenches 230 in the peripheral section 210 and the array section 220 remain isolated from the peripheral trenches 630 and the segments of the substrate 254. In some embodiments, for example with trench isolation structures that do not extend completely through the substrate 254, the segments of the substrate 254 in the peripheral section 210 and the array section 220 are essentially at the same electrical potential due to the electrically intact sections of the substrate that extend along the BS 258 in both the peripheral section 210 and the array section 220.

[0057] Therefore, in some exemplary embodiments, the substrate 254 and the peripheral trenches 630 in the peripheral section 210 can remain at essentially the same electrical potential during BEOL processing. If various plasma processes performed during BEOL processing generate excess charge on one or more metal layers, the peripheral trenches 630 and the segments of the substrate 254 remain at an equivalent electrical potential, thereby minimizing or otherwise reducing the electric field between the peripheral trenches 630 and the surrounding substrate 254. Furthermore, the array trenches 230 remain insulated from the metal conduction layers and are thus isolated from charge buildup during BEOL processing. This significantly reduces the risk of charge damage to the substrate 254 and the various trenches 230, 630 of the image sensor 14 during BEOL processing.After BEOL processing from the FS 256, the substrate can be turned over, for example attached to a support wafer, and further processed from the BS 258. If desired, for example in embodiments that include trench insulation structures that do not extend completely through the substrate 254, the substrate 254 can be thinned from the BS 258 at least to the array trenches 230, so that one or more segments of the substrate 254 are no longer in electrical contact. In some embodiments, the substrate 254 can be thinned from the BS 258 to remove the insulating material 234 from the bottom of the array trenches 230 and the peripheral trenches 630 to expose the conductive filler 232. In some embodiments, a passivation area 240 can be formed on the BS 258.

[0058] Therefore, as can be seen through Fig. As shown in Figure 6B, the segments of substrate 254 in array section 220 are electrically isolated from the segments of substrate 254 in peripheral section 210. The segments of substrate 254 in peripheral section 210 may be electrically isolated from the substrate 254 in other sections of the image sensor 14 outside array section 220. The segments of substrate 254 for each pixel in array section 220 may be physically and / or electrically isolated from each other due to thinning of the substrate 258 and / or the formation of full-depth trenches. The segments of substrate 254 in peripheral section 210 may remain electrically coupled to the peripheral trenches 630 via the trench contacts 270 and substrate contacts 272.

[0059] Referring to Fig. 6C, the array trenches 230 can be electrically coupled to the peripheral trenches 630 after BEOL processing. In some embodiments, a large backside area 640, spanning, for example, at least one array trench 230 and one peripheral trench 630, can be opened in the passivation area 240 in the peripheral section 210. The open large backside area 640 can expose the conductive filler 232 of the array trenches 230 and peripheral trenches 630.

[0060] A backside conductive layer 642 can be formed, for example, by deposition within the opening of the large backside region 640. In some embodiments, the backside conductive layer 642 can also extend over the passivation region 240, which surrounds the opening of the large backside region 640. In some embodiments, the backside conductive layer 642 can be formed at the same time and / or from the same material as a metal layer in the array section 220, but electrically isolated from it. For example, the backside conductive layer 642 can be formed from tungsten during the same processing steps as the formation of a tungsten light shield in the pixel array.In some embodiments, the light shield in the pixel array can be grounded, and the rear conductive layer 642 can receive a negative voltage through the peripheral trenches 630 to bias the array trenches 230.

[0061] The backside conductive layer 642 can electrically couple the array trenches 230 with the peripheral trenches 630 in the peripheral section 210. In some embodiments, the segments of the substrate 254 in the peripheral section 210 are also electrically coupled to the array trenches 230 and the peripheral trenches 630 by the backside conductive layer 642. In some embodiments, the backside conductive layer 642 can enclose a metal, for example, tungsten. The array trenches 230 can be biased during operation of the image sensor 14 by the electrical coupling of the backside conductive layer 642, the peripheral trenches 630, the trench contacts 270, the first metal layer 260, and other suitable circuit arrangements of the image sensor 14.

[0062] Advantageously, according to various embodiments, the array trenches 230 can be insulated against charge damage during BEOL processing and can be electrically coupled to the peripheral trenches 630 by a conductive layer 642 on the BS 258 to provide a bias voltage to the array trenches 230 during operation of the image sensor 14. Due to its relatively large size, the conductive layer 642, which couples the peripheral trenches 630 to the array trenches 230, can be a relatively inexpensive contact.

[0063] In some embodiments, with reference to Fig. 7A and Fig. 7B, the substrate contacts 272 located on the FS 256 from the first metal layer 260 to the segments of the substrate 254 in the peripheral section 210 are omitted. Apart from the omission of the substrate contacts 272, the formation of the structures of the peripheral section 210 and the array section 220 can remain the same as with respect to Fig. 6B and Fig. 6C described.

[0064] During BEOL processing, due to the presence of the trench contacts 270 and the omission of the substrate contacts 272, charge may accumulate in the peripheral trenches 630, and these may not remain at the same electrical potential as the surrounding segments of the substrate 254. Charge damage may occur in or around the peripheral trenches 630, and the damage may remain confined to the peripheral section 220, which may be acceptable. Furthermore, the backside conductive layer 642 can electrically couple the peripheral trenches 630 and the segments of the substrate 254 in the peripheral section 210 after BEOL processing, thereby reducing the effects of any charge damage that may have occurred in the peripheral trenches 630.

[0065] As described above, after BEOL processing, the array trenches 230 are electrically coupled to the peripheral trenches 630 by the rear conductive layer 642 and are not subject to charge damage from the BEOL processing. Various embodiments in which the substrate contacts 272 are omitted can otherwise provide the same advantages and functions as described above. Fig. Described in sections 6A to 6C.

[0066] In some embodiments, with reference to Fig. 8A and Fig. 8B, instead of opening the large backside area 640, or additionally, one or more small backside areas 840 can be opened in the passivation area 240. The openings in the small backside area 840 can be aligned with the conductive filler 232 of the array trenches 230 and peripheral trenches 630 in the peripheral section 210 and can avoid opening the passivation area 240 at the substrate segments 254. The open small backside areas 840 can expose the conductive filler 232 of the array trenches 230 and peripheral trenches 630. The openings in the small backside area 840 allow electrical coupling of the array trenches 230 and peripheral trenches 630 through the backside conductive layer 642, while avoiding electrical coupling with the substrate 254.

[0067] In some embodiments, the substrate contacts 272 can be omitted, as described above. Thus, the substrate 254 can remain isolated from the peripheral trenches 630 and array trenches 230 and their respective bias voltages during operation of the image sensor 14, as desired. In some alternative embodiments, the substrate contacts 272 located on the FS 256 can be included to electrically couple the array trenches 230, the peripheral trenches 630, and the segments of the substrate 254 in the peripheral section 210.

[0068] As described above, after BEOL processing, the array trenches 230 are electrically coupled to the peripheral trenches 630 by the backside conductive layer 642 and are not subject to charge damage from the BEOL processing. Various embodiments with small backside areas 840 open in the passivation area 240, and in which the opening(s) of the large backside area 640 are omitted, can otherwise provide the same advantages and functions as described above. Fig. Described in sections 6A to 6C.

[0069] In some embodiments, referring to Fig. 9A and Fig. 9B, the array trenches 230 can be conductively coupled after BEOL processing to generate a bias through a backside conductive layer 642. The backside conductive layer 642 can be formed in a large backside region 940 that is open in the passivation region 240 in the peripheral section 210. The large backside region 940 can span at least one array trench 230 and at least one adjacent segment of the substrate 254 in the peripheral section 210. In some embodiments, the large backside region 940 spans multiple array trenches 230 and multiple segments of the substrate 254. One or more of the substrate 254 segments spanned by the large backside region 940 can be coupled to a substrate contact 272 by the FS 256.

[0070] Fig. Figure 9B illustrates a simplified cross-section of a pixel 222 and the peripheral section 210. The pixel 222 can include a photodiode 910 formed in the substrate 254. The pixel 222 can also include one or more substrate contacts 272 and other structures for performing reset, readout, and other pixel functions. For example, a transistor gate 920 can form part of a transfer transistor (not shown) for transferring charge generated by incident photons and can be controlled via a substrate contact 272.

[0071] In the peripheral section, the substrate 254 adjacent to the array trenches 230 can be highly doped 930 to increase the conductivity of the substrate 254 from FS 256 to BS 258. The substrate 254 can be doped during the formation of the array trenches 230, for example, before filling them with conductive material 232 and / or lining them with insulating material 234. The substrate 254 adjacent to the array trenches 230 in the array section 220 can also be doped during the same process steps.

[0072] The doped sections of substrate 254 in the peripheral section can be coupled to the substrate contacts 272. Trench contacts 270 can be omitted. During BEOL processing, the array trenches 230 can therefore remain insulated from all metal conducting layers and are not subject to charge damage. After BEOL processing and any thinning of the BS 258 (as described above), the large backside area 940 in the passivation area 240 can be opened. Subsequently, the backside conductive layer 642 can be formed and can electrically couple one or more segments of substrate 254 to one or more array trenches 230 in the peripheral section 210.

[0073] The array trenches are electrically coupled for biasing by the rear conductive layer 642, the highly doped substrate 930 adjacent to the array trenches 230, and the substrate contacts 272 in the peripheral section 210. The same type of contacts, for example, the substrate contacts 272 used in the pixels 222, can also be used to bias the segments of the substrate 254 in the peripheral section. Advantageously, therefore, only one type of contact located on the FS 256 is required for both the peripheral section 210 and the array section 220, in order to protect the array trenches 230 from charge damage and to provide a bias to the array trenches 230 during operation of the image sensor 14.

[0074] Fig. 10A and Fig. Figure 10B are simplified block diagrams illustrating exemplary arrangements of the array section 220 and the peripheral section 210. As described above, the image sensor 14 may include other areas on the substrate 254 that are not the peripheral section 210 and the array section 220, and such other areas are not shown for clarity. The peripheral section 210 may be arranged in any suitable manner near the array section 220. Therefore, it can be seen that embodiments according to the present disclosure are not limited to those illustrated in the various figures contained herein.

[0075] Referring to Fig. In 10A, the peripheral section 210 can include one or more substrate areas located essentially at one or more corners of the array section 220, for example, at the four corners of the pixel array. The peripheral sections 210 can be essentially centered at the corners of the array section 220 and, for example, form an "L" shape with sides of equal length. The length of the peripheral sections 210 along the sides of the array section 220 can be minimized to minimize the metal surface area connected to the array trenches 230, peripheral trenches 630, and / or other structures during BEOL processing. Minimizing the connected metal surface area reduces the risk of charge damage.

[0076] Referring to Fig. In Section 10B, the peripheral section 220 can include one or more substrate areas arranged along one or more sides of the array section 220. For example, the image sensor 14 can include two peripheral sections 210, each arranged on opposite sides of the array section 220. Alternatively, the image sensor 14 can include four peripheral sections 210, each arranged on one side of the array section 220 (and, for example, not extending around the corners of the array section 220). The peripheral sections 210 extending along one or more sides of the array section 220 can provide more connections to the array trenches 230, peripheral trenches 630, and / or other structures, and can therefore reduce the resistance to the array trenches 230 in the array section 230.

[0077] Fig.Figure 11 illustrates a simplified process flow for a method 1100 for protecting array trench structures during the formation of an image sensor, for example, according to various embodiments described herein. The method may include a step 1102 of forming one or more array trenches in a substrate during FEOL processing, wherein the array trenches traverse array and peripheral sections of the substrate. The trenches may include deep trenches, for example, deep trenches on the front face. In step 1106, during BEOL processing in the peripheral section, a substrate contact may be formed on the front face of the substrate. The substrate contact may be formed with the substrate adjacent to the array trench. In some embodiments, the formation of the substrate contact may be omitted from the method 1100.

[0078] In step 1108, an electrical contact can be formed in the peripheral section with respect to the array trench. In some embodiments, the electrical contact can include a trench contact that is formed on the front of the substrate during BEOL processing. In step 1112, the substrate can be thinned, for example, from the back of the substrate after BEOL processing. In some embodiments, the substrate can be thinned in step 1112 to at least the bottom surface of the array trenches. In step 1114, a passivation area can be formed on the back of the substrate, for example, after thinning in step 1112.

[0079] Some embodiments include separate peripheral trenches that are coupled to array trenches after BEOL processing. In some of these embodiments, one or more peripheral trenches can be formed during FEOL processing in step 1104. The peripheral trenches can remain isolated from the array trenches during FEOL processing. In some of these embodiments, a front-side trench contact to one or more peripheral trenches can be formed in step 1110 during BEOL processing. Furthermore, in step 1108, the electrical contact to the array trenches can include the formation of a conductive layer on the back side of the substrate.

[0080] The rearward electrical contact can be formed during step 1108 after the thinning process of step 1112. For example, the electrical contact can be formed after step 1116 by forming one or more openings in the passivation area at the array trench and the peripheral trench. The opening(s) can include a large opening spanning both the array trench and the peripheral trench, separate openings at each of the array trench and the peripheral trench, and / or the like. The array trench can be coupled to the peripheral trench via the conductive layer at the opening(s) in the passivation area.

[0081] Accordingly, the steps of the exemplary methods described herein can be carried out in any suitable order, and the sequences of steps for forming the various structures described herein can be rearranged without deviating from the scope of protection of the invention.

[0082] Various embodiments therefore provide array trench isolation in a pixel array that is pre-stressed at a peripheral section of the image sensor. Various embodiments provide multiple arrangements for pre-stressing array trenches from the periphery, while protecting the array trenches from damage during BEOL processing. The systems, devices, and methods described herein provide improved load handling during BEOL processing.

[0083] Advantageously, the systems, devices, and methods described herein can provide reduced dark current through the use of prestressed array trenches, increased yield through minimizing charge damage, and lower costs through the use of large backside structures and / or standard frontside contacts. While the various trenches and other structures described herein may be said to belong to the FS 256 or BS 258, it is apparent that the structures and processes described herein can be suitably adapted for use on the alternative BS 258 or FS 256. The various trenches, contacts, and other structures can be distributed in any suitable manner within the substrate 254, and in other embodiments, the processing of various features can be organized in any number of other ways.

[0084] The general concepts set forth herein can be adapted to any number of alternative but equivalent embodiments. The term "exemplary" is used herein to represent an example, instance, or illustration that may have any number of alternatives. Each implementation described herein as "exemplary" is not necessarily to be construed as preferable or advantageous over other implementations, nor is it necessarily intended as a model that must be duplicated in other implementations. Although several exemplary embodiments have been presented in the preceding detailed description, it should be apparent that a large number of alternative but equivalent variations exist, and the examples presented herein are not intended to limit the scope of protection, applicability, or configuration of the invention in any way.Rather, various changes to the described function and arrangement of elements as well as the sequence of steps can be made without deviating from the scope of protection of the claims and their legal equivalents.

Claims

[1] Semiconductor device comprising: a substrate comprising an array section and a peripheral section; a plurality of substrate segments defined by a plurality of array trenches in the substrate, wherein the plurality of substrate segments include a first substrate segment in the peripheral section; a first array trench of the plurality of array trenches, wherein the first array trench traverses the array section and the peripheral section; a second array trench of the plurality of array trenches in the array section, wherein the first array trench intersects the second array trench in the array section; a first trench contact coupled to the first array trench in the peripheral section; a first substrate contact coupled with the first substrate segment; and a conductive signal line that electrically couples the first trench contact and the first substrate contact. [2] Semiconductor device according to claim 1, wherein the peripheral section is adjacent to the array section. [3] Semiconductor device according to claim 2, wherein: the peripheral section comprises a variety of substrate areas; and Each substrate area is located at a corner of the peripheral section. [4] Semiconductor device according to claim 1, wherein the first substrate segment is adjacent to the first array trench. [5] Semiconductor device according to claim 1, wherein the first trench contact and the first substrate contact are located on a front side of the substrate. [6] Semiconductor device according to claim 1, wherein the plurality of array trenches extend from a front side of the substrate to a back side of the substrate. [7] Semiconductor device according to claim 1, wherein the plurality of array trenches extend from a front side of the substrate and do not intersect a back side of the substrate. [8] Semiconductor device according to claim 1, wherein the first substrate contact is coupled to a protection diode in the first substrate segment. [9] Semiconductor device according to claim 1, wherein the first array trench comprises: a lining made of insulating material; and a filler made of conductive material, wherein: the insulating lining is open at a bottom surface of the first array trench; and The conductive filler is coupled to the substrate through the opening in the insulating lining. [10] Semiconductor device comprising: a substrate comprising an array section and a peripheral section; a variety of array trenches, including: a first array trench that traverses both the array section and the peripheral section; and a second array trench in the array section, wherein the first array trench intersects the second array trench and is electrically coupled to it; a peripheral trench in the peripheral section, wherein the peripheral trench does not intersect any of the multiple array trenches; a trench contact that is coupled to the peripheral trench in the peripheral section, where the trench contact is located on one front side of the substrate; and a conductive layer on a back side of the substrate, wherein the conductive layer couples the peripheral trench to the first array trench at the peripheral section. [11] Semiconductor device according to claim 10, wherein the substrate comprises a plurality of substrate segments defined by the peripheral trench and the first array trench, wherein the semiconductor device further comprises: a substrate contact coupled to at least one of the plurality of substrate segments at the front in the peripheral section, wherein the trench contact and the substrate contact are electrically coupled by a conductive signal line. [12] Semiconductor device according to claim 10, further comprising: a passivation area on the back of the substrate, wherein the conductive layer is coupled to the peripheral trench and the first array trench through a large opening in the passivation area. [13] Semiconductor device according to claim 10, further comprising: a passivation area on the back of the substrate, wherein: the conductive layer is coupled to the peripheral trench and the first array trench by a first small opening in the passivation area at the peripheral trench and a second small opening in the passivation area at the first array trench; and the conductive layer between the peripheral trench and the first array trench is not coupled to the substrate. [14] Semiconductor device according to claim 10, wherein the plurality of array trenches and the peripheral trench extend from the front of the substrate to the back of the substrate. [15] Semiconductor device according to claim 10, wherein: the array section comprises a large number of pixels; and The multitude of array trenches defines the multitude of pixels. [16] Method for forming an image sensor on a substrate, comprising: Forming a multitude of deep trenches from one side of the substrate during front-end-of-line (FEOL) processing, wherein: the multitude of deep trenches are formed in an array section of the substrate and in a peripheral section of the substrate; and a first trench of the multitude of deep trenches includes an array trench that crosses the array section and the peripheral section; Forming, in the peripheral section, a substrate contact with the substrate adjacent to the first trench on the front of the substrate during back-end-of-line (BEOL) processing; Forming an electrical contact with the first trench in the peripheral section; and Thinning the substrate from one side of the substrate after BEOL processing. [17] Method according to claim 16, wherein the electrical contact comprises a trench contact formed on the front of the substrate during BEOL processing. [18] Method according to claim 16, wherein the thinning step comprises thinning the substrate to at least one soil surface of the plurality of deep trenches. [19] Method according to claim 16, wherein a second trench of the plurality of deep trenches comprises a peripheral trench which is isolated from the first trench during FEOL processing, the method further comprising: Forming a trench contact at the front of the substrate to the second trench in the peripheral section, wherein: the electrical contact comprises a conductive layer on the back side of the substrate; and The conductive layer couples the first trench with the second trench at the peripheral section. [20] The method of claim 19, further comprising: Forming a passivation zone on the back side of the substrate after the thinning step; and Forming one or more openings in the passivation area at the first trench and the second trench, wherein the conductive layer couples the first trench to the second trench through one or more openings.

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