Semiconductor device and semiconductor system

Abstract

The semiconductor device comprises a first power supply voltage line to which a power supply voltage is supplied, a second power supply voltage line, a first impedance element provided between the first power supply voltage line and the second power supply voltage line, a first reference voltage line to which a reference voltage is supplied, a second reference voltage line, a second impedance element provided between the first reference voltage line and the second reference voltage line, an electronic circuit provided between the second power supply voltage line and the second reference voltage line and performing predetermined processing on an input signal, and provided in series between the second power supply voltage line and the second reference voltage line and having gates connected to drains,a first transistor which is a P-channel MOS transistor and a second transistor which is an N-channel MOS transistor.,

Description

CROSS REFERENCE TO RELATED APPLICATIONSThe disclosure of Japanese Patent Application No. 2023-207599 filed on Dec. 8, 2023, including the specification, the drawings and the abstract, is incorporated herein by reference in its entirety.BACKGROUNDThe present disclosure relates to a semiconductor device and a semiconductor system provided therewith, for example, relating to a semiconductor device and a semiconductor system suitable for achieving low power consumption.Techniques listed below are disclosed.[Patent Document 1] Japanese Patent Application Laid-Open No. 2007-332705There is a need to reduce power consumption in semiconductor systems. In particular, in recent years, for example, there is a need for reducing standby power consumption in systems such as keyless entry systems installed in vehicles and alarm systems installed in vehicles. That is, in recent years, there is a need for reducing standby power consumption in semiconductor systems and semiconductor devices installed therein. An example of technologies related to keyless entry systems is disclosed in Patent Document 1.SUMMARYAs described above, there is a need for reducing standby power consumption in semiconductor devices and semiconductor systems equipped therewith. Other objects and novel features will become apparent from the description of this application text and the accompanying drawings.The semiconductor device according to the present disclosure includes a first power supply voltage line to which a power supply voltage is supplied, a second power supply voltage line, a first impedance element provided between the first power supply voltage line and the second power supply voltage line, a first reference voltage line to which a reference voltage is supplied, a second reference voltage line, a second impedance element provided between the first reference voltage line and the second reference voltage line, an electronic circuit provided between the second power supply voltage line and the second reference voltage line and performing predetermined processing on an input signal, and a first transistor being a P-channel MOS transistor and a second transistor being an N-channel MOS transistor, both of which are provided in series between the second power supply voltage line and the second reference voltage line, and the gates of which are connected to their drains, respectively.The present disclosure may provide a semiconductor device and a semiconductor system provided therewith, which are capable of achieving low power consumption.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is a diagram showing a configuration example of a semiconductor device according to a first embodiment. FIG. 2 is a waveform diagram showing the operation of the semiconductor device shown in FIG. 1. FIG. 3 is a diagram showing a configuration example of a semiconductor device according to a second embodiment. FIG. 4 is a diagram showing a configuration example of a semiconductor system according to a third embodiment. FIG. 5 is a diagram showing simulation results of an EYE opening in a comparative example of a semiconductor system. FIG. 6 is a diagram showing simulation results of an EYE opening in the semiconductor system shown in FIG. 4. FIG. 7 is a diagram showing a configuration example of a semiconductor system according to a fourth embodiment. FIG. 8 is a diagram showing a specific configuration example of a first pseudo impedance circuit provided in the semiconductor system shown in FIG. 7. FIG. 9 is a diagram showing a specific configuration example of a second pseudo impedance circuit provided in the semiconductor system shown in FIG. 7. FIG. 10 is a diagram showing simulation results of an EYE opening in the semiconductor system shown in FIG. 7. FIG. 11 is a diagram showing AC analysis results of the semiconductor system shown in FIG. 7 when noise is applied to the power supply voltage VDD. FIG. 12 is a diagram showing a modified example of the semiconductor system shown in FIG. 7. FIG. 13 is a diagram showing a configuration example of a semiconductor device that has been pre-tested. FIG. 14 is a waveform diagram showing the operation of the semiconductor device shown in FIG. 13.DETAILED DESCRIPTIONHereinafter, embodiments will be described with reference to the drawings. It should not be construed closely to the technical scope of the embodiments based on the description of the drawings, because the drawings are simplified. In addition, the same reference numerals are assigned to the same elements, and redundant descriptions are omitted.For convenience, the following embodiments will be described in several sections, if necessary, or divided into different embodiments. Unless expressly stated otherwise, however, they are not in any reference to each other; one may refer to the other as part or all of modifications, applications, detailed explanations, supplementary explanations, etc. Moreover, in the following embodiments, when referring to the number of elements, etc. (including the number of elements, numerical values, amounts, ranges, etc.), it is not limited to the specific number, but may not be less than or equal to the specific number, except for cases where the number is expressly stated and is clearly limited to the specific number in principle.Moreover, in the following embodiments, the constituent elements (including the operation steps and the like) are not necessarily essential except for the case where they are expressly stated and the case where they are considered to be obviously essential in principle. Likewise, in the following embodiments, when referring to the shapes, positional relationships, and the like of components and the like, it is assumed that the shapes and the like are substantially approximate or similar to the shapes and the like except for the case where they are expressly stated and the case where they are considered to be obvious in principle, and the like. The same applies to the above-mentioned numbers and the like including the number, the numerical value, the amount, the range, and the like.(Preliminary Examination by the Inventors)First, a semiconductor device that has been preliminarily studied by the inventors will be described. FIG. 13 is a diagram showing an example of the configuration of the preliminarily inspected semiconductor device 50.As shown in FIG. 13, the semiconductor device 50 includes a power supply voltage terminal to which an external power supply voltage VDD is supplied, a reference voltage terminal to which an external reference voltage GND is supplied, an input terminal to which an external input signal IN is supplied, and a logic circuit (electronic circuit) 51.For example, the power supply voltage VDD indicates 3.3 V and the reference voltage GND indicates 0 V. Hereinafter, the line to which the power supply voltage VDD is supplied is referred to as the first power supply voltage line VDD, and the line to which the reference voltage GND is supplied is referred to as the first reference voltage line GND. The logic circuit 51 is provided between the first power supply voltage line VDD and the first reference voltage line GND, and performs a predetermined process on the input signal IN. In other words, the logic circuit 51 is driven by the power supply voltage VDD and the reference voltage GND, and performs a predetermined process on the input signal IN.The lower the average consumption current (dark current) of the logic circuit 51, the more the power consumption of the semiconductor device 50 is suppressed. For example, when the semiconductor device 50 is installed in a vehicle as part of a keyless entry system, the lower the dark current of the logic circuit 51, the more the consumption of the energy stored in the vehicle battery is suppressed.FIG. 14 is a waveform diagram showing the operation of the semiconductor device 50. In FIG. 14, the scale of the logic circuit 51 is equivalent to 2K gates with respect to NAND gates, the frequency of the master clock signal supplied to the logic circuit 51 is 16 MHz, and the operation rate of the logic circuit 51 is assumed to be 50%. In this case, the peak current of the logic circuit 51 is indicated as 225 mA, and the average consumption current (dark current) of the logic circuit 51 is indicated as 4.8 mA. In recent years, there is a need for further reducing the average power consumption of the logic circuits 51.Therefore, a semiconductor device 1 capable of realizing low power consumption has been found.(First Embodiment)FIG. 1 is a diagram showing an example of the configuration of the semiconductor device 1 according to a first embodiment. For example, the semiconductor device 1 is applicable to a keyless entry system mounted on a vehicle or an alarm system mounted on a vehicle.As shown in FIG. 1, the semiconductor device 1 includes a power supply voltage terminal to which an external power supply voltage VDD is supplied, a reference voltage terminal to which an external reference voltage GND is supplied, an input terminal to which an external input signal IN is supplied, a resistance element (first impedance element) R 1, a resistance element (second impedance element) R 2, a transistor (first transistor) MP 1 that is a P-channel MOS transistor, a transistor (second transistor) MN 1 that is an N-channel MOS transistor, and a logic circuit (electronic circuit) 10.For example, the power supply voltage VDD indicates 3.3 V and the reference voltage GND indicates 0 V. Hereinafter, the line to which the power supply voltage VDD is supplied is referred to as the first power supply voltage line VDD, and the line to which the reference voltage GND is supplied is referred to as the first reference voltage line GND. The resistor element R 1 is provided between the first power supply voltage line VDD and the second power supply voltage line VDD 2. The resistance element R 2 is provided between the first reference voltage line GND and the second reference voltage line GND 2.The logic circuit 10 is provided between the second power supply voltage line VDD 2 and the second reference voltage line GND 2, and performs a predetermined process on the input signal IN. In other words, the logic circuit 10 is driven by the power supply voltage (hereinafter referred to as the power supply voltage VDD 2) of the second power supply voltage line VDD 2 and the reference voltage (hereinafter referred to as the reference voltage GND 2) of the second reference voltage line GND 2, and performs a predetermined process on the input signal IN. The source and back gates of each P-channel MOS transistor provided in the logic circuit 10 are connected to the second power supply voltage line VDD2. Further, the source and back gates of each N-channel MOS transistor provided in the logic circuit 10 are connected to the second reference voltage line GND 2.The transistors MP 1, MN 1 are provided in series between the second power supply voltage line VDD 2 and the second reference voltage line GND 2. Specifically, in the transistor MP 1, the source and the back gates are connected to the second power supply voltage line VDD 2, and the gate and the drain are connected to the gate and the drain of the transistor MN 1. In the transistor MN 1, the source and the back gates are connected to the second reference voltage line GND 2. By providing the transistors MP 1, MN 1, the power supply voltage of the second power supply voltage line VDD 2 and the reference voltage of the second reference voltage line GND 2 are stabilized.The smaller the dark current of the logic circuit 10, the more the power consumption of the semiconductor device 1 is suppressed. For example, when the semiconductor device 1 is mounted on a vehicle, the smaller the dark current of the logic circuit 10, the more the consumption of the energy stored in the vehicle battery is suppressed.FIG. 2 is a waveform diagram showing the operation of the semiconductor device 1. In FIG. 2, the scale of the logic circuit 10 is 2K gates when it is converted into NAND gates, the frequency of the master clock signal supplied to the logic circuit 10 is 16 MHz, and the operation rate of the logic circuit 10 is assumed to be 50%. In this case, the average consumption current of the logic circuit 10 is shown to be 1.4 mA, which is an improvement over the case of the logic circuit 51.Specifically, when the gate charge-discharge current of the operation transistors provided in the logic circuit 10 is referred to as I_sw and the through current of the operation transistors provided in the logic circuit 10 is referred to as I_bick, the average consumption current of the logic circuit 10, that is, the dark current I_dark of the logic circuit 10, is represented by the following equation (1).Further, when the frequency of the master clock signal supplied to the logic circuit 10 is referred to as f, the gate capacitance of the operation transistors provided in the logic circuit 10 is referred to as C, and the amplitude of the clock signal is referred to as Vf, the gate charge-discharge current I_sw is represented by the following equation (2).Here, when the power supply voltage VDD is referred to as VDD and the resistance values of the resistance elements R 1, R 2 are referred to as R 1, R 2, the amplitude of the clock signal Vf is represented by the following equation (3).When the threshold voltage of each transistor is referred to as Vt, Equation (4) is established from Equation (3).That is, the through current I_bick is proportional to (Vf-Vt)^2.For example, in the logic circuit 51 provided in the semiconductor device 50 shown in FIG. 13, the amplitude of the clock signal Vf is VDD=3.3 V, whereas in the logic circuit 10 provided in the semiconductor device 1 shown in FIG. 1, the amplitude of the clock signal Vf is VDD- (I_dark x (R1+R2))<3.3 V. That is, in the logic circuit 10 provided in the semiconductor device 1, as compared with the case of the logic circuit 51 provided in the semiconductor device 50, the amplitude of the clock signal Vf is smaller, resulting in a smaller gate charge-discharge current I_sw and through current I_bick, and as a result, the dark current I_dark is reduced. Designers and the like can effectively suppress the dark current I_dark of the logic circuit 10 provided in the semiconductor device 1 by previously understanding the maximum value of the dark current I_dark and setting, for example, the resistance values of the resistance elements R 1, R 2 so that the amplitude Vf of the clock signal becomes smaller within the operation range of the logic circuit 10.Thus, the semiconductor device 1 according to the present embodiment includes a second power supply voltage line VDD 2 connected to the first power supply voltage line VDD via the resistor element R 1 and a second reference voltage line GND 2 connected to the first reference voltage line GND via the resistor element R 2, between which the logic circuit 10 and transistors MP 1, MN 1 connected in series are provided. Therefore, the semiconductor device 1 according to the present embodiment can reduce the amplitude Vf of the clock signal supplied to the logic circuit 10 within the operation range of the logic circuit 10, thereby reducing the dark current of the logic circuit 10. In other words, the semiconductor device 1 according to the present embodiment can achieve low power consumption.(Second Embodiment)FIG. 3 is a diagram showing an example of the configuration of the semiconductor device 2 according to a second embodiment.As shown in FIG. 3, the semiconductor device 2 includes the logic circuit 20 instead of the logic circuit 10 as compared with the semiconductor device 1. The back gates of each N-channel MOS transistor provided in the logic circuit 20 are connected to the first reference voltage line GND instead of the second reference voltage line GND 2. The other configurations of the semiconductor device 2 are the same as those of the semiconductor device 1, and description thereof is omitted.When simulations were performed under the same conditions as for the semiconductor device 1, the average consumption current (dark current) of the logic circuit 20 showed 679 μA, which was an improvement over the case of the logic circuit 10. This is because, as shown in the above-mentioned equation (4), the threshold voltage Vt of each transistor has been increased due to the back gate effect, resulting in a smaller leakage current I_bick.Thus, the semiconductor device 2 can achieve effects equal to or greater than those of the semiconductor device 1.In the present embodiment, the case where all the back gates of the P-channel MOS transistors in the logic circuit 20 are connected to the first power supply voltage line VDD and all the back gates of the N-channel MOS transistors are connected to the first reference voltage line GND will be described as an example, but is not limited thereto. It is only necessary that at least some of the back gates of the P-channel MOS transistors in the logic circuit 20 are connected to the first power supply voltage line VDD and at least some of the back gates of the N-channel MOS transistors are connected to the first reference voltage line GND.(Third Embodiment)FIG. 4 is a diagram showing an example of the configuration of the semiconductor system 3 according to a third embodiment. The semiconductor system 3 adopts the configuration of the semiconductor device 1. The semiconductor system 3 is used in, for example, a keyless entry system installed in a vehicle.Specifically, the semiconductor system 3 includes a semiconductor device 1 a, a crystal oscillator 13, a capacitive element (first capacitive element) Cxi, and a capacitive element (second capacitive element) Cxo. Further, the semiconductor device 1 aincludes a feedback resistor Rf, a buffer 11, and an inverter 12 in addition to the components of the semiconductor device 1.In the semiconductor device 1 a, the gates of the transistors MP 1, MN 1 are respectively connected to the external terminal XI, and the drains of the transistors MP 1, MN 1 are respectively connected to the external terminal XO. The crystal oscillator 13 is provided between the external terminal XI and the external terminal XO of the semiconductor device 1 aoutside the semiconductor device 1 a. That is, the crystal oscillator 13 is provided between the gates of the transistors MP 1, MN 1 and the drains of the transistors MP 1, MN 1 via the external terminals XI, XO of the semiconductor device 1 a.The capacitive element Cxi is provided between the external terminal XI of the semiconductor device 1 aand the reference voltage terminal GND outside the semiconductor device 1 a. The capacitive element Cxo is provided between the external terminal XO of the semiconductor device 1 aand the reference voltage terminal GND outside the semiconductor device 1 a.In the semiconductor device 1 a, the feedback resistor Rf is provided between the gates of the transistors MP 1, MN 1 and the drains of the transistors MP 1, MN 1. The buffer 11 is a so-called Schmitt buffer that drives and outputs the output signals of the drains of the transistors MP 1, MN 1. The inverter 12 outputs the inverted signal of the output signal of the buffer 11. The output signal of the inverter 12 is supplied to the logic circuit 10 as a clock signal.FIG. 5 is a diagram showing the simulation results of the EYE opening (EYE pattern) in the semiconductor system of the comparative example. In the semiconductor system of the comparative example, as compared with the semiconductor system 3, the resistance values of the resistance elements R 1, R 2 are set to 0Ω. Therefore, the power supply voltage VDD 2 of the second power supply voltage line VDD 2 indicates the same 3.3 V as the power supply voltage VDD. Further, the power supply voltage GND 2 of the second reference voltage line GND 2 indicates the same 0 V as the reference voltage GND.In FIG. 5, the oscillation frequency of the crystal oscillator 13 is 16 MHz, the scale of the logic circuit 10 is 40K gate when it is converted into NAND gates, the frequency of the master clock signal supplied to the logic circuit 10 is 16 MHz, and the operation rate of the logic circuit 10 is assumed to be 50%. Further, in FIG. 5, the amplitude of the external noise is assumed to be 3.3 V±100 mV, and the frequency of the external noise is assumed to be 40 MHz.In this case, the semiconductor system of the comparative example showed a jitter of 6.52 nsec / 100 mV.FIG. 6 is a diagram showing the simulation results of the EYE opening in the semiconductor system 3. In FIG. 6, while the power supply voltage VDD of the first power supply voltage line VDD indicates 3.3 V, the power supply voltage VDD 2 of the second power supply voltage line VDD 2 indicates 2.7 V due to the voltage drop by I_dark×R 1. Moreover, in FIG. 6, while the reference voltage GND of the first reference voltage line GND indicates 0 V, the reference voltage GND 2 of the second reference voltage line GND 2 indicates 0.5 V due to the voltage increase by I_dark×R 2.In the semiconductor system 3, when simulations were performed under the same conditions as the comparative example semiconductor system except for the resistance values of the resistance elements R 1, R 2, the jitter showed 2.74 nsec / 100 mV. That is, in the semiconductor system 3, the jitter was suppressed to about 42% compared to the case of the comparative example semiconductor system.In recent years, in the automobile industry, IEC62132-4 (DPI method) has attracted attention as an EMC test for ICs (integrated circuits) standardized by the IEC (International Electrotechnical Commission) standard. In this DPI method, even if noise of about ±600 mV is superimposed on the 3.3 V power supply voltage VDD supplied to the local pin based on 500 conversion, the IC is required not to malfunction. A local pin refers to a pin that is not connected to the outside of the ECU but is connected to components including other ICs within the ECU.Here, there is a proportional relationship between the noise superimposition amount of the power supply voltage VDD and the jitter. Therefore, in order to examine whether the comparative example semiconductor system satisfies the requirements of the DPI method, when the amplitude of the external noise, that is, the noise superposition amount of the power supply voltage VDD, was set to 3.3 V±600 mV in the simulation conditions of FIG. 5, the jitter exhibited 39.12 nsec / 100 mV (=6.52 x 6 nsec / 100 mV), and the EYE opening became narrow.In contrast, in order to examine whether the semiconductor system 3 satisfies the requirements of the DPI method, when the amplitude of the external noise, that is, the noise superposition amount of the power supply voltage VDD, was set to 3.3 V±600 mV in the simulation conditions of FIG. 6, the jitter showed 16.44 nsec / 100 mV (=2.74 x 6 nsec / 100 mV), and the EYE opening was maintained in a wide state. That is, the semiconductor system 3 can maintain the EYE opening in a wide state without using external components such as an external low-pass filter. In other words, the semiconductor system 3 can achieve low jitter.The low jitter achieved by the semiconductor system 3 will be explained in more detail. For example, when +100 mV noise is superimposed on the power supply voltage VDD, the power supply voltage VDD 2 also immediately increases by ΔVDD. At this time, the gate-source voltage of each of the transistors MP 1, MN 1 immediately increases, and current flows through the transistors MP 1, MN 1 and the resistor element R 2, resulting in the reference voltage GND 2 also immediately increasing by ΔGND. Thus, the potential difference between the power supply voltage VDD2 and the reference voltage GND2 is kept almost constant even when noise occurs. That is, the semiconductor system 3 can achieve low jitter because it is less affected by noise.Thus, the semiconductor system 3 including an oscillation circuit to which the configuration of the semiconductor device 1 is applied can achieve not only low power consumption similar to the semiconductor device 1 but also wide EYE opening without using external components such as external low-pass filters, thereby realizing low jitter.(Fourth Embodiment)FIG. 7 is a diagram showing an example of the configuration of a semiconductor system 4 according to a fourth embodiment. The semiconductor system 4 includes a semiconductor device 1 bin place of the semiconductor device 1 acompared to the semiconductor system 3. the semiconductor device 1 bincludes pseudo inductance circuits L 1, L 2 in place of resistance elements R 1, R 2. The pseudo inductance circuits L 1, L 2 are configured to form a pseudo inductance circuit by using transistors or the like instead of coils. Thus, the semiconductor device 1 bcan suppress an increase in circuit size more than when using coils. The other configurations of the semiconductor system 4 are the same as those of the semiconductor system 3, and therefore, the description thereof is omitted.FIG. 8 is a diagram showing a specific example of the configuration of the pseudo inductance circuit L 1. As shown in FIG. 8, the pseudo inductance circuit L1 includes transistors MU1 to MU4, a capacitance element CU1 and a resistance element RU1. The transistor MU1 is a P-channel MOS transistor, and the transistors MU2 to MU4 are N-channel MOS transistors.In the transistor MU 1, the source is connected to a first power supply voltage line VDD, and the drain is connected to a second power supply voltage line VDD 2. The capacitance element CU 1 is provided between the gate of the transistor MU 1 and a first reference voltage line GND. In the transistor MU 2, the source is connected to the gate of the transistor MU 1, the drain is connected to the first power supply voltage line VDD, and the gate is connected to the second power supply voltage line VDD 2. In the transistor MU 3, the source is connected to the first reference voltage line GND, and the drain is connected to the source of the transistor MU 2. The resistor element RU 1 is provided between the first power supply voltage line VDD and the gate of the transistor MU 3. In the transistor MU 4, the source is connected to the first reference voltage line GND, and both the drain and the gate are connected to the gate of the transistor MU 3.FIG. 9 is a diagram showing a specific example of the configuration of the pseudo inductance circuit L 2. As shown in FIG. 9, the pseudo inductance circuit L 2 includes transistors ML 1 to ML 4, a capacitance element CL 1, and a resistance element RL 1. The transistor ML1 is an N-channel MOS transistor, and the transistors ML2 to ML4 are P-channel MOS transistors.In the transistor ML 1, the source is connected to the first reference voltage line GND, and the drain is connected to the second reference voltage line GND 2. The capacitive element CL 1 is provided between the gate of the transistor ML 1 and the first power supply voltage line VDD. In the transistor ML 2, the source is connected to the gate of the transistor ML 1, the drain is connected to the first reference voltage line GND, and the gate is connected to the second reference voltage line GND 2. In the transistor ML 3, the source is connected to the first power supply voltage line VDD, and the drain is connected to the source of the transistor ML 2. The resistor element RL 1 is provided between the first reference voltage line GND and the gate of the transistor ML 3. In the transistor ML 4, the source is connected to the first power supply voltage line VDD, and both the drain and the gate are connected to the gate of the transistor ML 3.FIG. 10 is a diagram showing the simulation results of the EYE opening in the semiconductor system 4. When a simulation was performed under the same conditions as in the semiconductor system 3 in the semiconductor system 4, the jitter showed 1.03 nsec / 100 mV. That is, in the semiconductor system 4, the jitter is further suppressed compared to the semiconductor system 3.Further, in order to examine whether the semiconductor system 4 satisfies the requirements of the DPI method, under the simulation conditions of FIG. 10, when the amplitude of the noise is superimposed on the power supply voltage VDD, that is, the amplitude of the external noise is set to 3.3 V±600 mV, the jitter shows 6.18 nsec / 100 mV (=1.03 x 6 nsec / 100 mV), and the EYE opening is maintained in a wide state. That is, the semiconductor system 4 can maintain the EYE opening in a wider state compared to the semiconductor system 3. In other words, the semiconductor system 4 can further reduce the jitter as compared with the semiconductor system 3.FIG. 11 is a diagram showing the AC analysis results of the semiconductor system 4 when noise is applied to the power supply voltage VDD. In FIG. 11, the vertical axis 20 represents log (GND2 / VDD2), and the horizontal axis represents frequency in logarithmic notation. As shown in FIG. 11, in the semiconductor system 4, due to the provision of pseudo inductance circuits L 1, L 2 instead of resistance elements R 1, R 2, the following capability of the reference voltage GND 2 to the power supply voltage VDD 2 is improved for frequencies above 10 MHz. Therefore, the semiconductor system 4 can further reduce the jitter as compared with the semiconductor system 3.In the present embodiment, the case where the semiconductor system 4 is provided with pseudo inductance circuits L 1, L 2 instead of resistance elements R 1, R 2 will be described as an example, but is not limited thereto. As shown in FIG. 12, the semiconductor system 4 may be provided with impedance elements Z 1, Z 2 capable of realizing functions equivalent to those of resistance elements R 1, R 2 or pseudo inductance circuits L 1, L 2, etc.FIG. 12 is a diagram showing a modified example of the semiconductor system 4 as the semiconductor system 4 a. The semiconductor system 4 ais provided with a semiconductor device 1 cin place of a semiconductor device 1 bin comparison with the semiconductor system 4. The semiconductor device 1 cis provided with impedance elements Z 1, Z 2 instead of resistance elements R 1, R 2. The other configurations of the semiconductor system 4 aare the same as those of the semiconductor system 4, and therefore, the description thereof will be omitted.As described above, the semiconductor device according to the present disclosure includes a second power supply voltage line VDD 2 connected to the first power supply voltage line VDD via the resistor element R 1 and a second reference voltage line GND 2 connected to the first reference voltage line GND via the resistor element R 2, between which a logic circuit and transistors MP 1, MN 1 connected in series are provided. Thereby, the semiconductor device according to the present disclosure can reduce the amplitude Vf of the clock signal supplied to the logic circuit within the operation range of the logic circuit, thereby reducing the dark current of the logic circuit. In other words, the semiconductor device according to the present disclosure can achieve low power consumption.Further, a semiconductor system including an oscillation circuit to which the configuration of the semiconductor device disclosed herein is applied can achieve not only low power consumption but also a wide EYE opening without using external components such as an external low-pass filter, thereby realizing low jitter.Although the invention made by the inventor has been specifically described based on the embodiment, the present invention is not limited to the embodiment already described, and needless to say, various modifications may be made without departing from the gist thereof.For example, in this disclosure, the case where the semiconductor device 1 includes resistance elements R 1, R 2 has been described as an example, but is not limited thereto. The semiconductor device 1 can be suitably modified into a configuration including impedance elements Z 1, Z 2 such as pseudo inductance circuits L 1, L 2 instead of the resistance elements R 1, R 2. Likewise, in this disclosure, the case where the semiconductor device 2 includes resistance elements R 1, R 2 has been described as an example, but is not limited thereto. The semiconductor device 2 can be suitably modified into a configuration including impedance elements Z 1, Z 2 such as pseudo inductance circuits L 1, L 2 instead of the resistance elements R 1, R 2.Moreover, in this disclosure, the case where the semiconductor system 3 includes the semiconductor device 1 has been described as an example, but is not limited thereto. The semiconductor system 3 may be appropriately modified to a configuration including the semiconductor device 2 instead of the semiconductor device 1. In other words, the semiconductor system 3 may be appropriately modified to a configuration including the logic circuit 20 instead of the logic circuit 10. Likewise, in this disclosure, the case where the semiconductor system 4 includes the semiconductor device 1 has been described as an example, but is not limited thereto. The semiconductor system 4 may be appropriately modified to a configuration including the semiconductor device 2 instead of the semiconductor device 1. In other words, the semiconductor system 4 can be suitably modified into a configuration including the logic circuit 20 instead of the logic circuit 10.Further, this disclosure may be implemented by executing a computer program on a CPU to perform some or all of the processes of the semiconductor system including the semiconductor device 1, the semiconductor device 2, or either of them.The above-mentioned program, when loaded into a computer, comprises a group of instructions (or software code) for causing the computer to perform one or more functions described in the embodiment. The program may be stored on a non-transitory computer readable medium or a tangible storage medium. By way of example, and not limitation, non-transitory computer-readable media or tangible storage media may include RAM (random access memory), ROM (read only memory), flash memory, SSD (solid state drive), or other memory technology, CD-ROM, DVD (digital versatile disc), Blu-ray (registered trademark) disc, or other optical disk storage, magnetic cassette, magnetic tape, magnetic disk storage, or other magnetic storage devices. The program may also be transmitted on a transitory computer readable medium or communication medium. By way of example, and not limitation, transitory computer readable media or communication media may include electrical, optical, acoustic, or other forms of propagated signals.References included in the specificationThis list of documents cited by the applicant has been produced in an automated manner and is only included for the better information of the reader. The list is not part of the German patent application or utility model application. The DPMA does not take any adhesion for any faults or omissions.Patent Literature citedJP 2023-20759

[0001]

Claims

A semiconductor device, comprising: a first power supply voltage line to which a power voltage is supplied; a second power supply voltage line; a first impedance element provided between the first power supply voltage line and the second power supply voltage line; a first reference voltage line to which a reference voltage is supplied; a second reference voltage line; a second impedance element provided between the first reference voltage line and the second reference voltage line; an electronic circuit provided between the second power supply voltage line and the second reference voltage line and configured to perform predetermined processing on an input signal; and a first transistor which is a P-channel MOS transistor and a second transistor which is an N-channel MOS transistor, both of which are provided in series between the second power supply voltage line and the second reference voltage line and each of which has its gate connected to its drain; in the semiconductor device.The semiconductor device according to claim 1, wherein the first impedance element and the second impedance element are both resistance elements.The semiconductor device according to claim 1, wherein the first impedance element is formed by a first pseudo inductance circuit, the first pseudo inductance circuit comprising: a first upper-side transistor that is a P-channel MOS transistor provided between the first power supply voltage line and the second power supply voltage line; a first upper-side capacitive element provided between the gate of the first upper-side transistor and the first reference voltage line; a second upper-side transistor that is an N-channel MOS transistor provided between the first power supply voltage line and the gate of the first upper-side transistor, the gate being connected to the second power supply voltage line; a third upper-side transistor that is an N-channel MOS transistor provided between the source of the second upper-side transistor and the first reference voltage line; a first upper-side resistance element provided between the first power supply voltage line and the gate of the third upper-side transistor; a fourth upper-side transistor that is an N-channel MOS transistor provided between the gate of the third upper-side transistor and the first reference voltage line, the gate being connected to the gate of the third upper-side transistor; and wherein the second impedance element is formed by a second pseudo-inductance circuit, the second pseudo-inductance circuit comprising: a first sub-side transistor that is an N-channel MOS transistor provided between the first reference voltage line and the second reference voltage line; a first sub-side capacitive element provided between the gate of the first sub-side transistor and the first power supply voltage line; a second sub-side transistor that is a P-channel MOS transistor provided between the first reference voltage line and the gate of the first sub-side transistor, the gate being connected to the second reference voltage line; a third sub-side transistor being a P-channel MOS transistor provided between the source of the second sub-side transistor and the first power supply voltage line; a first sub-side resistance element provided between the first reference voltage line and the gate of the third sub-side transistor; a fourth sub-side transistor being a P-channel MOS transistor provided between the gate of the third sub-side transistor and the first power supply voltage line, the gate being connected to the gate of the third sub-side transistor.The semiconductor device according to claim 1, wherein in the first transistor, the source and the back gates are connected to the second power supply voltage line, and the gate and the drain are connected to the gate and the drain of the second transistor; wherein in the second transistor, the source and the back gates are connected to the second reference voltage line.The semiconductor device according to claim 1, wherein the back gates of each P-channel MOS transistor provided in the electronic circuit are connected to the second power supply voltage line, and the back gates of each N-channel MOS transistor provided in the electronic circuit are connected to the second reference voltage line.The semiconductor device according to claim 1, wherein the back gates of some of the plurality of P-channel MOS transistors provided in the electronic circuit are connected to the first power supply voltage line, and the back gates of some of the plurality of N-channel MOS transistors provided in the electronic circuit are connected to the first reference voltage line.The semiconductor device according to claim 1, wherein the back gates of all of the plurality of P-channel MOS transistors provided in the electronic circuit are connected to the first power supply voltage line, and the back gates of all of the plurality of N-channel MOS transistors provided in the electronic circuit are connected to the first reference voltage line.A semiconductor system comprising: the semiconductor device according to claim 1; a crystal oscillator provided between the gates and the drains of each of the first and second transistors; and first and second capacitive elements provided between both ends of the crystal oscillator and a reference voltage terminal; wherein the semiconductor device further comprises a feedback resistor provided in parallel to the crystal oscillator, a buffer that drives and outputs the output signals of the drains of each of the first and second transistors, and an inverter that outputs the inverted signal of the output signal of the buffer as a clock signal supplied to the electronic circuit.The semiconductor system of claim 8, wherein the buffer is a Schmitt buffer.The semiconductor system according to claim 8, applied to a keyless entry system mounted on a vehicle.

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