LOCATING INSTANCES IN A LAYOUT

Abstract

Systems and methods for locating instances in a circuit layout are described. A method for locating instances includes: assigning an initial name and an initial position to a tracking cell in a lower instance of a plurality of instances; determining whether the initial name corresponds to a name of an upper instance of the plurality of instances; determining a position parameter and number information for converting the initial name and the initial position in the lower instance to a name and position of another instance that is larger than the lower instance; and reporting the position of the instance that is larger than the lower instance to a user via a graphical interface (GUI). An integrated circuit is fabricated based on the circuit layout.

Description

Cross-reference to related application

[0001] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 555,435, filed on February 20, 2024, entitled "Locating Instances in GDS Layouts," which is incorporated by reference into this application. background

[0002] In certain integrated circuits, such as memory structures, tracking cells play a role in ensuring proper functioning of a memory array. In some examples, tracking cells are implemented as a means of tracking signal transmission and timing through memory cells to ensure proper operation of a memory array. These tracking cells may be created during a design phase to track signal transmission through a circuit or device and to confirm that the memory array can operate successfully. Because of this importance, design verification may include checking a design for the presence of tracking cells, which may increase the time required to perform design verification. Short description of the drawings

[0003] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Rather, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1 is a schematic diagram showing a layout of an integrated circuit according to an embodiment. Fig. 2 is a conceptual diagram showing a layout hierarchy according to an embodiment. The Fig. 3A, Fig. 3B and Fig. 3C are block diagrams illustrating example systems for implementing integrated circuit design methods described herein, according to one embodiment. The Fig. 4A and Fig. 4B show a flowchart illustrating a method for finding instances in a layout according to an embodiment, and a flowchart illustrating a method for designing and manufacturing a circuit according to an embodiment. Fig. 5 is a conceptual diagram showing a textual representation of circuit data according to an embodiment. The Fig. 6A and Fig. 6B are conceptual diagrams showing example results of a method for finding instances in a circuit diagram, according to an embodiment. Fig. 7 is a conceptual diagram showing a layout hierarchy according to an embodiment. Fig. 8 is a conceptual diagram showing number information represented as a 2D matrix according to one embodiment. Fig. 9 is a conceptual diagram showing number information represented as a 3D network according to one embodiment. Fig. 10 is a flowchart illustrating a method for finding instances in a circuit design according to one embodiment. Fig. 11 is a conceptual diagram showing number information according to an embodiment. Fig. 12 is a schematic diagram illustrating a method for finding instances using number information according to one embodiment. Fig. 13 is a conceptual diagram showing example results of a method for finding instances in a circuit diagram according to an embodiment.

[0004] Corresponding numbers and symbols in the various figures generally indicate corresponding parts unless otherwise noted. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. Detailed description

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present disclosure, reference numbers and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0006] As discussed above, in certain memory circuits, devices, and systems, such as static random access memory (SRAM), tracking cells can be used to track signal transmission and confirm that the design can be successfully operated. In particular, in the design of an SRAM compiler, tracking cells can ensure proper functioning of an SRAM macro generated from an SRAM design by tracking signal transmission and confirming successful operation. Because of this important functionality, a verification process may include checking the positions and quantity of tracking cells in the design.

[0007] However, manually searching the positions and quantity of these tracking cells among hundreds of macros can be a time-consuming and resource-consuming process. Such a manual search process may be difficult to implement and can lead to an undesirable reduction in test coverage. To address this problem, embodiments described herein implement an automated program that can quickly and accurately identify all tracking cells in a given SRAM macro.

[0008] The automated program can utilize numerical information, such as a count of tracking cell instances at each level of a layout hierarchy, to quickly and accurately identify all tracking cells in the macros. By using this numerical information when testing or verifying a layout, it can be demonstrated that all tracking cell instances in the layout are located. Accordingly, embodiments described herein can improve test efficiency by reducing test time, increasing test accuracy, and enabling test coverage of up to 100%.

[0009] According to embodiments described herein, number checking efficiency can be increased by using number information of a layout structure to locate all instances of a particular cell or structure, such as a single tracking cell or a group of tracking cells. Furthermore, using number information of a layout structure can enable the location of all small instances in the layout. The number information can be rendered as a 2D matrix, or it can adopt the format of a 3D network. Furthermore, embodiments described herein can process GDT files instead of GDS files. GDT files can be text versions of GDS files, making them smaller and faster to process. In some embodiments, a special library can be used to extract useful information from GDT files.For example, embodiments may utilize regular expressions of the Perl language to perform this information extraction. This information may be used in the process of identifying instances in an overall layout design. Accordingly, embodiments described herein may provide an efficient and accurate means for searching for specific instances or structures in an integrated circuit design.

[0010] Fig. 1 is a conceptual diagram showing a layout of an integrated circuit according to one embodiment. An integrated circuit may include a stacked structure with a plurality of layers. The stacked structure may include a plurality of levels, each level corresponding to a layer of an integrated circuit with devices, routing, or other circuit or semiconductor components. The plurality of layers of the integrated circuit may include a plurality of memory matrices or macros 101, and these layers may be stacked to form a stacked or 3D structure. In one embodiment, the stacked layers may include memory macros 101. Each memory macro 101 may include a plurality of segments 103, each performing one or more specific functions for the memory structure.

[0011] In one embodiment, memory segments 103 may include memory banks, local input / output (LIO) circuits, global input / output (GIO) circuits, decoder areas, local control (LCTRL) areas, and global control (GCTRL) areas. However, embodiments described herein are not limited thereto, and memory segments 103 may include any type of circuit or functional unit specified by a circuit designer. The structure and design of memory segments 103 may be specified according to basic building blocks, called cells, that a circuit designer may use when designing an integrated circuit.

[0012] As explained later with reference to the Fig. As further explained in Figures 3A through 3C, a circuit designer can use circuit design tools, such as computer-aided design (CAD) tools or other electronic design automation (EDA) solutions, to quickly realize precise designs. Cells used by designers may have a fixed, standard architecture chosen to perform specific logic or memory functions (e.g., AND gates, OR gates, XOR gates, NOT gates, NAND gates, NOR gates, XNOR gates, flip-flops, inverters, latches). In some cases, cell structures can be standardized, and the design of these standardized cells can be stored in and retrieved from a library, allowing designers to create complex and densely packed integrated circuits in less time and with reduced effort.

[0013] For example, memory segments 103 may comprise one or more cells, providing a more uniform and predictable structure for each segment. In one embodiment, each macro 101 may similarly comprise a standard layout of memory segments 103, such that the stack of macros is a stack of substantially uniform layouts. However, designs and layouts described herein are not so limited, and in other embodiments, the layouts of macros 101 may vary at different levels.

[0014] Before moving from a design phase to a tape-out, circuit designs can undergo a verification process to ensure that the proposed design adheres to all desired specifications and design rules. As part of this verification, a test process can be performed to check the design for specific instances. For example, in Fig. 1, each memory macro 101 may have a similar instance, represented by reference numeral 111. At a first layer, a first macro may have a first instance 111A. At a second layer directly above the first layer, a second macro may have a second instance 111B. This structure may repeat for all layers, including a second-to-last level, which may have a macro with a third instance 111C, and an upper level, which may have a macro with a fourth instance 111D. Although not shown, multiple segments 103 within the same macro 101 may have similar instances.

[0015] Instances 111 may designate specific parts of the layout that are populated with a particular structural element. In general, a particular instance may be a small instance, such as a specific cell or group of cells, or another basic component of the layout, or a large instance, such as a memory segment or macro. In one embodiment, instances 111 may be small instances created in a memory segment 103.

[0016] During a test process described above, it may be desirable to check a layout to obtain a position and number of a specific instance. The plurality of macros 101 may, for example, comprise SRAM macros. Each SRAM macro may have one or more tracking cells to track signal transmission and to confirm that the design can be successfully operated. Due to the function of these memory cells in a generated SRAM, it may be desirable to check the layout for all instances of tracking cells to ensure that there are a sufficient number of them and that they are in the correct positions.Therefore, instances 111A, 111B, 111C, and 111D may be instances having one or more tracking cells in the layout, and the process of designing and manufacturing an integrated circuit based on that layout may include testing the layout for those instances.

[0017] The SRAM macros 101 may contain thousands of cells, including multiple tracking cells, and these tracking cells may be distributed throughout an SRAM layout, in different layers and at different positions. Therefore, manually locating these tracking cells may be difficult, and determining their positions in the layout may require time-consuming manual steps. Systems and methods according to embodiments described herein may provide an automatic implementation of this process so that a single program can locate all tracking cell instances to be located. This may improve the efficiency and accuracy of the search process.

[0018] For example, a layout described above with reference to Fig. 1, it may be desirable to check the layout for all instances 111 of a tracking cell. In some systems, this may involve manually checking a layout using a manual search function or by moving a cursor through the layout to locate instances. Embodiments described herein may automate this process so that the entire layout can be quickly and accurately checked, and all instances of a tracking cell can be quickly and accurately located and accounted for.

[0019] Fig. 2 is a schematic diagram showing a layout hierarchy according to one embodiment. The layout hierarchy may represent a way to conceptually break down a complete integrated circuit design into components to simplify design and analysis. The hierarchy contains a single macro. Below this, a fifth level 205 may represent a specific group of segments. This structure continues such that a first level 201 may represent a smallest building block of the circuit design, for example, a single cell or a single functional unit consisting of a small number of cells. Some levels may be divided into multiple sub-levels. As in Fig. 2, for example, a fourth plane 204 may be divided into a first sub-plane 204A and a second sub-plane 204B.

[0020] In one embodiment, there may be one or more instances that have one or more tracking cells in each level. The cell name of the tracking cell(s) may be similar in each level. The cell name may refer to a string of alphanumeric (or other) characters used by a design tool for a particular cell. These names may be displayed to a user of the tool via a graphical interface so that they can identify a particular cell. For example, a cell in the lower level 201 may be labeled "S6ALVTWBZSHOCFUJA100U10_N2_8T2P_337_01_vod5p1_4x1_trk_onoff." In the second level 202, the cell name may be similar, but still different. For example, the second tracking cell level 202 may be "S6ALVTWBZSHOCFUJA10010_ARRAY_BL_TRK_2ON2OFF." While these names are not identical, they contain similar character strings, in particular sharing several characters at the beginning of the name. Embodiments described herein may utilize this similarity to identify all instances based on the name of a first instance.

[0021] In some embodiments, this naming rule may apply to all instances in the layout. However, in some cases, an upper or higher-level instance may not have a corresponding name. As in Fig. 2, for example, levels 1 through 6 each contain tracking cells with similar names. In particular, the tracking cells in each level may begin with the same character string. However, in the upper level 207, the tracking cell does not have this naming rule. To account for this, in some embodiments, cell names may be renamed to enable more efficient searching. The cell names may be renamed from one level to the next according to information from a gdt file. Using this process, a position of a higher-level instance may be inferred from a lower-level instance. These processes, as well as systems that represent and embody them, are described in more detail below.

[0022] For example, this process may involve assigning a starting name and starting position to a tracking cell in a lower instance of a plurality of instances in a layout. Then, for higher-level instances, it may be determined whether the starting name corresponds to a name of a higher instance of the plurality of instances. If so, the starting position may be reported as an instance. If not, a process may be performed to convert the starting name and starting position of the lower instance to those of another instance that is greater than the lower instance.

[0023] In one embodiment, this process may include determining a position parameter and number information used to implement the conversion. The position parameter may, for example, include a tilt operation, a rotate operation, and / or a translate operation. The number information may, for example, include a set of tracking cells at each level of the layout hierarchy. The position parameter and number information may be used to infer the position and name from higher-level instances. The inferred name may then be compared to the name of a top instance of the plurality of instances to determine if they match. If not, the loop may continue to identify all instances in the layout. The loop may end when the inferred name matches the name of the top instance.

[0024] The Fig. 3A, Fig. 3B and Fig. 3C are block diagrams illustrating example systems for implementing integrated circuit design methods described herein. These systems may represent circuit design tools capable of implementing the processes and functions described herein.

[0025] For example, Fig. 3A illustrates an exemplary system 300 having a single-computer architecture in which a processing system 302 (e.g., one or more computer processors that may be located in a given computer or in multiple computers that may be separate and distinct from each other) includes a computer-implemented electronic circuit design engine 304 running on the processing system 302. The processing system 302 has access to a machine-readable memory 307 and one or more data stores 308. The one or more data stores 308 may include a cell library database 310 and a circuit design database 312. The processing system 302 may be a distributed parallel computing environment that can be used to manipulate very large data sets.Cell library database 310 and circuit design database 312 may enable automatic testing of instances according to embodiments described herein. For example, cell library database 310 may contain designs or architectures for a tracking cell. Circuit design database 312 may store various programs or functions for implementing circuit design operations.

[0026] Fig. 3B shows a system 320 having a client-server architecture. One or more user PCs 322 access one or more servers 324 running an electronic circuit design engine 337 on a processing system 327 via one or more networks 328. The one or more servers 324 may access a machine-readable memory 330 and one or more data stores 332. The one or more data stores 332 may include a cell library database 334 and a circuit design database 338.

[0027] Fig. 3C shows a block diagram of exemplary hardware for a single-computer architecture 350, such as that shown in Fig. 3A that may be used to integrate and / or implement program instructions of system embodiments of the present disclosure. A bus 352 may serve as a data highway interconnecting the other illustrated hardware components. A processing system 354, labeled "CPU" (main processor) (e.g., one or more computer processors in a given computer or multiple computers), may perform calculations and logical operations to execute a program. A non-transitory processor-readable storage medium, such as read-only memory (ROM) 358 and random access memory (RAM) 359, may be in communication with the processing system 354 and may contain one or more programming instructions for performing the method of designing an integrated circuit.Optionally, programming instructions may be stored on a non-volatile machine-readable storage medium, such as a magnetic disk, an optical disk, a writable storage device, flash memory, or other physical storage medium.

[0028] In the Fig. 3A, Fig. 3B and Fig. 3C, the machine-readable memories 307, 330, 358, 359 or the data stores 308, 332, 383, 384, 388 may include one or more data structures for storing and associating various data used in example systems for designing an integrated circuit. For example, a data structure stored in any of the aforementioned locations may be used to store data from XML files, initial parameters, and / or data for other variables described herein. A disk storage controller 390 connects one or more optional disk drives to the system bus 352. These disk drives may be external or internal floppy disk drives, such as drives 383; external or internal CD-ROM, CD-R, CD-RW, or DVD drives, such as drives 384; or external or internal hard disk drives 385. The system bus 352 can be connected to cloud-based virtual drives in addition to physical drives.As stated above, these various disk drives and disk storage controllers are optional devices. In one embodiment, methods described herein may be stored as instructions in a non-transitory machine-readable medium. When the instructions are executed, one or more processors may implement the methods described herein.

[0029] Element managers, a real-time data buffer, transmitters, a file input processor, an access memory loader with a shared database index, a reference data buffer, and data managers may each comprise a software application stored in one or more of the disk drives connected to disk controller 390, ROM 358, and / or RAM 359. Processor 354 may access one or more components as needed. A monitor interface 387 allows information from bus 352 to be displayed on a monitor 380 in an audio, graphic, or alphanumeric format. Communication with external devices may optionally occur via various communication inputs 382.In addition to these computer components, the hardware may also include data input devices, such as a keyboard 379, or another input device 381, such as a microphone, a remote control, a pointer, a mouse, and / or a joystick.

[0030] Monitor interface 387 and interface 388 may include portions of a graphical user interface (GUI) that allows a user to interact with the systems via visual indicators displayed on monitor 380. This allows a user, such as a circuit design engineer, to interact with the system during the design of a circuit. Certain information pertaining to a design, such as the names and positions of specific cells or cell instances, may be presented to the user via this GUI.

[0031] Furthermore, the methods and systems described herein may be implemented on many different types of processing devices by means of program code containing program instructions executable by a subsystem of the processing device. The software program instructions may include source code, object code, machine code, or other stored data operable to cause a processing system to perform the methods and operations described herein, and may be provided in a suitable language, such as C, C++, or JAVA, or in another suitable programming language. However, other implementations may also be used, such as firmware or even appropriately designed hardware configured to implement the methods and systems described herein.

[0032] Data of the methods and systems (e.g., associations, mappings, data input, data output, intermediate data results, final data results, etc.) may be stored and implemented in one or more different types of computer-implemented data storage, such as various types of storage devices and programming constructs, e.g., RAM, ROM, flash memory, flat files, databases, programming data structures, programming variables, IF-THEN (or similar) statement constructs, etc. It should be noted that data structures refer to formats for use in organizing and storing data in databases, programs, memories, or other machine-readable media for use by a computer program.

[0033] The computer components, software modules, functions, data stores, and data structures described herein may be interconnected directly or indirectly to enable the data flow required for their operations. It should also be noted that a module or processor includes, among other things, a unit of code that performs a software operation and may be implemented, for example, as a subroutine unit of code, a software function unit of code, an object (as in an object-oriented paradigm), an applet, a computer scripting language, or some other type of computer code. The software components and / or functionality may be located on a single computer or may be distributed across multiple computers, depending on the specific situation.

[0034] An exemplary method for finding instances in a circuit design is described below with reference to the Fig. 4A, Fig. 4B and Fig. 5 described. Fig. 4A is a flowchart illustrating a method for finding instances in a layout according to one embodiment. Fig. Figure 4B is a flowchart illustrating a method for designing and manufacturing a circuit. Fig. Figure 5 is a conceptual diagram showing a text representation of circuit data according to one embodiment. Methods described herein may enable testing of a circuit design for desired instances. Therefore, these methods may utilize data from a text representation of a circuit design, such as a gdt file stored in Fig. 5 to locate and identify instances.

[0035] In one embodiment, the circuit design may include a plurality of instances of interest. Fig. For example, Figure 5 shows a GDT file that represents at least two instances. The GDT file may contain a first, "lower instance" 521 located at a lower level of a layout hierarchy, and a second, "upper instance" 525 located at an upper level of the layout hierarchy. In one embodiment, the lower instance 521 may be located at a lowest, Level 1 layer, and it may be a lower instance. The upper instance 525 may be located at a Level 2 layer. Although in Fig. 5 is not shown, but the layout hierarchy can have any number of levels. For example, the layout can have 7 levels, similar to the one in Fig. 2. As explained later, methods described here can be iterated over multiple levels to identify all instances of interest at each level.

[0036] The lower instance 521 and the upper instance 525 may each contain one or more tracking cells. Accordingly, by identifying the presence and locations of all instances similar to the lower instance 521, embodiments described herein may identify all tracking cells of the circuit design.

[0037] In one embodiment, the method may include associating an initial name and an initial position with a lower instance of a plurality of instances in an operation 401. The initial name may include a group of alphanumeric characters associated with a particular component of the lower instance. For example, the plurality of instances may include instances with one or more tracking cells, and the lower instance of the plurality of instances may include a lower instance of a tracking cell named “S6ALVTWBZSHOCFUJA100U10_N2_8T2P_337_01_vod5p1_4x1_trk_onoff” as in Fig. 5 is shown.

[0038] The gdt file representing the circuit design may also contain data specifying a position of that instance. Fig. For example, Figure 5 shows position data 527 being translated into coordinates of a position of the lower instance 521. Using the cell name and cell position, the method can also locate all other instances of the layout. In particular, the method can utilize information from a lower-level instance to obtain information about an instance at the next level. For example, information about an instance at level 1 can be used to infer the positions of level 2 instances. The method can be repeated in this way across all levels of a layout until an upper level is reached, at which point the positions of all instances can be reported.

[0039] This process is illustrated as an operation 403, where the method may include determining whether the initial name of a top instance of the plurality of instances corresponds. As described above with reference to Fig. 2, instances in different levels may have similar names, but upper-level instances may not have this commonality. Instances in an upper level may instead have a name that identifies that instance as an instance located in the upper level. Accordingly, in operation 403, the method may include analyzing the initial name to determine if it is an upper-level name. If the name is determined to be an upper-level name, the method may continue to operation 405, in which the method includes reporting locations of the instances. The reporting may be implemented using a graphical user interface (GUI) such that a user interacting with a system may view reported positions using a monitor, such as the one shown in Fig. 3C. However, if it is determined that the analyzed name does not correspond to a higher instance of the plurality of instances, the method may continue through the iterative process described above.

[0040] In one embodiment, the method may include, in an operation 407, finding a next-level instance and determining a position parameter for converting the initial position into a position of the next-level instance. In Fig. 5, in this case, the upper instance 525 may represent the next-level instance. In the method, this upper instance may be located using information from the lower instance 521. For example, the GDT file may further contain a position parameter 523. This position parameter may include one or more geometric operations, such as translations, tilts, rotations, translations, or the like.

[0041] As in Fig. 5, the position parameter can be denoted, for example, by "Fx a90 xy(o 0)", which can correspond to a sequence of three operations. Fx can indicate that the position is tilted around the x-axis, and a90 can indicate a 90° counterclockwise rotation. In general, xy(ab) can indicate a translation by increasing the x and y values ​​by a and b, respectively. Fig. However, in the embodiment shown in Figure 5, the values ​​a and b are set to zero, indicating that the position parameter 523 does not include any displacement.

[0042] In methods described herein, Pearl regular expressions may be used to extract data, such as the cell name, position information 527, and position parameter 523, from a GDT file representing a circuit design to infer the position of a top-level instance from a bottom-level instance. For example, in operation 409, the method may include determining the new position of the next-level instance and determining a new name of the next-level instance.

[0043] In one embodiment, this new position may be calculated from the initial position provided by the position information 527 and the position parameter 523. The lower instance may, for example, comprise a tracking cell of an SRAM represented by a design tool for a lower level of a layout hierarchy. When considering the next higher level in the hierarchy, the position of this instance may change due to the extent of this level compared to that of the lower level. However, this change may be predictable, and embodiments described herein may infer the next-level position from the initial position or a position parameter. The method may include subsequently identifying the cell located at the next-level position and determining the name of that cell.

[0044] The method may then return to operation 403, where it may be determined whether this name corresponds to a top-level instance. This loop may be repeated for as many loops as there are in a layout hierarchy. For example, for a seven-level layout hierarchy, as shown in Fig. 2, the loop may be repeated seven times. This loop may end when the upper-level instance has been identified by name. The results that may be returned according to one embodiment will be described later with reference to the Fig. 6A and Fig. 6B.

[0045] After determining in operation 403 that the initial name corresponds to a top-level instance and reporting the positions in operation 405, it may be determined in operation 411 whether the positions adhere to specified criteria or design rules. For example, methods described herein may be used to determine whether there is sufficient placement, spacing, number, density, or other characteristic of a particular instance. In one embodiment, the instance may include one or more tracking cells, and reporting the positions in operation 405 may provide information regarding the placement, number, density, or other characteristics of the tracking cells in the layout. This information may be used to determine whether the design or layout adheres to certain specified criteria or design rules.For example, the design may require a specific number or density of tracking cells, or it may require the tracking cells to be in a specific position or to have a specific spacing.

[0046] The reported positions can be compared with these target values ​​to determine whether the design complies with the rules and thus passes verification. In some embodiments, this process can be automated, and the method can include informing a user via a GUI whether the positions are sufficient or not. In other embodiments, the positions can be reported to the user via the GUI, and the user can determine whether the positions are sufficient or not.

[0047] In one embodiment, if the positions are deemed sufficient, the method may proceed to a tape-out in an operation 415. In this process, the method may enable the fabrication of an integrated circuit based on the layout. The tape-out process may include further design processes, such as final stimulation, verification, and design rule checks, before finally fabricating a circuit based on the layout. As set forth above, the method may include determining the sufficiency of the reported positions. In an embodiment where it is determined that the reported positions are sufficient, the method may then convert the layout into a form or format that can be used to fabricate an integrated circuit based on the layout.

[0048] In one embodiment, if the positions are deemed insufficient, the method may proceed to operation 413 and activate a design correction of the circuit or layout. For example, the method may notify a user via a GUI that the positions of the tracked instances do not comply with certain specified criteria or design rules, and the user may initiate a design correction to address this issue. Accordingly, this process may ensure that the tracked instances or their components, such as a plurality of tracking cells, comply with all specified criteria or design rules before proceeding with the tape-out. This process is described below with reference to Fig. 4B is described in more detail.

[0049] Fig. 4B shows a flow diagram illustrating a method for designing and manufacturing a circuit. The method may begin with an operation 471 by receiving a circuit design. This circuit design may be input by a user or may have predefined layouts that a user can edit or modify to fit a particular desired function. In an operation 475, the method continues with editing the circuit design. This editing may include multiple steps to transform an input design from a conceptual level into a verifiable design. The process in operation 475 may include, for example, steps such as floor planning, placement, clock tree synthesis, routing, and generating a layout. In addition, the editing in operation 475 may include one or more simulations or verification processes to optimize the design.In addition, one or more change orders (ECOs) can be implemented during processing in operation 475.

[0050] The method may then proceed to verification in an operation 477. In this process, the method may include performing a verification of a layout generated during processing of the circuit design. Performing the verification may, for example, include finding instances in a layout, as described with reference to Fig. 4. Accordingly, the reporting of positions in operation 405 can be Fig. 4A, for example, may be part of a verification process for determining the feasibility of a circuit design before proceeding with tape-out. In one embodiment, the instances include one or more tracking cells, and embodiments described herein may be used to determine whether there is a sufficient number, placement, spacing, density, or other property of tracking cells in a circuit design or layout. The method may further include, in an operation 479, proceeding with tape-out. The tape-out process may be similar to that described above with reference to Fig. 4A has been described.

[0051] The Fig. 6A and Fig. 6B are conceptual diagrams showing example results of a method for finding instances in a circuit diagram, according to an embodiment. Fig. 6A shows a first exemplary window 601 of a GUI displaying exemplary results, and Fig. Figure 6B shows a second exemplary window 611 of the GUI displaying exemplary results. 601 and 611 are illustrations of windows displaying exemplary results of the Fig. 4 and Fig. 5, provided to a user of a circuit design tool via a GUI. In some embodiments, the methods described herein may include a computer-implemented function or a computer-implemented program executed on a circuit design tool. The results of this method may be output to a user of the circuit design tool to inform the user of the identified instances and their locations.

[0052] In one embodiment, the results may be output to the user in text form, as shown in window 601. This window may show instances identified at all levels of a layout hierarchy and may provide their positions. Box 609 shows that, with an exemplary method described above, an instance at a higher level, level 7, of a layout hierarchy may be identified based on lower-level information.

[0053] Although only one instance may be found in a higher level, in some embodiments each instance may occur multiple times or contain multiple tracking cells. Fig. 6B, for example, window 611 shows a layout representation of the circuit design corresponding to the Fig. 6A. While there may be only one instance identified in level 7, this instance may contain four tracking cells 617, as shown in Fig. 6B is shown.

[0054] The number of tracking cells, or otherwise targeted small instances, in an identified instance may represent number information used to provide further details when searching for and locating instances in a circuit design. The use of number information to indicate all possible occurrences of a particular small instance is described below with reference to the Fig. 7 to 9 are described in more detail.

[0055] Fig. Figure 7 is a conceptual diagram showing a layout hierarchy according to one embodiment. The layout hierarchy of Fig. 7 may be similar to the layout hierarchy described above with reference to Fig. 2, and it may have seven levels. The layout hierarchy may, for example, include a lower level 701, a second level 702, a third level 703, a fourth level 704, a fifth level 705, a sixth level 706, and a seventh, upper level 707. Using methods described herein, instances in upper levels may be inferred from information about the lower instance in the first level 701.

[0056] Fig. 7 differs from Fig. 2 in that numerical information is also provided for each upper level. The framed number in each level can, for example, represent numerical information for that level, that is, the number of cells in each identified instance. In particular, Fig. 7 shows two numbers for each upper level, where the unboxed number may represent the number of instances identified at that level, while the boxed number may represent the number of cells in each instance. In one embodiment, the method may involve identifying all tracking cells of a circuit design, and the boxed numbers may represent the number of tracking cells in each instance for each level.

[0057] More specifically, the lower level 701 may include a representation of the smallest building blocks for a circuit design. In one embodiment, the lower level 701 may represent individual cells, and it may identify a single tracking cell. Using information provided in a gdt file for the circuit design, instances of the tracking cell may be identified in higher levels. In the second level 702, there may be only one instance identified, and this instance may contain a single tracking cell. Similarly, in the third level 703, there may be only one identified instance containing a single tracking cell.

[0058] However, in the fourth level 704, which may represent the circuit design at a segment level and may be divided into two segments, there may be instances identified in each segment, and each segment may contain two tracking cells.

[0059] In the fifth level 705, which may represent the circuit design at a higher level than the segment level, there may be only one identified instance. However, this instance may contain four tracking cells. This number represents two tracking cells from a first segment of the fourth level and two tracking cells from the second segment of the fourth level. Similarly, the sixth level 706 and the upper level 707 may each have only one instance, but these instances each contain four tracking cells. This number information may be represented mathematically so that, in methods described herein, the number information can be incorporated into instance locating methods to locate all target instances or other small instances in a layout.

[0060] Fig. Figure 8 is a conceptual diagram according to one embodiment showing number information represented as a 2D matrix. The number information of a layout hierarchy may be represented as a 2D matrix, where the matrix has a size of K n-1 x K n has, where K n denotes a number of instances at an n-th level and K n-1 denotes a number of instances on an (n-1)-th level. In Fig. For example, Figure 8 shows an example layout hierarchy 841 in which there are four instances in the nth level (u1, u2, u3, and u4) and eight instances in the (n-1)th level (d1, d2, d3, d4, d5, d6, d7, and d8). Accordingly, the number information of the nth layer can be represented as a 4x8 matrix. Also shown is an example matrix 843 in which levels u1 through u4 are each represented as a 1x8 matrix and combined into a 4x8 matrix representing the nth level. The number information represented as a 2D matrix can enable the program to find and locate all instances in a layout by ensuring that the number of instances in each level is accurately represented and accounted for during an instance discovery process.However, as will be explained later, embodiments are not so limited, and the number information may instead be represented as a 3D network.

[0061] Fig. 9 is a conceptual diagram according to one embodiment showing number information represented as a 3D network. Similar to the embodiment described above for a 2D matrix, the representation of the number information as a 3D network may depend on the number of instances at each level. For example, number information of a layout hierarchy 941 may be represented as a 3D network 943. At each level of the layout hierarchy, the structure of the 3D network may depend on the number of instances at that level. At a level between an upper and a lower level, the representation of the 3D network may depend on the number of instances at that level and a number of instances at the previous level.

[0062] Accordingly, if the layout 941 has four instances in the n-th level and eight instances in the (n-1)-th level, the 3D network 943 can consider this as a level with four (K n ) row components and eight column components (K n-1 ). By mapping the number information as a 3D network, methods described here can ensure that all instances in each layer are accurately represented and accounted for during an instance discovery process. Embodiments that utilize number information are described below with reference to the Fig. 10 to 12 are described in more detail.

[0063] Fig. 10 is a flowchart illustrating a method for finding instances in a layout according to one embodiment. Fig. 11 is a conceptual diagram showing number information according to an embodiment. Fig. 12 is a schematic diagram illustrating a method for finding instances using number information according to one embodiment.

[0064] In one embodiment, a method for finding instances in a layout may include assigning a starting name and a starting position to a lower instance of a plurality of instances in an operation 1001. As described above with reference to Fig. 4, the name and position may be assigned and provided in a text file, such as a GDT file. For example, the method may provide a means for locating tracking cells of a layout, and the initial name may be the name of the tracking cell in a lower-level instance. Embodiments described herein may extract the name and position information from this GDT file to locate other instances in the layout. In one embodiment, the method may use Pearl expressions to extract this information.

[0065] The layout can be represented, for example, by a layout hierarchy 1141, which is Fig. 11. The layout hierarchy 1141 may contain number information, indicated by boxed numbers of the layout, which may be used to identify and locate all instances in the layout. This number information may be represented by a 3D network 1143. Fig. Figure 12 is a schematic representation of the development of this 3D network during the process of Fig. 10.

[0066] In operation 1001, an initial name and initial position can be assigned to a lower-level instance. This can be assigned to the lower-level instance of Fig. 11 and can be represented as a single block 1201 in Fig. 12. As shown in Fig. 12, the initial position can be determined by four coordinates (x min , x max , y min , y max) can be defined, which can correspond to a representation of a circuit design with a circuit design tool and can be presented to a user via a GUI.

[0067] The method may further include, in an operation 1003, determining whether the initial name of a top instance of the plurality of instances corresponds. As described above with reference to Fig. 2, while instances in different levels may have similar names, upper-level instances may not have this commonality. An instance in an upper level may instead have a name that identifies that instance as an instance located in the upper level. Accordingly, in operation 1003, the method may include analyzing the initial name to determine if it is an upper-level name. If the name is determined to be an upper-level name, the method may continue to operation 1005, in which the method includes reporting locations of the instances.

[0068] If, on the other hand, it is determined that the parsed name does not correspond to an upper instance of the plurality of instances, the method may proceed to an operation 1007, which may include determining a position parameter and number information for converting the initial name and position in the lower instance into a name and position of another instance that is greater than the lower instance.

[0069] As mentioned above with reference to the Fig. 4 and Fig. As explained in Figure 5, a position parameter may include a geometric operation, such as a tilt, a translation, a rotation, or the like, that may specify the positions of similar instances in the layout. The position parameter may be extracted or inferred from a GDT file. The number information may also be extracted from the GDT file. However, embodiments described herein are not limited thereto, and the number information may also be determined by other means.

[0070] The method may then proceed to an operation 1009 and may include determining a new position of the instance that is larger than the lower instance and determining a new name of the instance that is larger than the lower instance.

[0071] Let us return to Fig. 11, where the second level can contain two instances, and each instance can contain a tracking cell. Accordingly, to obtain the positions of these instances, the method can use the initial position and a position parameter. This can be indicated by an arrow 1203 in Fig. 12. In addition, the method can determine that there are multiple instances in the second level based on number information. Accordingly, the second-level instances can be represented by the 3D network shown in Fig. 12 is designated 1205. In some embodiments, other position parameters may be identified and used to locate multiple upper-level instances from a single lower-level instance. For example, another position parameter may be used to locate p 1,1 of 1205 based on p oof 1201 as the position parameter used to find p 1,2 of 1205.

[0072] In an operation 1009, the method may also determine one or more names for the instance(s) that are greater than the lower instance. After this name has been determined, the method may return to operation 1003, and it may be determined whether this name corresponds to an upper instance of the plurality of instances. As stated above, this process may be repeated through each level of a layout hierarchy until an upper level is reached. For example, the layout of Fig. 11 may be repeated four times by the process, and in doing so, the method may detect that the name of the fifth-level instance corresponds to that of an upper-level instance, and the method may proceed to an operation 1005 for reporting positions.

[0073] After determining in operation 1003 that the initial name corresponds to a top-level instance and reporting the positions in operation 1005, it may be determined in operation 1011 whether the positions adhere to certain specified criteria or design rules. For example, methods described herein may determine whether there is sufficient placement, spacing, number, density, or other characteristic of a particular instance. In one embodiment, the instance may include one or more tracking cells, and reporting the positions in operation 1005 may provide information regarding the placement, number, density, or other characteristics of the tracking cells in the layout. This information may be used to determine whether the design or layout adheres to certain specified criteria or design rules.For example, the design may require a specific number or density of tracking cells, or it may require the tracking cells to be in a specific position or to have a specific spacing.

[0074] The reported positions can be compared with these target values ​​to determine whether the design complies with the rules and thus passes verification. In some embodiments, this process can be automated, and the method can include informing a user via a GUI whether the positions are sufficient or not. In other embodiments, the positions can be reported to the user via the GUI, and the user can determine whether the positions are sufficient or not.

[0075] In one embodiment, if the positions are deemed sufficient, the method may proceed to a tape-out in an operation 1015. In this process, the method may enable the fabrication of an integrated circuit based on the layout. The tape-out process may include further design processes, such as final stimulation, verification, and design rule checks, before finally fabricating a circuit based on the layout. As set forth above, the method may include determining the sufficiency of the reported positions. In an embodiment where it is determined that the reported positions are sufficient, the method may then convert the layout into a form or format that can be used to fabricate an integrated circuit based on the layout.

[0076] In one embodiment, if the positions are deemed insufficient, the method may proceed to operation 1013 and activate a design correction of the circuit or layout. For example, the method may notify a user via a GUI that the positions of the tracked instances do not comply with certain specified criteria or design rules, and the user may initiate a design correction to address this issue. Accordingly, this process may ensure that the tracked instances or their components, such as a plurality of tracking cells, comply with all specified criteria or design rules before proceeding with the tape-out. This process may be similar to the process described above with reference to Fig. 4B has been described.

[0077] As stated above, in some embodiments, processes may be repeated by layering a layout until an upper instance is reached. These iterations are described below with reference to Fig. 12. As explained above, a first loop may result in a second-level representation of number information 1205. In a next loop, the process may use a different position parameter to convert the second-level representation to a third-level representation 1209. Then, in an operation 1211, number information indicating that each instance in the third level contains three tracking cells (as indicated by the three blocks in oval 1215) may be used to generate another third-level representation 1213. In another loop, the process may use a different position parameter to convert representation 1213 to a fourth-level representation 1219.Then, in an operation 1221, numeric information indicating that each instance in the fourth level can contain six tracking cells (as indicated by the six blocks in the oval 1225) may be used to generate another, fourth-level representation 1223. Looping yet further, in an operation 1227, the process may use another position parameter to convert the fourth-level representation 1223 into a fifth and upper-level representation 1229. This last-level representation shows that there are twelve tracking cells in the upper-level instance. In one embodiment, the positions of these tracking cells may be a final output of the process.

[0078] Fig.13 is a conceptual diagram showing example results of a method for finding instances in a circuit diagram according to one embodiment. As stated above, the first input of embodiments described herein may include an initial position of a lower instance, as shown at 1301. The final output may be a report of positions of tracking cells in an upper instance, as shown at 1302. This report may be generated with systems and methods described herein and may be output to a user via a GUI, as shown at 1302. In particular, embodiments described herein may provide an automated process for determining the positions of all instances of a tracking cell in a layout.

[0079] Systems and methods are described here. An example method for locating instances in a layout includes: assigning an initial name and an initial position to a tracking cell in a lower instance of a plurality of instances; determining whether the initial name corresponds to a name of an upper instance of the plurality of instances; determining position parameter and number information for converting the initial name and the initial position in the lower instance to a name and position of another instance that is greater than the lower instance; and reporting the position of the other instance that is greater than the lower instance to a user via a graphical user interface (GUI), wherein an integrated circuit is fabricated based on the layout.

[0080] Another example method may be stored as instructions on a non-transitory machine-readable medium. When executed by a processor, the instructions may cause the processor to perform the following operations: assigning an initial name and an initial position to a lower instance of a plurality of instances; determining whether the initial name corresponds to a name of an upper instance of the plurality of instances; locating a next-level instance and determining a position parameter to convert the initial position to a position of the next-level instance; and determining the position of the next-level instance and determining a name of the next-level instance. The instructions may further cause the processor to determine whether the name of the next-level instance corresponds to the upper instance of the plurality of instances and to report the position of the next-level instance to a user via a GUI.

[0081] A system is provided for locating tracking cells in a layout of a memory circuit design. The system comprises one or more processors; and a non-transitory machine-readable medium storing instructions that, when executed by a processor, cause the one or more processors to perform operations. The operations include: assigning an initial name and position of a tracking cell in a lower instance of a plurality of instances; determining whether the initial name corresponds to a name of an upper instance of the plurality of instances; and determining position parameter and number information for converting the initial name and position in the lower instance to a name and position of another instance that is greater than the lower instance. The system enables fabrication of a circuit based on the layout.

[0082] Features of various embodiments have been described above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other methods and structures for achieving the same objectives and / or obtaining the same benefits as the embodiments presented herein. Those skilled in the art will also appreciate that such equivalent interpretations do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 555,435

[0001]

Claims

[1] Processor-implemented method for finding instances in a circuit layout, comprising: Assigning an initial name and an initial position to a tracking cell in a lower instance of a plurality of instances; Determine whether the initial name corresponds to a name of a superior instance of the plurality of instances; Determining a position parameter and number information for converting the initial name and position in the lower instance into a name and position of another instance that is greater than the lower instance; and Reporting the position of the instance that is larger than the lower instance to a user via a graphical user interface (GUI), whereby an integrated circuit is manufactured based on the circuit layout. [2] The method according to claim 1, wherein the position parameter includes a tilt operation, a rotation operation and a translation operation, the conversion involves using the position parameter for the initial position, the number information is represented as a 2D matrix or a 3D network, and the number information is used to detect the presence of more than one instance that is greater than the lower instance. [3] The method of claim 1 or 2, wherein the number information comprises a number of tracking cells of each instance of the plurality of instances. [4] The method of claim 3, wherein the number information is represented as a 3D network. [5] Method according to one of the preceding claims, wherein the circuit has one or more memory macros, and the tracking cell is arranged in a memory segment of a first macro of the one or more memory macros. [6] The method of any preceding claim, further comprising determining a new position of the instance that is greater than the lower instance and a name of the instance that is greater than the lower instance. [7] The method of claim 6, further comprising determining whether the name of the instance that is greater than the lower instance corresponds to the upper instance of the plurality of instances. [8] The method of claim 7, further comprising: Determine whether the reported positions are sufficient; and Activating a circuit layer design correction. [9] Method according to one of the preceding claims, wherein the layout comprises one or more memory macros. [10] A method according to any one of the preceding claims, wherein the instance that is larger than the lower instance contains a plurality of tracking cells. [11] A non-transitory machine-readable medium containing instructions which, when executed by a processor, cause the processor to perform the following operations: Assigning an initial name and an initial position to a lower instance of a plurality of instances; Determine whether the initial name corresponds to a name of a superior instance of the plurality of instances; Finding a next-level instance and determining a position parameter to convert the initial position into a position of the next-level instance; Determining the position of the next-level instance and determining a name of the next-level instance, Determine whether the name of the next-level instance matches the name of the upper instance of the plurality of instances; and Reporting the position of the next-level instance to a user via a graphical interface (GUI). [12] The non-transitory machine-readable medium of claim 11, wherein the operations further comprise: Determine whether the position complies with one or more design rules. [13] The non-transitory machine-readable medium of claim 11 or 12, wherein the one or more design rules comprise a number or a density of the next-level instance. [14] The non-transitory machine-readable medium of any of claims 11 to 13, wherein the operations further comprise: Enabling a position-based design correction of an integrated circuit. [15] The non-transitory machine-readable medium of any of claims 11 to 14, wherein the plurality of instances each comprise one or more tracking cells. [16] A non-transitory machine-readable medium according to any one of claims 11 to 15, wherein the initial name and initial position are extracted from a text file. [17] A system for locating tracking cells in a layout of a memory circuit design, the system comprising: one or more processors; and a non-transitory machine-readable medium having stored thereon instructions that, when executed by a processor, cause the one or more processors to perform operations that include: Assigning an initial name and an initial position of a tracking cell in a lower instance of a plurality of instances, Determine whether the initial name corresponds to a name of a higher instance of the plurality of instances, Determining a position parameter and number information for converting the initial name and position in the lower instance into a name and position of another instance that is greater than the lower instance, Determining a new position of the instance that is larger than the lower instance and a name of the instance that is larger than the lower instance, Determine whether the name of the instance that is greater than the lower instance matches the name of the upper instance of the plurality of instances, and Enabling the manufacture of an integrated circuit based on the layout. [18] The system of claim 17, wherein the operations further comprise: Determine positions of all tracking cells in an upper level of a layout hierarchy representing the circuit design. [19] The system of claim 17 or 18, wherein the number information is represented by a 2D matrix or a 3D network. [20] The system of claim 19, wherein converting comprises performing a tilt operation, a rotate operation, and / or a translate operation on the initial position based on the position parameter.

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