Method for manufacturing a trench capacitor structure and trench capacitor

Abstract

A method for fabricating a trench capacitor structure comprising the steps of providing a silicon substrate with a trench structure having a plurality of depressions in a major surface of the silicon substrate; forming a first silicon dioxide layer at least in the depressions of the silicon substrate; depositing a first silicon nitride layer on the first silicon dioxide layer; depositing a second silicon dioxide layer on the first silicon nitride layer by depositing a polycrystalline silicon layer and oxidizing the polycrystalline silicon layer; and depositing a second silicon nitride layer on the second silicon dioxide layer.

Description

[0001] Embodiments according to the invention relate to a method for producing a trench capacitor structure and to a trench capacitor, or to a method for producing a dielectric layer stack and to a trench capacitor with a dielectric layer stack. The dielectric layer stack is preferably a dielectric (ON) x -Stacks with x≥2, for example for Si-RC snubber devices, where a silicon dioxide layer is denoted by O and a silicon nitride layer is denoted by N.

[0002] Different concepts are known for reducing substrate distortion during the manufacture of an integrated capacitor.

[0003] For example, patent DE 10 2019 204 503 B3 discloses the introduction of a stress-free nitride layer to increase the peak dielectric strength to 1200 V and reduce wafer warping. However, a further increase in dielectric strength is hardly possible with such a design without losing integration density (e.g., through thicker dielectric layers) or drastically increasing wafer warping (e.g., thicker dielectric layers while simultaneously increasing the surface area through deeper hole structuring).

[0004] The document DE 10 2005 063 468 B4 relates to the field of semiconductor device manufacturing and discloses a method for manufacturing a bottle trench and a bottle trench capacitor.

[0005] Document US 2013 / 0 175 666 A1 describes semiconductor devices that include a capacitor integrated therein. In one embodiment, the semiconductor devices include a substrate in which trenches are formed. A metal-insulator-metal (MIM) capacitor is formed within the trenches and at least partially over the substrate.

[0006] In view of this, there is a need for a concept for components with dielectrics, e.g. trench capacitors or RC snubbers, or for dielectric layer structures to increase a breakdown voltage at a constant or increased integration density (capacitance) while taking into account the wafer bending due to thermomechanical stress during / after the deposition of the dielectric layers.

[0007] This problem is solved by the subject matter of the independent patent claims. Further developments according to the invention are defined in the subclaims. Summary of the invention

[0008] According to one aspect of the present invention, the inventors have recognized that a problem in the fabrication of a trench capacitor structure is that the dielectric strength can hardly be increased without losing integration density or drastically increasing the warpage of the silicon substrate. According to one aspect of the present invention, this difficulty is overcome by providing a dielectric layer stack comprising at least two silicon dioxide layers and at least two silicon nitride layers in a trench structure of a silicon substrate, in which the silicon dioxide layers and the silicon nitride layers are arranged alternately one above the other.While trench capacitors can achieve higher capacitance densities compared to planar capacitors, it is important to note that manufacturing mechanisms for planar capacitors cannot simply be applied to trench capacitors, especially since coating trench structures presents entirely different challenges, such as those related to uniform layer thicknesses and substrate warpage, than coating planar surfaces. In this context, the inventors recognized that the alternating formation of silicon dioxide and silicon nitride layers in trench structures not only controls substrate warpage during layer stack formation, but also allows for increased hole depth and thus surface area of ​​the capacitor.In particular, it was determined that the layer stack formed in the trench structure must comprise at least two silicon dioxide layers and at least two silicon nitride layers in order to minimize substrate distortion at large hole depths. Furthermore, it was observed that, in connection with trench structures, a silicon dioxide layer can be formed on a silicon nitride layer particularly advantageously, i.e., with high quality, such as a uniform structure, a uniform layer thickness, and / or with few defects, if a polycrystalline silicon layer is applied and oxidized. Thus, trench capacitor structures with a dielectric layer stack with high breakdown strength can be obtained.

[0009] Accordingly, one embodiment relates to a method for fabricating a trench capacitor structure. The method comprises providing a silicon substrate having a trench structure with a plurality of recesses in a main surface of the silicon substrate. The method further comprises forming a first silicon dioxide layer in the recesses of the silicon substrate; depositing a first silicon nitride layer on the first silicon dioxide layer; depositing a second silicon dioxide layer on the first silicon nitride layer by depositing a polycrystalline silicon layer and oxidizing the polycrystalline silicon layer; and depositing a second silicon nitride layer on the second silicon dioxide layer. The first silicon dioxide layer is formed at least in the recesses of the silicon substrate.Optionally, the first silicon dioxide layer can be additionally formed on at least parts of the main surface of the silicon substrate or on the entire main surface of the silicon substrate. For example, the first silicon dioxide layer is further formed on parts of the main surface of the silicon substrate that connect the recesses to one another. Thus, an (ON) is formed at least in the recesses of the silicon substrate and optionally additionally on the main surface of the silicon substrate. x -Stacks with x≥2 are formed, where a silicon dioxide layer is denoted by O and a silicon nitride layer is denoted by N. The index x indicates how many ON layer pairs are arranged one above the other.

[0010] According to one embodiment, during the oxidation of the polycrystalline silicon layer, an oxynitride layer is formed between the first silicon nitride layer and the second silicon dioxide layer. This results in a clean interface between the silicon nitride layer and the silicon dioxide layer. The formation of the oxynitride layer reduces potential defects between the silicon nitride layer and the silicon dioxide layer and increases electrical breakdown strength.

[0011] According to one embodiment, during the oxidation of the polycrystalline silicon layer, the polycrystalline silicon layer is completely converted into the second silicon dioxide layer. The inventors discovered that even if only a thin polycrystalline silicon layer remains, unpredictable electrical processes can occur in the trench capacitor structure and only a low breakdown strength can be achieved. This is based on the realization that the polycrystalline silicon layer is a semiconductor layer. However, since the layer stack of alternating silicon dioxide and silicon nitride layers serves as a dielectric in the trench capacitor structure, even a thin semiconductor layer between the layers of insulating material reduces the breakdown strength of the layer stack.

[0012] Optionally, after the polycrystalline silicon layer has been completely converted into the second silicon dioxide layer, the oxidation is continued to partially oxidize the first silicon nitride layer and form an oxynitride layer between the first silicon nitride layer and the second silicon dioxide layer. This achieves a clean interface between the silicon nitride layer and the silicon dioxide layer and a high electrical breakdown strength. The oxidation is continued, for example, for a period of at least 5 minutes, 20 minutes, or 1 hour. The period is, for example, in a range of 5 minutes to 5 hours, 20 minutes to 5 hours, or 1 hour to 5 hours, preferably in a range of 5 minutes to 1 hour. In a preferred embodiment, the oxidation is continued for approximately 20 minutes or approximately 1 hour.

[0013] According to one embodiment, the polycrystalline silicon layer is undoped. This is based on the finding that this allows a high-quality silicon dioxide layer to be formed in the trench capacitor structure. In particular, the inventors discovered that this allows a very pure silicon dioxide layer with low leakage current to be achieved. This improves the electrical properties of the trench capacitor structure.

[0014] According to one embodiment, the polycrystalline silicon layer is applied to the first silicon nitride layer by low-pressure chemical vapor deposition, i.e., using an LPCVD process. It has been recognized that while deposition of a silicon oxide layer directly onto the silicon nitride layer using an LPCVD process results in a defect-rich interface and low electrical breakdown strength, LPCVD deposition of polycrystalline silicon followed by oxidation of the polycrystalline silicon results in a clean interface and high electrical breakdown strength.

[0015] According to one embodiment, the first silicon dioxide layer, the first silicon nitride layer, the second silicon dioxide layer, and / or the second silicon nitride layer are applied with a respective layer thickness in a range from 100 nm to 1000 nm or 330 nm to 530 nm. The individual layers can have different layer thicknesses. It has also been found that a sequence of several thin silicon dioxide and silicon nitride layers achieves lower substrate deflection and higher breakdown strength than a sequence of less thick silicon dioxide and silicon nitride layers.

[0016] According to one embodiment, the first silicon dioxide layer is formed in the recesses of the silicon substrate by means of thermal growth, the first silicon nitride layer is applied to the first silicon dioxide layer by means of low-pressure chemical vapor deposition, ie an LPCVD process, and the second silicon nitride layer is applied to the second silicon dioxide layer by means of low-pressure chemical vapor deposition, ie an LPCVD process.

[0017] According to one embodiment, a silicon nitride layer together with a silicon dioxide layer forms a layer pair, wherein the silicon nitride layer is arranged on the silicon dioxide layer, e.g., as viewed from the silicon substrate in the layer stacking direction. In other words, a silicon dioxide layer and a silicon nitride layer on the silicon dioxide layer can be referred to as a layer pair. A layer pair can also be referred to herein as a layer stacking unit. The first silicon dioxide layer and the first silicon nitride layer form, e.g., a first layer pair, and the second silicon dioxide layer and the second silicon nitride layer form, e.g., a second layer pair. At least one further layer pair comprising a silicon dioxide layer and a silicon nitride layer can be applied to the second layer pair, e.g., as viewed from the silicon substrate in the layer stacking direction.The silicon dioxide layer of the respective further layer pair is applied to the silicon nitride layer of the respective preceding layer pair. The application of layer pairs comprising a silicon dioxide layer and a silicon nitride layer is repeated several times. Thus, an (ON) is formed at least in the recesses of the silicon substrate and optionally additionally on the main surface of the silicon substrate. x-Stack with x≥3 is formed, wherein a silicon dioxide layer is designated by O and a silicon nitride layer is designated by N. The at least one further layer pair is applied, for example, to the second layer pair in such a way that a layer structure with alternating silicon dioxide and silicon nitride layers is formed. From the second layer pair onwards, the silicon dioxide layer of the respective layer pair is applied by applying a polycrystalline silicon layer and oxidizing the polycrystalline silicon layer. The inventors recognized that even with a thicker overall dielectric stack layer, i.e. with more silicon dioxide and silicon nitride layers alternating one above the other, the integration density can be maintained or even increased.It has been found that by alternately stacking silicon dioxide and silicon nitride layers, substrate warping can be minimized and, at the same time, a layer stack with a large total thickness, e.g., of at least 1600 nm, 2000 nm, or 3000 nm, can be realized in the recesses of the silicon substrate. This results in a layer stack with high breakdown strength, e.g., of at least 1200 V, 1400 V, or 1500 V. It is particularly advantageous if an oxynitride layer is also formed between each individual layer pair.

[0018] According to one embodiment, the oxidation of the polycrystalline silicon layers described herein is carried out by means of dry chemical oxidation or wet chemical oxidation. In other words, the silicon dioxide layers described herein are grown thermally. The dry chemical or wet chemical oxidation may also be referred to herein as dry chemical or wet chemical reoxidation or oxidation build-up. The wet chemical oxidation may also be referred to herein as wet chemical oxidation. The inventors recognized that the formation of silicon dioxide layers by means of dry chemical or wet chemical oxidation of polycrystalline silicon leads to cleaner interfaces and a higher breakdown strength than when the silicon dioxide layers are applied directly using LPCVD (low-pressure chemical vapor deposition) or PECVD (plasma-enhanced chemical vapor deposition) processes.This produces high-quality silicon dioxide layers and improves the electrical properties of the trench capacitor structure. Wet-chemical oxidation has the advantage that the silicon dioxide layers can be formed more quickly than with dry-chemical oxidation, and dry-chemical oxidation has the advantage over wet-chemical oxidation that a higher breakdown strength can be achieved in the layer stack formed in the recesses of the silicon substrate.

[0019] According to one embodiment, an RC snubber element is formed or manufactured using the method described herein.

[0020] A further embodiment relates to a trench capacitor comprising a dielectric layer structure with a first silicon dioxide layer, a first silicon nitride layer, a second silicon dioxide layer, and a second silicon nitride layer. The trench capacitor comprises, for example, a silicon substrate with a trench structure having a plurality of depressions in a main surface of the silicon substrate. The dielectric layer structure is arranged, for example, in the depressions of the silicon substrate. The first silicon dioxide layer, the first silicon nitride layer, the second silicon dioxide layer, and the second silicon nitride layer are arranged in this order. The layers can be directly adjacent to one another. Optionally, an oxynitride layer is arranged between the first silicon nitride layer and the second silicon dioxide layer, wherein the oxynitride layer can also be considered part of the first silicon nitride layer.The second silicon dioxide layer may be an oxidized polycrystalline silicon layer.

[0021] The trench capacitor is based on the same considerations as the method described above. The trench capacitor can be supplemented with all the features and functions also described with regard to the method. Furthermore, at least parts of the trench capacitor can be manufactured using a method described herein. Short character description

[0022] Embodiments according to the present invention are explained in more detail below with reference to the accompanying figures. They show: Fig. 1a shows a block diagram of an embodiment of a method for producing a trench capacitor structure according to the invention; Fig. 1b shows schematic representations of method steps of an embodiment of a method according to the invention for producing a trench capacitor structure; Fig. 2 shows schematic representations of method steps of an embodiment of a method according to the invention for producing a dielectric layer structure with an oxynitride layer; Fig. 3 shows a schematic representation of an embodiment of a trench capacitor structure according to the invention with a plurality of ON layer pairs; Fig. 4 shows a schematic representation of an embodiment of a trench capacitor structure according to the invention with a plurality of ON layer pairs, each of which further comprises an oxynitride layer; Fig. 5 shows a diagram with a characteristic curve of an embodiment of the invention of a snubber component whose silicon dioxide layers were applied by means of dry chemical oxidation, and a characteristic curve of a snubber component whose silicon dioxide layers were applied by means of LPCVD deposition; Fig. 6 shows a diagram with a characteristic curve of an exemplary embodiment of a snubber component according to the invention, the silicon dioxide layers of which were applied by means of dry chemical oxidation, and a characteristic curve of an exemplary embodiment of a snubber component according to the invention, the silicon dioxide layers of which were applied by means of wet chemical oxidation; and Fig. 7 shows a diagram with a characteristic curve of an embodiment of a snubber component according to the invention, the silicon dioxide layers of which were applied by means of dry chemical oxidation, and a characteristic curve of a snubber component with a stress-free nitride layer. Detailed description of the embodiments according to the figures

[0023] Before exemplary embodiments of the present invention are explained in more detail below with reference to the drawings, it is pointed out that identical, functionally equivalent or equivalent elements, objects and / or structures in the different figures are provided with the same or similar reference numerals, so that the description of these elements shown in different exemplary embodiments is interchangeable or can be applied to one another.

[0024] To facilitate the description of the various embodiments, some of the figures have a Cartesian coordinate system x, y, z, where the xy-plane corresponds to a first main surface area of ​​a substrate (= a reference plane = xy-plane), i.e. is parallel to it, where the direction vertically upwards with respect to the reference plane (xy-plane) corresponds to the "+z" direction, and where the direction vertically downwards with respect to the reference plane (xy-plane) corresponds to the "-z" direction. In the following description, the term "lateral" means a direction parallel to the x and / or y direction, i.e. parallel to the xy-plane, where the term "vertical" means a direction parallel to the z-direction.

[0025] Fig. 1a and Fig. 1b show a method 100 for producing a trench capacitor structure 200 or a trench capacitor.

[0026] The method 100 comprises providing 110 a silicon substrate 210 with a trench structure. The trench structure has a plurality of recesses 212 in a main surface 214 of the silicon substrate 210. The silicon substrate 210 can be, for example, a silicon wafer. For the method 100, for example, a prefabricated silicon substrate 210 with a pre-integrated trench structure can be used. Alternatively, providing 110 the silicon substrate 210 with the trench structure can include forming the trench structure in the main surface 214 of the silicon substrate 210. The trench structure is formed, for example, by means of silicon substrate structuring. Forming the trench structure in the main surface 214 of the silicon substrate 210 can comprise one or more lithographic steps and one or more etching steps.

[0027] A further step of the method 100 relates to forming 120 a first silicon dioxide layer 2201 at least in the recesses 212 of the silicon substrate 210. In Fig. 1b, the first silicon dioxide layer 2201 is also formed, by way of example, on the main surface 214 of the silicon substrate 210. The first silicon dioxide layer 2201 is formed, for example, by means of thermal growth or thermal oxidation. For this purpose, the silicon substrate 210 is oxidized, for example, using dry-chemical or wet-chemical oxidation, with dry-chemical oxidation being preferred. For example, surfaces within the plurality of recesses 212 and optionally the main surface 214 or parts of the main surface 214 are oxidized to form the first silicon dioxide layer 2201. The first silicon dioxide layer 2201 comprises, for example, SiO2 material or thermal oxide. A thickness of the first silicon dioxide layer 2201 is, for example, in a range from 100 nm to 1000 nm, preferably in a range from 100 nm to 450 nm, such as, for example, 330 nm.

[0028] A first silicon nitride layer 2301 is applied 130 to the first silicon dioxide layer 2201. The first silicon nitride layer 2301 is deposited, for example, by low-pressure vapor deposition, i.e., using an LPCVD process. The first silicon nitride layer 2301 comprises, for example, Si3N4 material. A thickness of the first silicon nitride layer 2301 is, for example, in a range from 100 nm to 1000 nm, preferably in a range from 100 nm to 550 nm, such as 460 nm.

[0029] A second silicon dioxide layer 2202 is applied 140 to the first silicon nitride layer 2301. In this case, a polycrystalline silicon layer 222, i.e., polysilicon, is applied 142 to the first silicon nitride layer 2301 and oxidized 144. The polycrystalline silicon layer 222 is, for example, undoped. The polycrystalline silicon layer 222 is deposited, for example, by means of low-pressure chemical vapor deposition, i.e., using an LPCVD process. The oxidation 144 of the polycrystalline silicon layer 222 is carried out, for example, by dry-chemical or wet-chemical oxidation, with dry-chemical oxidation being preferred. A thickness of the second silicon dioxide layer 2202 is, for example, in a range from 100 nm to 1000 nm, preferably in a range from 100 nm to 450 nm, such as, for example, 330 nm.

[0030] The method 100 further comprises applying 150 a second silicon nitride layer 2302 on the second silicon dioxide layer 2202. The second silicon nitride layer 2302 is deposited, for example, by means of low-pressure chemical vapor deposition, i.e., using an LPCVD process. The second silicon nitride layer 2302 comprises, for example, Si3N4 material. A thickness of the second silicon nitride layer 2302 is, for example, in a range from 100 nm to 1000 nm, preferably in a range from 100 nm to 550 nm, such as, for example, 530 nm.

[0031] Thus, a trench capacitor (see trench capacitor structure 200) is formed or provided with a dielectric layer structure 240. The dielectric layer structure 240 includes the first silicon dioxide layer 2201, the first silicon nitride layer 2301, the second silicon dioxide layer 2202, and the second silicon nitride layer 2302. Optionally, the dielectric layer structure 240 may include further silicon dioxide and silicon nitride layers, see, for example, Fig. 3 and Fig. 4. The dielectric layer structure 240 is arranged at least in the plurality of recesses 212, e.g., on surfaces of the plurality of recesses 212. Optionally, the dielectric layer structure 240 is further arranged on the main surface 214 of the silicon substrate 210 or on parts of the main surface 214 of the silicon substrate 210.

[0032] The first silicon dioxide layer 2201, the first silicon nitride layer 2301, the second silicon dioxide layer 2202, and the second silicon nitride layer 2302 are arranged adjacent to one another, for example, in this order. The dielectric layer structure 240 can also be viewed as a layer stack with dielectric layers, see layers 2201, 2202, 2301, and 2302. The first silicon dioxide layer 2201 is arranged, for example, directly on the substrate 210 of the trench capacitor, and the first silicon nitride layer 2301, the second silicon dioxide layer 2202, and the second silicon nitride layer 2302 are arranged, for example, in this order on the first silicon dioxide layer 2201. The order of the dielectric layers of the dielectric layer structure 240 is indicated, for example, from the silicon substrate 210 in the layer stacking direction.

[0033] Optionally, the method may include 100 additional steps as described in connection with Fig. 2. Likewise, the trench capacitor structure 200 may, for example, comprise further layers as described in connection with Fig. 2. The first silicon nitride layer 2301 may, for example, comprise the silicon nitride layer described in connection with Fig. 2. The oxynitride layer 232 of the first silicon nitride layer 2301 is arranged, for example, at an interface between the first silicon nitride layer 2301 and the second silicon dioxide layer 2202.

[0034] Fig. 2 shows, by way of example, the method 100 for a section of a trench capacitor structure 200 formed by the method. In other words, a recess 212 of the plurality of recesses of the trench structure in the silicon substrate 210 and the layers applied therein are shown schematically in detail. That is, Fig. Figure 2 shows the process steps in detail for one of the majority of depressions in the trench structure. Even though Fig. 2 shows the method steps only in connection with one recess 212 of the plurality of recesses, it is clear that the method steps can also be applied in connection with the remaining recesses of the plurality of recesses.

[0035] The procedure 100 in Fig. 2, as well as the procedure 100 in Fig. 1a and Fig. 1b, the steps of providing 110 the silicon substrate 210; forming 120 the first silicon dioxide layer 2201 in the recesses 212 of the silicon substrate 210; applying 130 the first silicon nitride layer 2301 on the first silicon dioxide layer 2201; applying 140 the second silicon dioxide layer 2202 on the first silicon nitride layer 2301; and applying 150 the second silicon nitride layer 2302 on the second silicon dioxide layer 2202.

[0036] As in connection with Fig. 1a and Fig. 1b, the application 140 of the second silicon dioxide layer 2202 on the first silicon nitride layer 2301 comprises an application 142 of the polycrystalline silicon layer 222 and an oxidation 144 of the polycrystalline silicon layer 222. The oxidation 144 can be carried out, for example, using dry chemical or wet chemical methods. During the oxidation 144 of the polycrystalline silicon layer 222, an oxynitride layer 232 is optionally formed between the first silicon nitride layer 2301 and the second silicon dioxide layer 2202, or in the first silicon nitride layer 2301 at an interface between the first silicon nitride layer 2301 and the second silicon dioxide layer 2202. The polycrystalline silicon layer 222 is, for example, completely converted into the second silicon dioxide layer 2202, i.e.completely oxidized, and optionally the oxidation 144 is subsequently continued in order to partially oxidize the first silicon nitride layer 2301 and to form the oxynitride layer 232 in the first silicon nitride layer 2301, or at an interface between the first silicon nitride layer 2301 and the second silicon dioxide layer 2302. The nitride surface of the first silicon nitride layer 2301 is oxidized, for example, to a depth of a few nm, by continuing the oxidation 144 for longer than is necessary for the complete consumption of the polycrystalline silicon. This step is optional and is intended primarily to optimize the interface between oxide and nitride / to make it more defect-free. The first silicon nitride layer 2301 serves, for example, as an oxidation stop. An oxidation duration of the oxidation 144 is, for example, B. in a range of 5 h-72 h, 5 h-48 h or 5 h-32 h, such as 9.75 h or 10 h. The oxidation 144 is e.g.Depending on the thickness of the second silicon dioxide layer 2202 to be formed, the oxidation is carried out for a period of at least 5 hours, 9 hours, or 24 hours to ensure that the polycrystalline silicon layer 222 has been completely converted into the second silicon dioxide layer 2202 and the oxynitride layer 232 has been formed. The thicker the second silicon dioxide layer 2202 to be formed or the polycrystalline silicon layer 222 to be oxidized, the longer the oxidation 144 should be carried out.

[0037] The oxynitride layer 232 comprises, for example, thermal oxide. The thickness of the oxynitride layer 232 is, for example, in a range from 1 nm to 12 nm or 1 nm to 11 nm. The oxynitride layer 232 preferably has a maximum thickness of 11 nm.

[0038] The first silicon dioxide layer 2201, the first silicon nitride layer 2301, the oxynitride layer 232, the second silicon dioxide layer 2202, and the second silicon nitride layer 2302 form, for example, a dielectric layer structure 240.

[0039] Optionally, a layer 250 containing doped polysilicon material can be applied 160 to the second silicon nitride layer 2302. The layer 250 containing doped polysilicon material is applied 160, for example, such that at least the recesses 212 in which the silicon dioxide and silicon nitride layers are arranged are filled with the doped polysilicon material. The layer 250 containing doped polysilicon material, for example, closes off the plurality of recesses 212. The layer 250 containing doped polysilicon material can further be applied 160 to a surface of the second silicon nitride layer 2302 facing away from the main surface of the silicon substrate 210. The layer 250 with doped polysilicon material is applied 160, for example, such that a surface parallel to the main surface 214 of the silicon substrate 210 is formed on a side of the layer 250 facing away from the dielectric layer structure 240.The layer 250 with doped polysilicon material is deposited, for example, by low-pressure chemical vapor deposition, i.e., using an LPCVD process. The doped polysilicon material is, for example, in-situ doped polycrystalline silicon material. The layer 250 with doped polysilicon material forms, for example, an electrode, such as a front-side electrode, of an RC snubber element 300.

[0040] Optionally, an aluminum layer (see 2601 and 2602) can be deposited 170 on the layer 250 with doped polysilicon material and on a side of the silicon substrate 210 facing away from the dielectric layer structure 240. The aluminum layers 2601 and 2602 are, for example, front-side and back-side metallizations of an RC snubber element 300.

[0041] A trench capacitor or an RC snubber element 300 comprises, for example, a silicon substrate 210 with a trench structure having a plurality of recesses 212 and the dielectric layer structure 240 at least in the recesses 212 of the silicon substrate 210. The first silicon dioxide layer 2201 of the dielectric layer structure 240 is arranged, for example, directly on the substrate 210 of the trench capacitor, and the first silicon nitride layer 2301 with the oxynitride layer 232, the second silicon dioxide layer 2202, and the second silicon nitride layer 2302 are arranged, for example, in this order on the first silicon dioxide layer 2201. The order of the dielectric layers of the dielectric layer structure 240 is indicated, for example, from the silicon substrate 210 in the layer stacking direction.Optionally, the trench capacitor comprises a doped polycrystalline silicon layer (see layer 250) on a surface of the dielectric layer structure 240 facing away from the silicon substrate 210. Furthermore, the trench capacitor may comprise, for example, a first aluminum layer 2601 on a surface of the silicon substrate 210 opposite the main surface 214 and a second aluminum layer 2602 on a surface of the doped polycrystalline silicon layer facing away from the main surface 214.

[0042] Fig. Show 1a-2 (ON) x Snubber processing with x=2. However, processes 100 or a trench capacitor structure 200, e.g., for a trench capacitor or for an RC snubber element 300, with more ON layer pairs, ie, silicon dioxide-silicon nitride layer pairs, are also possible. Fig. 3 shows an example of a trench capacitor structure 200 with x≥5 and Fig. 4 shows an example of a trench capacitor structure 200 with x=3. The silicon dioxide layers discussed herein may also be referred to as oxide layers or by the letter O. The silicon nitride layers discussed herein may also be referred to as nitride layers or by the letter N.

[0043] As in Fig. 3 and Fig. 4, a dielectric layer structure 240 described herein may comprise three or more silicon dioxide-silicon nitride layer pairs, ie, ON layer pairs 242, see, for example, 242 1-5 in Fig. 3 and Fig. 242 1-3 in Fig. 4. A silicon dioxide layer 220 and a silicon nitride layer 230 together form an ON layer pair 242. Viewed from the silicon substrate 210 in the layer stacking direction, ie in the direction of the dielectric layer structure 240, the respective silicon nitride layer 230 is arranged on the respective silicon dioxide layer 220, for example, within an ON layer pair 242.

[0044] The ON layer pairs 242 are arranged one above the other in the layer stacking direction. Starting with the second layer pair 2422, the respective silicon dioxide layer 220 is arranged on a silicon nitride layer 230 of the respective preceding layer pair 242. The dielectric layer structure 240 comprises, for example, a layer stack with alternating silicon dioxide and silicon nitride layers.

[0045] Starting with the second layer pair 2422, the respective silicon dioxide layer 220 is applied by applying a polycrystalline silicon layer and oxidizing the polycrystalline silicon layer. Optionally, the oxidation can be continued after the respective polycrystalline silicon layer has been completely converted into the respective silicon dioxide layer 220 in order to oxidize the nitride surface of the respective silicon nitride layer 2301, on which the respective silicon dioxide layer 220 is arranged, and to form an oxynitride layer 232 in each case.

[0046] In a dielectric layer structure 240 with x ON layer pairs 242, as in Fig. 4, the first silicon nitride layer 230 up to the (x-1)th silicon nitride layer 230 each have an oxynitride layer 232, where x≥3. The oxynitride layers are arranged, for example, at an interface to a subsequent layer pair 242. This means that when a new layer pair 242 is formed on a preceding layer pair 242, a nitride surface of the silicon nitride layer 230 of the preceding layer pair is oxidized, for example, to a depth of a few nm, in order to form the oxynitride layer 232, wherein the nitride surface is arranged facing the new layer pair 242.

[0047] According to one embodiment, the oxynitride layers 232 may alternatively be considered as independent layers, each arranged between two consecutive ON layer pairs 242.

[0048] Optionally, the Fig. 3 and Fig. 4 illustrated trench capacitor structures 200 furthermore those associated with Fig. 2 described doped polycrystalline silicon layer 250 and / or the aluminum layers 1601 and 2602.

[0049] Instead of relying on stress-free nitride, as in patent DE 10 2019 204 503 B3 mentioned at the beginning of this application, these dielectric layers (silicon dioxide under silicon nitride) are created again on the underlying dielectric layers of silicon dioxide (thermally grown) and silicon nitride (deposited via LPCVD), see patent application DE 10 2014 223 904 A1, in any number of repetitions, greater than two, with layer thicknesses of 100 nm to 1000 nm each. This further utilizes the opposing material stresses to reduce or control wafer warping, thereby significantly increasing the breakdown voltage. The counteracting mechanical stresses can increase the hole depth and thus the surface area of ​​the capacitor, and the integration density can be maintained or even increased even with a thicker overall dielectric stack layer.

[0050] To maximize the quality of the silicon dioxide layers 220, they are produced by thermal oxidation. The first silicon dioxide layer 2201 is thus grown thermally on the silicon substrate 210, and the further silicon dioxide layers 2202-220 x (with x≥3) are deposited on the respective silicon nitride layers 2301-230 x-1(with x≥3), a layer of undoped polycrystalline silicon (100-1000 nm) is deposited using LPCVD and completely thermally oxidized or reoxidized using dry chemical oxidation. After the respective polycrystalline silicon layer 222 has been completely converted into silicon dioxide 220, oxidation continues for a certain period of time, so that the silicon nitride 230 is also slightly oxidized and an oxynitride layer 232 is formed. This leads to a clean interface between the silicon nitride layer 230 and the silicon dioxide layer 220, the silicon nitride serves as a kind of "growth stop" and is only slightly oxidized due to the very low dry oxidation rate of silicon nitride itself (see RL Guldi et al 1989 J. Electrochem. Soc. 136 3815, DOI 10.1149 / 1.2096555) and the partly thick silicon dioxide layer 220 (formerly polycrystalline silicon 222) above, which slows down the diffusion of oxygen to the silicon nitride.By continuously balancing the mechanical stresses caused by the opposing pressures of silicon nitride and silicon oxide, wafer warping is kept as low as possible, allowing the integration density to be further increased by increasing the hole depth and, at the same time, the thickness of the entire dielectric stack, and thus the breakdown strength.

[0051] An increase in breakdown strength could only be achieved with the materials and methods known to date by increasing the overall layer thickness. This leads, on the one hand, to an increase in wafer warping and, on the other hand, to a reduction in integration density. If the aim is to increase integration density, deeper holes must be created, which in turn increases wafer warping. As a solution, the mutual mechanical pressures of the dielectrics used here, i.e. the silicon dioxide layer 220 and the silicon nitride layer 230, are used, namely by arranging at least two silicon dioxide layers 220 and at least two silicon nitride layers 230 alternately one above the other. In order to combine this with the best possible electrical properties, dry chemical oxidation or PECVD is used instead of LPCVD or PECVD.Oxidation or reoxidation of the polysilicon is used to form the silicon dioxide layer 220 and create the layer stack.

[0052] By depositing silicon dioxide layers directly onto silicon nitride layers, e.g., using LPCVD or PECVD processes, a fundamentally similar stack can be created. However, the interfaces are more defect-rich when using LPCVD or PECVD processes, and the electrical breakdown strength is significantly lower, see Fig. 5. Fig. 5 shows a first characteristic curve 400 for a component which, according to Fig. 2 and has an equivalent oxide thickness of approximately 1175 nm. The silicon dioxide layers of the component underlying the characteristic curve 400 were applied by dry chemical oxidation. Furthermore, Fig. 5 a second characteristic curve 500 for a component of the same construction, in which, however, the silicon dioxide layers were applied by means of LPCVD deposition and not by means of dry chemical oxidation of a polysilicon layer.

[0053] Polycrystalline silicon can also be reoxidized wet instead of dry chemically, which is also faster in terms of process technology, but also has a lower breakdown strength, see Fig. 6. Fig. 6 shows a first characteristic curve 400 for a component which, according to Fig. 2 and has an equivalent oxide thickness of approximately 1175 nm. The silicon dioxide layers of the component underlying the characteristic curve 400 were applied by dry chemical oxidation. Furthermore, Fig. 6 a second characteristic curve 600 for a likewise according to Fig. 2, in which, however, silicon dioxide layers (e.g. at least the silicon dioxide layers from the second silicon dioxide layer 2202 onwards) were applied by means of moist-chemical or wet-chemical oxidation of a polysilicon layer and not by means of dry-chemical oxidation of a polysilicon layer.

[0054] Furthermore, the component has Fig. 2 also has a higher breakdown strength compared to components with a stress-free nitride layer, as known from DE 10 2019 204 503 B3. Fig. 7 shows a first characteristic curve 400 for a component which, according to Fig. 2 and has an equivalent oxide thickness of approximately 1175 nm. The silicon dioxide layers of the component underlying the characteristic curve 400 were applied by dry chemical oxidation. Furthermore, Fig. 7 a second characteristic curve 700 for a component with a dielectric layer structure with 330 nm SiO2, 550 nm Si3N4, 500 nm Si x N y and 500 nm Si3N4 with an equivalent oxide thickness of approximately 1085 nm.

[0055] With the methods 100 described herein, components, e.g., RC snubber elements, can be provided with voltage classes of at least 1000 V, 1200 V, or even at least 1500 V. For example, a component according to Fig. 2 with a total oxide thickness of 680 nm and a total nitride thickness of 1000 nm, a breakdown voltage of 1500 V can be achieved at 10 mA.

[0056] Whether a Si-RC snubber component was manufactured using one of the methods 100 described herein can be determined by FIB cross-sectional analysis (Focused Ion Beam with SEM imaging). The leakage current behavior at nominal voltage can indicate the quality of the oxide used, i.e., the silicon dioxide layers 220. Here, a rough distinction can be made between PECVD, wet-chemically grown, and dry-chemically grown oxides (decreasing leakage current from PECVD to wet to dry oxide). Furthermore, TEM analyses can be used to investigate the oxide layer generation used (deposition vs. growth). Another possibility is to investigate etch rate differences of the generated oxide layers.

[0057] The processes described herein can be used to manufacture snubber components for surge suppression in power modules. These snubber components, for example, allow silicon carbide transistors in conventional power modules to switch faster without module-related induction leading to high voltage spikes, which could potentially be damaging to all components in the module. The capacitor absorbs the energy (over several cycles), and this energy is converted into heat and dissipated via the integrated resistor.

[0058] Possible applications for such modules include vehicle electronics (in charging modules or e-mobility drive trains) or renewable energy (wind turbines, etc.). The ability to switch faster can increase the overall efficiency of the power modules, as less power loss occurs.

Claims

[1] Method (100) for producing a trench capacitor structure (200), comprising the steps: Providing (110) a silicon substrate (210) having a trench structure with a plurality of recesses (212) in a main surface (214) of the silicon substrate (210); Forming (120) a first silicon dioxide layer (2201) at least in the recesses (212) of the silicon substrate (210); Applying (130) a first silicon nitride layer (2301) on the first silicon dioxide layer (2201); Applying (140) a second silicon dioxide layer (2202) on the first silicon nitride layer (2301) by applying (142) a polycrystalline silicon layer (222) and oxidizing (144) the polycrystalline silicon layer (222); and Applying (150) a second silicon nitride layer (2302) on the second silicon dioxide layer (2202). [2] The method (100) of claim 1, wherein the oxidizing (144) is continued after the polycrystalline silicon layer (222) has been completely converted into the second silicon dioxide layer (2202) to partially oxidize the first silicon nitride layer (2301) and form an oxynitride layer (232) between the first silicon nitride layer (2301) and the second silicon dioxide layer (2202). [3] The method (100) according to any one of the preceding claims, wherein the polycrystalline silicon layer (222) is undoped. [4] Method (100) according to one of the preceding claims, wherein the polycrystalline silicon layer (222) is applied to the first silicon nitride layer (2301) by means of low-pressure vapor deposition. [5] Method (100) according to one of the preceding claims, wherein the first silicon dioxide layer (2201), the first silicon nitride layer (2301), the second silicon dioxide layer (2202) and the second silicon nitride layer (2302) are applied with a respective layer thickness in a range of 100 nm to 1000 nm. [6] Method (100) according to one of the preceding claims, wherein the formation (120) of the first silicon dioxide layer (2201) at least in the recesses (212) of the silicon substrate (210) is carried out by means of thermal growth; the application (130) of the first silicon nitride layer (2301) on the first silicon dioxide layer (2201) is carried out by means of low-pressure vapor deposition; and the application (150) of the second silicon nitride layer (2302) on the second silicon dioxide layer (2202) is carried out by means of low-pressure vapor deposition. [7] Method (100) according to one of the preceding claims, wherein a silicon nitride layer (230) on a silicon dioxide layer (220) forms a layer pair (242), wherein the first silicon dioxide layer (2201) and the first silicon nitride layer (2301) form a first layer pair (2421) and the second silicon dioxide layer (2202) and the second silicon nitride layer (2302) form a second layer pair (2422), wherein at least one further layer pair (242) is applied to the second layer pair (2422), and wherein, starting from the second layer pair (2422), the respective silicon dioxide layer (220) is applied by applying (142) a polycrystalline silicon layer (222) and oxidizing (144) the polycrystalline silicon layer (222). [8] Method (100) according to one of the preceding claims, wherein the oxidation (144) of the polycrystalline silicon layer (222) is carried out by means of dry chemical oxidation or wet chemical oxidation. [9] Use of the method (100) according to one of the preceding claims for forming an RC snubber element (300). [10] Trench capacitor comprising: a dielectric layer structure (240) having a first silicon dioxide layer (2201), a first silicon nitride layer (2301), a second silicon dioxide layer (2202) and a second silicon nitride layer (2302); wherein the first silicon dioxide layer (2201), the first silicon nitride layer (2301), the second silicon dioxide layer (2202) and the second silicon nitride layer (2302) are adjacent to one another in this order; wherein the trench capacitor is manufactured by the method (100) according to one of claims 1 to 8. [11] The trench capacitor according to claim 10, wherein a layer thickness of the first silicon dioxide layer (2201), the first silicon nitride layer (2301), the second silicon dioxide layer (2202) and the second silicon nitride layer (2302) is in a range of 100 nm to 1000 nm.

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