Process for manufacturing MEMS assemblies

Abstract

The invention relates to a method for producing MEMS assemblies (100), comprising providing a functional wafer with a plurality of chips (124) with first MEMS structures and an SOI-based wafer, said wafer having a functional layer with second MEMS structures, a handle wafer, and a silicon dioxide layer arranged between the handle wafer and the functional layer, separating the functional wafer into chips, removing the chips from the functional wafer, producing a carrier wafer-chip assembly by connecting at least some of the removed chips to a surface of the functional layer and a surface of a carrier wafer (150) such that the functional layer and the carrier wafer are arranged on opposite sides of the chips, removing the handle wafer and the silicon dioxide layer after producing the carrier wafer-chip assembly,exposing the MEMS structures of the carrier wafer-chip assembly after removing the handle wafer and the silicon dioxide layer, separating the carrier wafer-chip assembly after exposing it into MEMS assemblies such that each MEMS assembly has a plurality of chips, and removing the MEMS assemblies from the separated carrier wafer-chip assembly.

Description

Technical area

[0001] The present invention relates to the field of manufacturing microelectromechanical devices and relates to a method for manufacturing MEMS assemblies and a corresponding MEMS assembly. State of the art

[0002] Devices with microelectromechanical systems (MEMS), such as micromirror arrays or micromirror actuators, are used today in a wide variety of devices, for example, in smartphones, projectors, head-up displays, barcode readers, mask exposure units in semiconductor manufacturing, and microscopes. Corresponding micromirror arrays are known, for example, from DE 10 2013 208 446 A1, EP 0 877 272 A1, and WO 2010 / 049076 A2. DE 10 2006 032 195 A1 describes a method for producing microelectromechanical structures (MEMS structures). DE 10 2009 029 202 A1 discloses a micromechanical system and a method for producing a micromechanical system.From DE 10 2015 206 996 A1, the so-called EPyC process (EPyC: epitaxial polysilicon cycle) for the production of microelectromechanical structures with a large vertical extent is known, which uses epitaxial polysilicon as functional and sacrificial material and builds up a layer structure of epitaxial polysilicon layers (EpiPoly layers) by means of repeating cycles.

[0003] Particularly for components that are constructed from a large number of MEMS elements arranged in an array, such as micromirror arrays, the challenge is often to achieve a high yield of functional MEMS components. Disclosure of the invention

[0004] According to the invention, a method for producing MEMS assemblies and a corresponding MEMS assembly are proposed.

[0005] According to a first aspect of the invention, a method for manufacturing MEMS assemblies is proposed. For this purpose, a functional wafer comprising a plurality of semiconductor chips with first MEMS structures is first provided. Such semiconductor chips are referred to below as MEMS chips or simply as chips. Furthermore, an SOI-based wafer (Silicon-on-Insulator) is provided, wherein the SOI-based wafer comprises a functional layer with second MEMS structures, a handle wafer, and a silicon dioxide layer (also referred to as BOX, buried oxide) arranged between the handle wafer and the functional layer.

[0006] An SOI-based wafer is understood to be a semiconductor wafer that, in addition to an SOI wafer, optionally has further layers. These further layers, for example grown using the EPyC process, are arranged layer by layer on the SOI device layer (which is typically a single-crystal silicon layer) of the SOI wafer. The SOI device layer, together with the optionally present further layers, forms the functional layer. In other words, an SOI-based wafer comprises an SOI wafer, which in turn consists of the handle wafer, an SOI device layer, and a silicon dioxide layer located between them, as well as further layers optionally arranged layer by layer on the SOI device layer.The functional layer with the second MEMS structures consists of the SOI device layer and any additional layers of the SOI-based wafer, which may have been grown layer by layer on the SOI device layer using, for example, the EPyC process. These additional layers can be used alone or together with the device layer to implement the second MEMS structures.

[0007] The first structures and / or the second MEMS structures can comprise or be structures for one or more MEMS components to be manufactured, such as MEMS sensors and / or MEMS actuators. In particular, the first and / or the second MEMS structures can be arranged such that the MEMS components to be manufactured have an array-like and, in particular, rectangular or square arrangement, for example, a 2x2, 3x2, 3x3, 3x4, or 4x4 arrangement. The MEMS components can be, for example, MEMS inertial sensors, MEMS pressure sensors, MEMS microphones, MEMS micromirrors, and / or MEMS resonators.

[0008] The functional wafer typically has one or more semiconductors or consists of one or more semiconductors, for example comprising silicon or consisting of silicon. The functional layer and the handle wafer of the SOI-based wafer consist of silicon or comprise it. Metals and / or semiconductor oxides can also be contained in the functional wafer and / or the functional layer. For example, the functional wafer and / or the functional layer can comprise sacrificial regions made of a semiconductor such as silicon and / or a semiconductor oxide such as silicon dioxide. In addition to purely mechanical structures, the first and / or second MEMS structures can comprise, for example, structures for actuators, sensors, mirror surfaces, one or more electronic circuits, integrated circuits (ICs), electrodes and / or vias such as through-silicon vias (TSVs).The silicon dioxide layer of the SOI-based wafer consists of silicon dioxide (SiO2) or comprises silicon dioxide.

[0009] The functional wafer is then singulated into chips, for example, by means of plasma etching and / or gas-phase etching. For this purpose, prior to singulation of the functional wafer, the functional wafer can preferably be applied to a first carrier element such as an adhesive film, an adhesive tape, a dicing film, a wafer, and / or a glass plate. The first carrier element is designed such that, after singulation of the functional wafer, the singulated chips are fixed to the first carrier element. It must therefore be ensured that the singulated chips remain fixed in their position, i.e., are held at least temporarily, and cannot fall off the first carrier element. Such fixation can be achieved, for example, using an adhesive.Before singulating the functional wafer, a wafer-level test (WLT) may be performed to test one or more of the chips and preferably a selection of the tested chips for the subsequent creation of a carrier wafer-chip assembly based on the wafer-level test.

[0010] The separated chips are then removed from the functional wafer, possibly by detaching them from the first carrier element, for example, using a pick-and-place process. Special surfaces may be provided on the chips to facilitate removal.

[0011] A carrier wafer-chip composite is then created by bonding at least some of the removed chips to a surface of the functional layer of the SOI-based wafer and a surface of a carrier wafer such that the functional layer and the carrier wafer are arranged on opposite sides of the chips. Testing procedures can be used to select the chips before bonding in order to exclude defective chips. The carrier wafer serves for mechanical stabilization and can be designed in a simple or complex manner depending on the desired functionality; for example, it can have through-silicon vias (TSV). The carrier wafer can be, for example, a silicon wafer or a glass wafer, for example consisting of or comprising SiO2 and / or Al2O3.As a bonding method for connecting at least some of the removed chips to a surface of the functional layer and a surface of a carrier wafer, for example, silicon direct bonding (for example for SiO2-SiO2, Si-Si compounds), thermocompression bonding (for example for Au-Au, Cu-Cu, Fe-Fe, Al-Al compounds), eutectic bonding (for example for Al-Ge, Au-Si, Al-Si, Cu-Sn, Au-In compounds), glass frit bonding, adhesive bonding (gluing) and / or reactive bonding can be used.

[0012] After creating the carrier wafer-chip assembly, the handle wafer and the silicon dioxide layer of the SOI-based wafer are removed. For this purpose, the carrier wafer-chip assembly may be rotated, for example, along an axis parallel to one of the surfaces, to position the carrier wafer-chip assembly more appropriately for subsequent steps. Furthermore, the carrier wafer can be rethinned before removing the handle wafer.

[0013] The first MEMS structures and the second MEMS structures of the carrier wafer-chip assembly are then exposed, for example, by means of isotropic silicon sacrificial layer etching. Such silicon sacrificial layer etching for exposing MEMS structures can be carried out, for example, by means of plasma-free and / or plasma-assisted etching. In the case of silicon sacrificial regions to be removed, sacrificial layer etching is preferably carried out using sulfur hexafluoride (SF6), xenon difluoride (XeF2), chlorine trifluoride (ClF3), and / or nitrogen trifluoride (NF3). Furthermore, deep reactive ion etching (DRIE) can also be used for exposure. In the etching of silicon dioxide, which often follows silicon sacrificial layer etching, hydrogen fluoride (HF) can be used as the etching gas (HF gas-phase etching) and / or BOE (buffered oxide etch) can be used as the wet etchant.

[0014] The carrier wafer-chip assembly is then separated, for example, by stealth dicing, into a plurality of MEMS assemblies such that each assembly comprises a plurality of chips. The MEMS assemblies can therefore comprise or be, in particular, arrays of MEMS components such as micromirrors, i.e., in particular, a square arrangement (such as a 12x12, 20x20, or 24x24 array) of MEMS components. Such MEMS assemblies can then be removed from the separated carrier wafer-chip assembly and further processed.

[0015] Before this singulation of the carrier wafer-chip assembly, it is particularly advantageous if the carrier wafer-chip assembly is applied to a second carrier element such as an adhesive film, an adhesive tape, a dicing film, a wafer and / or a glass plate in such a way that the carrier wafer is brought into contact with the carrier element alone, wherein the second carrier element is designed in such a way, for example by means of an adhesive, that after the carrier wafer-chip assembly has been singulated, the MEMS assemblies are fixed to the second carrier element. Typically, for this purpose, the carrier wafer-chip assembly is rotated such that the carrier element, for example a dicing film, extends parallel to the carrier wafer, wherein the carrier wafer is oriented in the direction of the carrier element. The second carrier element can be identical to the first carrier element.

[0016] Advantageously, the first MEMS structures comprise or are structures for actuators for MEMS micromirrors and the second MEMS structures comprise structures for mirror plates for MEMS micromirrors, wherein the MEMS assemblies are formed by singulating the carrier wafer-chip assembly such that each MEMS assembly has a plurality of MEMS micromirrors, wherein each of the MEMS micromirrors has one of the actuators and one of the mirror plates.

[0017] Advantageously, the chips of the functional wafer have metal contacts, also referred to as metal pads. These can be created by backside metallization (metallization of the back of a chip) and / or used for wafer-level tests. The metal contacts can consist of or comprise aluminum, gold, and / or copper. The metal contacts can also consist of or comprise alloys such as AlCu and / or AlSiCu. Furthermore, the metal contacts can be provided with an OPM (over pad metallization), consisting of or comprising nickel, palladium, and / or gold, for example in the form of ENIG (electroless nickel immersion gold) and / or ENEPIG (electroless nickel electroless palladium immersion gold).Before the actual backside metallization, the backside of the chip can be passivated, i.e., a passivation layer can be applied that has recesses, wherein the recesses serve to accommodate the metal contacts. Such a passivation layer can preferably consist of silicon dioxide (SiO2) and / or a silicon nitride (for example, stoichiometric silicon nitride, i.e., Si3N4, and / or a non-stoichiometric silicon nitride, i.e., a silicon nitride with a non-stoichiometric composition) or can comprise silicon dioxide and / or a silicon nitride. In the case of such metal contacts, it is further advantageous if, after the carrier wafer-chip composite has been generated, the metal contacts are exposed by generating recesses in the carrier wafer.

[0018] The chips are preferably shaped such that, after the functional wafer has been singulated, two of the chips, preferably two of the chips each, can be arranged next to one another in such a way that at least one of the two chips laterally overlaps the second of the two chips, at least in part, with a projection. In other words, one of the two chips has a lateral projection designed to overlap the second chip. Such a lateral overlap achieves greater stability of the carrier wafer-chip assembly and the assemblies. For details regarding such an approach, reference is made to DE 10 2023 204 321, which is hereby fully incorporated into the present application as a component thereof.

[0019] According to a second aspect of the invention, a MEMS assembly is proposed which is manufactured by a method as described above. Advantages of the invention

[0020] The invention enables the manufacturing process of MEMS assemblies for MEMS-based devices to be designed to achieve the highest possible yield. More specifically, an approach is proposed that is based on the separate production of MEMS component parts with different yields. This approach can be used when such assemblies consist of a plurality of MEMS components and an SOI-based wafer forms the basis for one of the components of the MEMS assemblies.

[0021] The invention also offers further advantages: The approach enables parallelized production of the underlying wafers for the components of the MEMS assemblies, thereby reducing overall throughput time. Furthermore, handling during the separation of the MEMS chips is simplified.

[0022] A further important advantage is that the separate production of the MEMS components according to the invention allows MEMS chips with different specifications and / or functionalities to be used. Such a procedure is particularly advantageous when large MEMS assemblies (i.e. with a large number of MEMS components, for example with 20x20 or 24x24 MEMS components), such as micromirror arrays, are to be constructed on the basis of small MEMS chips (i.e. chips for a few MEMS components, for example in a 2x2 or 3x3 arrangement). The MEMS chip variants can be produced in separate wafer process streams, which in turn offers greater flexibility in chip selection. To enable simple quality control, backside contacts can be integrated into the MEMS chips to be manufactured, which enable preselection through electrical measurements.

[0023] The invention can be used in particular in the production of large micromirror arrays, which typically require a high optical fill factor. Short description of the drawings

[0024] Embodiments of the invention are explained in more detail with reference to the drawings and the following description.

[0025] They show: Fig. 1A to 1J are schematic cross-sectional views illustrating a method according to the invention for manufacturing MEMS assemblies; Fig. 2 schematic cross-sectional view to explain a second method according to the invention for producing MEMS assemblies; Fig. 3A to 3E are schematic cross-sectional views illustrating a third method according to the invention for manufacturing MEMS assemblies; and Fig. 4 shows in schematic form as a flow chart an exemplary method according to the invention for producing MEMS assemblies. Embodiments of the invention

[0026] In the following description of the embodiments of the invention, identical or similar elements are designated by the same reference numerals, whereby a repeated description of these elements is omitted in individual cases. The figures only schematically illustrate the subject matter of the invention.

[0027] The Fig. 1A to 1J show schematic cross-sectional views to explain a method according to the invention for manufacturing MEMS assemblies.

[0028] Fig. 1A shows a section of a functional wafer 120 with a plurality of chips 124 with first MEMS structures 126. These first MEMS structures 126 can be, for example, structures for actuators for micromirrors. The functional wafer 120 is provided with first MEMS structures 126 in a defined chip size, including a bond metallization 130, which, as described below, will serve for attachment to elements of a second wafer. The distance between the individual chips 124 is not critical and can be freely selected, as long as singulation of the chips 124 remains possible.

[0029] Shown in Fig. 1B shows the result of such a singulation of the functional wafer 120 into the chips 124, for example, by means of plasma and / or gas-phase etching. This singulation is typically accompanied, as shown, by an at least partial removal of the regions 128 of the functional wafer 120 laterally surrounding the chips by the etching process. Before the corresponding etching process, the functional wafer 120 can be Fig. 1B shown, can be applied to a suitable first carrier element 102 such as an adhesive film in order to hold, i.e. fix, the chips 124 at least temporarily in a fixed position on a surface 103 of the first carrier element 102 even after singulation.

[0030] Then, as in Fig. 1C, the separated chips 124 are removed from the functional wafer 120. A pick-and-place method can be used for this purpose, for which corresponding surfaces can be provided on the top side of the chips 124 for gripping by a pick-and-place robot. Fig. 1C, the direction of removal is indicated by arrows 104, as are positions 106 of possible surfaces for gripping the chips 124.

[0031] The isolated chips 124 are now as in Fig. 1D in sub-figure (i) is connected to a surface 141 of a functional layer 142 of an SOI-based wafer 140, wherein the SOI-based wafer 140 further comprises a handle wafer 146 and a silicon dioxide layer 144 (BOX) arranged between the handle wafer 146 and the functional layer 142. The functional layer 142 comprises second MEMS structures 143. In the example shown, the chips 124 are moved toward the surface 141, exemplified by an arrow 145 for a chip 125 that is about to be placed. It should be noted that preferably the first MEMS structures 126 of a single chip 124 in combination with a suitable number of second MEMS structures 143 of the functional layer 142 of the SOI-based wafer 140 can together result in a plurality of identical MEMS components per chip 124.In order to keep the figures general, individual MEMS components per chip 124 have not been identified; instead, only continuous hatched areas for the first and second MEMS structures 126, 143 are shown.

[0032] In the figure shown in sub-figure (i) of the Fig. In the example shown in Figure 1D, the chips 124 were rotated 180° around an axis parallel to the surface 141 before being connected to the SOI-based wafer 140. The SOI-based wafer 140 also has bond metallizations 132, which are connected to the bond metallizations 130 of the chips 124 for connection to the latter and form bond connections 131. Partial figure (ii) of the Fig. 1D shows a top view of an SOI-based wafer 140 with a functional layer 142, onto which chips 124 have already been applied in certain positions. Also shown, in particular, is the row of three chips 124 already shown in the partial figure, as well as regions with second MEMS structures 143, whose positions are not yet occupied by chips 124. The wafer 140 shown in this partial figure (ii), like the wafers in the other figures, is only shown in detail, whereby regions with second MEMS structures 143 and positions with already placed chips 124 can continue to the sides, which is indicated in the partial figure by the points 148.

[0033] An important advantage of this approach is that, using suitable testing methods, the chips 124 can be selected before being connected to the SOI-based wafer 140, in order to use only those chips 124 that meet defined criteria. This is particularly helpful when the first MEMS structures 126 of the chips 124 are significantly more difficult to manufacture than the second MEMS structures of the SOI-based wafer.

[0034] Then, as in Fig. 1E, a carrier wafer-chip composite 105 is produced for stabilization by connecting a surface 151 of a carrier wafer 150 to the chips 124 such that the functional layer 142 and the carrier wafer 150 are arranged on opposite sides 121, 122 of the chips 124.

[0035] Now, the carrier wafer-chip assembly 105 can be rotated by 180° about an axis parallel to the surface 141 of the functional layer 142, and then the handle wafer 146 and the silicon dioxide layer 144 can be removed. The result is shown in Fig. 1F. Before such a rotation of the carrier wafer-chip assembly 105, the carrier wafer 150 can be re-thinned.

[0036] This simplifies the subsequent step of exposing the first and second MEMS structures 126, 143, for example by silicon sacrificial layer etching. Fig. 1G shows the carrier wafer-chip assembly 105 after such a step of isolating, wherein the isolating first MEMS structures 126' and the isolating second MEMS structures 143' have been hatched with a different hatching than the first MEMS structures 126 and the second MEMS structures 143 of the previous figures for clarity.

[0037] The subsequent dicing into individual MEMS assemblies 100, each comprising several chips 124, is carried out by means of suitable dicing methods, for example by stealth dicing as in the Fig. 1H to 1J. For this purpose, the carrier wafer-chip assembly 105 is applied to a second carrier element 160, which in the present exemplary case is an adhesive sawing foil. After severing the carrier wafer 150 laterally of the MEMS assembly 100 to be removed, represented by the lightning-shaped symbols 156, the sawing foil 160 is stretched. This is shown in FIG. Fig. 1I indicated by the arrows 154 and the lateral distance between the MEMS assembly 100 and the remainder 152 of the carrier wafer 150 compared to Fig. 1H. Finally, the MEMS assembly 100 can be assembled as shown in Fig. 1J, the chip can be removed from the sawing foil 160 (in the direction of arrows 180) and thus removed from the separated carrier wafer-chip assembly 105 and then further processed. For easy further processing, support elements 190 can be pushed from the sides, ie, in the direction of the arrows 192, under the removed carrier wafer-chip assembly 105.

[0038] Fig. 2 now shows a schematic cross-sectional view to explain a second method according to the invention for producing MEMS assemblies 100. This method differs from the method according to the Fig. 1A to 1J merely in that the chips 124 are designed such that, after the functional wafer 120 has been singulated, they can be arranged next to one another in such a way that, when two chips 124 are arranged next to one another, one of the two chips 124 laterally overlaps the other of the two chips 124 at least in some areas. As in Fig. 2, each of the chips 124 has a lateral projection 127 which is designed to overlap the respective chip 124 arranged on the right side.

[0039] The Fig. 3A to 3E now show schematic cross-sectional views to explain a third method according to the invention for producing MEMS assemblies 100. In contrast to the previously shown embodiments, a passivation layer 110 with recesses is a component of the functional wafer 120, wherein the passivation layer 110 is located on the side of the functional wafer 120 facing away from the bonding metallization 130, i.e., the rear side. In the recesses, as shown in Fig. 3A, metal contacts 112, which are also referred to as backside contacts 112, can be produced as part of a backside metallization and can be used to perform wafer-level tests. In Fig. 3A, contact pins 114 for performing such wafer-level tests are shown purely as examples. Based on the results of the wafer-level tests, the chips 124 to be further processed can be selected.

[0040] The Fig. The process steps shown in Figures 3B to 3E are identical to those shown in Fig. 1B to 1G, wherein, however, the production of the carrier wafer-chip composite 105 is followed by exposing the metal contacts 112 by forming recesses 158 in the carrier wafer 150.

[0041] Fig. 4 shows in schematic form as a flow chart 400 an exemplary inventive method for manufacturing MEMS assemblies 100.

[0042] First, a functional wafer 120 with a plurality of chips 124 having first MEMS structures 126 is provided 410. This functional wafer 120 is separated into chips 124 in step 420. Subsequently, the chips 124 can be removed from the functional wafer 120 in step 430.

[0043] Independently of these steps, an SOI-based wafer 140 is provided 440, wherein the SOI-based wafer 140 has a functional layer 142 with second MEMS structures 143, a handle wafer 146 and a silicon dioxide layer 144 arranged between the handle wafer 146 and the functional layer 142.

[0044] By connecting at least a portion of the chips 124 removed from the functional wafer 120 to a surface 141 of the functional layer 142 and a surface 151 of a carrier wafer 150 such that the functional layer 142 and the carrier wafer 150 are arranged on opposite sides 121, 122 of the chips 124, a carrier wafer-chip composite 105 is created 450.

[0045] In the subsequent steps, the handle wafer 146 and the silicon dioxide layer 144 are removed 460 after the carrier wafer-chip assembly 105 has been produced 450, and then the first MEMS structures 126 and the second MEMS structures 143 of the carrier wafer-chip assembly 105 are exposed 470.

[0046] Before the subsequent singulation 480 of the carrier wafer-chip assembly 105, the carrier wafer-chip assembly 105 can be applied 475 to a second carrier element 160, such as a dicing foil, such that the carrier wafer 150 is brought into contact only with the second carrier element 160. The singulation 480 of the carrier wafer-chip assembly 105 takes place after the separation 470 into a plurality of MEMS assemblies 100 such that each MEMS assembly 100 has a plurality of chips 124. Finally, the MEMS assemblies 100 are removed from the singulated carrier wafer-chip assembly 105 in step 490.

[0047] The invention is not limited to the embodiments described here and the aspects highlighted therein. Rather, numerous modifications are possible within the scope of the claims, which are within the scope of one skilled in the art. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] DE 10 2013 208 446 A1

[0002] EP 0 877 272 A1

[0002] WO 2010 / 049076 A2

[0002] DE 10 2006 032 195 A1

[0002] DE 10 2009 029 202 A1

[0002] DE 10 2015 206 996 A1

[0002] DE 10 2023 204 321

[0018]

Claims

[1] A method for manufacturing MEMS assemblies (100) comprising the following steps: a. Providing (410) a functional wafer (120) having a plurality of chips (124) with first MEMS structures (126); b. Providing (440) an SOI-based wafer (140), wherein the SOI-based wafer (140) has a functional layer (142) with second MEMS structures (143), a handle wafer (146) and a silicon dioxide layer (144) arranged between the handle wafer (146) and the functional layer (142); c. separating (420) the functional wafer (120) into the chips (124); d. removing (430) the separated chips (124) from the functional wafer (120); e. producing (450) a carrier wafer-chip composite (105) by connecting at least a portion of the removed chips (124) to a surface (141) of the functional layer (142) and a surface (151) of a carrier wafer (150) such that the functional layer (142) and the carrier wafer (150) are arranged on opposite sides (121, 122) of the chips (124); f. removing (460) the handle wafer (146) and the silicon dioxide layer (144) after producing (450) the carrier wafer-chip composite (105); g. exposing (470) the first MEMS structures (126) and the second MEMS structures (143) of the carrier wafer-chip assembly (105) after removing (460) the handle wafer (146) and the silicon dioxide layer (144); h. singulating (480) the carrier wafer-chip assembly (105) after the release (470) into a plurality of MEMS assemblies (100) such that each MEMS assembly (100) has a plurality of chips (124); and i. Removing (490) the MEMS assemblies (100) from the separated carrier wafer-chip assembly (105). [2] Method according to claim 1, wherein prior to the singulation (420) of the functional wafer (120), the functional wafer (120) is applied to a first carrier element (102), wherein the first carrier element (102) is designed such that after the singulation (420) of the functional wafer (120), the singulated chips (124) are fixed on the first carrier element (102). [3] Method according to claim 1 or 2, wherein the first MEMS structures (126) and / or the second MEMS structures (143) comprise or are structures for one or more MEMS components such as MEMS sensors and / or MEMS actuators, for example MEMS inertial sensors, MEMS pressure sensors, MEMS microphones, MEMS micromirrors and / or MEMS resonators. [4] Method according to one of the preceding claims, wherein the first MEMS structures (126) comprise or are structures for actuators for MEMS micromirrors and the second MEMS structures (143) comprise or are structures for mirror plates for MEMS micromirrors, wherein the MEMS assemblies (100) are formed by the singulation (480) of the carrier wafer-chip assembly (105) such that each MEMS assembly (100) has a plurality of MEMS micromirrors, wherein each of the MEMS micromirrors has one of the actuators and one of the mirror plates. [5] Method according to one of the preceding claims, wherein the carrier wafer (150) is re-thinned before removing (460) the handle wafer (146). [6] Method according to one of the preceding claims, wherein, before the singulation (480) of the carrier wafer-chip composite (105), the carrier wafer-chip composite (105) is applied (475) to a second carrier element (160) in such a way that the carrier wafer (150) is brought into contact with the second carrier element (160) alone, wherein the second carrier element (160) is designed in such a way that after the singulation (480) of the carrier wafer-chip composite (105), the MEMS assemblies (100) are fixed on the second carrier element (160). [7] Method according to one of the preceding claims, wherein prior to the singulation (420) of the functional wafer (120) a wafer-level test is carried out for testing one or more of the chips (124) and preferably a selection of the tested chips (124) for the production (450) of the carrier wafer-chip assembly (105) is carried out on the basis of the wafer-level test. [8] Method according to one of the preceding claims, wherein the chips (124) of the functional wafer (120) have metal contacts (112). [9] Method according to claim 8, wherein after producing the carrier wafer-chip composite (105), the metal contacts (112) of the chips (124) are exposed by generating recesses (158) in the carrier wafer (150). [10] Method according to one of the preceding claims, wherein the chips (124) are shaped such that after the separation (420) of the functional wafer (120) two of the chips (124) can be arranged next to one another such that at least one of the two chips (124) laterally overlaps the second of the two chips (124) at least in some areas with a projection (127). [11] MEMS assembly (100) manufactured by a method according to any one of the preceding claims.

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