Inverter, method and device for operating an inverter

Abstract

An inverter (100) comprises a first supply voltage terminal (105), a second supply voltage terminal (110), a switching unit (115), an output terminal (120), a fault detection unit (122) comprising at least a first fault detection device (125) and / or a second fault detection device (130), and a control unit (135). The first fault detection device (125) is configured to detect a short circuit in at least a first switch (T1) and / or a second switch (T2) and / or a fifth switch (T5) as a first fault condition. The second fault detection device (130) is configured to detect a short circuit in a third switch (T3) and / or a fourth switch (T4) and / or a sixth switch (T6) as a second fault condition.The control device (135) is configured to close the sixth switch (T6) and the third switch (T3) and open the fourth switch (T4) depending on a detected first fault condition and / or to close the fifth switch (T5) and the second switch (T2) and open the first switch (T1) depending on a detected second fault condition.

Description

The present invention relates to an inverter and to a method and apparatus for operating an inverter.Conventional three-phase two-level inverters start operating as soon as a transistor fails. Three-level three-phase inverters may have higher redundancy and may treat faults of transistors at certain locations.Against this background, the present invention provides an improved inverter, an improved method and an improved apparatus for operating an inverter according to the main claims. Advantageous embodiments are evident from the dependent claims and the following description.The advantages which can be achieved with the approach presented here consist in particular in the fact that an inverter is created which can reliably detect a short circuit in one of the switches, for example, and can enable operation of the inverter, despite a short circuit, at least with reduced power.An inverter comprises a first supply voltage connection, a second supply voltage connection, a switch unit, an output connection, a fault determination unit having a first fault detection device and / or a second fault detection device, and a control device. The switch unit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a sixth switch. The first switch, the second switch, the third switch and the fourth switch are connected in series between the first supply voltage terminal and the second supply voltage terminal. The fifth switch and the sixth switch are connected in series and in parallel with the second switch and the third switch. The output terminal represents a tap point between the second switch and the third switch. The first fault detection device is connected between the first supply voltage terminal and the output terminal. The first fault detection device is designed to detect a short circuit in at least the first switch and additionally or alternatively the second switch and additionally or alternatively the fifth switch as a first fault state. The second fault detection device is connected between the second supply voltage terminal and the output terminal. The second fault detection device is designed to detect a short circuit in the third switch and / or the fourth switch and additionally or alternatively the sixth switch as a second fault state. The control device is configured to close the sixth switch and the third switch as a function of a detected first fault state and to open the fourth switch (and in particular additionally also the first, second and fifth switches) and additionally or alternatively to close the fifth switch and the second switch as a function of a detected second fault state and to open the first switch (and in particular additionally also the third, fourth and sixth switches).The inverter can be an active neutral point clamped inverter, also called an active neutral point clamped inverter, for short ANPC inverter. The inverter may convert DC voltage to AC voltage. The first switch, the second switch and the fifth switch can be embodied as high-side switches. The third switch, the fourth switch and the sixth switch can be embodied as low-side switches. The switches can also be configured as transistors, especially as high-power transistors for switching powers above 100 watts, for example. In the event of a short circuit in at least one of the switches, the inverter can nevertheless continue to be operated without the inverter or at least further components of the inverter being damaged in the process. For this purpose, at least one of the fault detection devices can detect the at least one short circuit as a fault state. The fault state can subsequently be forwarded to the control device. The control device can then actuate a corresponding switching state depending on the detected fault state in order to be able to continue to operate the inverter despite a short circuit.The approach presented here can therefore also be understood as a detection system for fault isolation and further operation in the inverter with parallelized switches.With the approach presented here, active neutral point clamped inverters can continue their operation if one of their switches, which can also be referred to as component transistors, has a short circuit as a fault. To define safe operating vectors after a fault, normally the faulty switch and its fault type is to be properly identified.Assuming that switches may only fail in the short-circuit mode, a simplified fault detection system may be enabled, where only a determination is made as to whether the faulty switch is on the high side or the low side of the inverter phase. The fault detection system may enable a simplified strategy for determining the safe switching state, which may allow the operation of the inverter to be maintained.In other words, the use presented here can enable simple fault detection on the assumption that switches can only fail as a short circuit. The inverter can continue to be operated with reduced maximum power. In this way, increased system reliability for autonomous driving applications may be enabled.The approach presented here can create complete detection electronics which can evaluate each switch individually.The inverter may include a first capacitance and a second capacitance that may be connected in series between the first supply voltage terminal and the second supply voltage terminal. A capacitance tap point between the capacitances may be electrically conductively connected to a tap point between the fifth switch and the sixth switch. The capacitances can be embodied as capacitors. Capacitors can have a long life and have good temperature resistance.The control device can be configured to open the first switch, the second switch and the fifth switch in the first fault state. Additionally or alternatively, the control device can be configured to open the third switch, the fourth switch and the sixth switch in the detected second fault state. In this way, despite a fault state, a safe and / or reliable operation of the inverter can be made possible. Damage to the inverter can be avoided.The switches can be configured as transistors and / or as semiconductor components. Transistors can be manufactured cost-effectively and in large numbers.The switches can at least partially each have a plurality of parallel-connected sub-switches, in particular wherein the sub-switches can be of the same design. This allows higher powers to be switched using simple technical means.The first fault detection device and additionally or alternatively the second fault detection device can be designed to detect the first fault state and additionally or alternatively the second fault state by means of desaturation detection and additionally or alternatively by means of a comparison of a voltage applied to one of the switches. Desaturation detection may be very robust with respect to false detections.The first supply voltage terminal may be configured to be supplied with a positive voltage with respect to the output terminal. Additionally or alternatively, the second supply voltage terminal may be configured to be supplied with a negative voltage with respect to the output terminal.A method for operating an inverter comprises a step of detecting and a step of driving. In the detection step, the first fault state is detected using the first fault detection device and, additionally or alternatively, the second fault state is detected using the second fault detection device. In the step of controlling, the switches are controlled in such a way that, depending on the detected first fault state, the sixth switch and the third switch are closed and the fourth switch is opened. Additionally or alternatively, the fifth switch and the second switch are closed and the first switch is opened depending on a detected second fault state. The advantages of the approach described here can also be realized very efficiently by such an embodimentThe approach presented here furthermore creates a control device which is designed to carry out, actuate or implement the steps of a variant of a method presented here in corresponding devices. This embodiment variant of the invention in the form of a control device also enables the object on which the invention is based to be achieved quickly and efficiently.A control device can be an electrical device which processes electrical signals, for example sensor signals, and outputs control signals as a function thereof. The control device can have one or more suitable interfaces, which can be designed as hardware and / or software. In a hardware configuration, the interfaces can be part of an integrated circuit, for example, in which functions of the device are implemented. The interfaces can also be dedicated, integrated circuits or consist at least partially of discrete components. In the case of a software configuration, the interfaces can be software modules which are present, for example, on a microcontroller in addition to other software modules.A computer program product having program code which can be stored on a machine-readable carrier such as a semiconductor memory, a hard disk memory or an optical memory and is used for carrying out the method according to one of the embodiments described above when the program is executed on a computer or a control device is also advantageous.The invention is explained in more detail by way of example with reference to the appended drawings. The following are shown: FIG. 1 is a circuit diagram of an embodiment of an inverter; FIG. 2 shows an illustration of a switch for an exemplary embodiment of an inverter; FIG. 3 shows a tabular representation of switching states for an exemplary embodiment of an inverter; FIG. 4 shows a flow diagram of an exemplary embodiment of a method for operating an inverter; and FIG. 5 shows a block diagram of an exemplary embodiment of a control device for operating an inverter.In the following description of preferred exemplary embodiments of the present invention, the same or similar reference numerals are used for the elements shown in the different figures and acting in a similar manner, wherein a repeated description of these elements is omitted.FIG. 1 shows a circuit diagram of an embodiment of an inverter 100. The inverter 100 is designed, for example, to convert DC voltage into AC voltage. In other words, FIG. 1 shows a scheme for error detection.The inverter 100 has a first supply voltage terminal 105, a second supply voltage terminal 110, a switch unit 115, an output terminal 120, a fault determination unit 122, having at least one first fault detection device 125 and / or one second fault detection device 130, and a control device 135. Optionally, the inverter 100 comprises a first capacitance 140 and a second capacitance 145.According to an embodiment, the first supply voltage terminal 105 is configured to be supplied with a positive voltage, wherein the second supply voltage terminal 110 is configured to be supplied with a negative voltage. The capacitors 140, 145 are connected in series, merely by way of example, wherein the first capacitor 140 is connected, for example, between the first supply voltage connection 105 and a capacitor tap point 150. The second capacitance 145 is connected between the second supply voltage terminal 110 and the capacitance tap point 150. The capacitances 140, 145 are designed merely as capacitors by way of example. The capacitance tap point 150 is connected to the switch unit 115, for example.The switch unit 115 includes a first switch T 1, a second switch T 2, a third switch T 3, a fourth switch T 4, a fifth switch T 5, and a sixth switch T 6. According to one exemplary embodiment, the switches T 1, T 2, T 3, T 4, T 5, T 6 are designed as transistors. Additionally or alternatively, the switches T 1, T 2, T 3, T 4, T 5, T 6 comprise a plurality of part switches, as is shown and described, for example, in FIG. 2.The first switch T 1, the second switch T 2, the third switch T 3 and the fourth switch T 4 are connected in series between the first supply voltage terminal 105 and the second supply voltage terminal 110.The fifth switch T 5 and the sixth switch T 6 are connected in series and in parallel with the second switch T 2 and the third switch T 3 connected in series.According to one exemplary embodiment, a tap point 155 is arranged between the fifth switch T 5 and the sixth switch T 6, via which tap point the capacitance tap point 150 is electrically conductively connected to the fifth switch T 5 and the sixth switch T 6.The first switch, the second switch and the fifth switch of the switch unit 115 are designed, for example, as high-side switches, wherein the third switch, the fourth switch and the sixth switch are designed as low-side switches.The output terminal 120 is disposed between the second switch T 2 and the third switch T 3.The first fault detection device 125 of the fault determination unit 122 is connected between the first supply voltage terminal 105 and the output terminal 120 and can also be referred to as fault detection HS. The first fault detection device 125 is designed to detect a short circuit in at least one of the switches T 1, T 2, T 5 as a first fault state. For this purpose, the first fault detection device 125 is connected to the switches T 1, T 2, T 5, for example, via a plurality of tap points.The second fault detection device 130 of the fault determination unit 122 is connected between the second supply voltage terminal 110 and the output terminal 120 and can also be referred to as fault detection LS. The second fault detection device 130 is designed to detect a short circuit in at least one of the switches T 3, T 4, T 6 as a second fault state. For this purpose, the second fault detection device 130 is connected to the switches T 3, T 4, T 6, for example, via a plurality of tap points.The control device 135 is connected to the first fault detection device 125 and the second fault detection device 130 and is designed to close or open at least one of the switches of the switch unit 115 depending on the fault states. The control device 135 can also be referred to as a control unit.In order to enable a detailed description of the mode of operation of the approach presented here, a brief representation of the individual switching states of the transistors is reproduced. Only those transistors which are closed are mentioned below in each switching state. All other transistors should then be open.In normal (without fault) operation, the inverter presented here has four valid switching states:P: T1, T2 and T6 are closed0H: T2 and T5 are closed0L: T3 and T6 are closedN: T3, T4 and T5 are closedAs soon as a fault occurs, the switching states P and N should no longer be activated. Whether 0H or 0L should be activated depends on whether the fault would be detected at the HS or at the LS. If an HS fault is detected, the state 0L would have to be activated. If an LS fault is detected, the state 0H would have to be activated.The first fault detection device 125 detects the first fault state if a short circuit occurs in at least one of the switches T 1, T 2, T 5. The control device 135 then controls the switch unit 115 in a first switching state. In the first switching state, the controller 135 closes the third switch T 3 and the sixth switch T 6. Additionally or alternatively, the controller 135 opens the fourth switch T 4. According to an embodiment, the controller 135 then opens the first switch T 1, the second switch T 2, and the fifth switch T 5.The second fault detection device 130 detects the second fault state if a short circuit occurs in at least one of the switches T 3, T 4, T 6. The control device 135 then controls the switch unit 115 in a second switching state. In the second switching state, the controller 135 closes the fifth switch T 5 and the second switch T 2. Additionally or alternatively, the controller 135 opens the first switch T 1. According to an embodiment, the controller 135 then opens the third switch T 3, the fourth switch T 4 and the sixth switch T 6.According to one exemplary embodiment, the first fault state and / or second fault state is detected by the first fault detection device 125 and / or the second fault detection device 130 by means of desaturation detection and / or by means of comparison of a voltage applied to one of the switches T 1, T 2, T 3, T 4, T 5, T 6.The approach presented here enables reliable operation of the inverter 100 despite a short circuit.In other words, the inverter 100 is configured as an ANPC inverter, i.e. as an active neutral point clamped inverter, and has six switches T 1, T 2, T 3, T 4, T 5, T 6, which can also be referred to as topological transistors.The DC link is divided into three potentials HV+, 0 and HV-. The inverter 100 enables the use of 650V switches in an 800V system.The switches T 1, T 2, T 3, T 4, T 5, T 6, which may also be referred to as transistors, may fail and behave either as an open circuit or as a short circuit. These errors reduce switching states, as illustrated and described for example in FIG. 3. The switching states may be generated with the inverter 100.In order to keep the inverter 100 in operation, it is sufficient to know whether a short circuit is present in the high-side switches T 1, T 2, T 5 or in the low-side switches T 3, T 4, T 6.Short circuit failures and open circuit failures are not likely to occur.If parallel-connected switches are now considered, short-circuit faults are dominant. As long as a physical switch is short-circuited, the entire topological switch is short-circuited. No idle errors are prevalent. When a physical switch is open, the topological switch may continue to operate. Short circuits are thus becoming increasingly important in parallel-connected transistorsOnly errors on the high side (HS) or low side (LS) are detected. It is no longer necessary or relevant to know exactly which switch is defective. The recognition itself can be implemented as desired, for example desaturation recognition and / or comparison of input voltages and output voltages, etc.FIG. 2 shows an illustration of a switch T 1 for an exemplary embodiment of an inverter. The first switch T 1 is similar or corresponds to the switch from FIG. 1.According to one exemplary embodiment, the first switch T1 has a plurality of parallel-connected sub-switches T1.1, T1.2, T1.3. The partial switches T 1.1, T 1.2, T 1.3 are embodied in the same way merely by way of example.In other words, each topological switch is implementable in hardware as a plurality of physical switches connected in parallel.FIG. 3 shows a tabular representation of switching states for an exemplary embodiment of an inverter. The switching states correspond to the switching states described in FIG. 1.If a short-circuit fault occurs in T 1, the switching states P, 0H or N should not be activated, since these should lead to damage or destruction of the inverter. Only 0L remains as the sole valid state, which is to be activated.It can also be seen that for all transistors of the HS, i.e. T 1, T 2 and T 5, exactly the same reaction state remains, i.e. 0L. In the event of a short circuit in one of the switches T 1, T 2, T 3, T 4, T 5, T 6, either the first switching state 0L or the second switching state 0H is controlled by the control device in order to operate the inverter. Depending on the location of the short circuit, i.e. high side or low side, either the first switching state 0L or the second switching state 0H is actuated.In other words, in the third switching state P, the first switch T 1, the second switch T 2 and the sixth switch T 6 are active and the potential HV+ is present at the output. In the second switching state 0H, the second switch T 2 and the fifth switch T 5 are active and the potential 0 is present at the output. In the first switching state 0L, the third switch T 3 and the sixth switch T 6 are active and the potential 0 is present at the output. In the fourth switching state N, the third switch T3, the fourth switch T4 and the fifth switch T5 are active and the potential HV- is present at the output.In other words, FIG. 3 shows an error table for error detection with parallelization. If an error is detected by T1, T2 or T5, the switching state 0L is to be activated. In other words, if a short circuit is detected at, for example, T1, T2, T4, T5should be opened and T3and T6should be closed.In a two-level topology, an occurring fault on a transistor embodied in column 300 may be detected as a switch of a side defined in column 305 (HS=high side=supply voltage side; LS=low side=ground side) by making a measurement of the signals of that particular transistor, e.g., when switch T 1 has a short circuit, this may be detected by measuring the voltages of T 1. This is not the case with an ANPC Topology DÜberdefiningie and with the development method presented here. The fault of a particular transistor can be detected only by measuring one or two other transistors, for example, if the switch T2 has a short circuit fault, it is detected not by measuring T2 itself, but by measuring T3 and T4.As explained above, the response logic depends only on the position of the transistor and not on the transistor itself.a short circuit to HS (either T1, T2 or T5), response: activation state OL (entered in column 315 of FIG. 3)a short circuit to LS (either T3, T4 or T6, response: activation of the OH stateIn the approach presented here, only faults on the high side or low side can be detected. It is no longer necessary or relevant to know exactly which switch is defective. The detection itself can be implemented as desired, for example by means of desaturation detection (entered in column 310 of FIG. 3 ) and / or by means of a comparison of input voltages and output voltages, etc.FIG. 4 shows a flow diagram of an exemplary embodiment of a method 400 for operating an inverter. The inverter thereby resembles or corresponds to the inverter from one of the figures described above.The method 400 comprises a step 405 of detecting and a step 410 of driving.In the detection step 405, the first fault state is detected using the first fault detection device and, additionally or alternatively, the second fault state is detected using the second fault detection device of the fault identification unit. In step 410 of the actuation, the switches are actuated in such a way that, depending on the detected first fault state, the sixth switch and the third switch are closed and the fourth switch is opened. Additionally or alternatively, the fifth switch and the second switch are closed and the first switch is opened depending on a detected second fault state.FIG. 5 shows a block diagram of an exemplary embodiment of a control device 500 for operating an inverter. The control device 500 is designed to control the method from FIG. 4 or a similar method.For this purpose, the control device 500 has a unit 505 for detection and a unit 510 for actuation.The unit 505 for detecting is configured to detect the first fault state using the first fault detection device and additionally or alternatively the second fault state using the second fault detection device.The control unit 510 is designed to control the switches in such a way that, depending on the detected first fault state, the sixth switch and the third switch are closed and the fourth switch is opened. Additionally or alternatively, in the unit 510 for driving, the fifth switch and the second switch are closed and the first switch is opened depending on a detected second fault state.The exemplary embodiments described and shown in the figures are chosen only by way of example. Different exemplary embodiments can be combined with one another completely or with respect to individual features. An exemplary embodiment can also be supplemented by features of a further exemplary embodiment.Furthermore, method steps according to the invention can be repeated and carried out in a sequence other than that described.If an embodiment includes an "and / or" combination between a first feature and a second feature, this can be read such that the embodiment has both the first feature and the second feature according to one embodiment and either only the first feature or only the second feature according to a further embodiment.Reference numerals denote reference numerals100 Inverter 105 First supply voltage terminal 110 Second supply voltage terminal 115 Switch unit 120 Output terminal 122 Fault identification unit 125 First fault detection device 130 Second fault detection device 135 Control device 140 First capacitance 145 Second capacitance 150 Capacitance tap point 155 Tap point 300 First column 305 Second column 310 Third column 315 Fourth column 400 Method for operating an inverter 405 Step of detecting 410 Step of driving 500 Control device for operating an inverter 505 Unit for detecting 510 Unit for driving T 1 First switch T 2 Second switch T 3 Third switch T 4 Fourth switch T 5 Fifth switch T 6 Sixth switch 0L First switching state 0H Second switching state P Third switching state N Fourth switching state

Claims

Inverter (100) comprising the following features: a first supply voltage terminal (105) and a second supply voltage terminal (110); a switch unit (115), the switch unit (115) comprising a first switch (T1), a second switch (T2), a third switch (T3), a fourth switch (T4), a fifth switch (T5) and a sixth switch (T6), wherein the first switch (T1), the second switch (T2), the third switch (T3) and the fourth switch (T4) are connected in series between the first supply voltage terminal (105) and the second supply voltage terminal (110), wherein the fifth switch (T5) and the sixth switch (T6) are connected in series and in parallel to the second switch (T2) and the third switch (T3); an output terminal (120) constituting a tap point between the second switch (T 2) and the third switch (T 3); a fault determination unit (122) comprising at least one first fault detection device (125) connected between the first supply voltage terminal (105) and the output terminal (120), wherein the first fault detection device (125) is configured to detect a short circuit in at least the first switch (T1) and / or the second switch (T2) and / or the fifth switch (T5) as a first fault state, and / or further comprising a second fault detection device (130) connected between the second supply voltage terminal (110) and the output terminal (120), wherein the second fault detection device (130) is configured to detect a short circuit in the third switch (T3) and / or the fourth switch (T4) and / or the sixth switch (T6) as a second fault state; and a control device (135) which is designed to close the sixth switch (T6) and the third switch (T3) and to open the fourth switch (T4) as a function of a detected first fault state and / or to close the fifth switch (T5) and the second switch (T2) and to open the first switch (T1) as a function of a detected second fault state.The inverter (100) of claim 1, comprising a first capacitance (140) and a second capacitance (145) connected in series between the first supply voltage terminal (105) and the second supply voltage terminal (110), wherein a capacitance tap point (150) between the capacitances (140, 145) is electrically conductively connected to a tap point (155) between the fifth switch (T5) and the sixth switch (T6).Inverter (100) according to one of the preceding claims, wherein the control device (135) is configured to open the first switch (T1), the second switch (T2) and the fifth switch (T5) in the first fault state and / or to open the third switch (T3), the fourth switch (T4) and the sixth switch (T6) in the detected second fault state.Inverter (100) according to one of the preceding claims, wherein the switches (T1, T2, T3, T4, T5, T6) are formed as transistors and / or as semiconductor components.Inverter (100) according to one of the preceding claims, wherein the switches (T1, T2, T3, T4, T5, T6) each have at least partially a plurality of parallel-connected sub-switches, in particular wherein the sub-switches are of similar design.Inverter (100) according to one of the preceding claims, wherein the first fault detection device (125) and / or the second fault detection device (130) are designed to detect the first fault state and / or second fault state by means of desaturation detection and / or a comparison of a voltage applied to one of the switches (T1, T2, T3, T4, T5, T6).Inverter (100) according to one of the preceding claims, wherein the first supply voltage terminal (105) is configured to be supplied with a positive voltage with respect to the output terminal (120) and / or wherein the second supply voltage terminal (110) is configured to be supplied with a negative voltage with respect to the output terminal (120).Method (400) for operating an inverter (100) according to one of Claims 1 to 7, wherein the method (400) comprises the following steps: detecting (405) the first fault state using the first fault detection device (125) and / or the second fault state using the second fault detection device (130); and actuating (410) the switches (T1, T2, T3, T4, T5, T6) in such a way that, depending on the detected first fault state, the sixth switch (T6) and the third switch (T3) are closed and the fourth switch (T4) is opened and / or, depending on a detected second fault state, the fifth switch (T5) and the second switch (T2) is closed and the first switch (T1) is opened.Control device (500) which is designed to control and / or execute the steps (405, 410) of the method (400) according to Claim 8 in corresponding units (505, 510).A computer program product comprising program code for performing the method (400) of claim 8, when the computer program product is executed on a controller (500).

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