Method and device for an integrated circuit

Abstract

A method for a first integrated circuit arranged together with at least one further integrated circuit on a substrate, comprising: determining whether a setup operation should be performed with respect to a communication interface associated with the first integrated circuit and with the at least one further integrated circuit, and, if the determination results in the setup operation being performed with respect to the communication interface, performing the setup operation with respect to the communication interface.

Description

Prior ArtThe disclosure relates to at least one method for an integrated circuit.The disclosure further relates to at least one integrated circuit device.Disclosure of the InventionSome examples relate to a method, for example a computer-implemented method, for a first integrated circuit which is arranged together with at least one further integrated circuit on a substrate, comprising: determining whether a setup operation with respect to a communication interface which is associated with the first integrated circuit and with the at least one further integrated circuit is to be carried out, and, if the determination reveals that the setup operation with respect to the communication interface is to be carried out, carrying out the setup operation with respect to the communication interface. In some examples, this enables a flexible determination as to whether the device process is to be carried out and, if appropriate, a corresponding execution of the device process, for example without resetting the integrated circuit.In some examples, the method includes: if the determining results in the setup operation with respect to the communication interface not being performed, omitting the execution of the setup operation with respect to the communication interface.For example, the communication interface realizes a data connection at least between the first integrated circuit and the at least one further integrated circuit.For example, the communication interface is designed as a serial interface or as a parallel interface, or as a combination of at least one serial interface and at least one parallel interface.For example, the communication interface or individual data or signal lines of the communication interface are designed as differential lines or as non-differential (e.g. single-ended) lines.For example, the setup process can have an initialization, for example a reset of at least some, for example all, parameters, for example with respect to the communication interface.For example, the setup process can have training, i.e. e.g. determining optimum parameters, e.g. with respect to the communication interface.For example, the setup process can have the initialization and the training, e.g. jointly, e.g. in the sense of a setup and training process (e.g. "EuTV").For example, the setup operation may include synchronizing at least one component of the first integrated circuit, e.g., with at least one component of the at least one further integrated circuit.For example, the setup process can comprise transmitting at least one training sequence, which is known for example to both integrated circuits, e.g. from the first integrated circuit to the at least one further integrated circuit (and / or vice versa), which enables for example a synchronization and / or an adaptation of other parameters for the data transmission via the communication interface, see for example the training already mentioned above.In some examples, it is provided that the first integrated circuit and the at least one further integrated circuit are each configured as a chip, for example a chiplet, wherein, for example, the first integrated circuit and the at least one further integrated circuit form a multi-chiplet system. In some examples, the multi-chiplet system may also include more than two chips.In some examples, it is provided that the determination of at least one of the following elements comprises: a) determining whether at least the first integrated circuit is started (e.g. as a result of an activation of an electrical power supply or an enable signal or the like), or b) determining whether at least one, for example higher, protocol layer, for example a layer 2 according to the ISO / OSI layer model or higher, signals an error or a requirement for the execution of the setting process. The protocol layer may be associated with an application executing on the first integrated circuit, e.g., chiplet, for example. For example, this makes it possible for an application executed on the first chiplet to be able to initiate, for example in a targeted manner, a device of the communication interface, for example without the first chiplet or a system having the first chiplet having to be reset. As a result, the communication interface can be set up, e.g. re-set up (e.g. resynchronized), in a targeted manner, e.g. dynamically, e.g. during execution of the application on the first chiplet, for example in order to take account of detected transmission errors in data communication via the communication interface, in particular without the first chiplet having to be reset. Thus, in some examples, a context of the application executing on the first chiplet may be advantageously obtained, for example.In some examples, it is provided that the method comprises: initiating a synchronization process with respect to the communication interface, and, optionally, sending at least one training sequence via the communication interface, for example to the at least one further integrated circuit. For example, the at least one training sequence of the at least one further integrated circuit, e.g. a second chiplet, can be used for synchronization with the first chiplet.In some examples, it is provided that the initiation of the synchronization process with respect to the communication interface comprises at least one of the following elements: a) signaling the synchronization process to the at least one further integrated circuit, for example via an optionally present synchronization connection (e.g. control line), or b) applying a predefinable first potential, e.g. a ground potential, to a circuit node to which the first integrated circuit and the at least one further integrated circuit are connected.In some examples, it is provided that the method comprises at least one of the following elements: a) determining whether a training sequence is received via the communication interface, for example from the at least one further integrated circuit, or b) optionally, synchronizing by means of the received training sequence, or c) signaling a synchronization, for example successful or already existing, for example to the at least one further integrated circuit.In some examples, it is provided that the signaling of the, for example successful or already existing, synchronization comprises: applying a predefinable second potential, which is different from the first potential, to a or the circuit node to which the first integrated circuit and the at least one further integrated circuit are connected.In some examples, it is provided that the circuit node is connected by means of a resistor to a first reference potential, for example a reference potential corresponding to a positive operating voltage, wherein the application of the predeterminable first potential to the circuit node comprises a connection of the circuit node to a second reference potential, for example a reference potential corresponding to a ground potential, and / or wherein the application of the predeterminable second potential to the circuit node comprises a disconnection of the circuit node from the second reference potential, for example a reference potential corresponding to the ground potential. For example, the resistor thus operates as a pull-up resistor, which pulls the circuit node to the first reference potential, provided that the circuit node is not simultaneously connected to another potential, e.g., the ground potential, for example (e.g., by one of the integrated circuits).Some examples relate to an apparatus for carrying out the method according to the disclosure. For example, the device is integrated into the first integrated circuit and / or into the at least one further integrated circuit, or is arranged on the substrate, for example.Some examples relate to an integrated circuit, for example for a multi-chiplet system having a plurality of chiplets, having at least one device according to the disclosure, wherein for example the device or a functionality of the device is integrated into the integrated circuit.Some examples relate to a system, for example a multi-chiplet system, comprising at least one device according to the disclosure or at least one integrated circuit according to the disclosure. By way of example, the system may also include multiple integrated circuits in accordance with the disclosure.In some examples, it is provided that a circuit node to which the first integrated circuit and the at least one further integrated circuit are connected is arranged on the substrate.In some examples, it is provided that one, for example at least one, connecting line is provided, which connects respective terminals of the first integrated circuit and of the at least one further integrated circuit to the circuit node, wherein, for example, the connecting line is arranged at least partially on the substrate.Some examples relate to a use of the method according to the disclosure and / or the apparatus according to the disclosure and / or the integrated circuit according to the disclosure and / or the system according to the disclosure for at least one of the following elements: a) starting the communication interface, b) training at least one component associated with the communication interface, c) maximizing a bandwidth of the communication interface, d) minimizing an error rate, for example bit error rate of the communication interface, e) avoiding resetting or restarting of the integrated circuit, for example for synchronizing with respect to the communication interface, f) synchronizing with respect to the communication interface, g) providing synchronizing with respect to the communication interface as, for example, regular, operating state, h) enabling initiation of the setup operation with respect to the communication interface by the integrated circuit or a component of the integrated circuit or by another device.Further features, possible applications and advantages of the invention are evident from the following description of examples of the invention which are illustrated in the figures of the drawing. All features described or shown form the subject matter of the invention, either alone or in any combination, independently of their summary in the claims or their reference, and independently of their formulation or representation in the description or in the drawing.The drawing shows: FIG. 1 is a schematic simplified flow diagram, FIG. 2 is a schematic simplified block diagram, FIG. 3 is a schematic simplified flow diagram, FIG. 4 is a schematic simplified flow diagram, FIG. 5 is a schematic simplified block diagram, FIG. 6 is a schematic simplified block diagram, FIG. 7 schematically shows examples of uses.Some examples, FIGS. 1, 2, relate to a method, for example a computer-implemented method, for a first integrated circuit 110- 1 which is arranged together with at least one further integrated circuit 110- 2 on a substrate 120, comprising: determining 200 whether a setup operation EV with respect to a communication interface 130 which is associated with the first integrated circuit 110- 1 and with the at least one further integrated circuit 110- 2, for example allowing data communication between at least the two integrated circuits 110- 1, 110- 2, is to be carried out, and if the determination 200 reveals that the setup operation EV is to be carried out with respect to the communication interface 130, carrying out 202 the setup operation EV with respect to the communication interface 130. In some examples, this enables a flexible determination 200 as to whether the device operation EV is to be carried out and, if appropriate, a corresponding execution 202 of the device operation EV, for example without resetting the integrated circuit 110- 1.In some examples, FIG. 1, the method includes: if the determination 200 reveals that the setup process EV with respect to the communication interface 130 is not to be executed, omitting 204 the execution 202 of the setup process EV with respect to the communication interface 130.For example, the communication interface 130 (FIG. 2 ) realizes a data connection at least between the first integrated circuit 110- 1 and the at least one further integrated circuit 110- 2.For example, the communication interface 130 is designed as a serial interface or as a parallel interface, or as a combination of at least one serial interface and at least one parallel interface.For example, the communication interface 130 or individual data or signal lines (not shown) of the communication interface 130 are designed as differential lines or as non-differential (e.g. single-ended) lines.For example, the setup operation EV can have an initialization, for example a resetting of at least some, for example all, parameters, for example with respect to the communication interface 130.For example, the setup process EV can have training, i.e. e.g. a determination of optimum parameters, e.g. with respect to the communication interface 130.For example, the setup operation EV may include the initialization and the training.For example, the setup operation EV may include synchronizing at least one component of the first integrated circuit 110- 1, e.g., with at least one component of the at least one further integrated circuit 110- 2.For example, the setup process EV can comprise transmitting at least one training sequence known, for example, to both integrated circuits, e.g., from the first integrated circuit 110- 1 to the at least one further integrated circuit 110- 2 (and / or vice versa), which enables, for example, a synchronization and / or an adaptation of other parameters for the data transmission via the communication interface 130.In some examples, FIG. 2, it is provided that the first integrated circuit 110- 1 and the at least one further integrated circuit 110- 2 are each configured as a chip, for example chiplet, wherein, for example, the first integrated circuit 110- 1 and the at least one further integrated circuit 110- 2 form a multi-chiplet system 1000. In some examples, the multi-chiplet system 1000 may also include more than two chiplets 110- 1, 110- 2.In some examples, FIG. 1, it is provided that the determination 200 comprises at least one of the following elements: a) determining 200 a, whether at least the first integrated circuit 110- 1 is started (e.g. as a result of an activation of an electrical power supply or an enable signal or the like), or b) determining 200 b, whether at least one, for example higher, protocol layer S (FIG. 2 ), for example a layer 2 according to the ISO / OSI layer model or higher (e.g. a layer of the layers 3 to 7), signals an error or a requirement for the execution of the setup process EV. The protocol layer PS may be associated with an application ANW executing on the first integrated circuit, e.g. chiplet, 110- 1. For example, this makes it possible for an application ANW executed on the first chiplet 110- 1 to be able to initiate, e.g. in a targeted manner, a device of the communication interface 130, e.g. without the first chiplet 110- 1 or a system 1000 having the first chiplet 110- 1 being to be reset. As a result, the communication interface 130 can be set up, e.g. re-set up (e.g. resynchronized), e.g. dynamically, e.g. during execution of the application ANW on the first chiplet 110- 1, for example in order to take account of detected transmission errors during data communication via the communication interface 130, in particular without the first chiplet 110- 1 having to be reset. Thus, in some examples, advantageously, e.g. a context of the application ANW executing on the first chiplet 110- 1 may be obtained.In some examples, FIG. 3, it is provided that the method comprises: initiating 210 a synchronization process SYNCH with respect to the communication interface 130 (FIG. 2 ) and, optionally, sending 212 at least one, for example first, training sequence TS- 1 via the communication interface 130, for example to the at least one further integrated circuit 110- 2. For example, the at least one training sequence TS- 1 can be used by the at least one further integrated circuit, e.g. a second chiplet 110- 2, for synchronization with the first chiplet 110- 1.In some examples, FIG. 3, it is provided that the initiation 210 of the synchronization process SYNCH with respect to the communication interface 130 comprises at least one of the following elements: a) signaling 210 aof the synchronization process to the at least one further integrated circuit 110- 2, for example via an optionally present synchronization connection (e.g. control line, e.g. different from the communication interface 130, not shown in FIG. 2 ), or b) applying 210 b(FIG. 3 ) of one, for example at least one, circuit node N- 1 to which the first integrated circuit 110- 1 and the at least one further integrated circuit 110- 2 are connected, with a predefinable first potential P- 1, e.g. a ground potential.In some examples, FIG. 4, it is provided that the method comprises at least one of the following elements: a) determining 220 whether a, for example second, training sequence TS- 2 is received via the communication interface 130, for example from the at least one further integrated circuit 110- 2, or b) optionally, synchronizing 222 by means of the received training sequence TS- 2, or c) signaling 224 a, for example successful or already existing, synchronization SYNCH', for example to the at least one further integrated circuit 110- 2.In some examples, it is provided that signaling 224 the, for example successful or already existing, synchronization SYNCH' comprises: applying 224 aof a or the circuit node N- 1 (FIG. 2 ), to which the first integrated circuit 110- 1 and the at least one further integrated circuit 10- 2 are connected, a predefinable second potential P- 2 which is different from the first potential P- 1.In some examples, see multi-chiplet system 1000' according to FIG. 5, having a plurality of chiplets 110- 1', 110- 2', 110- 3,... on a substrate 120', it is provided that circuit node N- 1 is connected by means of a resistor R- 1 to a first reference potential BP- 1, for example a reference potential corresponding to a positive operating voltage, wherein the application 210 b(FIG. 3 ) of circuit node N- 1 to the predefinable first potential P- 1 comprises a connection of circuit node N- 1 to a second reference potential BP- 2, for example a reference potential corresponding to a ground potential, and / or wherein the application 224 a(FIG. 4 ) of the node N- 1 with the predefinable second potential P- 2 comprises a disconnection of the node N- 1 from the second reference potential BP- 2, for example corresponding to the ground potential. For example, resistor R- 1 thus operates as a pull-up resistor, which pulls circuit node N- 1 to first reference potential BP- 1, provided circuit node N- 1 is not simultaneously connected to another potential, e.g., ground potential, for example (e.g., by one of chiplets 110- 1, 110- 2,... ).Some examples, FIGS. 2, 5, relate to an apparatus 300 for carrying out the method according to the disclosure. For example, the device 300 is integrated (not shown) into the first integrated circuit and / or into the at least one further integrated circuit, or is arranged on the substrate 120, 120', for example. Further details of the apparatus 300 according to some examples are described further below with reference to FIG. 6.Some examples relate to an integrated circuit 110- 1, 110- 2, 110- 1', 110- 2', for example for a multi-chiplet system 1000, 1000' comprising a plurality of chiplets, comprising at least one device 300 according to the disclosure, wherein for example the device 300 or a functionality of the device is integrated into the integrated circuit.Some examples, FIGS. 2, 5, relate to a system, for example a multi-chiplet system, 1000, 1000' comprising at least one device 300 according to the disclosure or at least one integrated circuit 110- 1, 110- 2, 110- 1', 110- 2',... according to the disclosure. By way of example, the system 1000, 1000' may also include multiple integrated circuits according to the disclosure, see FIG. 5, reference numerals 110- 3,...In some examples, FIG. 5, it is provided that a circuit node N- 1 to which the first integrated circuit 110- 1' and the at least one further integrated circuit 110- 2' are connected is arranged on the substrate 120'.In some examples, FIG. 5, it is provided that one, for example at least one, connecting line 116 is provided, which connects respective terminals 113, 115 of the first integrated circuit 110- 1' and of the at least one further integrated circuit 110- 2' to the circuit node N- 1, wherein, for example, the connecting line 116 is arranged at least partially on the substrate 120'. In some examples, the connecting line 116 can be used, for example, as a "synchronization line", which can be supplied, for example, with the ground potential by at least one integrated circuit 110- 1', 110- 2', for example, in order to signal a setup operation EV, for example, a synchronization. In further examples (not shown), multiple connection lines may be provided.In the examples according to FIG. 5, the communication interface 130' has two communication connections 132, 134, which enable data communication between the chiplets 110- 1', 110- 2' in a respective direction, see the arrows 132, 134. The communication connection 132 connects a first terminal 112 aof the first chiplet 110- 1' to a first terminal 114 aof the second chiplet 110- 2', and the communication connection 134 connects a second terminal 112 bof the first chiplet 110- 1' to a second terminal 114 bof the second chiplet 110- 2'.FIG. 6 schematically illustrates a block diagram of the apparatus 300 according to some examples.In some examples, it is provided that the apparatus 300 comprises: a computing device ("computer") 302 comprising at least one computing core 302 a, a storage device 304 assigned to the computing device 302 for at least temporarily storing at least one of the following elements: a) data DAT (e.g. the data associated with the setup operation EV and / or the training sequences TS- 1, TS- 2 and / or the synchronization SYNCH), b) computer program PRG, for example for executing the method according to the disclosure.In further examples, the memory device 304 comprises a volatile memory (e.g. random access memory (RAM)) 304 aand / or a nonvolatile (NVM) memory (e.g. flash EEPROM) 304 b, or a combination thereof or with other memory types not explicitly mentioned.In further examples, the device 300 is configured as a hardware circuit, for example pure hardware circuit (not shown).Further examples relate to a computer readable storage medium SM comprising instructions PRG which, when executed by a computer 302, cause the computer 302 to execute the method according to the disclosure.Further examples relate to a computer program PRG comprising instructions which, when the program PRG is executed by a computer 302, cause the computer to execute the method according to the disclosure.Further examples relate to a data carrier signal DCS characterizing and / or transmitting the computer program PRG according to the disclosure. The data carrier signal DCS can be received, for example, via an optional data interface 306 of the device 200.Some examples, FIG. 7, relate to a use of the method according to the disclosure and / or the apparatus 300 according to the disclosure and / or the integrated circuit 110- 1, 110- 2, 110- 1', 110- 2',... according to the disclosure and / or the system 1000, 1000' according to the disclosure for at least one of the following elements: a) starting 401 the communication interface 130, b) training 402 at least one component associated with the communication interface 130, c) maximizing 403 a bandwidth of the communication interface 130, d) minimizing 404 an error rate, for example bit error rate of the communication interface 130, e) avoiding 405 a resetting or restarting of the integrated circuit 110- 1, 110- 2, for example for synchronizing with the communication interface 130, f) synchronizing 406 with the communication interface 130, g) Providing 407 synchronization with respect to the communication interface 130 as, for example, regular, operating state, h) Enabling 408 the triggering of the setup process EV with respect to the communication interface 130 by the integrated circuit 110- 1, 110- 2 or a component of the integrated circuit (e.g. also application ANW or, e.g. higher protocol layer PS) or by another device.Further aspects and examples are described below which-in further examples-can each be combined individually by themselves or in any combination with one another with at least one of the aspects and / or examples described above.In some examples, efficient establishment and / or training of the communication interface 130, 130' is enabled for a multi-chiplet system or multi-chiplet packet.Some examples make it possible to check transactions transmitted via the communication interface 130, 130', for example by using redundancy (for example parity, CRC, data repetition or the like), as a result of which the multi-chiplet system 1000, 1000' can also be used, for example, for safety-critical systems or target systems such as, for example, control units for motor vehicles.Some examples allow, e.g., secure, starting and / or training of the communication interface 130, 130', such that, e.g., the bandwidth of the interface connection is maximized and / or the bit error rate is minimized.For example, in some examples, communication interface 130, 130' realizes a point-to-point connection between two chiplets 110- 1, 110- 2 in a system 1000 (FIG. 2 ), 1000', which in some examples, FIG. 5, may include a plurality of chiplets 110- 1', 110- 2', 110- 3',... In some examples (not shown), topologies for communication interface 130, 130' other than the point-to-point connection mentioned by way of example are possible. The principle according to the examples can be transferred in a corresponding manner to such other topologies for the communication interface 130, 130'.In some examples, FIGS. 2, 5, at least one chiplet 110- 1, 110- 1', for example each chiplet, may initiate a setup operation EV, e.g., including a setup and training sequence, as needed.In some examples, the setup operation EV may be useful, e.g., 1) at the start of the system 1000, 1000', e.g., for an initial synchronization, and / or 2) when, e.g., higher, protocol layers PS report an error, e.g., by means of parity bits, CRC, MD5,...In some examples, FIG. 5, a setup and training sequence, for example within the scope of a setup process EV, can be provided as follows. By way of example, the first chiplet 110- 1' can be designed, for example, as a master chiplet, and the at least one further chiplet 110- 2' is designed, for example, as a slave chiplet.1) During power-up, master chiplet 110- 1' initiates a synchronization sequence, for example, by connecting synchronization line 116 to ground potential. During a normal operating time, for example, each chiplet detecting a fault (e.g., through a higher protocol layer PS and / or an application ANGEW) pulls the synchronization line 116 down (e.g., to ground potential). In other words, in some examples, either the master chiplet and / or at least one slave chiplet may bias the synchronization line 116 with ground potential. In some examples, the synchronization line 116 is connected, for example, according to the open drain / open collector principle, i.e., two or more chiplets 110- 1', 110- 2',... the signal associated with the synchronization line 116 or the synchronization line 116 itself may, for example, only draw active to the ground potential or enable the signal. In the case of enabling, in some examples, the signal associated with the synchronization line 116 or the synchronization line 116 itself is set, for example via the pull-up resistor R- 1, to a potential different from the ground potential, for example "HIGH" (for example corresponding to a positive operating voltage). With the aid of this signaling, in some examples both chiplets 110- 1', 110- 2' can start a training sequence or initiate a setup operation EV.2) In some examples, a sequence for initiating the setup process EV is the same, e.g. regardless of whether the master or the slave chiplet has started the request for synchronization, e.g. by supplying the synchronization line 116 with the ground potential. In some examples, at least one chiplet 110- 1', 110- 2' may monitor a potential of the synchronization line 116 or the circuit node N- 1, e.g. repeatedly, e.g. periodically, e.g. continuously, e.g. to determine whether at least one other chiplet signals the initiation of the setup process EV via the synchronization line 116.3) In some examples, the master chiplet 110- 1', e.g., after the synchronization line 116 has been pulled to ground potential, begins transmitting a training pattern, e.g., the first training sequence TS- 1, via the master-2 slave interface 134 (FIG. 5 ). In some examples, the slave chiplet 110- 2', e.g., also, starts transmitting a training pattern, e.g., the second training sequence TS- 2, via the slave 2 master interface 132. In some examples, both chiplets 110- 1', 110- 2' actively pull synchronization line 116 down (i.e., to ground potential) if, for example, they do not already receive the correct training pattern, which is the case, for example, if synchronization is not already established.4) In some examples, at least one chiplet or both chiplets 110- 1', 110- 2' start searching, at their receiving side 112 a, 114 b, for the training pattern (e.g., corresponding to the respective known training sequence TS- 1, TS- 2), e.g., by time-shifting the bits with delay taps, for example. In some examples, both training sequences TS- 1, TS- 2 may be identical or different from each other.5) In some examples, e.g., when the slave chiplet 110- 2' receives the proper (training) sequence, e.g., synchronization towards master-> slave is performed. In some examples, the slave chiplet 110- 2' then enables the synchronization line 116, for example, by terminating the application of the ground potential to the synchronization line 116. If necessary, however, in some examples the synchronization line 116 can then still have the ground potential, because e.g. at least one other chiplet, e.g. the master chiplet, still acts on the synchronization line 116 with the ground potential. In some examples, the above-described principle also applies to the direction slave->master: if e.g. the master chiplet 110- 1' receives the correct (training) sequence, the master chiplet 110- 1', e.g. likewise, releases the synchronization line 116. As a result, the synchronization line 116 is pulled to the HIGH potential, for example by means of the resistor R- 1, and all devices, for example chiplets, which optionally monitor the potential of the synchronization line 116, can thereby establish that synchronization of the involved chiplets 110- 1', 110- 2' is completed.6) In other words, in some examples, e.g. when both or all chiplets involved in a synchronization release the synchronization line 116, e.g. because they are synchronized, the signal associated with the synchronization line 116 is set to "HIGH" by the pull-up resistor R- 1, i.e. the synchronization line 116 is connected via the pull-up resistor R- 1 to the positive potential corresponding to the "HIGH" level or state. In some examples, the synchronization sequence is then completed. In some examples, the two chiplets 110- 1', 110- 2' are informed of the successful synchronization by repeatedly, e.g. periodically, e.g. continuously reading back the signal associated with the synchronization line 116.In some examples, the function of the synchronization line 116, for example alternatively or additionally, can also be implemented by means of a reset or error request, for example a generic reset or error request, for example from one chiplet 110- 1' to the other chiplet 110- 2' (and / or vice versa), for example depending on the application.In some examples, at least one or more of the following aspects or advantages may result at least temporarily:A chiplet, e.g. each chiplet, can initiate a setup process EV, e.g. comprising a synchronization sequence, e.g. when e.g. higher protocol layers PS or applications ANW detect an error, e.g. by evaluating a checksum.In some examples, a setup operation EV can be initiated during the start of the system 1000, 1000' and / or during a normal operating time, e.g. when a chiplet comes out of synchronization, e.g. due to temperature fluctuations, or self-heating or heating / cooling by the environment.In some examples, for example, no complete power failure or resetting of the system 1000, 1000' or of a chiplet is required in order to trigger the setup operation EV, for example in order to restore the synchronization. In some examples, the setup operation EV, e.g., synchronization, may be recognized as, e.g., normal, system mode.Some examples may be used, for example, where chiplets are interconnected in a, e.g., single, package (not shown), e.g., to exchange data with each other, e.g., a chiplet implementing a microcontroller system and a second package containing a memory.In some examples, at least one chiplet may include, for example, a microcontroller, and in some examples, at least one chiplet may include, for example, a memory device.

Claims

A method for a first integrated circuit (110-1) co-located with at least one further integrated circuit (110-2) on a substrate (120), comprising: determining (200) whether to perform a setup operation (EV) with respect to a communication interface (130) associated with the first integrated circuit (110-1) and with the at least one further integrated circuit (110-2), and if the determining (200) reveals that the setup operation (EV) is to be performed with respect to the communication interface (130), performing (202) the setup operation (EV) with respect to the communication interface (130).The method of claim 1, comprising: if the determining (200) reveals that the setup operation (EV) with respect to the communication interface (130) is not to be executed, omitting (204) the executing (202) of the setup operation (EV) with respect to the communication interface (130).Method according to Claim 1 or 2, wherein the first integrated circuit (110-1) and the at least one further integrated circuit (110-2) are each formed as a chip, for example chiplet, wherein, for example, the first integrated circuit (110-1) and the at least one further integrated circuit (110-2) form a multi-chiplet system (1000).Method according to at least one of the preceding claims, wherein the determination (200) comprises at least one of the following elements: a) determining (200a) whether at least the first integrated circuit (110-1) is started, or b) determining (200b) whether at least one, for example higher, protocol layer (PS), for example a layer 2 according to the ISO / OSI layer model or higher, signals an error or a requirement for the execution of the setup process (EV).Method according to at least one of the preceding claims, comprising: initiating (210) a synchronization process (SYNCH) with respect to the communication interface (130), and optionally sending (212) at least one training sequence (TS-1) via the communication interface (130), for example to the at least one further integrated circuit (110-2).Method according to Claim 5, wherein the initiation (210) comprises at least one of the following elements: a) signaling (210a) the synchronization process (SYNCH) to the at least one further integrated circuit (110-2), or b) applying (210b) to one, for example at least one, circuit node (N-1), to which the first integrated circuit (110-1) and the at least one further integrated circuit (110-2) are connected, a predefinable first potential (P-1).Method according to at least one of the preceding claims, comprising at least one of the following elements: a) determining (220) whether a training sequence (TS-2) is received via the communication interface (130), for example from the at least one further integrated circuit (110-2), or b) optionally, synchronizing (222) by means of the received training sequence (TS-2), or c) signaling (224) a, for example successful or already existing, synchronization (SYNCH').Method according to Claim 7, wherein the signalling (224) comprises: applying (224a) a predefinable second potential (P-2) to a or the circuit node (N-1) to which the first integrated circuit (110-1) and the at least one further integrated circuit (110-2) are connected.Method according to at least one of Claims 6 to 8, wherein the circuit node (N-1) is connected by means of a resistor (R-1) to a first reference potential (BP-1), for example a reference potential corresponding to a positive operating voltage, wherein the application (210b) of the circuit node (N-1) to the predeterminable first potential (P-1) comprises a connection of the circuit node (N-1) to a second reference potential (BP-2), for example a reference potential corresponding to a ground potential, and / or wherein the application (224a) of the circuit node (N-1) to the predeterminable second potential (P-2) comprises a disconnection of the circuit node (N-1) from the second reference potential (BP-2), for example a reference potential corresponding to the ground potential.Device (300) for carrying out the method according to at least one of the preceding claims.Integrated circuit (110-1; 110-1'), for example for a multi-chiplet system (1000; 1000') comprising a plurality of chiplets, comprising at least one device (300) according to claim 10, wherein for example the device (300) or a functionality of the device (300) is integrated into the integrated circuit (110-1; 110-1').A system, for example a multi-chiplet system (1000; 1000'), comprising at least one device (300) according to claim 10 or at least one integrated circuit (110-1; 110-1') according to claim 11.The system (1000; 1000') of claim 12, wherein a circuit node (N-1) to which the first integrated circuit (110-1) and the at least one further integrated circuit (110-2) is connected is disposed on the substrate (120).The system (1000; 1000') according to claim 13, wherein one, for example at least one, connection line (116) is provided, which connects respective terminals (113, 115) of the first integrated circuit (110- 1) and of the at least one further integrated circuit (110- 2) to the circuit node (N- 1), wherein, for example, the connection line (116) is arranged at least partially on the substrate (120).Use (400) of the method according to at least one of claims 1 to 9 and / or of the apparatus (300) according to claim 10 and / or of the integrated circuit (110-1; 110-2) according to claim 11 and / or of the system (1000) according to at least one of claims 12 to 14 for at least one of the following elements: a) starting (401) the communication interface (130), b) training (402) at least one component associated with the communication interface (130), c) maximizing (403) a bandwidth of the communication interface (130), d) minimizing (404) an error rate, for example bit error rate, of the communication interface (130), e) avoiding (405) a resetting or restarting of the integrated circuit (110-1), for example for synchronizing with respect to the communication interface (130), f) synchronizing (406) with respect to the communication interface (130), g) providing (407) synchronization with respect to the communication interface (130) as, for example, regular, operating state, h) enabling (408) the initiation of the setup process (EV) with respect to the communication interface (130) by the integrated circuit (110- 1) or a component (PS; ANW) of the integrated circuit (110- 1) or by another device (110- 2).

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