Manufacturing and testing procedures for a power module

Abstract

A manufacturing method of a power module includes the following operations: bonding a semiconductor device to a lower substrate; disposing an upper bonding member on an upper portion of the semiconductor device; contacting a probe device with the upper bonding member; electrically connecting the probe device to a tester and testing electrical characteristics of the semiconductor device; and bonding an upper substrate to the semiconductor device through the upper bonding member.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a manufacturing method and a testing method for a power module, in particular to a manufacturing method and a testing method that can test the electrical characteristics of a power module before its completion. BACKGROUND

[0002] A power module is a device used to convert direct current (DC) to alternating current (AC) when driving motors of hybrid vehicles, electric vehicles, or the like. Typically, the power module may include a substrate, a power semiconductor device, a switching device connected to the substrate, a power supply line for applying power to the power semiconductor device, a signal line for providing a control signal to the power semiconductor device, and the like.

[0003] After the power module described above is manufactured, it is selected as a good or defective product through an inspection of its electrical properties. The inspection of the electrical properties of the power module can generally be performed as part of an end-of-line (EOL) evaluation process and may include a DC test, an AC test, and a withstand voltage test.

[0004] In some cases where the electrical characteristics of power modules are tested in the form of a finished product with complete packaging, since defects in a semiconductor device cannot be detected in advance and even in the case of a semiconductor device with problems, all subsequent processes are carried out, there is a problem of unnecessary material consumption and significant process losses. SUMMARY

[0005] One aspect of the present disclosure is to provide a manufacturing method capable of testing electrical properties by bringing an inspection device into contact with a solder part disposed on a semiconductor device to detect defects in the semiconductor device in an intermediate process before the power module is completed.

[0006] According to one aspect of the present disclosure, a manufacturing method of a power module may include the following operations: bonding a semiconductor device to a lower substrate; disposing an upper bonding member on an upper portion of the semiconductor device; contacting a probe device with the upper bonding member; electrically connecting the probe device to a tester and testing electrical characteristics of the semiconductor device; and bonding an upper substrate to the semiconductor device through the upper bonding member.

[0007] In some implementations, the manufacturing method may further include a molding process performed after the upper substrate bonding process.

[0008] In some implementations, the manufacturing method may further include a process of wire bonding a signal line and the semiconductor device, wherein the wire bonding may be performed between the process of testing the electrical properties of the semiconductor device and the process of bonding the upper substrate.

[0009] In some implementations, the semiconductor device may be bonded to the lower substrate by a lower bonding element disposed between a lower surface of the semiconductor device and the lower substrate.

[0010] In some implementations, the lower bonding element and the upper bonding element may include a material with electrical conductivity.

[0011] In some implementations, the lower bonding element and the upper bonding element may be made of a material that can be at least either soldered or sintered.

[0012] In some implementations, the probe device may comprise a contact pin electrically connected to the test device and configured to contact the upper bonding element, wherein the contact pin may be configured to be electrically connected to the semiconductor device via the upper bonding element.

[0013] In some implementations, the probe device may further comprise a plate to which the contact pin is removably coupled, and the semiconductor device and the contact pins may be multiple.

[0014] In some implementations, the act of contacting the probe device with the upper bonding member may include an act of adjusting the number and position of the plurality of contact pins connected to the board according to the number and position of the plurality of semiconductor devices.

[0015] In some implementations, the act of disposing a top bonding element on an upper region of the semiconductor device may include an act of disposing a first top bonding element on an upper surface of the semiconductor device, and the probe device may be configured to contact the first top bonding element.

[0016] In some implementations, the act of disposing a top bonding element on an upper region of the semiconductor device may include the acts of disposing a first top bonding element on an upper surface of the semiconductor device, disposing a spacer on an upper region of the first top bonding element, and disposing a second top bonding element on an upper region of the spacer, and the probe device may be configured to contact the second top bonding element.

[0017] In some implementations, the probe device may be configured to be electrically connected to the semiconductor device via the second upper bonding element, the spacer, and the first upper bonding element.

[0018] In some implementations, when testing the electrical characteristics of the semiconductor device, the tester may apply an electrical signal to the semiconductor device via the probe device.

[0019] According to another aspect of the present disclosure, a testing method of a power module may include the steps of: preparing a power module, a device under test, for testing electrical characteristics; contacting a probe device with the power module, the device under test; and electrically connecting the probe device to a tester and applying an electrical signal to the power module, the device under test, wherein the process of preparing the power module, the device under test may include a process of manufacturing a power module in process in which a semiconductor device is bonded to a lower substrate and a bonding element is disposed on an upper region of the semiconductor device, wherein the probe device may contact the bonding element disposed on the upper region of the semiconductor device.

[0020] In some implementations, the probe device may include a contact pin provided in a number corresponding to that of the semiconductor device, and may be configured such that the contact pin contacts the bonding member in the process of contacting the probe device with the power module, the device under test.

[0021] In some implementations, the bonding element may include a material with electrical conductivity.

[0022] In some implementations, a finished product of the power module may be a structure in which the semiconductor device is disposed and bonded between the upper substrate and the lower substrate, and the work-in-progress power module may be in a state before the upper substrate is bonded to the upper portion of the semiconductor device by the bonding member. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other aspects, features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Fig. 1 is a perspective view showing an example of a power module. Fig. 2 is a cross-sectional view showing an example of a power module. Fig. Figure 3 illustrates an example of a probe device for testing the electrical characteristics of a power module. Fig. Figure 4 illustrates an example of a method for testing a power module. Fig. 5 schematically illustrates an example state in which a probe device and a power module are in contact in a power module testing method. Fig. 6 schematically illustrates an example state in which a probe device and a power module are in contact in a power module testing method. The Fig. 7A, Fig. 7B and Fig. 7C illustrate a manufacturing process for a power module. DETAILED DESCRIPTION

[0024] Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings. In the addition of reference numerals to elements of each of the drawings, like reference numerals may refer to like elements even though the same elements are shown in different drawings. Since the present disclosure is susceptible to various changes and different implementations, specific implementations are illustrated and described in detail in the drawings. However, this is not intended to limit the present disclosure to particular embodiments, but is to be understood as including all modifications, equivalents, and substitutes included within the spirit and scope of the present disclosure.

[0025] One or more implementations of the present disclosure are described below with reference to the drawings.

[0026] Fig. 1 is a perspective view of an example of a power module 1. Fig. 2 is a cross-sectional view of the power module 1.

[0027] Fig. Figure 2 is a diagram schematically showing a cross section along the line AA' of the Fig. 1 illustrated power module 1.

[0028] In some implementations that focus on the Fig. 1 and Fig. 2, the power module 1 may include a housing 10, a lower substrate 20, an upper substrate 30, a semiconductor device 40, a power line 50, a signal line 60, a wire W, a spacer 70, and a bonding member 80.

[0029] The housing 10 can accommodate at least a portion of the components that make up the power module 1. For example, the housing 10 can surround components arranged between the lower substrate 20 and the upper substrate 30, such that at least a portion of the lower substrate 20, the upper substrate 30, the power line 50, and the signal line 60 are exposed to the outside. The housing 10 can be a molded part formed from an insulating material that molds the components that make up the power module 1.

[0030] The lower substrate 20 may include an insulating layer 22 and metal layers 21 and 23 disposed on both surfaces of the insulating layer 22. The metal layers 21 and 23 may include a first metal layer 21 connected to an upper surface of the insulating layer 22 and a second metal layer 23 connected to a lower surface of the insulating layer 22. The first metal layer 21 of the lower substrate 20 may be in electrical contact with a lower surface of the semiconductor device 40. At least a portion (e.g., a bottom surface) of the second metal layer 23 of the lower substrate 20 may be located outside the housing 10 and exposed. In some examples, the second metal layer 23 of the lower substrate 20 may be in contact with a cooling channel for cooling the power module 1.

[0031] The upper substrate 30 may include an insulating layer 32 and metal layers 31 and 33 disposed on both surfaces of the insulating layer 32. The metal layers 31 and 33 may include a first metal layer 33 bonded to a lower surface of the insulating layer 32 and a second metal layer 31 bonded to an upper surface of the insulating layer 32. The first metal layer 33 of the upper substrate 30 may be in electrical contact with the upper surface of the semiconductor device 40 via a first spacer 71. At least a portion (e.g., the upper surface) of the second metal layer 31 of the upper substrate 30 may be located outside the housing 10 and exposed. In some examples, the second metal layer 31 of the upper substrate 30 may be in contact with a cooling channel for cooling the power module 1.

[0032] The lower substrate 20 and the upper substrate 30 may be double bonded copper (DBC) substrates. For example, the upper substrate 30 and the lower substrate 20 may include insulating layers 22 and 32 made of a ceramic material and metal layers 21, 23, 31, and 33 made of a copper material, but the present disclosure is not limited thereto.

[0033] The lower substrate 20 and the upper substrate 30 may be electrically connected by a spacer 70. For example, the first metal layer 21 of the lower substrate 20 and the first metal layer 33 of the upper substrate 30 may be electrically connected by a second spacer 72. Some regions of the first metal layer 21 of the lower substrate 20 are electrically connected to the lower surface of the semiconductor device 40, and some regions of the first metal layer 21 of the lower substrate 20 that are electrically connected to the first metal layer 33 via the second spacer 72 may be configured to be electrically isolated.

[0034] A semiconductor device (or a semiconductor chip) 40 may be disposed between the lower substrate 20 and the upper substrate 30. For example, the semiconductor device 40 may be bonded to the first metal layer 21 of the lower substrate 20 and located between the lower substrate 20 and the upper substrate 30. The semiconductor device 40 may be electrically connected to the upper substrate 30 and the lower substrate 20. For example, the semiconductor device 40 may have power terminals formed on the upper and lower surfaces, respectively, through which power is input and output for power conversion, and the power terminal formed on the lower surface may be electrically connected to the lower substrate 20, and the power terminal formed on the upper surface may be electrically connected to the upper substrate 30.The semiconductor device 40 may be composed of an insulated gate bipolar transistor (IGBT) and a diode, but the present disclosure is not limited thereto.

[0035] The bottom surface of the semiconductor device 40 may be connected to the first metal layer 21 of the lower substrate 20 via a bottom bonding element 81. The top surface of the semiconductor device 40 may be connected to the first spacer 71 via an upper bonding element 82 (e.g., a first upper bonding element). For example, the semiconductor device 40 may be electrically connected to the first metal layer 33 of the upper substrate 30 via the first spacer 71. The semiconductor device 40 may be electrically connected to a signal line 60 by a wire W.

[0036] The power line 50 can be connected to the semiconductor device 40 and can transmit and receive high-voltage power. The power line 50 can be electrically connected to the semiconductor device 40. The power line 50 can be provided in multiples. At least a portion of the power line 50 can be electrically connected to the first metal layer 21 of the lower substrate 20 via a bonding member 80. For example, the power line 50 can be bonded together with the semiconductor device 40 to the upper surface of the first metal layer 21 of the lower substrate 20. A portion of the power line 50 can be exposed to the outside of the housing 10 to transmit power to and receive power from the outside of the power module 1. The power line 50 can extend from the inside of the housing 10 to the outside of the housing 10 such that at least a portion is exposed to the outside of the housing 10.

[0037] The signal line 60 can receive a control signal for controlling the semiconductor device 40 from the outside of the power module 1. A plurality of signal lines 60 can be provided. The signal line 60 can extend from the inside of the housing 10 toward the outside of the housing 10 so that at least a portion is exposed to the outside of the housing 10. The signal line 60 can be electrically connected to the semiconductor device 40 via a wire W.

[0038] The spacer 70 may include a first spacer 71 disposed between the upper substrate 30 and the semiconductor device 40, and a second spacer 72 disposed between the upper substrate 30 and the lower substrate 20.

[0039] The first spacer 71 may have an upper surface bonded to the first metal layer 33 of the upper substrate 30 and a lower surface bonded to the semiconductor device 40 to establish an electrical connection between the upper substrate 30 and the semiconductor device 40. For example, the lower surface of the first spacer 71 may be electrically and physically bonded to the semiconductor device 40 (e.g., an upper surface of the semiconductor device 40) by a first upper bonding element 82, and the upper surface of the first spacer 71 may be electrically and physically bonded to the first metal layer 33 of the upper substrate 30 (e.g., a lower surface of the first metal layer 33) by a second upper bonding element 83.

[0040] The second spacer 72 may have an upper surface bonded to the first metal layer 33 of the upper substrate 30 and a lower surface bonded to the first metal layer 21 of the lower substrate 20 to establish an electrical connection between the upper substrate 30 and the lower substrate 20. For example, the upper and lower surfaces of the second spacer 72 may be connected to the first metal layer 33 of the upper substrate 30 (e.g., a lower surface of the first metal layer 33) and to the first metal layer 21 of the lower substrate 20 (e.g., an upper surface of the first metal layer 21), respectively, via a bonding element 80.

[0041] The bonding element 80 can electrically and physically connect components arranged on both surfaces of the bonding element 80. For example, the components arranged on both surfaces of the bonding element 80 can be electrically connected and simultaneously mechanically (or physically) coupled to each other by the bonding element 80. The bonding element 80 can be made of various materials that can be soldered and / or sintered. For example, the bonding element 80 can be referred to as a solder part and / or a sintered part.

[0042] As in Fig. 1 and Fig. 2, the power module 1 may be a double-sided cooling (DSC) type according to one implementation, configured such that a semiconductor device 40 is disposed between an upper substrate 30 and a lower substrate 20. However, a structure of the power module 1 is not limited to the illustrated implementation, but may be modified in various ways within the scope of implementing a structure in which a semiconductor device 40 is disposed between the upper and lower substrates 20 and 30, and heat generated by the semiconductor device 40 is cooled using a cooler installed outside the two substrates.

[0043] Fig. 3 illustrates a probe device 100 for testing the electrical properties of the power module 1.

[0044] As in Fig. 3, according to one implementation, the probe device 100 can be used to examine and test the electrical properties of the power module 1 by contacting at least a portion of the power module 1. The probe device 100 can electrically connect and interface the power module 1 and a test device (or test equipment).

[0045] The probe device 100 according to one implementation may include a plate 110 and a plurality of contact pins 120 arranged on the plate 110.

[0046] The board 110 may be provided with a plurality of contact pins 120, and the plurality of contact pins 120 may be connected to a surface of the board 110. The board 110 may be referred to, for example, as a probe card.

[0047] The plurality of contact pins 120 may be connected to the board 110 as an electrical connector. The plurality of contact pins 120 may contact some components (e.g., the semiconductor device 40) of the power module, the device under test 1. The plurality of contact pins 120 may comprise, for example, a pogo pin or a spring-loaded pin.

[0048] The plurality of contact pins 120 can electrically connect a test device and the power module 1. The plurality of contact pins 120 can be coupled to the board 110 and electrically connected to the test device. For example, the plurality of contact pins 120 can be electrically connected to the test device via a separate electrical cable. However, a method in which the plurality of contact pins 120 are electrically connected to the test device is not limited to the example described above.

[0049] According to various embodiments, the plurality of contact pins 120 may be electrically connected to the test device via a board 110. For example, the board 110 may be comprised of a printed circuit board and electrically connected to the test device, and since the plurality of contact pins 120 are electrically contacted and connected to the board 110, the plurality of contact pins 120 may be electrically connected to the test via the board 110.

[0050] The plurality of contact pins 120 may be detachably connected to the board 110. For example, the probe device 100 may be configured such that the number of the plurality of contact pins 120 and a position where the plurality of contact pins 120 are connected to the board 110 are changed according to the position and number of the semiconductor device 40 in a power module 1, a device under test. A plurality of coupling holes to which a plurality of contact pins 120 can be coupled may be formed in the board 110 and may be coupled to a coupling hole that can contact the semiconductor device 40 among the plurality of coupling holes according to the position and / or number of the semiconductor device 40.For example, when testing the power module 1 using the probe device 100, the number and / or position of the plurality of contact pins 120 may be adjusted according to the number and / or position of the semiconductor device 40.

[0051] Fig. Figure 4 illustrates a test procedure for power module 1. Fig. 5 shows a state in which the probe device 100 and the power module 1 are in contact in the testing process of the power module 1.

[0052] With reference to the Fig. 4 and Fig. 5, the method for testing the electrical properties of the power module 1 can be carried out according to an implementation in an intermediate process before the Fig. 1 and Fig. 2 shown power module 1 is completed. In the description of Fig. 4 and Fig. 5 is on Fig. 1 and Fig. 2 are referred to jointly.

[0053] Hereinafter, the testing method of the power module 1 according to one implementation will be described as a method for testing the DC characteristics of the semiconductor device 40 of the power module 1, but the electrical characteristics and elements evaluated by the testing method of the present disclosure are not limited to the DC characteristics.

[0054] A DC test is a test in which DC characteristics such as open / short circuit, input current, output voltage, and power current are applied to the power module 1 by applying a preset voltage and / or current to determine whether the semiconductor device 40 in the power module 1 is functioning properly.

[0055] In the test method of the power module 1 according to an implementation, a power module 1, a device under test (DUT), may be in a state of processing before the double-sided cooled power module 1 of the Fig. 1 and Fig. 2 is completed.

[0056] The power module, the device to be tested 1, may be a power module in production (e.g. the one shown in 703 in Fig. 7B), in which at least one semiconductor device 40 is bonded to a lower substrate 20, and in a state in which a bonding element 80 for bonding an upper substrate (e.g., upper substrate 30 in Fig. 1 and Fig. 2) and / or a spacer (e.g. spacer 70 in Fig. 2) is arranged on an upper region of the semiconductor device 40.

[0057] For example, in the power module, the device under test (DUT) 1, the lower substrate 20, and the semiconductor device 40 may be connected by a lower bonding member 81 disposed between the lower surface 41 of the semiconductor device 40 and the lower substrate 20 (e.g., by primary soldering and / or sintering), and the upper bonding member (e.g., the first upper bonding member) 82 may be disposed on an upper surface 42 of the semiconductor device 40 before the upper substrate 30 (or the upper substrate 30 and the first spacer 71) is connected to the semiconductor device 40 (e.g., by secondary soldering and / or sintering).Here, the upper bonding member 82 can be bonded to the upper surface 42 of the semiconductor device 40 while being melted and solidified together with the lower bonding member 81 in the process of bonding the semiconductor device 40 and the lower substrate 20, so that the upper bonding member 82 can be bonded to the upper surface 42 of the semiconductor device 40.

[0058] The semiconductor devices 40 connected to the lower substrate 20 may be multiple. Furthermore, the number and / or position of the semiconductor devices 40 is not limited to the illustrated embodiment.

[0059] The testing method of the power module 1 may include operations for preparing a power module, a device under test 1, for contacting the probe device 100 (e.g., a plurality of contact pins 120) with the upper bonding element 82, and for applying an electrical signal for testing. Here, the operation of preparing the power module, the device under test 1, may refer to a process of manufacturing an unfinished device in which the upper bonding element 82 is arranged on an upper region of the semiconductor device 40 and bonded to the lower substrate 20. According to various embodiments, at least some operations of the method for testing the power module 1 may be included in a method for manufacturing the power module 1 (see, e.g., Fig. 7A, Fig. 7B and Fig. 7C).

[0060] In the testing method of the power module 1, the probe device 100 may be configured such that the plurality of contact pins 120 contact an upper bonding member 82 disposed on the upper surface 42 of the semiconductor device 40 above the power module, the device 1 under test. The plurality of contact pins 120 may be electrically connected to the semiconductor device 40 by contacting the upper bonding member 82, which is electrically conductive. For example, the plurality of contact pins 120 may transmit an electrical signal received from the DC tester 200 to the semiconductor device 40 via the upper bonding member 82.

[0061] The probe device 100 may be electrically connected to a DC tester 200. For example, the probe device 100 may include a plurality of contact pins 120 arranged from a lower surface through an upper surface of the plate 110, and a portion of the plurality of contact pins 120 that pass through the upper surface of the plate 110 may be electrically connected to the DC tester 200. The plurality of contact pins 120 may be electrically connected to the DC tester 200 via conductive wires. However, an electrical connection method between the plurality of contact pins 120 and the DC tester 200 is not limited to the illustrated implementation.

[0062] The DC tester 200 can apply and detect an electrical signal for a DC test to the semiconductor device 40 via the plurality of contact pins 120. For example, after the plurality of contact pins 120 of the probe device 100 are contacted with the upper bonding member 82 disposed on the upper surface 42 of the semiconductor device 40, current and / or voltage application conditions for each circuit are set for each terminal in the DC tester 200, and the set current and / or voltage are applied for testing. Since the DC testing method for semiconductors is a well-known technology in the related technical field, a detailed description of more specific methods will be omitted.

[0063] According to the testing method of the present disclosure, the electrical characteristics are tested by contacting the probe device 100 with the bonding member 80 arranged on the upper part of the semiconductor device 40 in an intermediate process before the completion of the power module 1, whereby defects can be detected at an initial stage of the manufacturing process without damaging or destroying the semiconductor device 40.

[0064] Fig. 6 schematically illustrates a state in which a probe device 100 and a power module 1 are in contact in a testing process of the power module 1.

[0065] With reference to Fig. 6 can, in contrast to the Fig. 5, in the testing method of the power module 1, in a state where a first spacer 71 is bonded to an upper surface 42 of a semiconductor device 40, the probe device 100 may be configured to contact an upper bonding element 83 (e.g., a second bonding element) disposed on an upper portion of the first spacer 71.

[0066] In the Fig. 6, in the power module, the device under test 1, the lower substrate 20, the semiconductor device 40, and the first spacer 71 are stacked and bonded (e.g., primary soldering and / or sintering) by a lower bonding member 81 disposed between the lower surface 41 of the semiconductor device 40 and the lower substrate 20, and a first upper bonding member 82 disposed between the upper surface 42 of the semiconductor device 40 and the first spacer 71, and the second upper bonding member 82 may be disposed on the upper surface 42 of the first spacer 71 before the upper substrate 30 is bonded to the first spacer 71 (e.g., secondary soldering and / or sintering).Here, in a process of bonding the semiconductor device 40, the lower substrate 20, and the first spacer 71, the second upper bonding member 82 may be bonded to the upper surface of the first spacer 71 while being melted and solidified together with the lower bonding member 81 and the first upper bonding member 82.

[0067] According to the Fig. In the implementation illustrated in Figure 6, the plurality of contact pins 120 may be configured to contact the second upper bonding member 83 disposed on the upper surface of the first spacer 71. The plurality of contact pins 120 may be electrically connected to the semiconductor device 40 through the first spacer 71 and the first upper bonding member 82 by contacting the second upper bonding member 83 with electrical conductivity. For example, the plurality of contact pins 120 may transmit an electrical signal received from the DC tester 200 to the semiconductor device 40 via the second upper bonding member 83, the first spacer 71, and the first upper bonding member 82.

[0068] The Fig. 7A, Fig. 7B and Fig. 7C illustrate a manufacturing process for the power module 1.

[0069] With reference to the Fig. 7A, Fig. 7B and Fig. 7C, a manufacturing method of the power module 1 may be described with reference to the Fig. 4 to 6 contain the test procedures (or test process) of the power module 1.

[0070] The manufacturing method of the power module 1 may include a process of mounting a component on a lead frame (701), a process of bonding a semiconductor device to a lower substrate (702), a process of attaching a bonding element to an upper region of the semiconductor device (703), a process of testing electrical characteristics by contacting a probe device with a bonding element on an upper region of the semiconductor device (704), a process of bonding an upper substrate (705), and a molding step (706).

[0071] The process of bonding the semiconductor device to the lower substrate 702 and the process of attaching the bonding member 703 to an upper portion of the semiconductor device 703 can be performed simultaneously. For example, in a state where a lower bonding member 81 is interposed between the lower substrate 20 and the semiconductor device 40, and an upper bonding member 80 is disposed on an upper portion of the semiconductor device 40, by applying heat to melt and solidify the bonding member 80, the semiconductor device 40 can be bonded to the lower substrate 20, and the bonding member 80 can be disposed on the upper portion of the semiconductor device 40. However, this is an example, and the manufacturing method is not limited to the above-described content.

[0072] When testing the electrical properties by touching the probe device with the bonding element on the upper part of the semiconductor device 704, the bonding element 80 arranged on the upper part of the semiconductor device 40 may be a first upper bonding element 82 or a second upper bonding element 83, which may be determined according to various implementations of the manufacturing method.

[0073] For example, depending on the manufacturing method, in the process of attaching a bonding member to the upper part of the semiconductor device, only the first upper bonding member 82 may be disposed on the upper part of the semiconductor device 40, and in this case, the probe device 100 may be in contact with the first upper bonding member 82. Moreover, in this case, the process of bonding the upper substrate 705 is performed so that the upper substrate 30 is bonded to the semiconductor device 40 in a state where the first spacer 71 is bonded.

[0074] As another example, depending on the manufacturing method, when attaching a bonding member to the upper part of the semiconductor device 703, the first upper bonding member 82, the first spacer 71, and the second upper bonding member 83 may be sequentially stacked and arranged on the upper part of the semiconductor device 40, and in this case, the probe device 100 may contact the second upper bonding member 83. Furthermore, in this case, the upper substrate bonding process is performed so that the upper substrate 30 is bonded to the first spacer 71 in a state where the upper substrate 30 is bonded to the upper part of the semiconductor device 40.

[0075] In the molding step 706, epoxy resin molding compound (EMC) may be melted and then cured to form a housing (e.g., the housing 10 in Fig. 1) that surrounds and protects the semiconductor device 40. The forming step 706 may be referred to, for example, as an encapsulation process.

[0076] In some examples, in the manufacturing method of the power module 1 according to an implementation, a process of connecting the signal line 60 and the semiconductor device 40 with a wire W may be performed before the process of bonding the upper substrate 705.

[0077] In some examples, in the manufacturing method of the power module 1, after the forming step 706, a trimming process may be performed to remove dams (English: “dambar”) that maintain the shape of a lead frame 90 in order to separate the power line 50 and the signal line 60 from the lead frame 90. For example, since the trimming process in step 706 of Fig. 7C, it can take the form of the Fig. 1 shown power module 1.

[0078] Meanwhile, the Fig. 7A, Fig. 7B and Fig. 7C illustrates an example of a manufacturing method, and the manufacturing method of the power module 1 according to one implementation is not limited to the illustrated implementation, and according to different implementations, some operations may be omitted and / or added, or some operations may be combined and / or separated.

[0079] As explained above, material and processing costs can be reduced by detecting defects in a semiconductor device in advance before a power module is completed, and the cause of the defects in the semiconductor device can be easily analyzed.

[0080] In addition, in a double-sided cooling power module, the test can be performed without damaging the semiconductor device by contacting a bonding element on the top side of the semiconductor device that is connected to the lower substrate before connecting the upper substrate and testing it.

[0081] The above description merely illustrates the technical concept of the present disclosure, and those skilled in the art to which the present disclosure belongs may make various changes and modifications without departing from the essential features of the present disclosure.

[0082] In some implementations, some components may be deleted, and the components of each implementation may be combined.

[0083] Therefore, the embodiments disclosed in this specification and the drawings are intended to illustrate the technical concept of the present disclosure, not to limit it, and the scope of the technical idea of ​​the present disclosure is not limited by these embodiments. The scope of the present disclosure should be interpreted by the following claims, and all technical ideas within the equivalent scope should be construed as being included within the scope of the present disclosure.

Claims

[1] A method of manufacturing a power module, comprising: Bonding a semiconductor device to a lower substrate; disposing an upper bonding element on an upper region of the semiconductor device; Contacting a probe device with the upper bonding element; electrically connecting the probe device to a test device; Detecting electrical properties of the semiconductor device using the test device; and Bonding an upper substrate to the semiconductor device with the upper bonding element. [2] The manufacturing method according to claim 1, further comprising: Performing a molding process after bonding the upper substrate to the semiconductor device. [3] The manufacturing method according to claim 1, further comprising: Connecting a signal line to the semiconductor device, wherein bonding of the signal line to the semiconductor device is performed between detecting the electrical characteristics of the semiconductor device and bonding the upper substrate. [4] The manufacturing method according to claim 1, wherein bonding the semiconductor device to the lower substrate comprises: Disposing a lower bonding element between a lower surface of the semiconductor device and the lower substrate; and Connecting the semiconductor device to the lower substrate using the lower bonding element. [5] The manufacturing method according to claim 4, wherein the lower bonding member and the upper bonding member comprise a material having electrical conductivity. [6] A manufacturing method according to claim 5, wherein the lower bonding member and the upper bonding member comprise a material capable of being at least one of soldered and sintered. [7] The manufacturing method according to claim 1, wherein the probe device comprises a contact pin electrically connected to the tester and configured to contact the upper bonding member, and wherein contacting the probe device with the upper bonding member comprises electrically connecting the contact pin to the semiconductor device through the upper bonding member. [8] The manufacturing method according to claim 7, wherein the probe device further comprises a board to which a plurality of contact pins are detachably coupled, the contact pin being one of the plurality of contact pins, and wherein bonding the semiconductor device to the lower substrate comprises bonding a plurality of semiconductor devices to the lower substrate, the semiconductor device being one of the plurality of semiconductor devices. [9] The manufacturing method according to claim 8, wherein bringing the probe device into contact with the upper bonding element comprises: Adjusting a number and a position of the plurality of contact pins to match a number and a position of the plurality of semiconductor devices, respectively. [10] The manufacturing method according to claim 1, wherein disposing the upper bonding member on the upper region of the semiconductor device comprises disposing a first upper bonding member on an upper surface of the semiconductor device, and wherein bringing the probe device into contact with the upper bonding member comprises bringing the probe device into contact with the first upper bonding member. [11] The manufacturing method according to claim 1, wherein disposing the upper bonding element on the upper part of the semiconductor device comprises: disposing a first upper bonding element on an upper surface of the semiconductor device; Arranging a spacer on an upper portion of the first upper bonding element; and Arranging a second upper bonding element on an upper region of the spacer, and wherein contacting the probe device with the upper bonding element comprises contacting the probe device with the second upper bonding element. [12] The manufacturing method according to claim 11, wherein contacting the probe device with the second upper bonding member comprises electrically connecting the probe device to the semiconductor device through the second upper bonding member, the spacer, and the first upper bonding member. [13] The manufacturing method according to claim 1, wherein detecting the electrical characteristics of the semiconductor device comprises: Applying an electrical signal by the test device to the semiconductor device through the probe device. [14] Test procedure for a power module, comprising: Preparing the power module under test for testing its electrical properties; Contacting a probe device with the power module; electrically connecting the probe device to a test device; and Applying an electrical signal through the test device to the power module, The preparation of the performance module includes: Providing the power module in a processing state in which a semiconductor device is bonded to a lower substrate and a bonding element is arranged on an upper region of the semiconductor device, and wherein contacting the probe device with the power module comprises contacting the probe device with the bonding element arranged on the upper part of the semiconductor device of the power module in the as-manufactured state. [15] The test method of claim 14, wherein the probe device comprises one or more contact pins, wherein a number of the one or more contact pins corresponds to a number of one or more semiconductor devices of the power module, wherein the one or more semiconductor devices include the semiconductor device, and wherein contacting the probe device to the power module comprises contacting the one or more contact pins to the bonding element. [16] The test method of claim 14, wherein the bonding element comprises a material having electrical conductivity. [17] The testing method according to claim 14, wherein a finished product of the power module includes the semiconductor device bonded between an upper substrate and the lower substrate, and wherein the working state of the power module is before the upper substrate is bonded to an upper portion of the semiconductor device by the bonding member.

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