Method and device for setting a system clock of an integrated circuit

Abstract

The present invention relates to a method for setting a system clock of an integrated circuit (1), wherein the integrated circuit (1) has an oscillator module (2) designed to specify a system clock (100) of the integrated circuit (1), a counter module (3), a signal input (4), and a communication interface (5), wherein the method comprises the following steps: a) receiving a reference signal (100) at the signal input (4) for a predefined duration (t), b) incrementing the counter module (3) by one per system clock (100) of the integrated circuit over the duration (t) of the application of the reference signal (200), c) determining a counter value (3a) of the counter module (3) after the duration (t) has elapsed, d) receiving a counter setpoint at the communication interface (5) that corresponds to a number of system clocks during the duration (t) at a setpoint frequency,and e) comparing the counter value (3a) of the counter module (3) with the counter target value and correcting a frequency of the oscillator module (2) based on a deviation of the counter value (3a) from the counter target value.,

Description

State of the artThe present invention

[0001] Embedded oscillators in application-specific integrated circuits (ASICs) are widely known and used in a wide variety of applications across a wide range of industries. Furthermore, it can be generally stated that today's ASICs usually contain function blocks for counting specific events (counter modules).

[0002] To compensate for production-related process variations, a process for adjusting the desired target frequency (oscillator trimming) is often performed after ASIC manufacturing. To perform this frequency adjustment, individual frequency measurements are usually performed on individual components using external test equipment, which is time-consuming and therefore costly.

[0003] To adjust the frequency of an embedded oscillator, the clock signal is typically connected via an ASIC output pin to an external test device, which performs a frequency measurement. Based on the measurement result, the embedded oscillator's configuration is then changed so that the measured frequency deviates as little as possible from the desired target frequency. This is an iterative process that requires multiple frequency measurements and configuration changes. Disclosure of the invention

[0004] The method according to the invention can be carried out quickly and is cost-effective. In particular, it uses a very simple test device connected to an integrated circuit. Furthermore, no complex calculations are required, making the method resource-efficient.

[0005] The method is used to set a system clock of an integrated circuit. The integrated circuit has an oscillator module configured to specify a system clock of the integrated circuit, a counter module, a signal input, and a communication interface. A frequency can be set for the oscillator module, and the method is used to set the frequency to a desired value. The frequency of the oscillator module then determines the system clock during operation of the integrated circuit. The counter module is preferably an event counter. In the simplest case, the counter module can count the number of system clocks over a specific period of time.

[0006] The method comprises the following steps: First, step a) receives a reference signal at the signal input for a predefined duration. Furthermore, step b) increments the counter module by one per system clock cycle of the integrated circuit over the duration of the reference signal. The counter module thus counts the number of system clock cycles as long as the reference signal is present. Knowing the duration for which the reference signal is present allows the counter module to determine the actual system clock cycle.

[0007] A step c) of determining a counter value of the counter module after the duration has elapsed follows. Furthermore, a step d) of receiving a counter setpoint at the communication interface follows. The counter setpoint is generated, in particular, by an external device, wherein the counter setpoint corresponds to a number of system clock cycles during the duration at a setpoint frequency. In other words, the external device advantageously generates the reference signal on the one hand and determines the number of system clock cycles that should occur during the duration of the reference signal on the other hand. This corresponds to a system clock setting, wherein the system clock setting is to be set for the integrated circuit.

[0008] Therefore, step e) is performed to compare the counter value of the counter module with the counter target value and to correct a frequency of the oscillator module based on a deviation of the counter value from the counter target value. If the frequency of the oscillator module matches the specified target frequency, then the system clock of the integrated circuit has the desired value. If this is not the case, this can be detected by the counter module not counting the correct number of system clock cycles during the duration of the reference signal. The frequency of the oscillator module is then either too high, causing the system clock to be too fast and the counter module to have a counter value greater than the counter target value. Alternatively, the frequency of the oscillator module is too low, causing the system clock to be too slow and the counter module to have a counter value lower than the counter target value. In both cases, the incorrect frequency is detectable and correctable.

[0009] No complex external systems are required for the process; only the reference signal and the counter setpoint must be provided. The system clock is primarily set using on-board resources within the integrated circuit, particularly the counter module. Complex or time-consuming calculations are avoided. The process is quick and easy to implement.

[0010] The subclaims show preferred developments of the invention.

[0011] Preferably, after step e) of comparing and correcting, the counter reading of the counter module is reset. Then, all steps a) to e) are repeated to iteratively correct the frequency of the oscillator module. This allows for precise adjustment of the frequency of the oscillator module, thus optimally adapting the system clock of the integrated circuit to a specified value.

[0012] It is particularly advantageous if the duration of the reference signal is longer for each repetition of steps a) to e) than for previously performed repetitions of these steps. This allows for short reference signal durations, particularly for the first few repetitions, where a rough adjustment can be made, while longer durations are provided for later on. The total time required to adjust the system clock is thus minimized.

[0013] Alternatively, it is preferably provided that the duration is the same for all repetitions. In this case, it is particularly unnecessary to perform step d) of receiving the counter setpoint multiple times for each repetition of steps a) to e), since the counter setpoint is always the same. Thus, step d) is only performed once and not repeated. The individual iterations can be better compared in this way. In particular, the repetition that leads to the smallest deviation between the counter setpoint and the counter value can be saved as the final result.

[0014] The frequency of the oscillator module is advantageously adjustable using a binary value with N bits. This is common, for example, in application-specific integrated circuits (ASICs). N stands for a natural number. The iterative frequency correction preferably begins with a value in the middle of the value range that can be represented by the N bits and, particularly advantageously, is adjusted more finely with each iteration.

[0015] In a particularly preferred embodiment, the following steps are carried out to set the system clock of the integrated circuit: First, a step f) of using the most significant bit as the bit to be set takes place. Then, a step g) of setting the bit to be set to 1 takes place. Preferably, all other bits of the N bits, i.e. all bits except the most significant bit, are set to 0. In this way, a value in the middle of the numerical range that can be represented by the N bits is preferably set. As step h), the previously described steps a) to e) are carried out, wherein in step e) the bit to be set is set to 0 if the counter target value is less than the counter value and is left at 1 if the counter target value is greater than or equal to the counter value. This is followed by a step i) of using the next lowest bit as the bit to be set.Finally, steps g) to i) are repeated until all N bits have been processed. Thus, starting with the most significant bit, all bits are adjusted one after the other until the least significant bit is adjusted. In each repetition of steps a) to e), only the bit to be adjusted is changed. All other bits, especially all higher-order bits, remain unchanged, which is particularly advantageous. This leads to an iterative adjustment of the frequency of the oscillator module in order to set the system clock of the integrated circuit. By iterating, starting with the most significant bit, the adjustment is initially coarse and then becomes more fine with each lower-order bit.

[0016] The invention also relates to an integrated circuit. The integrated circuit comprises an oscillator module configured to specify a system clock of the integrated circuit, a counter module, a signal input, and a communication interface. A frequency can be set for the oscillator module, which frequency should be set to a desired value. The frequency of the oscillator module then determines the system clock during operation of the integrated circuit. The counter module is preferably an event counter. In the simplest case, the counter module can count the number of system clock cycles over a specific period of time.

[0017] The integrated circuit is particularly advantageously designed to carry out a method as described above. In particular, the integrated circuit is designed to carry out the steps explained below. The integrated circuit is designed to first carry out step a) of receiving a reference signal at the signal input for a predefined duration. Furthermore, the integrated circuit is configured to carry out step b) of incrementing the counter module by one per system clock cycle of the integrated circuit over the duration for which the reference signal is present. The counter module thus counts the number of system clock cycles as long as the reference signal is present. With knowledge of the duration for which the reference signal is present, the actual system clock cycle can be deduced from the counter module.

[0018] Furthermore, the integrated circuit is designed to perform a step c) of determining a counter value of the counter module after the duration has elapsed. Furthermore, the integrated circuit is designed to output a step d) of receiving a counter setpoint at the communication interface. The counter setpoint is generated in particular by an external device, wherein the counter setpoint corresponds to a number of system clock cycles during the duration at a setpoint frequency. In other words, the external device advantageously generates the reference signal on the one hand and determines the number of system clock cycles that should occur during the duration of the reference signal on the other hand. This corresponds to a system clock setting, wherein the system clock setting is to be set for the integrated circuit.

[0019] Therefore, the integrated circuit is designed to perform step e) of comparing the counter value of the counter module with the counter target value and correcting a frequency of the oscillator module based on a deviation of the counter value from the counter target value. If the frequency of the oscillator module matches the predetermined target frequency, then the system clock of the integrated circuit has the desired value. If this is not the case, this can be recognized by the fact that the counter module does not count the correct number of system clock cycles during the duration of the reference signal. The frequency of the oscillator module is then either too high, whereby the system clock is too fast and the counter module has a larger counter value than the counter target value. Alternatively, the frequency of the oscillator module is too low, whereby the system clock is too slow and the counter module has a lower counter value than the counter target value.In both cases, the faulty frequency can be identified and corrected.

[0020] The integrated circuit is preferably configured to reset the counter reading of the counter module after step e) of comparing and correcting. Furthermore, the integrated circuit is preferably configured to subsequently repeat all steps a) to e) to iteratively correct the frequency of the oscillator module. In this way, the frequency of the oscillator module can be precisely adjusted, thus optimally adapting the system clock of the integrated circuit to a specified value.

[0021] The frequency of the oscillator module is advantageously adjustable using a binary value with N bits. This is common, for example, in application-specific integrated circuits (ASICs). N stands for a natural number. The integrated circuit is preferably designed to begin the iterative frequency correction with a value in the middle of the value range that can be represented by the N bits. The integrated circuit is particularly advantageously designed to adjust the frequency more finely with each iteration.

[0022] The integrated circuit particularly preferably comprises a calibration module. The calibration module is designed to perform steps a) to e).

[0023] In particular, a matching algorithm for performing the method described above is implemented on the matching module. Short description of the drawings

[0024] Embodiments of the invention are described in detail below with reference to the accompanying drawings. In the drawing: Fig. 1 is a schematic view of an integrated circuit according to an embodiment of the invention, Fig. 2 a schematic representation of a time sequence of signals of the integrated circuit according to an embodiment of the invention, and Fig. 3 a schematic representation of a sequence of setting a system clock of the integrated circuit according to the embodiment of the invention. Embodiments of the invention

[0025] Preferably, all identical components, elements and / or units in all figures are provided with the same reference numerals.

[0026] Fig. 1 schematically shows an integrated circuit 1 according to an embodiment of the invention. The integrated circuit is, in particular, an application-specific integrated circuit, abbreviated to ASIC.

[0027] The integrated circuit 1 has an oscillator module 2. The oscillator module 2 is configured to specify a system clock 100 of the integrated circuit 1. Furthermore, the integrated circuit 1 has a counter module 3, a signal input 4, and a communication interface 5. Furthermore, a calibration module 8 is provided, which is coupled in particular to the communication interface 5.

[0028] An external device 7 can be connected to the communication interface 5 in order to establish a communication connection 300 with the calibration module 8. Furthermore, the external device 7 can be connected to the signal input 4 in order to output a reference signal 100 to the integrated circuit 1.

[0029] The signal input 4 is coupled to a synchronization module 6, wherein the synchronization module 6 is designed to synchronize the reference signal 200 with the system clock 100. The resulting synchronized reference signal 200a is output to the counter module 3 and serves to start and stop the counter module 3. If the level of the synchronized reference signal 100a corresponds to a logical one, the value of the counter module 3 is incremented by one with each rising edge of the system clock. The calibration module 8 is coupled to the counter module 3 and allows a query of a counter value 3a of the counter module 3 and a reset 3b of the counter module 1. Furthermore, the calibration module 8 is designed to set a frequency of the oscillator module 2. For this purpose, a calibration algorithm is preferably implemented on the calibration module 8.

[0030] The frequency of oscillator module 2 can be set using a binary value with N bits. N is a natural number. An iterative procedure is used to set the frequency, as shown in Fig. 3. For this purpose, several iterations 10, 20, 30 are performed, each with the same steps.

[0031] The iterative correction of the frequency of the oscillator module 2 begins with a frequency value in the middle of the value range that can be represented by the N bits. The adjustment algorithm is designed to perform the following steps: Initially, the most significant bit of the N bits is considered the bit to be set. Each iteration 10, 20, 30 begins by setting the bit to be set to 1. All lower-order bits are preferably set to the value 0 or left at this value. In the first iteration 10, an average value of the number range that can be represented by the N bits is used by setting the most significant bit to 1. The number range that can be represented is Fig. 3 schematically shown as a column.

[0032] The adjustment algorithm then performs several steps to adjust the set frequency to a desired frequency. A reference signal 100 is received at signal input 4 from external device 7 for a duration t. This means that reference signal 200 represents a logical 1 for duration t. As previously explained, this starts counter module 3, so that counter module 3 is incremented by one per system clock cycle of the integrated circuit for the duration t of the reference signal 200 being present. After duration t has elapsed, counter value 3a of counter module 3 is determined by the adjustment algorithm. In addition, adjustment module 8 receives a counter setpoint from external device 7 via communication interface 5, which counter setpoint corresponds to a number of system clock cycles during duration t at a desired setpoint frequency.By comparing the counter value 3a of the counter module 3 with the counter setpoint, a deviation in the frequency of the oscillator module 2 can be determined. The adjustment algorithm corrects the frequency of the oscillator module 2 based on the deviation of the counter value 3a from the counter setpoint.

[0033] Frequency adjustment is based on the principle that the counter module 3 is influenced for the duration t of the external reference signal 200, i.e., the level corresponding to a logical one. A counter value 3a of the counter module 3 correlates directly with the frequency of the oscillator via the system clock. Using the signal shape of the reference signal 100 specified by the external device 7 and the desired target frequency f to be set for the oscillator module 2, the counter setpoint of the counter module 3 can be calculated as follows: Counter setpoint = t * f.

[0034] If the counter setpoint is less than the counter value 3a, the bit to be set is set to 0. In this case, the frequency of oscillator module 2 is too high and the system clock 100 is too fast, which is why too many increments of counter module 3 occur over the duration t. A reduction 12 occurs. However, the value of the bit to be set is left at 1 if the counter setpoint is greater than or equal to the counter value 3a. In this case, the frequency of oscillator module 2 is too low and the system clock 100 is too slow. Therefore, too few increments of counter module 3 occur over the duration t. An increase 11 occurs.

[0035] This completes the respective iteration 10, 20, and 30. The next lower bit is then used as the bit to be adjusted, and the above steps are repeated for the new bit to be adjusted. This results in an increasingly finer adjustment of the frequency of oscillator module 2 until all N bits are adjusted.

[0036] Method according to claim 2, characterized in that the duration (t) is the same for all repetitions, wherein step d) of receiving the counter setpoint is carried out only once and is not repeated.

[0037] The matching algorithm allows the following options: • Because the oscillator configuration is initially set roughly with the most significant bit and then more precisely with each iteration (10, 20, 30), the duration t of the reference signal 200 can also be selected to be short initially and longer with each iteration (10, 20, 30). This results in a new counter setpoint for the counter value, which is to be transmitted via communication interface 5, with each iteration (10, 20, 30). The total test time can thus be reduced even further. • Alternatively, the duration t of the reference signal 100 is selected to be the same for each iteration 10, 20, and 30. Therefore, the counter setpoint for the counter value is always the same and only needs to be transmitted once via communication interface 5. This also makes iterations 10, 20, and 30 comparable. The calibration algorithm can therefore save the oscillator configuration that results in the smallest deviation between counter value 3a and the counter setpoint and provide it as the final result after completion of iterations 10, 20, and 30.

[0038] The external device's task is limited to providing the reference signal 200 and the counter setpoint. Individual calculations or configurations are not required. The individual calibration of the oscillator module 2 is performed by the integrated circuit 1 itself. This allows the same stimulus from the external device 7 to be used to calibrate any number of integrated circuits 1 simultaneously.

[0039] The adjustment of the oscillator frequency within the integrated circuit 1, in particular within the ASIC, with the aid of the counter module 3 and an external time reference can be carried out much faster than via an otherwise usual iterative frequency measurement on an external test device.

[0040] Furthermore, this invention enables the simultaneous frequency alignment of multiple ASICs, since the external device 7 does not require a dedicated measurement channel to each ASIC. By executing the alignment algorithm within the ASIC, any number of components can be aligned in parallel using a single external time reference. The resulting savings in test time enable a direct reduction in test costs.

[0041] The additional logic that has to be implemented on the ASIC is hardly significant, in particular an already integrated counter module 3 can be reused.

Claims

[1] Method for setting a system clock of an integrated circuit (1), wherein the integrated circuit (1) has an oscillator module (2) designed to specify a system clock (100) of the integrated circuit (1), a counter module (3), a signal input (4) and a communication interface (5), the method comprising the following steps: a) receiving a reference signal (100) at the signal input (4) for a predefined duration (t), b) incrementing the counter module (3) by one over the duration (t) of the application of the reference signal (200) per system clock cycle (100) of the integrated circuit, c) determining a counter value (3a) of the counter module (3) after the duration (t) has elapsed, d) receiving a counter setpoint at the communication interface (5) which corresponds to a number of system clock cycles during the duration (t) at a setpoint frequency, and e) comparing the counter value (3a) of the counter module (3) with the counter target value and correcting a frequency of the oscillator module (2) based on a deviation of the counter value (3a) from the counter target value. [2] Method according to claim 1, characterized by that after step e) of comparing and correcting, the counter reading of the counter module (3) is reset, wherein all steps a) to e) are repeated in order to iteratively correct the frequency of the oscillator module (2). [3] Method according to claim 2, characterized by that the duration (t) of the reference signal is longer for each repetition of steps a) to e) than for previously performed repetitions of these steps. [4] Method according to claim 2, characterized by that the duration (t) is the same for all repetitions, whereby step d) of receiving the counter setpoint is only carried out once and is not repeated. [5] Method according to one of claims 2 to 4, characterized by that the frequency of the oscillator module (2) can be set by a binary value with N bits, where N is a natural number, and the iterative correction of the frequency is started with a value in the middle of the value range that can be represented by the N bits. [6] Method according to claim 5, characterized by the steps: f) Using the most significant bit as the bit to be set, g) Set the bit to be set to 1, h) carrying out steps a) to e), wherein in step e) the bit to be set is set to 0 if the counter setpoint is less than the counter value (3a) and is left at 1 if the counter setpoint is greater than or equal to the counter value (3a), i) using the next lowest bit as the bit to be set, and j) Repeat steps g) to i) until all N bits have been passed through. [7] Integrated circuit (1) comprising - an oscillator module (2) designed to specify a system clock (100) of the integrated circuit (1) - a counter module (3), - a signal input (4), and - a communication interface (5), - wherein the integrated circuit (1) is designed to: a) receiving a reference signal (200) at the signal input (4) for a predefined duration (t), b) incrementing the counter module (3) by one over the duration (t) of the application of the reference signal (200) per system clock cycle (100) of the integrated circuit, c) determining a counter value (3a) of the counter module (3) after the duration (t) has elapsed, d) receiving a counter setpoint at the communication interface (5) which corresponds to a number of system clock cycles during the duration (t) at a setpoint frequency, and e) comparing the counter value (3a) of the counter module (3) with the counter target value and correcting a frequency of the oscillator module (2) based on a deviation of the counter value (3a) from the counter target value. [8] Integrated circuit (1) according to claim 7, characterized by that the integrated circuit (1) is designed, after step e) of comparing and correcting, to reset the counter reading of the counter module (3) and to repeatedly execute all steps in order to iteratively correct the frequency of the oscillator module (2). [9] Integrated circuit (1) according to claim 8, characterized by that the frequency of the oscillator module (2) can be adjusted by a binary value with N bits, where N is a natural number, and where the integrated circuit (1) is designed to start the iterative correction of the frequency with a value in the middle of the value range that can be represented by the N bits. [10] Integrated circuit (1) according to one of claims 7 to 9, characterized by a calibration module (8) designed to carry out steps a) to e).

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